From 5219b4bfbe2f7008a44dd8afb657a1a96a04e3bb Mon Sep 17 00:00:00 2001 From: nzasch <> Date: Mon, 3 Jan 2022 17:56:55 +0100 Subject: [PATCH] init --- hw/Driver_FET.dcm | 1156 + hw/Driver_FET.lib | 3026 ++ hw/fp-info-cache | 701 + hw/fzzt-cache.lib | 279 + hw/fzzt-rescue.dcm | 3 + hw/fzzt-rescue.lib | 27 + hw/fzzt.kicad_pcb | 1130 + hw/fzzt.kicad_pcb-bak | 1086 + hw/fzzt.pro | 240 + hw/fzzt.sch | 618 + hw/fzzt.sch-bak | 443 + hw/ixdn609pi.dcm | 10 + hw/ixdn609pi.lib | 27 + hw/sym-lib-table | 4 + note.txt | 14 + squero/.mxproject | 25 + squero/Core/Inc/main.h | 70 + squero/Core/Inc/si5351.h | 330 + squero/Core/Inc/si5351_asserts.h | 84 + squero/Core/Inc/si5351_errors.h | 67 + squero/Core/Inc/stm32g0xx_hal_conf.h | 351 + squero/Core/Inc/stm32g0xx_it.h | 62 + squero/Core/Src/main.c | 295 + squero/Core/Src/si5351.c | 713 + squero/Core/Src/stm32g0xx_hal_msp.c | 149 + squero/Core/Src/stm32g0xx_it.c | 146 + squero/Core/Src/system_stm32g0xx.c | 304 + .../Device/ST/STM32G0xx/Include/stm32g031xx.h | 7876 +++++ .../Device/ST/STM32G0xx/Include/stm32g0xx.h | 249 + .../ST/STM32G0xx/Include/system_stm32g0xx.h | 104 + .../CMSIS/Device/ST/STM32G0xx/LICENSE.txt | 6 + squero/Drivers/CMSIS/Include/cmsis_armcc.h | 894 + squero/Drivers/CMSIS/Include/cmsis_armclang.h | 1444 + .../CMSIS/Include/cmsis_armclang_ltm.h | 1891 ++ squero/Drivers/CMSIS/Include/cmsis_compiler.h | 283 + squero/Drivers/CMSIS/Include/cmsis_gcc.h | 2168 ++ squero/Drivers/CMSIS/Include/cmsis_iccarm.h | 964 + squero/Drivers/CMSIS/Include/cmsis_version.h | 39 + squero/Drivers/CMSIS/Include/core_armv81mml.h | 2968 ++ squero/Drivers/CMSIS/Include/core_armv8mbl.h | 1921 ++ squero/Drivers/CMSIS/Include/core_armv8mml.h | 2835 ++ squero/Drivers/CMSIS/Include/core_cm0.h | 952 + squero/Drivers/CMSIS/Include/core_cm0plus.h | 1085 + squero/Drivers/CMSIS/Include/core_cm1.h | 979 + squero/Drivers/CMSIS/Include/core_cm23.h | 1996 ++ squero/Drivers/CMSIS/Include/core_cm3.h | 1937 ++ squero/Drivers/CMSIS/Include/core_cm33.h | 2910 ++ squero/Drivers/CMSIS/Include/core_cm35p.h | 2910 ++ squero/Drivers/CMSIS/Include/core_cm4.h | 2124 ++ squero/Drivers/CMSIS/Include/core_cm7.h | 2725 ++ squero/Drivers/CMSIS/Include/core_sc000.h | 1025 + squero/Drivers/CMSIS/Include/core_sc300.h | 1912 ++ squero/Drivers/CMSIS/Include/mpu_armv7.h | 272 + squero/Drivers/CMSIS/Include/mpu_armv8.h | 346 + squero/Drivers/CMSIS/Include/tz_context.h | 70 + squero/Drivers/CMSIS/LICENSE.txt | 201 + .../Inc/Legacy/stm32_hal_legacy.h | 3830 +++ .../STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h | 839 + .../Inc/stm32g0xx_hal_cortex.h | 387 + .../Inc/stm32g0xx_hal_def.h | 214 + .../Inc/stm32g0xx_hal_dma.h | 803 + .../Inc/stm32g0xx_hal_dma_ex.h | 280 + .../Inc/stm32g0xx_hal_exti.h | 389 + .../Inc/stm32g0xx_hal_flash.h | 1036 + .../Inc/stm32g0xx_hal_flash_ex.h | 119 + .../Inc/stm32g0xx_hal_gpio.h | 364 + .../Inc/stm32g0xx_hal_gpio_ex.h | 838 + .../Inc/stm32g0xx_hal_i2c.h | 838 + .../Inc/stm32g0xx_hal_i2c_ex.h | 180 + .../Inc/stm32g0xx_hal_pwr.h | 328 + .../Inc/stm32g0xx_hal_pwr_ex.h | 643 + .../Inc/stm32g0xx_hal_rcc.h | 3138 ++ .../Inc/stm32g0xx_hal_rcc_ex.h | 1593 + .../Inc/stm32g0xx_hal_tim.h | 2439 ++ .../Inc/stm32g0xx_hal_tim_ex.h | 495 + .../Inc/stm32g0xx_ll_dma.h | 2272 ++ .../Inc/stm32g0xx_ll_dmamux.h | 1828 ++ .../Inc/stm32g0xx_ll_rcc.h | 3886 +++ .../Drivers/STM32G0xx_HAL_Driver/License.md | 3 + .../STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c | 759 + .../Src/stm32g0xx_hal_cortex.c | 417 + .../Src/stm32g0xx_hal_dma.c | 1191 + .../Src/stm32g0xx_hal_dma_ex.c | 320 + .../Src/stm32g0xx_hal_exti.c | 672 + .../Src/stm32g0xx_hal_flash.c | 723 + .../Src/stm32g0xx_hal_flash_ex.c | 1310 + .../Src/stm32g0xx_hal_gpio.c | 551 + .../Src/stm32g0xx_hal_i2c.c | 6796 ++++ .../Src/stm32g0xx_hal_i2c_ex.c | 366 + .../Src/stm32g0xx_hal_pwr.c | 545 + .../Src/stm32g0xx_hal_pwr_ex.c | 1019 + .../Src/stm32g0xx_hal_rcc.c | 1457 + .../Src/stm32g0xx_hal_rcc_ex.c | 1681 + .../Src/stm32g0xx_hal_tim.c | 7782 +++++ .../Src/stm32g0xx_hal_tim_ex.c | 2843 ++ .../Src/stm32g0xx_ll_dma.c | 369 + .../Src/stm32g0xx_ll_rcc.c | 1358 + squero/Makefile | 194 + squero/STM32G031J6Mx_FLASH.ld | 189 + squero/build/main.d | 63 + squero/build/main.lst | 1193 + squero/build/main.o | Bin 0 -> 15732 bytes squero/build/si5351.d | 63 + squero/build/si5351.lst | 4064 +++ squero/build/si5351.o | Bin 0 -> 42784 bytes squero/build/squero.bin | Bin 0 -> 19340 bytes squero/build/squero.elf | Bin 0 -> 390304 bytes squero/build/squero.hex | 1214 + squero/build/squero.map | 2348 ++ squero/build/startup_stm32g031xx.d | 1 + squero/build/startup_stm32g031xx.o | Bin 0 -> 4296 bytes squero/build/stm32g0xx_hal.d | 58 + squero/build/stm32g0xx_hal.lst | 2246 ++ squero/build/stm32g0xx_hal.o | Bin 0 -> 22660 bytes squero/build/stm32g0xx_hal_cortex.d | 59 + squero/build/stm32g0xx_hal_cortex.lst | 3801 +++ squero/build/stm32g0xx_hal_cortex.o | Bin 0 -> 17096 bytes squero/build/stm32g0xx_hal_dma.d | 59 + squero/build/stm32g0xx_hal_dma.lst | 3969 +++ squero/build/stm32g0xx_hal_dma.o | Bin 0 -> 23056 bytes squero/build/stm32g0xx_hal_dma_ex.d | 59 + squero/build/stm32g0xx_hal_dma_ex.lst | 898 + squero/build/stm32g0xx_hal_dma_ex.o | Bin 0 -> 10504 bytes squero/build/stm32g0xx_hal_exti.d | 59 + squero/build/stm32g0xx_hal_exti.lst | 2137 ++ squero/build/stm32g0xx_hal_exti.o | Bin 0 -> 18188 bytes squero/build/stm32g0xx_hal_flash.d | 59 + squero/build/stm32g0xx_hal_flash.lst | 3225 ++ squero/build/stm32g0xx_hal_flash.o | Bin 0 -> 16904 bytes squero/build/stm32g0xx_hal_flash_ex.d | 59 + squero/build/stm32g0xx_hal_flash_ex.lst | 3400 ++ squero/build/stm32g0xx_hal_flash_ex.o | Bin 0 -> 22684 bytes squero/build/stm32g0xx_hal_gpio.d | 59 + squero/build/stm32g0xx_hal_gpio.lst | 1774 ++ squero/build/stm32g0xx_hal_gpio.o | Bin 0 -> 12468 bytes squero/build/stm32g0xx_hal_i2c.d | 59 + squero/build/stm32g0xx_hal_i2c.lst | 26463 ++++++++++++++++ squero/build/stm32g0xx_hal_i2c.o | Bin 0 -> 134624 bytes squero/build/stm32g0xx_hal_i2c_ex.d | 59 + squero/build/stm32g0xx_hal_i2c_ex.lst | 1000 + squero/build/stm32g0xx_hal_i2c_ex.o | Bin 0 -> 13416 bytes squero/build/stm32g0xx_hal_msp.d | 59 + squero/build/stm32g0xx_hal_msp.lst | 480 + squero/build/stm32g0xx_hal_msp.o | Bin 0 -> 11064 bytes squero/build/stm32g0xx_hal_pwr.d | 59 + squero/build/stm32g0xx_hal_pwr.lst | 1197 + squero/build/stm32g0xx_hal_pwr.o | Bin 0 -> 10740 bytes squero/build/stm32g0xx_hal_pwr_ex.d | 59 + squero/build/stm32g0xx_hal_pwr_ex.lst | 2819 ++ squero/build/stm32g0xx_hal_pwr_ex.o | Bin 0 -> 20560 bytes squero/build/stm32g0xx_hal_rcc.d | 59 + squero/build/stm32g0xx_hal_rcc.lst | 6610 ++++ squero/build/stm32g0xx_hal_rcc.o | Bin 0 -> 25404 bytes squero/build/stm32g0xx_hal_rcc_ex.d | 59 + squero/build/stm32g0xx_hal_rcc_ex.lst | 3625 +++ squero/build/stm32g0xx_hal_rcc_ex.o | Bin 0 -> 19352 bytes squero/build/stm32g0xx_hal_tim.d | 59 + squero/build/stm32g0xx_hal_tim.lst | 27 + squero/build/stm32g0xx_hal_tim.o | Bin 0 -> 2152 bytes squero/build/stm32g0xx_hal_tim_ex.d | 59 + squero/build/stm32g0xx_hal_tim_ex.lst | 27 + squero/build/stm32g0xx_hal_tim_ex.o | Bin 0 -> 2156 bytes squero/build/stm32g0xx_it.d | 61 + squero/build/stm32g0xx_it.lst | 298 + squero/build/stm32g0xx_it.o | Bin 0 -> 4372 bytes squero/build/stm32g0xx_ll_dma.d | 2 + squero/build/stm32g0xx_ll_dma.lst | 25 + squero/build/stm32g0xx_ll_dma.o | Bin 0 -> 1112 bytes squero/build/stm32g0xx_ll_rcc.d | 2 + squero/build/stm32g0xx_ll_rcc.lst | 25 + squero/build/stm32g0xx_ll_rcc.o | Bin 0 -> 1112 bytes squero/build/system_stm32g0xx.d | 58 + squero/build/system_stm32g0xx.lst | 631 + squero/build/system_stm32g0xx.o | Bin 0 -> 6320 bytes squero/note | 13 + squero/squero.ioc | 110 + squero/startup_stm32g031xx.s | 289 + 177 files changed, 188890 insertions(+) create mode 100644 hw/Driver_FET.dcm create mode 100644 hw/Driver_FET.lib create mode 100644 hw/fp-info-cache create mode 100644 hw/fzzt-cache.lib create mode 100644 hw/fzzt-rescue.dcm create mode 100644 hw/fzzt-rescue.lib create mode 100644 hw/fzzt.kicad_pcb create mode 100644 hw/fzzt.kicad_pcb-bak create mode 100644 hw/fzzt.pro create mode 100644 hw/fzzt.sch create mode 100644 hw/fzzt.sch-bak create mode 100644 hw/ixdn609pi.dcm create mode 100644 hw/ixdn609pi.lib create mode 100644 hw/sym-lib-table create mode 100644 note.txt create mode 100644 squero/.mxproject create mode 100644 squero/Core/Inc/main.h create mode 100644 squero/Core/Inc/si5351.h create mode 100644 squero/Core/Inc/si5351_asserts.h create mode 100644 squero/Core/Inc/si5351_errors.h create mode 100644 squero/Core/Inc/stm32g0xx_hal_conf.h create mode 100644 squero/Core/Inc/stm32g0xx_it.h create mode 100644 squero/Core/Src/main.c create mode 100644 squero/Core/Src/si5351.c create mode 100644 squero/Core/Src/stm32g0xx_hal_msp.c create mode 100644 squero/Core/Src/stm32g0xx_it.c create mode 100644 squero/Core/Src/system_stm32g0xx.c create mode 100644 squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h create mode 100644 squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h create mode 100644 squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h create mode 100644 squero/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.txt create mode 100644 squero/Drivers/CMSIS/Include/cmsis_armcc.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_armclang.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_armclang_ltm.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_compiler.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_gcc.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_iccarm.h create mode 100644 squero/Drivers/CMSIS/Include/cmsis_version.h create mode 100644 squero/Drivers/CMSIS/Include/core_armv81mml.h create mode 100644 squero/Drivers/CMSIS/Include/core_armv8mbl.h create mode 100644 squero/Drivers/CMSIS/Include/core_armv8mml.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm0.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm0plus.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm1.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm23.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm3.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm33.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm35p.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm4.h create mode 100644 squero/Drivers/CMSIS/Include/core_cm7.h create mode 100644 squero/Drivers/CMSIS/Include/core_sc000.h create mode 100644 squero/Drivers/CMSIS/Include/core_sc300.h create mode 100644 squero/Drivers/CMSIS/Include/mpu_armv7.h create mode 100644 squero/Drivers/CMSIS/Include/mpu_armv8.h create mode 100644 squero/Drivers/CMSIS/Include/tz_context.h create mode 100644 squero/Drivers/CMSIS/LICENSE.txt create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/License.md create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c create mode 100644 squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c create mode 100644 squero/Makefile create mode 100644 squero/STM32G031J6Mx_FLASH.ld create mode 100644 squero/build/main.d create mode 100644 squero/build/main.lst create mode 100644 squero/build/main.o create mode 100644 squero/build/si5351.d create mode 100644 squero/build/si5351.lst create mode 100644 squero/build/si5351.o create mode 100755 squero/build/squero.bin create mode 100755 squero/build/squero.elf create mode 100644 squero/build/squero.hex create mode 100644 squero/build/squero.map create mode 100644 squero/build/startup_stm32g031xx.d create mode 100644 squero/build/startup_stm32g031xx.o create mode 100644 squero/build/stm32g0xx_hal.d create mode 100644 squero/build/stm32g0xx_hal.lst create mode 100644 squero/build/stm32g0xx_hal.o create mode 100644 squero/build/stm32g0xx_hal_cortex.d create mode 100644 squero/build/stm32g0xx_hal_cortex.lst create mode 100644 squero/build/stm32g0xx_hal_cortex.o create mode 100644 squero/build/stm32g0xx_hal_dma.d create mode 100644 squero/build/stm32g0xx_hal_dma.lst create mode 100644 squero/build/stm32g0xx_hal_dma.o create mode 100644 squero/build/stm32g0xx_hal_dma_ex.d create mode 100644 squero/build/stm32g0xx_hal_dma_ex.lst create mode 100644 squero/build/stm32g0xx_hal_dma_ex.o create mode 100644 squero/build/stm32g0xx_hal_exti.d create mode 100644 squero/build/stm32g0xx_hal_exti.lst create mode 100644 squero/build/stm32g0xx_hal_exti.o create mode 100644 squero/build/stm32g0xx_hal_flash.d create mode 100644 squero/build/stm32g0xx_hal_flash.lst create mode 100644 squero/build/stm32g0xx_hal_flash.o create mode 100644 squero/build/stm32g0xx_hal_flash_ex.d create mode 100644 squero/build/stm32g0xx_hal_flash_ex.lst create mode 100644 squero/build/stm32g0xx_hal_flash_ex.o create mode 100644 squero/build/stm32g0xx_hal_gpio.d create mode 100644 squero/build/stm32g0xx_hal_gpio.lst create mode 100644 squero/build/stm32g0xx_hal_gpio.o create mode 100644 squero/build/stm32g0xx_hal_i2c.d create mode 100644 squero/build/stm32g0xx_hal_i2c.lst create mode 100644 squero/build/stm32g0xx_hal_i2c.o create mode 100644 squero/build/stm32g0xx_hal_i2c_ex.d create mode 100644 squero/build/stm32g0xx_hal_i2c_ex.lst create mode 100644 squero/build/stm32g0xx_hal_i2c_ex.o create mode 100644 squero/build/stm32g0xx_hal_msp.d create mode 100644 squero/build/stm32g0xx_hal_msp.lst create mode 100644 squero/build/stm32g0xx_hal_msp.o create mode 100644 squero/build/stm32g0xx_hal_pwr.d create mode 100644 squero/build/stm32g0xx_hal_pwr.lst create mode 100644 squero/build/stm32g0xx_hal_pwr.o create mode 100644 squero/build/stm32g0xx_hal_pwr_ex.d create mode 100644 squero/build/stm32g0xx_hal_pwr_ex.lst create mode 100644 squero/build/stm32g0xx_hal_pwr_ex.o create mode 100644 squero/build/stm32g0xx_hal_rcc.d create mode 100644 squero/build/stm32g0xx_hal_rcc.lst create mode 100644 squero/build/stm32g0xx_hal_rcc.o create mode 100644 squero/build/stm32g0xx_hal_rcc_ex.d create mode 100644 squero/build/stm32g0xx_hal_rcc_ex.lst create mode 100644 squero/build/stm32g0xx_hal_rcc_ex.o create mode 100644 squero/build/stm32g0xx_hal_tim.d create mode 100644 squero/build/stm32g0xx_hal_tim.lst create mode 100644 squero/build/stm32g0xx_hal_tim.o create mode 100644 squero/build/stm32g0xx_hal_tim_ex.d create mode 100644 squero/build/stm32g0xx_hal_tim_ex.lst create mode 100644 squero/build/stm32g0xx_hal_tim_ex.o create mode 100644 squero/build/stm32g0xx_it.d create mode 100644 squero/build/stm32g0xx_it.lst create mode 100644 squero/build/stm32g0xx_it.o create mode 100644 squero/build/stm32g0xx_ll_dma.d create mode 100644 squero/build/stm32g0xx_ll_dma.lst create mode 100644 squero/build/stm32g0xx_ll_dma.o create mode 100644 squero/build/stm32g0xx_ll_rcc.d create mode 100644 squero/build/stm32g0xx_ll_rcc.lst create mode 100644 squero/build/stm32g0xx_ll_rcc.o create mode 100644 squero/build/system_stm32g0xx.d create mode 100644 squero/build/system_stm32g0xx.lst create mode 100644 squero/build/system_stm32g0xx.o create mode 100644 squero/note create mode 100644 squero/squero.ioc create mode 100644 squero/startup_stm32g031xx.s diff --git a/hw/Driver_FET.dcm b/hw/Driver_FET.dcm new file mode 100644 index 0000000..38b5eec --- /dev/null +++ b/hw/Driver_FET.dcm @@ -0,0 +1,1156 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP 1EDN7550B +D Single-Channel EiceDRIVER With True Differential Inputs, 4V UVLO, +4/-8A, SOT-23-6 +K Driver, Dual MOSFET +F https://www.infineon.com/dgdl/Infineon-1EDN7550B-DS-v02_00-EN.pdf?fileId=5546d46262b31d2e01635d9799ef264f +$ENDCMP +# +$CMP 1EDN8550B +D Single-Channel EiceDRIVER With True Differential Inputs, 8V UVLO, +4/-8A, SOT-23-6 +K Driver, Dual MOSFET +F https://www.infineon.com/dgdl/Infineon-1EDN7550B-DS-v02_00-EN.pdf?fileId=5546d46262b31d2e01635d9799ef264f +$ENDCMP +# +$CMP ACPL-336J +D 2.5A Gate Drive Optocoupler with Integrated LED Driver, Active Miller Clamp, DESAT Detection, and Fault & UVLO Status Feedback, SOIC-16 +K Gate Driver IGBT +F https://docs.broadcom.com/docs/AV02-4391EN +$ENDCMP +# +$CMP ACPL-P343 +D Gate Drive Optocoupler, Output Current 4.0/4.0A, Propagation Delay 200ns, SSO-6 +K MOSFET Driver IGBT Driver Optocoupler +F https://docs.broadcom.com/docs/AV02-2928EN +$ENDCMP +# +$CMP ACPL-W343 +D Gate Drive Optocoupler, Output Current 4.0/4.0A, Propagation Delay 200ns, SSO-6 +K MOSFET Driver IGBT Driver Optocoupler +F http://www.avagotech.com/docs/AV02-2928EN +$ENDCMP +# +$CMP AN34092B +D Single-Channel GaN-Tr High-Speed Gate Driver, Output Current 6.0A, 24V, -5V Negative Gate Voltage, HQFN-16 +K GaN Gate Driver +F https://industrial.panasonic.com/content/data/SC/ds/ds4/AN34092B_E.pdf +$ENDCMP +# +$CMP BSP75N +D Self-Protected Low Side Driver with Temperature and Current Limit, SOT−223 +K MOSFET ESD Overcurrent +F https://www.infineon.com/dgdl/Infineon-BSP75N-DS-v01_04-en.pdf?fileId=db3a30431ed1d7b2011f471f5a0256d1 +$ENDCMP +# +$CMP EL7202CN +D High Speed, Dual Channel Power MOSFET Driver, DIP-8/SOIC-8 +K Driver, Dual MOSFET +F http://www.intersil.com/content/dam/Intersil/documents/el72/el7202-12-22.pdf +$ENDCMP +# +$CMP EL7212CN +D High Speed, Dual Channel Power MOSFET Driver, DIP-8/SOIC-8 +K Driver, Dual MOSFET +F http://www.intersil.com/content/dam/Intersil/documents/el72/el7202-12-22.pdf +$ENDCMP +# +$CMP EL7222CN +D High Speed, Dual Channel Power MOSFET Driver, DIP-8/SOIC-8 +K Driver, Dual MOSFET +F http://www.intersil.com/content/dam/Intersil/documents/el72/el7202-12-22.pdf +$ENDCMP +# +$CMP FAN3268 +D Low-Voltage 18V PMOS-NMOS Bridge Driver, SOIC-8 +K Driver MOSFET +F http://www.onsemi.com/pub/Collateral/FAN3268T_F085-D.PDF +$ENDCMP +# +$CMP FAN3278 +D 8-27V PMOS-NMOS Bridge Driver, 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https://www.infineon.com/dgdl/Infineon-IR2x33-IR2x35-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a4015355c890ba169f +$ENDCMP +# +$CMP IR2301 +D High and Low Side Driver, 600V, 200/350mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir2301.pdf?fileId=5546d462533600a4015355c97bb216dc +$ENDCMP +# +$CMP IR2302 +D Half-Bridge Driver, 600V, 200/350mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir2302.pdf?fileId=5546d462533600a4015355c988b216de +$ENDCMP +# +$CMP IR2304 +D Half-Bridge Driver, 600V, 60/130mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir2304.pdf?fileId=5546d462533600a4015355c9954a16e0 +$ENDCMP +# +$CMP IR2308 +D Half-Bridge Driver, 600V, 200/350mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir2308.pdf?fileId=5546d462533600a4015355c9a2b816e2 +$ENDCMP +# +$CMP IR25602S +D Half-Bridge Driver, 600V, 210/360mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir25602.pdf?fileId=5546d462533600a4015355c9d6c216eb +$ENDCMP +# +$CMP IR25603 +D Self-Oscillating Half-Bridge Driver, 600V, 180/260mA, PDIP-8/SOIC-8 +K Oscillating Gate Driver +F https://www.infineon.com/dgdl/ir25603.pdf?fileId=5546d462533600a4015355c9e46716ef +$ENDCMP +# +$CMP IR25604S +D High and Low Side Driver, 600V, 200/350mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir25604.pdf?fileId=5546d462533600a4015355c9f1ca16f1 +$ENDCMP +# +$CMP IR25607S +D High and Low Side Driver, 600V, 2.0/2.0A, SOIC-16W +K Gate Driver +F https://www.infineon.com/dgdl/ir25607.pdf?fileId=5546d462533600a4015355ca0e7916f5 +$ENDCMP +# +$CMP IR7106S +D High and Low Side Driver, 700V, 200/350mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir7106s.pdf?fileId=5546d462533600a4015355d61a06182a +$ENDCMP +# +$CMP IR7184S +D 700V Half-Bridge Driver, 1.9/2.3A, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir7184s.pdf?fileId=5546d462533600a4015355d62230182c +$ENDCMP +# +$CMP IR7304S +D 700V Half-Bridge Driver, 60/130mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir7304s.pdf?fileId=5546d462533600a4015355d62a63182e +$ENDCMP +# +$CMP IRS2001 +D High and Low Side Driver, 200V, 200/420mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2001pbf.pdf?fileId=5546d462533600a401535675a760277e +$ENDCMP +# +$CMP IRS2001M +D High and Low Side Driver, 200V, 290/600mA, MLPQ-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2001mpbf.pdf?fileId=5546d462533600a4015356759e20277c +$ENDCMP +# +$CMP IRS2003 +D Half-Bridge Driver, 200V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2003pbf.pdf?fileId=5546d462533600a401535675afec2780 +$ENDCMP +# +$CMP IRS2004 +D Half-Bridge Driver, 200V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2004pbf.pdf?fileId=5546d462533600a401535675b86b2782 +$ENDCMP +# +$CMP IRS2005M +D High and Low Side Driver, 200V, 290/600mA, MLPQ-14 +K Gate Driver +F https://www.infineon.com/dgdl/Infineon-IRS2005S-DS-v02_00-EN.pdf?fileId=5546d462533600a4015364c4246229e1 +$ENDCMP +# +$CMP IRS2005S +D High and Low Side Driver, 200V, 290/600mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/Infineon-IRS2005S-DS-v02_00-EN.pdf?fileId=5546d462533600a4015364c4246229e1 +$ENDCMP +# +$CMP IRS2008S +D 200-V Half-Bridge Driver With Shutdown Input, 200V, 290/600mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/Infineon-IRS2008S-DS-v01_00-EN.pdf?fileId=5546d46259d9a4bf015a3e76b6361c1a +$ENDCMP +# +$CMP IRS2011 +D High and Low Side Driver, 200V, 1.0/1.0A, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2011pbf.pdf?fileId=5546d462533600a401535675c19f2784 +$ENDCMP +# +$CMP IRS2101 +D High and Low Side Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir2101.pdf?fileId=5546d462533600a4015355c7a755166c +$ENDCMP +# +$CMP IRS2103 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2103.pdf?fileId=5546d462533600a4015356762b71279f +$ENDCMP +# +$CMP IRS2104 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2104.pdf?fileId=5546d462533600a40153567633f727a1 +$ENDCMP +# +$CMP IRS2106 +D High and Low Side Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2106.pdf?fileId=5546d462533600a4015356763aa527a3 +$ENDCMP +# +$CMP IRS21064 +D High and Low Side Driver, 600V, 290/600mA, PDIP-14/SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2106.pdf?fileId=5546d462533600a4015356763aa527a3 +$ENDCMP +# +$CMP IRS2108 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2108.pdf?fileId=5546d462533600a40153567649d627a8 +$ENDCMP +# +$CMP IRS21084 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-14/SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2108.pdf?fileId=5546d462533600a40153567649d627a8 +$ENDCMP +# +$CMP IRS2109 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2109.pdf?fileId=5546d462533600a401535676508f27ab +$ENDCMP +# +$CMP IRS21091 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs21091.pdf?fileId=5546d462533600a401535676573d27ae +$ENDCMP +# +$CMP IRS21094 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2109.pdf?fileId=5546d462533600a401535676508f27ab +$ENDCMP +# +$CMP IRS2110 +D High and Low Side Driver, 500V, 2.0/2.0A, PDIP-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2110.pdf?fileId=5546d462533600a40153567660ff27b0 +$ENDCMP +# +$CMP IRS2110S +D High and Low Side Driver, 500V, 2.0/2.0A, SOIC-16W +K Gate Driver +F https://www.infineon.com/dgdl/irs2110.pdf?fileId=5546d462533600a40153567660ff27b0 +$ENDCMP +# +$CMP IRS2111 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2111pbf.pdf?fileId=5546d462533600a401535676679b27b3 +$ENDCMP +# +$CMP IRS2112 +D High and Low Side Driver, 600V, 290/600mA, PDIP-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2112pbf.pdf?fileId=5546d462533600a401535676702827b5 +$ENDCMP +# +$CMP IRS2112S +D High and Low Side Driver, 500V, 290/600mA, SOIC-16W +K Gate Driver +F https://www.infineon.com/dgdl/irs2112pbf.pdf?fileId=5546d462533600a401535676702827b5 +$ENDCMP +# +$CMP IRS2113 +D High and Low Side Driver, 600V, 2.0/2.0A, PDIP-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2110.pdf?fileId=5546d462533600a40153567660ff27b0 +$ENDCMP +# +$CMP IRS2113M +D High- and Low-Side Driver, 600V, 2.5/2.5A, MLPQ-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2113mpbf.pdf?fileId=5546d462533600a40153567676a227b7 +$ENDCMP +# +$CMP IRS2113S +D High and Low Side Driver, 500V, 2.0/2.0A, SOIC-16W +K Gate Driver +F https://www.infineon.com/dgdl/irs2110.pdf?fileId=5546d462533600a40153567660ff27b0 +$ENDCMP +# +$CMP IRS21531D +D Self-Oscillating Half-Bridge Driver IC, 600V, 180/260mA, PDIP-8/SOIC-8 +K Oscillating Gate Driver +F https://www.infineon.com/dgdl/irs2153d.pdf?fileId=5546d462533600a401535676951e27c3 +$ENDCMP +# +$CMP IRS2153D +D Self-Oscillating Half-Bridge Driver IC, 600V, 180/260mA, PDIP-8/SOIC-8 +K Oscillating Gate Driver +F https://www.infineon.com/dgdl/irs2153d.pdf?fileId=5546d462533600a401535676951e27c3 +$ENDCMP +# +$CMP IRS2181 +D High and Low Side Driver, 600V, 1.4/1.8A, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2181.pdf?fileId=5546d462533600a401535676c12b27d3 +$ENDCMP +# +$CMP IRS21814 +D High and Low Side Driver, 600V, 1.4/1.8A, PDIP-14/SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2181.pdf?fileId=5546d462533600a401535676c12b27d3 +$ENDCMP +# +$CMP IRS21814M +D High- and Low-Side Driver, 600V, 1.9/2.3A, MLPQ-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs21814mpbf.pdf?fileId=5546d462533600a401535676c8a827d6 +$ENDCMP +# +$CMP IRS2183 +D Half-Bridge Driver, 600V, 1.4/1.8A, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2183.pdf?fileId=5546d462533600a401535676d20c27d8 +$ENDCMP +# +$CMP IRS21834 +D Half-Bridge Driver, 600V, 1.4/1.8A, PDIP-14/SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2183.pdf?fileId=5546d462533600a401535676d20c27d8 +$ENDCMP +# +$CMP IRS2184 +D Half-Bridge Driver, 600V, 1.4/1.8A, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2184.pdf?fileId=5546d462533600a401535676d8da27db +$ENDCMP +# +$CMP IRS21844 +D Half-Bridge Driver, 600V, 1.4/1.8A, PDIP-14/SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs2184.pdf?fileId=5546d462533600a401535676d8da27db +$ENDCMP +# +$CMP IRS21844M +D Half-Bridge Driver, 600V, 1.9/2.3A, MLPQ-14 +K Gate Driver +F https://www.infineon.com/dgdl/irs21844mpbf.pdf?fileId=5546d462533600a401535676dfb027de +$ENDCMP +# +$CMP IRS2186 +D High and Low Side Driver, 600V, 4A, PDIP-8/SOIC-8 +K gate driver +F https://www.infineon.com/dgdl/irs2186pbf.pdf?fileId=5546d462533600a40153567716c427ed +$ENDCMP +# +$CMP IRS21864 +D High and Low Side Driver, 600V, 4A, PDIP-14/SOIC-14 +K gate driver +F https://www.infineon.com/dgdl/irs2186pbf.pdf?fileId=5546d462533600a40153567716c427ed +$ENDCMP +# +$CMP IRS21867S +D High and Low Side Driver, 600V, 4.0/4.0A, SOIC-8 +K Gate Driver +F http://www.infineon.com/dgdl/irs21867spbf.pdf?fileId=5546d462533600a4015356770e8327eb +$ENDCMP +# +$CMP IRS2301S +D High and Low Side Driver, 600V, 200/350mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2301pbf.pdf?fileId=5546d462533600a40153567a7ec527fe +$ENDCMP +# +$CMP IRS2302S +D Half-Bridge Driver, 600V, 200/350mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/Infineon-IRS2302-DS-v02_01-EN.pdf?fileId=5546d462533600a40153567a87382800 +$ENDCMP +# +$CMP IRS2304 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2304spbf.pdf?fileId=5546d462533600a40153567a8fe72802 +$ENDCMP +# +$CMP IRS2308 +D Half-Bridge Driver, 600V, 290/600mA, PDIP-8/SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/irs2308.pdf?fileId=5546d462533600a40153567a98ac2804 +$ENDCMP +# +$CMP IRS25606S +D Half-Bridge Driver, 600V, 200/350mA, SOIC-8 +K Gate Driver +F https://www.infineon.com/dgdl/ir25606.pdf?fileId=5546d462533600a4015355ca002316f3 +$ENDCMP +# +$CMP IRS2890DS +D Half-Bridge Driver with Overcurrent Protection, 600V, 220/480mA, SOIC-14 +K Gate Driver +F https://www.infineon.com/dgdl/Infineon-IRS2890DS-DS-v01_00-EN.pdf?fileId=5546d4625a888733015aad6fbc8a4bf4 +$ENDCMP +# +$CMP ITS711L1 +D Smart High-Side Power Switch for Industrial Applications, Four Channels, Rds 200mΩ, SOIC-20W +K driver fet quad +F https://www.infineon.com/dgdl/Infineon-ITS711L1-DS-v01_03-en.pdf?fileId=db3a30432239cccd0122e560bae03c62 +$ENDCMP +# +$CMP ITS716G +D Smart High-Side Power Switch for Industrial Applications, Four Channels, Rds 140mΩ, SOIC-20W +K driver fet quad +F https://www.infineon.com/dgdl/Infineon-ITS716G-DS-v01_01-en.pdf?fileId=db3a304412b407950112b428c2cf3e6d +$ENDCMP +# +$CMP ITS724G +D Smart High-Side Power Switch for Industrial Applications, Four Channels, Rds 90mΩ, SOIC-20W +K driver fet quad +F https://www.infineon.com/dgdl/Infineon-ITS724G-DS-v01_01-en.pdf?fileId=db3a304412b407950112b428d6083e90 +$ENDCMP +# +$CMP IXDN609PI +D 9-Ampere Low-Side +Ultrafast MOSFET Driver +K Gate Driver +F http://www.onsemi.com/pub/Collateral/FAN7842-D.pdf +$ENDCMP +# +$CMP L6491 +D High voltage high and low-side 4 A gate driver, SO-14 +K fet driver +F https://www.st.com/resource/en/datasheet/l6491.pdf +$ENDCMP +# +$CMP LM5109AMA +D Half-Bridge Gate Driver, Output Current 1.0A, 100V, SOIC-8 +K Half-Bridge Gate Driver +F http://www.ti.com/lit/ds/symlink/lm5109a.pdf +$ENDCMP +# +$CMP LM5109ASD +D Half-Bridge Gate Driver, Output Current 1.0A, 100V, WSON-8 +K Half-Bridge Gate Driver +F http://www.ti.com/lit/ds/symlink/lm5109a.pdf +$ENDCMP +# +$CMP LM5109BMA +D Half-Bridge Gate Driver, Output Current 1.0A, 100V, SOIC-8 +K Half-Bridge Gate Driver +F http://www.ti.com/lit/ds/symlink/lm5109b.pdf +$ENDCMP +# +$CMP LM5109BSD +D Half-Bridge Gate Driver, Output Current 1.0A, 100V, WSON-8 +K Half-Bridge Gate Driver +F http://www.ti.com/lit/ds/symlink/lm5109b.pdf +$ENDCMP +# +$CMP LM5109MA +D Half-Bridge Gate Driver, Output Current 1.0A, 100V, SOIC-8 +K Half-Bridge Gate Driver +F http://www.ti.com/lit/ds/symlink/lm5109.pdf +$ENDCMP +# +$CMP LTC4440EMS8 +D High-side, N-Channel, Mosfet driver, 80V input, -40°C to +85°C, MSOP-8 +K high-side mosfet-driver +F https://www.analog.com/media/en/technical-documentation/data-sheets/4440fb.pdf +$ENDCMP +# +$CMP LTC4440ES6 +D High-side, N-Channel, Mosfet driver, 80V input, -40°C to +85°C, SOT23-6 +K high-side mosfet-driver +F https://www.analog.com/media/en/technical-documentation/data-sheets/4440fb.pdf +$ENDCMP +# +$CMP LTC4440IMS8 +D High-side, N-Channel, Mosfet driver, 80V input, -40°C to +125°C, MSOP-8 +K high-side mosfet-driver +F https://www.analog.com/media/en/technical-documentation/data-sheets/4440fb.pdf +$ENDCMP +# +$CMP LTC4440IS6 +D High-side, N-Channel, Mosfet driver, 80V input, -40°C to +85°C, SOT23-6 +K high-side mosfet-driver +F https://www.analog.com/media/en/technical-documentation/data-sheets/4440fb.pdf +$ENDCMP +# +$CMP MAX15012AxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, CMOS Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15012BxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, CMOS Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15012CxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, CMOS Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15012DxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, CMOS Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15013AxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, TTL Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15013BxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, TTL Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15013CxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, TTL Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MAX15013DxSA +D High Frequency Half Bridge Driver, Output Current 2.0A, 175V, TTL Input, SOIC-8 +K Half Bridge Gate Driver +F https://datasheets.maximintegrated.com/en/ds/MAX15012-MAX15013B.pdf +$ENDCMP +# +$CMP MC33152 +D High Speed Dual MOSFET Drivers, 1.5A, -40 to 125C, DIP-8/SOIC-8 +K Driver, Dual MOSFET +F https://www.onsemi.com/pub/Collateral/MC34152-D.PDF +$ENDCMP +# +$CMP MC34152 +D High Speed Dual MOSFET Drivers, 1.5A, 0 to 70C, DIP-8/SOIC-8 +K Driver, Dual MOSFET +F https://www.onsemi.com/pub/Collateral/MC34152-D.PDF +$ENDCMP +# +$CMP MCP1415 +D 1.5A High speed power MOSFET driver with inverting output, SOT-23-5 +K mosfet gate driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20002092F.pdf +$ENDCMP +# +$CMP MCP1415R +D 1.5A High speed power MOSFET driver with inverting output, SOT-23-5 +K mosfet gate driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20002092F.pdf +$ENDCMP +# +$CMP MCP1416 +D 1.5A High speed power MOSFET driver with non-inverting output, SOT-23-5 +K mosfet gate driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20002092F.pdf +$ENDCMP +# +$CMP MCP1416R +D 1.5A High speed power MOSFET driver with non-inverting output, SOT-23-5 +K mosfet gate driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20002092F.pdf +$ENDCMP +# +$CMP MCP14A0303xMNY +D Dual 3A-Peak MOSFET Driver, inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A0303_4_5-Data-Sheet-20006046A.pdf +$ENDCMP +# +$CMP MCP14A0304xMNY +D Dual 3A-Peak MOSFET Driver, non-inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A0303_4_5-Data-Sheet-20006046A.pdf +$ENDCMP +# +$CMP MCP14A0305xMNY +D Dual 3A-Peak MOSFET Driver, inverting/non-inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A0303_4_5-Data-Sheet-20006046A.pdf +$ENDCMP +# +$CMP MCP14A0901xMNY +D Dual 9A-Peak MOSFET Driver, inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A0901_2-Data-Sheet-20006183A.pdf +$ENDCMP +# +$CMP MCP14A0902xMNY +D Dual 9A-Peak MOSFET Driver, non-inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A0901_2-Data-Sheet-20006183A.pdf +$ENDCMP +# +$CMP MCP14A1201xMNY +D Dual 12A-Peak MOSFET Driver, inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A1201-Family-Data-Sheet-DS20006228A.pdf +$ENDCMP +# +$CMP MCP14A1202xMNY +D Dual 12A-Peak MOSFET Driver, non-inverting outputs, DFN-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/MCP14A1201-Family-Data-Sheet-DS20006228A.pdf +$ENDCMP +# +$CMP MIC4426 +D Dual 1.5A-Peak Low-Side MOSFET Driver, DIP-8/SOIC-8/MSOP-8 +K Driver, Dual MOSFET +F http://www.intersil.com/content/dam/Intersil/documents/el72/el7202-12-22.pdf +$ENDCMP +# +$CMP MIC4427 +D Dual 1.5A-Peak Low-Side MOSFET Driver, DIP-8/SOIC-8/MSOP-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/mic4426.pdf +$ENDCMP +# +$CMP MIC4428 +D Dual 1.5A-Peak Low-Side MOSFET Driver, DIP-8/SOIC-8/MSOP-8 +K Driver, Dual MOSFET +F http://ww1.microchip.com/downloads/en/DeviceDoc/mic4426.pdf +$ENDCMP +# +$CMP MIC4604YM +D 85V Half-Bridge MOSFET Driver with up to 16V Programmable Gate Drive, SOIC-8 +K Half-Bridge Gate Driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20005852A.pdf +$ENDCMP +# +$CMP NCD5702 +D High Current IGBT Gate, +4/-6A, SOIC-16 +K igbt gate driver +F https://www.onsemi.com/pub/Collateral/NCD5702-D.PDF +$ENDCMP +# +$CMP NCV8402xST +D Self-Protected Low Side Driver with Temperature and Current Limit, SOT−223 +K MOSFET ESD Overcurrent +F https://www.onsemi.com/pub/Collateral/NCV8402-D.PDF +$ENDCMP +# +$CMP PE29101 +D UltraCMOS High-Speed FET Driver, 40 MHz, Output Current 2.0A/4.0A, 80V, Half Bridge, Low Side Output, CSP-16 +K GaN Gate Driver +F http://www.psemi.com/pdf/datasheets/pe29101ds.pdf +$ENDCMP +# +$CMP PE29102 +D UltraCMOS High-Speed FET Driver, 40 MHz, Output Current 2.0A/4.0A, 80V, Half Bridge, Phase Control, CSP-16 +K GaN Gate Driver +F http://www.psemi.com/pdf/datasheets/pe29102ds.pdf +$ENDCMP +# +$CMP PM8834 +D 4A dual low-side MOSFET driver, SOIC-8 +K mosfet driver +F http://www.st.com/resource/en/datasheet/pm8834.pdf +$ENDCMP +# +$CMP PM8834M +D 4A dual low-side MOSFET driver, MSOP-8 +K mosfet driver +F http://www.st.com/resource/en/datasheet/pm8834.pdf +$ENDCMP +# +$CMP SM72295MA +D Full Bridge Gate Driver with integrated Current Sense Amplifier, 3A, 115V, SOIC-28 +K Full Bridge Gate Driver +F http://www.ti.com/lit/gpn/sm72295 +$ENDCMP +# +$CMP STGAP1AS +D Galvanically isolated 5 A advanced single gate driver, Dual Output, Miller Clamp, Sense, Desaturation, UVLO, OVLO, SPI, AEC-Q100, SOIC-24 +K isolated fet driver +F https://www.st.com/resource/en/datasheet/stgap1as.pdf +$ENDCMP +# +$CMP STGAP2SCM +D Galvanically isolated 4 A single gate driver, Single Output, Miller Clamp, SOIC-8 +K isolated fet driver +F https://www.st.com/resource/en/datasheet/stgap2s.pdf +$ENDCMP +# +$CMP STGAP2SM +D Galvanically isolated 4 A single gate driver, Dual Output, SOIC-8 +K isolated fet driver +F https://www.st.com/resource/en/datasheet/stgap2s.pdf +$ENDCMP +# +$CMP TC4421 +D 9A High-Speed inverting MOSFET Driver +K MOSFET IGBT driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20001420F.pdf +$ENDCMP +# +$CMP TC4422 +D 9A High-Speed non-inverting MOSFET Driver +K MOSFET IGBT driver +F http://ww1.microchip.com/downloads/en/DeviceDoc/20001420F.pdf +$ENDCMP +# +$CMP TLP250 +D Gate Drive Optocoupler, Output Current 1.5/1.5A, DIP-8 +K MOSFET Driver IGBT Driver Optocoupler +F http://toshiba.semicon-storage.com/info/docget.jsp?did=16821&prodName=TLP250 +$ENDCMP +# +$CMP UCC21520ADW +D Isolated Dual-Channel Gate Driver, Output Current 4.0/6.0A, 5.7kV Isolation, 5V UVLO, SOIC-16W +K Dual Isolated Gate Driver +F http://www.ti.com/lit/ds/symlink/ucc21520.pdf +$ENDCMP +# +$CMP UCC21520DW +D Isolated Dual-Channel Gate Driver, Output Current 4.0/6.0A, 5.7kV Isolation, 8V UVLO, SOIC-16W +K Dual Isolated Gate Driver +F http://www.ti.com/lit/ds/symlink/ucc21520.pdf +$ENDCMP +# +$CMP UCC27714D +D High-Speed, 600-V High-Side Low-Side Gate Driver, SOIC-14 +K gate driver bootstrap +F http://www.ti.com/lit/ds/symlink/ucc27714.pdf +$ENDCMP +# +$CMP ZXGD3001E6 +D 9A (peak) Gate driver, 12V, 3ns delay, SOT-23-6 +K gate driver +F http://www.diodes.com/_files/datasheets/ZXGD3001E6.pdf +$ENDCMP +# +$CMP ZXGD3002E6 +D 9A (peak) Gate driver, 20V, 2ns delay, SOT-23-6 +K gate driver +F http://www.diodes.com/_files/datasheets/ZXGD3002E6.pdf +$ENDCMP +# +$CMP ZXGD3003E6 +D 5A (peak) Gate driver, 40V, 2ns delay, SOT-23-6 +K gate driver +F http://www.diodes.com/_files/datasheets/ZXGD3003E6.pdf +$ENDCMP +# +$CMP ZXGD3004E6 +D 8A (peak) Gate driver, 40V, 1ns delay, SOT-23-6 +K gate driver +F http://www.diodes.com/_files/datasheets/ZXGD3004E6.pdf +$ENDCMP +# +$CMP ZXGD3006E6 +D 40V 10A gate driver, SOT-23-6 +K mosfet igbt driver buffer +F https://www.diodes.com/assets/Datasheets/ZXGD3006E6.pdf +$ENDCMP +# +$CMP ZXGD3009E6 +D 2A (peak) Gate driver, 40V, SOT-23-6 +K gate driver +F https://www.diodes.com/assets/Datasheets/ZXGD3009E6.pdf +$ENDCMP +# +#End Doc Library diff --git a/hw/Driver_FET.lib b/hw/Driver_FET.lib new file mode 100644 index 0000000..5465128 --- /dev/null +++ b/hw/Driver_FET.lib @@ -0,0 +1,3026 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# 1EDN7550B +# +DEF 1EDN7550B U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "1EDN7550B" 50 350 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-6" 0 0 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +ALIAS 1EDN8550B +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X IN- 1 -400 -100 100 R 50 50 1 1 I +X GND 2 0 -400 100 U 50 50 1 1 W +X IN+ 3 -400 100 100 R 50 50 1 1 I +X VDD 4 0 400 100 D 50 50 1 1 W +X OUT_SRC 5 400 100 100 L 50 50 1 1 O +X OUT_SNK 6 400 -100 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# ACPL-336J +# +DEF ACPL-336J U 0 20 Y Y 1 F N +F0 "U" -400 650 50 H V R CNN +F1 "ACPL-336J" -200 550 50 H V R CNN +F2 "Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm" 200 -600 50 H I L CNN +F3 "" 250 -200 50 H I C CNN +$FPLIST + SOIC*7.5x10.3*P1.27mm* +$ENDFPLIST +DRAW +S -400 500 400 -500 0 1 10 f +P 2 0 1 0 0 -450 0 -350 N +P 2 0 1 0 0 -250 0 -150 N +P 2 0 1 0 0 -50 0 50 N +P 2 0 1 0 0 150 0 250 N +P 2 0 1 0 0 350 0 450 N +X VEE1 1 -100 -600 100 U 50 50 1 1 W +X VCLAMP 10 500 -200 100 L 50 50 1 1 B +X VOUT 11 500 0 100 L 50 50 1 1 O +X VCC2 12 100 600 100 D 50 50 1 1 W +X VE 13 300 600 100 D 50 50 1 1 W +X DESAT 14 500 100 100 L 50 50 1 1 B +X VLED 15 500 300 100 L 50 50 1 1 O +X VEE2 16 100 -600 100 U 50 50 1 1 W +X VIN+ 2 -500 400 100 R 50 50 1 1 I +X VCC1 3 -100 600 100 D 50 50 1 1 W +X VLEDDRV 4 -500 200 100 R 50 50 1 1 O +X ~UVLO 5 -500 -200 100 R 50 50 1 1 C +X ~FAULT 6 -500 -300 100 R 50 50 1 1 C +X ANODE 7 -500 100 100 R 50 50 1 1 P +X CATHODE 8 -500 0 100 R 50 50 1 1 P +X VEE2 9 100 -600 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# ACPL-P343 +# +DEF ACPL-P343 U 0 20 Y N 1 F N +F0 "U" 0 500 50 H V C CNN +F1 "ACPL-P343" 0 400 50 H V C CNN +F2 "Package_SO:SSO-6_6.8x4.6mm_P1.27mm_Clearance7mm" 0 -400 50 H I C CIN +F3 "" -90 5 50 H I L CNN +$FPLIST + SSO*6.8x4.6mm*P1.27mm*Clearance7mm* +$ENDFPLIST +DRAW +C 200 -300 10 0 1 0 F +C 200 -225 10 0 1 0 F +C 200 -75 10 0 1 0 F +C 200 0 10 0 1 0 F +C 200 75 10 0 1 0 F +C 200 225 10 0 1 0 F +C 200 300 10 0 1 0 F +S -300 350 300 -350 0 1 10 f +S 25 250 25 250 0 1 0 N +S 25 250 25 300 0 1 0 N +P 2 0 1 10 -225 -25 -175 -25 N +P 2 0 1 10 -25 25 -75 25 N +P 2 0 1 0 50 -150 75 -150 N +P 2 0 1 0 50 150 75 150 N +P 2 0 1 0 75 -200 75 -100 N +P 2 0 1 0 75 100 75 200 N +P 2 0 1 20 100 -225 100 -75 N +P 2 0 1 20 100 75 100 225 N +P 2 0 1 0 175 -75 100 -75 N +P 2 0 1 0 175 225 100 225 N +P 2 0 1 0 200 -225 200 -300 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 75 200 -75 N +P 2 0 1 0 200 300 200 225 N +P 2 0 1 10 250 -125 200 -125 N +P 2 0 1 10 250 175 200 175 N +P 2 0 1 0 300 300 25 300 N +P 3 0 1 0 -50 -25 -50 -100 0 -100 N +P 3 0 1 0 -50 25 -50 100 0 100 N +P 3 0 1 0 25 -250 25 -300 300 -300 N +P 3 0 1 0 175 -75 225 -75 225 -125 N +P 3 0 1 0 175 225 225 225 225 175 N +P 3 0 1 0 225 -175 225 -225 100 -225 N +P 3 0 1 0 225 125 225 75 100 75 N +P 4 0 1 0 -300 300 -200 300 -200 -300 -300 -300 N +P 4 0 1 10 -200 -25 -225 25 -175 25 -200 -25 F +P 4 0 1 10 -50 25 -25 -25 -75 -25 -50 25 F +P 4 0 1 0 130 225 175 240 175 210 130 225 F +P 4 0 1 0 175 -225 130 -210 130 -240 175 -225 F +P 4 0 1 10 225 -125 250 -175 200 -175 225 -125 F +P 4 0 1 10 225 175 250 125 200 125 225 175 F +P 5 0 1 0 -150 -20 -100 -20 -115 -25 -115 -15 -100 -20 N +P 5 0 1 0 -150 20 -100 20 -115 15 -115 25 -100 20 N +P 5 0 1 0 50 250 50 -250 0 -250 0 250 50 250 N +X A 1 -400 300 100 R 50 50 1 1 P +X NC 2 -300 0 100 R 50 50 1 1 N N +X C 3 -400 -300 100 R 50 50 1 1 P +X VEE 4 400 -300 100 L 50 50 1 1 W +X VO 5 400 0 100 L 50 50 1 1 O +X VCC 6 400 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# ACPL-W343 +# +DEF ACPL-W343 U 0 20 Y N 1 F N +F0 "U" 0 500 50 H V C CNN +F1 "ACPL-W343" 0 400 50 H V C CNN +F2 "Package_SO:SSO-6_6.8x4.6mm_P1.27mm_Clearance8mm" 0 -400 50 H I C CIN +F3 "" -90 5 50 H I L CNN +$FPLIST + SSO*6.8x4.6mm*P1.27mm*Clearance8mm* +$ENDFPLIST +DRAW +C 200 -300 10 0 1 0 F +C 200 -225 10 0 1 0 F +C 200 -75 10 0 1 0 F +C 200 0 10 0 1 0 F +C 200 75 10 0 1 0 F +C 200 225 10 0 1 0 F +C 200 300 10 0 1 0 F +S -300 350 300 -350 0 1 10 f +S 25 250 25 250 0 1 0 N +S 25 250 25 300 0 1 0 N +P 2 0 1 10 -225 -25 -175 -25 N +P 2 0 1 10 -25 25 -75 25 N +P 2 0 1 0 50 -150 75 -150 N +P 2 0 1 0 50 150 75 150 N +P 2 0 1 0 75 -200 75 -100 N +P 2 0 1 0 75 100 75 200 N +P 2 0 1 20 100 -225 100 -75 N +P 2 0 1 20 100 75 100 225 N +P 2 0 1 0 175 -75 100 -75 N +P 2 0 1 0 175 225 100 225 N +P 2 0 1 0 200 -225 200 -300 N +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 75 200 -75 N +P 2 0 1 0 200 300 200 225 N +P 2 0 1 10 250 -125 200 -125 N +P 2 0 1 10 250 175 200 175 N +P 2 0 1 0 300 300 25 300 N +P 3 0 1 0 -50 -25 -50 -100 0 -100 N +P 3 0 1 0 -50 25 -50 100 0 100 N +P 3 0 1 0 25 -250 25 -300 300 -300 N +P 3 0 1 0 175 -75 225 -75 225 -125 N +P 3 0 1 0 175 225 225 225 225 175 N +P 3 0 1 0 225 -175 225 -225 100 -225 N +P 3 0 1 0 225 125 225 75 100 75 N +P 4 0 1 0 -300 300 -200 300 -200 -300 -300 -300 N +P 4 0 1 10 -200 -25 -225 25 -175 25 -200 -25 F +P 4 0 1 10 -50 25 -25 -25 -75 -25 -50 25 F +P 4 0 1 0 130 225 175 240 175 210 130 225 F +P 4 0 1 0 175 -225 130 -210 130 -240 175 -225 F +P 4 0 1 10 225 -125 250 -175 200 -175 225 -125 F +P 4 0 1 10 225 175 250 125 200 125 225 175 F +P 5 0 1 0 -150 -20 -100 -20 -115 -25 -115 -15 -100 -20 N +P 5 0 1 0 -150 20 -100 20 -115 15 -115 25 -100 20 N +P 5 0 1 0 50 250 50 -250 0 -250 0 250 50 250 N +X A 1 -400 300 100 R 50 50 1 1 P +X NC 2 -300 0 100 R 50 50 1 1 N N +X C 3 -400 -300 100 R 50 50 1 1 P +X VEE 4 400 -300 100 L 50 50 1 1 W +X VO 5 400 0 100 L 50 50 1 1 O +X VCC 6 400 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# AN34092B +# +DEF AN34092B U 0 20 Y Y 1 F N +F0 "U" -350 550 50 H V C CNN +F1 "AN34092B" 250 550 50 H V C CNN +F2 "Package_DFN_QFN:Panasonic_HQFN-16-1EP_4x4mm_P0.65mm_EP2.9x2.9mm" 0 -900 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Panasonic*HQFN*1EP*4x4mm*P0.65mm*EP2.9x2.9mm* +$ENDFPLIST +DRAW +S -400 -500 400 500 0 1 10 f +X OUT1 1 500 400 100 L 50 50 1 1 O +X VREG 10 -500 0 100 R 50 50 1 1 P +X IGCNT 11 -500 -100 100 R 50 50 1 1 P +X VRCNT 12 -500 -200 100 R 50 50 1 1 P +X VR 13 -500 -300 100 R 50 50 1 1 P +X ~FAULT 14 -500 200 100 R 50 50 1 1 C +X CP 15 500 -200 100 L 50 50 1 1 P +X CN 16 500 -400 100 L 50 50 1 1 P +X GND 17 -100 -600 100 U 50 50 1 1 P N +X OUT2 2 500 200 100 L 50 50 1 1 O +X OUT3 3 500 0 100 L 50 50 1 1 O +X VEE 4 0 -600 100 U 50 50 1 1 W +X GND 5 -100 -600 100 U 50 50 1 1 W +X VCC 6 0 600 100 D 50 50 1 1 W +X INP 7 -500 400 100 R 50 50 1 1 I +X INN 8 -500 300 100 R 50 50 1 1 I +X TEST 9 -500 -400 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# BSP75N +# +DEF BSP75N Q 0 0 Y N 1 F N +F0 "Q" 200 350 50 H V R CNN +F1 "BSP75N" -400 350 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-223" -125 -475 50 H I C CNN +F3 "" 300 0 50 H I C CNN +$FPLIST + SOT?223* +$ENDFPLIST +DRAW +C -300 0 11 1 1 0 F +C -25 -230 11 1 1 0 F +C -25 0 11 1 1 0 F +C 100 0 11 1 1 0 F +C 265 0 111 1 1 10 N +C 300 -230 11 1 1 0 F +C 300 -155 11 1 1 0 F +C 300 -70 11 1 1 0 F +C 300 70 11 1 1 0 F +C 300 150 11 1 1 0 F +T 0 -60 -135 21 0 0 0 Limit Normal 0 C C +T 0 -50 -90 21 0 0 0 "Temp & Current" Normal 0 C C +T 0 -130 60 21 0 1 1 dV/dt Normal 0 C C +T 0 -135 15 21 0 1 1 Limit Normal 0 C C +S -400 300 400 -300 0 0 0 f +S -200 -50 100 -180 0 1 0 N +S -200 100 -50 -25 1 1 0 N +P 2 0 0 0 300 100 300 -300 N +P 2 0 0 0 300 100 300 300 N +P 3 0 0 0 -25 -50 -25 -25 -25 0 N +P 3 0 0 0 100 0 100 150 300 150 N +P 3 0 0 0 300 -230 -25 -230 -25 -180 N +P 4 0 0 0 -25 -230 -300 -230 -300 0 -200 0 N +P 2 0 1 0 -300 0 -400 0 N +P 2 0 1 0 300 -155 105 -155 N +P 2 1 1 0 100 0 -50 0 N +P 2 1 1 0 100 0 210 0 N +P 2 1 1 0 230 -70 300 -70 N +P 2 1 1 10 230 -50 230 -90 N +P 2 1 1 0 230 0 300 0 N +P 2 1 1 10 230 20 230 -20 N +P 2 1 1 0 230 70 300 70 N +P 2 1 1 10 230 90 230 50 N +P 2 1 1 0 300 -70 300 -100 N +P 2 1 1 0 300 -70 300 0 N +P 2 1 1 0 300 100 300 70 N +P 3 1 1 10 210 75 210 -75 210 -75 N +P 4 1 1 0 -320 -70 -315 -75 -285 -75 -280 -80 N +P 4 1 1 0 -300 -145 -285 -120 -315 -120 -300 -145 N +P 4 1 1 0 -300 -75 -315 -100 -285 -100 -300 -75 N +P 4 1 1 0 -280 -150 -285 -145 -315 -145 -320 -140 N +P 4 1 1 0 80 120 85 115 115 115 120 110 N +P 4 1 1 0 100 45 115 70 85 70 100 45 N +P 4 1 1 0 100 115 85 90 115 90 100 115 N +P 4 1 1 0 120 40 115 45 85 45 80 50 N +P 4 1 1 0 240 0 280 15 280 -15 240 0 F +P 4 1 1 0 300 -70 330 -70 330 70 300 70 N +P 4 1 1 0 310 20 315 15 345 15 350 10 N +P 4 1 1 0 330 15 315 -10 345 -10 330 15 N +X G 1 -500 0 100 R 50 50 1 1 I +X D 2 300 400 100 D 50 50 1 1 P +X S 3 300 -400 100 U 50 50 1 1 P +X S 4 300 -400 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# EL7202CN +# +DEF EL7202CN U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "EL7202CN" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +ALIAS MC33152 MC34152 +$FPLIST + DIP*W7.62mm* + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# EL7212CN +# +DEF EL7212CN U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "EL7212CN" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*P1.27mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X ~OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# EL7222CN +# +DEF EL7222CN U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "EL7222CN" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*P1.27mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# FAN3268 +# +DEF FAN3268 U 0 20 Y Y 1 F N +F0 "U" -100 550 50 H V R CNN +F1 "FAN3268" -100 450 50 H V R CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 50 -450 50 H I L CNN +F3 "" 0 100 50 H I C CNN +ALIAS FAN3278 +$FPLIST + *SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 400 300 -400 0 1 10 f +X ENA 1 -400 -100 100 R 50 50 1 1 I +X INA 2 -400 200 100 R 50 50 1 1 I +X GND 3 0 -500 100 U 50 50 1 1 W +X INB 4 -400 100 100 R 50 50 1 1 I +X ~OUTB~ 5 400 100 100 L 50 50 1 1 O +X VDD 6 0 500 100 D 50 50 1 1 W +X OUTA 7 400 200 100 L 50 50 1 1 O +X ENB 8 -400 -200 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# FAN7371 +# +DEF FAN7371 U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "FAN7371" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -450 50 H I C CNN +F3 "" 0 -100 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 400 200 -400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X IN 2 -300 -100 100 R 50 50 1 1 I +X NC 3 -200 -200 100 R 50 50 1 1 N N +X GND 4 -300 -300 100 R 50 50 1 1 W +X NC 5 200 -300 100 L 50 50 1 1 N N +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 -100 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# FAN7888 +# +DEF FAN7888 U 0 20 Y Y 1 F N +F0 "U" -100 950 50 H V R CNN +F1 "FAN7888" -100 850 50 H V R CNN +F2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" 50 -750 50 H I L CNN +F3 "" 0 0 50 H I C CNN +ALIAS FAN7388 +$FPLIST + SOIC*7.5x12.8*P1.27mm* +$ENDFPLIST +DRAW +S -300 800 300 -700 0 1 10 f +X HIN1 1 -400 600 100 R 50 50 1 1 I +X VB3 10 400 -300 100 L 50 50 1 1 P +X GND 11 0 -800 100 U 50 50 1 1 W +X VDD 12 0 900 100 D 50 50 1 1 W +X LO2 13 400 -100 100 L 50 50 1 1 O +X VS2 14 400 0 100 L 50 50 1 1 P +X HO2 15 400 100 100 L 50 50 1 1 O +X VB2 16 400 200 100 L 50 50 1 1 P +X LO1 17 400 400 100 L 50 50 1 1 O +X VS1 18 400 500 100 L 50 50 1 1 P +X HO1 19 400 600 100 L 50 50 1 1 O +X LIN1 2 -400 500 100 R 50 50 1 1 I +X VB1 20 400 700 100 L 50 50 1 1 P +X HIN2 3 -400 100 100 R 50 50 1 1 I +X LIN2 4 -400 0 100 R 50 50 1 1 I +X HIN3 5 -400 -400 100 R 50 50 1 1 I +X LIN3 6 -400 -500 100 R 50 50 1 1 I +X LO3 7 400 -600 100 L 50 50 1 1 O +X VS3 8 400 -500 100 L 50 50 1 1 P +X HO3 9 400 -400 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# FL5150MX +# +DEF FL5150MX U 0 20 Y Y 1 F N +F0 "U" 200 -500 50 H V C CNN +F1 "FL5150MX" 300 -600 50 H V C CNN +F2 "Package_SO:SSOP-10_3.9x4.9mm_P1.00mm" 0 -700 50 H I C CNN +F3 "" -100 -100 50 H I C CNN +ALIAS FL5160MX +$FPLIST + SSOP?10?3.9x4.9mm*1.00mm* +$ENDFPLIST +DRAW +S -500 400 500 -400 0 1 10 f +X ZC_Monitor 1 -600 300 100 R 50 50 1 1 I +X OC_Sense1 10 600 300 100 L 50 50 1 1 I +X DIM_Control 2 -600 0 100 R 50 50 1 1 I +X VDD 3 0 500 100 D 50 50 1 1 w +X DIM_Mode 4 -600 -300 100 R 50 50 1 1 I +X GND 5 0 -500 100 U 50 50 1 1 w +X VS 6 600 -300 100 L 50 50 1 1 W +X Low_Power 7 600 -200 100 L 50 50 1 1 I +X OC_Sense2 8 600 100 100 L 50 50 1 1 I +X DRV_Gate 9 600 200 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# HCPL-3120 +# +DEF HCPL-3120 U 0 20 Y N 1 F N +F0 "U" 0 500 50 H V C CNN +F1 "HCPL-3120" 0 400 50 H V C CNN +F2 "Package_DIP:DIP-8_W7.62mm" 0 -400 50 H I C CIN +F3 "" -90 5 50 H I L CNN +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +C 200 -300 10 0 1 0 F +C 200 -225 10 0 1 0 F +C 200 -75 10 0 1 0 F +C 200 0 10 0 1 0 F +C 200 300 10 0 1 0 F +C 270 0 10 0 1 0 F +S -300 350 300 -350 0 1 10 f +S 25 250 25 250 0 1 0 N +S 25 250 25 300 0 1 0 N +P 2 0 1 10 -225 -25 -175 -25 N +P 2 0 1 10 -25 25 -75 25 N +P 2 0 1 0 50 -150 75 -150 N +P 2 0 1 0 75 -200 75 -100 N +P 2 0 1 20 100 -225 100 -75 N +P 2 0 1 0 120 150 50 150 N +P 2 0 1 0 125 175 200 250 N +P 2 0 1 0 175 -75 100 -75 N +P 2 0 1 0 200 -225 200 -300 N +P 2 0 1 0 200 0 270 0 N +P 2 0 1 0 200 50 125 125 F +P 2 0 1 0 200 50 200 -75 N +P 2 0 1 0 200 250 200 300 N +P 2 0 1 10 250 -125 200 -125 N +P 2 0 1 0 300 300 25 300 N +P 3 0 1 0 -50 -25 -50 -100 0 -100 N +P 3 0 1 0 -50 25 -50 100 0 100 N +P 3 0 1 0 25 -250 25 -300 300 -300 N +P 3 0 1 20 125 225 125 75 125 75 N +P 3 0 1 0 175 -75 225 -75 225 -125 N +P 3 0 1 0 225 -175 225 -225 100 -225 N +P 4 0 1 0 -300 300 -200 300 -200 -300 -300 -300 N +P 4 0 1 10 -200 -25 -225 25 -175 25 -200 -25 F +P 4 0 1 10 -50 25 -25 -25 -75 -25 -50 25 F +P 4 0 1 0 175 -225 130 -210 130 -240 175 -225 F +P 4 0 1 10 225 -125 250 -175 200 -175 225 -125 F +P 4 0 1 0 300 100 270 100 270 -100 300 -100 N +P 5 0 1 0 -150 -20 -100 -20 -115 -25 -115 -15 -100 -20 N +P 5 0 1 0 -150 20 -100 20 -115 15 -115 25 -100 20 N +P 5 0 1 0 50 250 50 -250 0 -250 0 250 50 250 N +P 5 0 1 0 145 85 165 105 185 65 145 85 145 85 F +X NC 1 -300 100 100 R 50 50 1 1 N N +X A 2 -400 300 100 R 50 50 1 1 P +X C 3 -400 -300 100 R 50 50 1 1 P +X NC 4 -300 -100 100 R 50 50 1 1 N N +X VEE 5 400 -300 100 L 50 50 1 1 w +X VO 6 400 100 100 L 50 50 1 1 O +X VO 7 400 -100 100 L 50 50 1 1 O +X VCC 8 400 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# HCPL-314J +# +DEF HCPL-314J U 0 20 Y N 2 F N +F0 "U" 0 500 50 H V C CNN +F1 "HCPL-314J" 0 400 50 H V C CNN +F2 "Package_SO:SOIC-16W-12_7.5x10.3mm_P1.27mm" 0 -400 50 H I C CIN +F3 "" -90 5 50 H I L CNN +$FPLIST + SOIC*16*12*7.5x10.3mm*P1.27mm* +$ENDFPLIST +DRAW +C 200 -300 10 0 1 0 F +C 200 0 10 0 1 0 F +C 200 300 10 0 1 0 F +S -300 350 300 -350 0 1 10 f +S 25 250 25 250 0 1 0 N +S 25 250 25 300 0 1 0 N +S 200 50 200 -50 0 1 0 N +P 2 0 1 10 -225 -25 -175 -25 N +P 2 0 1 10 -25 25 -75 25 N +P 2 0 1 0 120 -150 50 -150 N +P 2 0 1 0 120 150 50 150 N +P 2 0 1 0 125 -175 200 -250 N +P 2 0 1 0 125 175 200 250 N +P 2 0 1 0 200 -250 200 -300 N +P 2 0 1 0 200 -50 125 -125 F +P 2 0 1 0 200 0 300 0 N +P 2 0 1 0 200 50 125 125 F +P 2 0 1 0 200 250 200 300 N +P 2 0 1 0 300 300 25 300 N +P 3 0 1 0 -50 -25 -50 -100 0 -100 N +P 3 0 1 0 -50 25 -50 100 0 100 N +P 3 0 1 0 25 -250 25 -300 300 -300 N +P 3 0 1 20 125 -225 125 -75 125 -75 N +P 3 0 1 20 125 225 125 75 125 75 N +P 4 0 1 0 -300 300 -200 300 -200 -300 -300 -300 N +P 4 0 1 10 -200 -25 -225 25 -175 25 -200 -25 F +P 4 0 1 10 -50 25 -25 -25 -75 -25 -50 25 F +P 5 0 1 0 -150 -20 -100 -20 -115 -25 -115 -15 -100 -20 N +P 5 0 1 0 -150 20 -100 20 -115 15 -115 25 -100 20 N +P 5 0 1 0 50 250 50 -250 0 -250 0 250 50 250 N +P 5 0 1 0 145 85 165 105 185 65 145 85 145 85 F +P 5 0 1 0 195 -75 175 -55 155 -95 195 -75 195 -75 F +X NC 1 -300 0 100 R 50 50 1 1 N N +X VEE 14 400 -300 100 L 50 50 1 1 W +X VO 15 400 0 100 L 50 50 1 1 O +X VCC 16 400 300 100 L 50 50 1 1 W +X A 2 -400 300 100 R 50 50 1 1 P +X C 3 -400 -300 100 R 50 50 1 1 P +X VO 10 400 0 100 L 50 50 2 1 O +X VCC 11 400 300 100 L 50 50 2 1 W +X A 6 -400 300 100 R 50 50 2 1 P +X C 7 -400 -300 100 R 50 50 2 1 P +X NC 8 -300 0 100 R 50 50 2 1 N N +X VEE 9 400 -300 100 L 50 50 2 1 W +ENDDRAW +ENDDEF +# +# HIP2100_DFN +# +DEF HIP2100_DFN U 0 20 Y Y 1 F N +F0 "U" 0 525 50 H V C CNN +F1 "HIP2100_DFN" 0 450 50 H V C CNN +F2 "Package_DFN_QFN:DFN-12-1EP_4x4mm_P0.5mm_EP2.66x3.38mm" 0 -700 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS HIP2101_DFN +$FPLIST + DFN*1EP*4x4mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X NC 10 200 100 100 L 50 50 1 1 N N +X VSS 11 -300 -300 100 R 50 50 1 1 W +X LO 12 300 -300 100 L 50 50 1 1 O +X EP 13 0 -500 100 U 50 50 1 1 O +X NC 2 -200 200 100 R 50 50 1 1 N N +X NC 3 -200 100 100 R 50 50 1 1 N N +X HB 4 300 300 100 L 50 50 1 1 P +X HO 5 300 -100 100 L 50 50 1 1 O +X HS 6 300 -200 100 L 50 50 1 1 P +X HI 7 -300 -100 100 R 50 50 1 1 I +X LI 8 -300 -200 100 R 50 50 1 1 I +X NC 9 200 200 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# HIP2100_EPSOIC +# +DEF HIP2100_EPSOIC U 0 20 Y Y 1 F N +F0 "U" 0 525 50 H V C CNN +F1 "HIP2100_EPSOIC" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm" 0 -700 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS HIP2101_EPSOIC +$FPLIST + SOIC*1EP*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X HB 2 300 300 100 L 50 50 1 1 P +X HO 3 300 -100 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X HI 5 -300 -100 100 R 50 50 1 1 I +X LI 6 -300 -200 100 R 50 50 1 1 I +X VSS 7 -300 -300 100 R 50 50 1 1 W +X LO 8 300 -300 100 L 50 50 1 1 O +X EP 9 0 -500 100 U 50 50 1 1 O +ENDDRAW +ENDDEF +# +# HIP2100_QFN +# +DEF HIP2100_QFN U 0 20 Y Y 1 F N +F0 "U" 0 525 50 H V C CNN +F1 "HIP2100_QFN" 0 450 50 H V C CNN +F2 "Package_DFN_QFN:QFN-16-1EP_5x5mm_P0.8mm_EP2.7x2.7mm" 0 -700 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS HIP2101_QFN +$FPLIST + QFN*1EP*5x5mm*P0.8mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X NC 1 -200 200 100 R 50 50 1 1 N N +X LI 10 -300 -200 100 R 50 50 1 1 I +X VSS 11 -300 -300 100 R 50 50 1 1 W +X NC 12 200 100 100 L 50 50 1 1 N N +X NC 13 200 0 100 L 50 50 1 1 N N +X LO 14 300 -300 100 L 50 50 1 1 O +X NC 15 200 -400 100 L 50 50 1 1 N N +X VDD 16 -300 300 100 R 50 50 1 1 W +X EP 17 0 -500 100 U 50 50 1 1 O +X HB 2 300 300 100 L 50 50 1 1 P +X HO 3 300 -100 100 L 50 50 1 1 O +X NC 4 -200 100 100 R 50 50 1 1 N N +X NC 5 -200 0 100 R 50 50 1 1 N N +X HS 6 300 -200 100 L 50 50 1 1 P +X HI 7 -300 -100 100 R 50 50 1 1 I +X NC 8 -200 -400 100 R 50 50 1 1 N N +X NC 9 200 200 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# HIP2100_SOIC +# +DEF HIP2100_SOIC U 0 20 Y Y 1 F N +F0 "U" 0 525 50 H V C CNN +F1 "HIP2100_SOIC" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS HIP2101_SOIC +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X HB 2 300 300 100 L 50 50 1 1 P +X HO 3 300 -100 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X HI 5 -300 -100 100 R 50 50 1 1 I +X LI 6 -300 -200 100 R 50 50 1 1 I +X VSS 7 -300 -300 100 R 50 50 1 1 W +X LO 8 300 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# HIP4080A +# +DEF HIP4080A U 0 20 Y Y 1 F N +F0 "U" 200 850 50 H V L CNN +F1 "HIP4080A" 200 750 50 H V L CNN +F2 "" -50 150 50 H I C CIN +F3 "" -50 -400 50 H I C CNN +$FPLIST + SOIC*7.5x12.8mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -400 -700 400 700 0 1 10 f +X BHB 1 500 600 100 L 50 50 1 1 I +X AHB 10 500 500 100 L 50 50 1 1 I +X AHO 11 500 -600 100 L 50 50 1 1 O +X AHS 12 500 -500 100 L 50 50 1 1 P +X ALO 13 500 -400 100 L 50 50 1 1 O +X ALS 14 500 -300 100 L 50 50 1 1 P +X VCC 15 -100 800 100 D 50 50 1 1 W +X VDD 16 100 800 100 D 50 50 1 1 W +X BLS 17 500 -100 100 L 50 50 1 1 P +X BLO 18 500 0 100 L 50 50 1 1 O +X BHS 19 500 100 100 L 50 50 1 1 P +X HEN 2 -500 600 100 R 50 50 1 1 O +X BHO 20 500 200 100 L 50 50 1 1 O +X DIS 3 -500 500 100 R 50 50 1 1 O +X VSS 4 0 -800 100 U 50 50 1 1 W +X OUT 5 -500 200 100 R 50 50 1 1 O +X IN+ 6 -500 -200 100 R 50 50 1 1 I +X IN- 7 -500 -300 100 R 50 50 1 1 I +X HDEL 8 -500 -500 100 R 50 50 1 1 P +X LDEL 9 -500 -600 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# HIP4081A +# +DEF HIP4081A U 0 20 Y Y 1 F N +F0 "U" 200 850 50 H V L CNN +F1 "HIP4081A" 200 750 50 H V L CNN +F2 "" -50 150 50 H I C CIN +F3 "" -50 -400 50 H I C CNN +$FPLIST + SOIC*7.5x12.8mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -400 -700 400 700 0 1 10 f +X BHB 1 500 600 100 L 50 50 1 1 I +X AHB 10 500 500 100 L 50 50 1 1 I +X AHO 11 500 -600 100 L 50 50 1 1 O +X AHS 12 500 -500 100 L 50 50 1 1 P +X ALO 13 500 -400 100 L 50 50 1 1 O +X ALS 14 500 -300 100 L 50 50 1 1 P +X VCC 15 -100 800 100 D 50 50 1 1 W +X VDD 16 100 800 100 D 50 50 1 1 W +X BLS 17 500 -100 100 L 50 50 1 1 P +X BLO 18 500 0 100 L 50 50 1 1 O +X BHS 19 500 100 100 L 50 50 1 1 P +X BHI 2 -500 0 100 R 50 50 1 1 I +X BHO 20 500 200 100 L 50 50 1 1 O +X DIS 3 -500 600 100 R 50 50 1 1 O +X VSS 4 0 -800 100 U 50 50 1 1 W +X BLI 5 -500 -100 100 R 50 50 1 1 I +X ALI 6 -500 100 100 R 50 50 1 1 I +X AHI 7 -500 200 100 R 50 50 1 1 I +X HDEL 8 -500 -500 100 R 50 50 1 1 P +X LDEL 9 -500 -600 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# HIP4082xB +# +DEF HIP4082xB U 0 20 Y Y 1 F N +F0 "U" 100 650 50 H V L CNN +F1 "HIP4082xB" 100 550 50 H V L CNN +F2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" 100 750 50 H I L CNN +F3 "" 100 750 50 H I C CNN +$FPLIST + SOIC*3.9x9.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -400 -600 400 500 1 1 10 f +X DEL 5 -500 -400 100 R 50 50 0 0 P +X BHB 1 500 400 100 L 50 50 1 1 I +X AHO 10 500 -500 100 L 50 50 1 1 O +X AHS 11 500 -400 100 L 50 50 1 1 P +X VDD 12 0 600 100 D 50 50 1 1 W +X ALO 13 500 -300 100 L 50 50 1 1 O +X BLO 14 500 -100 100 L 50 50 1 1 O +X BHS 15 500 0 100 L 50 50 1 1 P +X BHO 16 500 100 100 L 50 50 1 1 O +X BHI 2 -500 -100 100 R 50 50 1 1 I +X BLI 3 -500 -200 100 R 50 50 1 1 I +X ALI 4 -500 0 100 R 50 50 1 1 I +X VSS 6 0 -700 100 U 50 50 1 1 W +X AHI 7 -500 100 100 R 50 50 1 1 I +X DIS 8 -500 400 100 R 50 50 1 1 I +X AHB 9 500 300 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# HIP4082xP +# +DEF HIP4082xP U 0 20 Y Y 1 F N +F0 "U" 100 650 50 H V L CNN +F1 "HIP4082xP" 100 550 50 H V L CNN +F2 "Package_DIP:DIP-16_W7.62mm" 100 750 50 H I L CNN +F3 "" 100 750 50 H I C CNN +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -400 -600 400 500 1 1 10 f +X DEL 5 -500 -400 100 R 50 50 0 0 P +X BHB 1 500 400 100 L 50 50 1 1 I +X AHO 10 500 -500 100 L 50 50 1 1 O +X AHS 11 500 -400 100 L 50 50 1 1 P +X VDD 12 0 600 100 D 50 50 1 1 W +X ALO 13 500 -300 100 L 50 50 1 1 O +X BLO 14 500 -100 100 L 50 50 1 1 O +X BHS 15 500 0 100 L 50 50 1 1 P +X BHO 16 500 100 100 L 50 50 1 1 O +X BHI 2 -500 -100 100 R 50 50 1 1 I +X BLI 3 -500 -200 100 R 50 50 1 1 I +X ALI 4 -500 0 100 R 50 50 1 1 I +X VSS 6 0 -700 100 U 50 50 1 1 W +X AHI 7 -500 100 100 R 50 50 1 1 I +X DIS 8 -500 400 100 R 50 50 1 1 I +X AHB 9 500 300 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# ICL7667 +# +DEF ICL7667 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "ICL7667" 50 350 50 H V L CNN +F2 "" 150 -850 50 H I L CNN +F3 "" 200 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X INA 2 -400 100 100 R 50 50 1 1 I +X V- 3 0 -400 100 U 50 50 1 1 W +X INB 4 -400 -100 100 R 50 50 1 1 I +X ~OUTB 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUTA 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2010 +# +DEF IR2010 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2010" 50 450 50 H V L CNN +F2 "Package_DIP:DIP-14_W7.62mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2110 IR2112 IR2113 IR2213 IRS2110 IRS2112 IRS2113 +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X LO 1 300 -300 100 L 50 50 1 1 O +X HIN 10 -300 0 100 R 50 50 1 1 I +X SD 11 -300 -200 100 R 50 50 1 1 I +X LIN 12 -300 -100 100 R 50 50 1 1 I +X VSS 13 -100 -500 100 U 50 50 1 1 W +X NC 14 -200 100 100 R 50 50 1 1 N N +X COM 2 0 -500 100 U 50 50 1 1 W +X VCC 3 300 -200 100 L 50 50 1 1 W +X NC 4 -200 300 100 R 50 50 1 1 N N +X VS 5 300 -100 100 L 50 50 1 1 P +X VB 6 300 300 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X NC 8 -200 200 100 R 50 50 1 1 N N +X VDD 9 0 500 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# IR2010S +# +DEF IR2010S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2010S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2110S IR2112S IR2113S IR2213S IR25607S IRS2110S IRS2112S IRS2113S +$FPLIST + SOIC*7.5x10.3mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X LO 1 300 -300 100 L 50 50 1 1 O +X NC 10 200 100 100 L 50 50 1 1 N N +X VDD 11 0 500 100 D 50 50 1 1 W +X HIN 12 -300 0 100 R 50 50 1 1 I +X SD 13 -300 -200 100 R 50 50 1 1 I +X LIN 14 -300 -100 100 R 50 50 1 1 I +X VSS 15 -100 -500 100 U 50 50 1 1 W +X NC 16 200 0 100 L 50 50 1 1 N N +X COM 2 0 -500 100 U 50 50 1 1 W +X VCC 3 300 -200 100 L 50 50 1 1 W +X NC 4 -200 300 100 R 50 50 1 1 N N +X NC 5 -200 200 100 R 50 50 1 1 N N +X VS 6 300 -100 100 L 50 50 1 1 P +X VB 7 300 300 100 L 50 50 1 1 P +X HO 8 300 200 100 L 50 50 1 1 O +X NC 9 -200 100 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2011 +# +DEF IR2011 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2011" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2011 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X VB 2 300 300 100 L 50 50 1 1 P +X HO 3 300 200 100 L 50 50 1 1 O +X VS 4 300 -200 100 L 50 50 1 1 P +X HIN 5 -300 0 100 R 50 50 1 1 I +X LIN 6 -300 -100 100 R 50 50 1 1 I +X COM 7 0 -500 100 U 50 50 1 1 W +X LO 8 300 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IR2085S +# +DEF IR2085S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2085S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X CS 1 -300 -200 100 R 50 50 1 1 I +X OSC 2 -300 0 100 R 50 50 1 1 P +X GND 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X VCC 5 0 500 100 D 50 50 1 1 W +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2101 +# +DEF IR2101 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2101" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2106 IR2301 IR2308 IRS2001 IRS2101 IRS2106 IRS2308 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X HIN 2 -300 0 100 R 50 50 1 1 I +X LIN 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2102 +# +DEF IR2102 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2102" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X ~HIN 2 -300 0 100 R 50 50 1 1 I +X ~LIN 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2103 +# +DEF IR2103 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2103" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2108 IRS2003 IRS2103 IRS2108 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X HIN 2 -300 0 100 R 50 50 1 1 I +X ~LIN 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2104 +# +DEF IR2104 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2104" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2109 IRS2004 IRS2104 IRS2109 IR2302 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X ~SD 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR21064 +# +DEF IR21064 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR21064" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21064 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X NC 10 200 100 100 L 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 0 100 L 50 50 1 1 N N +X HIN 2 -300 0 100 R 50 50 1 1 I +X LIN 3 -300 -100 100 R 50 50 1 1 I +X NC 4 -200 300 100 R 50 50 1 1 N N +X VSS 5 -100 -500 100 U 50 50 1 1 W +X COM 6 0 -500 100 U 50 50 1 1 W +X LO 7 300 -300 100 L 50 50 1 1 O +X NC 8 -200 200 100 R 50 50 1 1 N N +X NC 9 -200 100 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR21084 +# +DEF IR21084 U 0 20 Y Y 1 F N +F0 "U" 50 550 50 H V L CNN +F1 "IR21084" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21084 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X NC 10 -200 100 100 R 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 100 100 L 50 50 1 1 N N +X HIN 2 -300 0 100 R 50 50 1 1 I +X ~LIN 3 -300 -100 100 R 50 50 1 1 I +X DT 4 -300 -200 100 R 50 50 1 1 I +X VSS 5 -100 -500 100 U 50 50 1 1 W +X COM 6 0 -500 100 U 50 50 1 1 W +X LO 7 300 -300 100 L 50 50 1 1 O +X NC 8 -200 300 100 R 50 50 1 1 N N +X NC 9 -200 200 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR21091 +# +DEF IR21091 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR21091" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21091 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X DT/SD 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR21094 +# +DEF IR21094 U 0 20 Y Y 1 F N +F0 "U" 50 550 50 H V L CNN +F1 "IR21094" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21094 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X NC 10 -200 100 100 R 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 100 100 L 50 50 1 1 N N +X IN 2 -300 0 100 R 50 50 1 1 I +X ~SD 3 -300 -100 100 R 50 50 1 1 I +X DT 4 -300 -200 100 R 50 50 1 1 I +X VSS 5 -100 -500 100 U 50 50 1 1 W +X COM 6 0 -500 100 U 50 50 1 1 W +X LO 7 300 -300 100 L 50 50 1 1 O +X NC 8 -200 300 100 R 50 50 1 1 N N +X NC 9 -200 200 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2111 +# +DEF IR2111 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2111" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2111 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X COM 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X NC 5 -200 300 100 R 50 50 1 1 N N +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2114S +# +DEF IR2114S U 0 20 Y Y 1 F N +F0 "U" 50 725 50 H V L CNN +F1 "IR2114S" 50 650 50 H V L CNN +F2 "Package_SO:SSOP-24_5.3x8.2mm_P0.65mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR2214S +$FPLIST + SSOP*5.3x8.2mm*P0.65mm* +$ENDFPLIST +DRAW +S -300 -600 300 600 0 1 10 f +X HIN 1 -400 200 100 R 50 50 1 1 I +X LOP 10 400 -300 100 L 50 50 1 1 O +X VCC 11 0 700 100 D 50 50 1 1 W +X DSL 12 400 -200 100 L 50 50 1 1 I +X NC 13 -300 500 100 R 50 50 1 1 N N +X NC 14 -300 400 100 R 50 50 1 1 N N +X NC 15 -300 300 100 R 50 50 1 1 N N +X NC 16 -300 -300 100 R 50 50 1 1 N N +X NC 17 -300 -400 100 R 50 50 1 1 N N +X SSDH 18 400 100 100 L 50 50 1 1 I +X VS 19 400 -100 100 L 50 50 1 1 P +X LIN 2 -400 100 100 R 50 50 1 1 I +X HON 20 400 200 100 L 50 50 1 1 O +X HOP 21 400 300 100 L 50 50 1 1 O +X NC 22 -300 -500 100 R 50 50 1 1 N N +X VB 23 400 500 100 L 50 50 1 1 P +X DSH 24 400 400 100 L 50 50 1 1 I +X FLT_CLR 3 -400 0 100 R 50 50 1 1 I +X ~SY_FLT 4 -400 -100 100 R 50 50 1 1 B +X ~FAULT/SD 5 -400 -200 100 R 50 50 1 1 B +X VSS 6 -100 -700 100 U 50 50 1 1 W +X SSDL 7 400 -500 100 L 50 50 1 1 I +X COM 8 0 -700 100 U 50 50 1 1 W +X LON 9 400 -400 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IR2133 +# +DEF IR2133 U 0 20 Y Y 1 F N +F0 "U" -300 900 50 H V C CNN +F1 "IR2133" 300 900 50 H V C CNN +F2 "Package_DIP:DIP-28_W15.24mm" 0 -1300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS IR2135 IR2233 IR2235 +$FPLIST + DIP*W15.24mm* +$ENDFPLIST +DRAW +S -300 -800 300 800 0 1 10 f +X ITRIP 1 -400 -400 100 R 50 50 1 1 I +X LO2 10 400 -500 100 L 50 50 1 1 O +X LO1 11 400 -400 100 L 50 50 1 1 O +X VS3 12 400 -200 100 L 50 50 1 1 P +X HO3 13 400 -100 100 L 50 50 1 1 O +X VB3 14 400 0 100 L 50 50 1 1 P +X VS2 15 400 100 100 L 50 50 1 1 P +X HO2 16 400 200 100 L 50 50 1 1 O +X VB2 17 400 300 100 L 50 50 1 1 P +X VS1 18 400 400 100 L 50 50 1 1 P +X HO1 19 400 500 100 L 50 50 1 1 O +X ~FLT-CLR 2 -400 -100 100 R 50 50 1 1 I +X VB1 20 400 600 100 L 50 50 1 1 P +X VCC 21 0 900 100 D 50 50 1 1 W +X ~HIN1 22 -400 700 100 R 50 50 1 1 I +X ~HIN2 23 -400 600 100 R 50 50 1 1 I +X ~HIN3 24 -400 500 100 R 50 50 1 1 I +X ~LIN1 25 -400 400 100 R 50 50 1 1 I +X ~LIN2 26 -400 300 100 R 50 50 1 1 I +X ~LIN3 27 -400 200 100 R 50 50 1 1 I +X ~FALUT 28 -400 0 100 R 50 50 1 1 O +X CAO 3 -400 -500 100 R 50 50 1 1 O +X CA- 4 -400 -700 100 R 50 50 1 1 I +X CA+ 5 -400 -600 100 R 50 50 1 1 I +X SD 6 -400 -200 100 R 50 50 1 1 I +X VSS 7 0 -900 100 U 50 50 1 1 W +X COM 8 400 -700 100 L 50 50 1 1 P +X LO3 9 400 -600 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IR2133S +# +DEF IR2133S U 0 20 Y Y 1 F N +F0 "U" -300 900 50 H V C CNN +F1 "IR2133S" 300 900 50 H V C CNN +F2 "Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm" 0 -1500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS IR2135S IR2233S IR2235S +$FPLIST + SOIC*7.5x17.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -800 300 800 1 1 10 f +X ITRIP 1 -400 -400 100 R 50 50 1 1 I +X LO2 10 400 -500 100 L 50 50 1 1 O +X LO1 11 400 -400 100 L 50 50 1 1 O +X VS3 12 400 -200 100 L 50 50 1 1 P +X HO3 13 400 -100 100 L 50 50 1 1 O +X VB3 14 400 0 100 L 50 50 1 1 P +X VS2 15 400 100 100 L 50 50 1 1 P +X HO2 16 400 200 100 L 50 50 1 1 O +X VB2 17 400 300 100 L 50 50 1 1 P +X VS1 18 400 400 100 L 50 50 1 1 P +X HO1 19 400 500 100 L 50 50 1 1 O +X ~FLT-CLR 2 -400 -100 100 R 50 50 1 1 I +X VB1 20 400 600 100 L 50 50 1 1 P +X VCC 21 0 900 100 D 50 50 1 1 W +X ~HIN1 22 -400 700 100 R 50 50 1 1 I +X ~HIN2 23 -400 600 100 R 50 50 1 1 I +X ~HIN3 24 -400 500 100 R 50 50 1 1 I +X ~LIN1 25 -400 400 100 R 50 50 1 1 I +X ~LIN2 26 -400 300 100 R 50 50 1 1 I +X ~LIN3 27 -400 200 100 R 50 50 1 1 I +X ~FALUT 28 -400 0 100 R 50 50 1 1 O +X CAO 3 -400 -500 100 R 50 50 1 1 O +X CA- 4 -400 -700 100 R 50 50 1 1 I +X CA+ 5 -400 -600 100 R 50 50 1 1 I +X SD 6 -400 -200 100 R 50 50 1 1 I +X VSS 7 0 -900 100 U 50 50 1 1 W +X COM 8 400 -700 100 L 50 50 1 1 P +X LO3 9 400 -600 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IR2153 +# +DEF IR2153 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2153" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR21531 IR2155 IRS2153D IRS21531D +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X RT 2 -300 0 100 R 50 50 1 1 P +X CT 3 -300 -200 100 R 50 50 1 1 P +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR2181 +# +DEF IR2181 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2181" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2181 IRS2186 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X HIN 1 -300 0 100 R 50 50 1 1 I +X LIN 2 -300 -100 100 R 50 50 1 1 I +X COM 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X VCC 5 0 500 100 D 50 50 1 1 W +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR21814 +# +DEF IR21814 U 0 20 Y Y 1 F N +F0 "U" 50 550 50 H V L CNN +F1 "IR21814" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21814 IRS21864 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X HIN 1 -300 0 100 R 50 50 1 1 I +X NC 10 200 100 100 L 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 0 100 L 50 50 1 1 N N +X LIN 2 -300 -100 100 R 50 50 1 1 I +X VSS 3 -100 -500 100 U 50 50 1 1 W +X NC 4 -200 300 100 R 50 50 1 1 N N +X COM 5 0 -500 100 U 50 50 1 1 W +X LO 6 300 -300 100 L 50 50 1 1 O +X VCC 7 0 500 100 D 50 50 1 1 W +X NC 8 -200 200 100 R 50 50 1 1 N N +X NC 9 -200 100 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2183 +# +DEF IR2183 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2183" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2183 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X HIN 1 -300 0 100 R 50 50 1 1 I +X ~LIN 2 -300 -100 100 R 50 50 1 1 I +X COM 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X VCC 5 0 500 100 D 50 50 1 1 W +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR21834 +# +DEF IR21834 U 0 20 Y Y 1 F N +F0 "U" 50 550 50 H V L CNN +F1 "IR21834" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21834 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X HIN 1 -300 0 100 R 50 50 1 1 I +X NC 10 -200 100 100 R 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 100 100 L 50 50 1 1 N N +X ~LIN 2 -300 -100 100 R 50 50 1 1 I +X VSS 3 -100 -500 100 U 50 50 1 1 W +X DT 4 -300 -200 100 R 50 50 1 1 I +X COM 5 0 -500 100 U 50 50 1 1 W +X LO 6 300 -300 100 L 50 50 1 1 O +X VCC 7 0 500 100 D 50 50 1 1 W +X NC 8 -200 300 100 R 50 50 1 1 N N +X NC 9 -200 200 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2184 +# +DEF IR2184 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2184" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2184 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X IN 1 -300 0 100 R 50 50 1 1 I +X ~SD 2 -300 -100 100 R 50 50 1 1 I +X COM 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X VCC 5 0 500 100 D 50 50 1 1 W +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR21844 +# +DEF IR21844 U 0 20 Y Y 1 F N +F0 "U" 50 550 50 H V L CNN +F1 "IR21844" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS21844 +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X IN 1 -300 0 100 R 50 50 1 1 I +X NC 10 -200 100 100 R 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 100 100 L 50 50 1 1 N N +X ~SD 2 -300 -100 100 R 50 50 1 1 I +X VSS 3 -100 -500 100 U 50 50 1 1 W +X DT 4 -300 -200 100 R 50 50 1 1 I +X COM 5 0 -500 100 U 50 50 1 1 W +X LO 6 300 -300 100 L 50 50 1 1 O +X VCC 7 0 500 100 D 50 50 1 1 W +X NC 8 -200 300 100 R 50 50 1 1 N N +X NC 9 -200 200 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IR2304 +# +DEF IR2304 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR2304" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2304 +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X LIN 1 -300 -100 100 R 50 50 1 1 I +X HIN 2 -300 0 100 R 50 50 1 1 I +X VCC 3 0 500 100 D 50 50 1 1 W +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR25602S +# +DEF IR25602S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR25602S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2008S IRS2302S +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X ~SD 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR25603 +# +DEF IR25603 U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR25603" 50 450 50 H V L CNN +F2 "" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X RT 2 -300 0 100 R 50 50 1 1 P +X CT 3 -300 -200 100 R 50 50 1 1 P +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR25604S +# +DEF IR25604S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR25604S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IR7106S IRS2005S IRS21867S IRS2301S IRS25606S +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X HIN 2 -300 0 100 R 50 50 1 1 I +X LIN 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR7184S +# +DEF IR7184S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR7184S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X IN 1 -300 0 100 R 50 50 1 1 I +X ~SD 2 -300 -100 100 R 50 50 1 1 I +X COM 3 0 -500 100 U 50 50 1 1 W +X LO 4 300 -300 100 L 50 50 1 1 O +X VCC 5 0 500 100 D 50 50 1 1 W +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IR7304S +# +DEF IR7304S U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IR7304S" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X LIN 1 -300 -100 100 R 50 50 1 1 I +X HIN 2 -300 0 100 R 50 50 1 1 I +X VCC 3 0 500 100 D 50 50 1 1 W +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X VS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 200 100 L 50 50 1 1 O +X VB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# IRS2001M +# +DEF IRS2001M U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IRS2001M" 50 450 50 H V L CNN +F2 "Package_DFN_QFN:Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS IRS2005M +$FPLIST + Infineon*MLPQ*EP*4x4mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X NC 1 -200 300 100 R 50 50 1 1 N N +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 -100 100 L 50 50 1 1 N N +X VCC 16 0 500 100 D 50 50 1 1 W +X COM 17 0 -500 100 U 50 50 1 1 P N +X HIN 2 -300 0 100 R 50 50 1 1 I +X LIN 3 -300 -100 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X NC 5 -200 200 100 R 50 50 1 1 N N +X NC 6 -200 100 100 R 50 50 1 1 N N +X LO 7 300 -300 100 L 50 50 1 1 O +X NC 8 200 100 100 L 50 50 1 1 N N +X NC 9 200 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IRS2113M +# +DEF IRS2113M U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IRS2113M" 50 450 50 H V L CNN +F2 "Package_DFN_QFN:Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + Infineon*MLPQ*EP*4x4mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X NC 11 -200 200 100 R 50 50 1 1 N N +X VS 12 300 -100 100 L 50 50 1 1 P +X VB 13 300 300 100 L 50 50 1 1 P +X HO 14 300 200 100 L 50 50 1 1 O +X NC 16 -200 100 100 R 50 50 1 1 N N +X COM 17 0 -500 100 U 50 50 1 1 P N +X HIN 2 -300 0 100 R 50 50 1 1 I +X SD 3 -300 -200 100 R 50 50 1 1 I +X LIN 4 -300 -100 100 R 50 50 1 1 I +X VSS 5 -100 -500 100 U 50 50 1 1 W +X LO 6 300 -300 100 L 50 50 1 1 O +X COM 7 0 -500 100 U 50 50 1 1 W +X NC 8 -200 300 100 R 50 50 1 1 N N +X VCC 9 300 -200 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# IRS21814M +# +DEF IRS21814M U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IRS21814M" 50 450 50 H V L CNN +F2 "Package_DFN_QFN:Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + Infineon*MLPQ*EP*4x4mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X LIN 1 -300 -100 100 R 50 50 1 1 I +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 0 100 L 50 50 1 1 N N +X HIN 16 -300 0 100 R 50 50 1 1 I +X COM 17 0 -500 100 U 50 50 1 1 P N +X VSS 2 -100 -500 100 U 50 50 1 1 W +X NC 3 -200 300 100 R 50 50 1 1 N N +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X NC 6 -200 200 100 R 50 50 1 1 N N +X VCC 7 0 500 100 D 50 50 1 1 W +X NC 8 -200 100 100 R 50 50 1 1 N N +X NC 9 200 100 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IRS21844M +# +DEF IRS21844M U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IRS21844M" 50 450 50 H V L CNN +F2 "Package_DFN_QFN:Infineon_MLPQ-16-14-1EP_4x4mm_P0.5mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + Infineon*MLPQ*EP*4x4mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X ~SD 1 -300 -100 100 R 50 50 1 1 I +X VS 11 300 -200 100 L 50 50 1 1 P +X HO 12 300 200 100 L 50 50 1 1 O +X VB 13 300 300 100 L 50 50 1 1 P +X NC 14 200 100 100 L 50 50 1 1 N N +X IN 16 -300 0 100 R 50 50 1 1 I +X COM 17 0 -500 100 U 50 50 1 1 P N +X VSS 2 -100 -500 100 U 50 50 1 1 W +X DT 3 -300 -200 100 R 50 50 1 1 I +X COM 4 0 -500 100 U 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X NC 6 -200 300 100 R 50 50 1 1 N N +X VCC 7 0 500 100 D 50 50 1 1 W +X NC 8 -200 200 100 R 50 50 1 1 N N +X NC 9 -200 100 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# IRS2890DS +# +DEF IRS2890DS U 0 20 Y Y 1 F N +F0 "U" 50 525 50 H V L CNN +F1 "IRS2890DS" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 0 50 H I C CIN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VCC 1 0 500 100 D 50 50 1 1 W +X NC 10 200 100 100 L 50 50 1 1 N N +X NC 11 200 0 100 L 50 50 1 1 N N +X VS 12 300 -200 100 L 50 50 1 1 P +X HO 13 300 200 100 L 50 50 1 1 O +X VB 14 300 300 100 L 50 50 1 1 P +X HIN 2 -300 0 100 R 50 50 1 1 I +X LIN 3 -300 -100 100 R 50 50 1 1 I +X ITRIP 4 0 -500 100 U 50 50 1 1 P +X NC 5 -200 300 100 R 50 50 1 1 N N +X COM 6 -100 -500 100 U 50 50 1 1 W +X RFE 7 -300 100 100 R 50 50 1 1 C +X NC 8 -200 200 100 R 50 50 1 1 N N +X LO 9 300 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# ITS724G +# +DEF ITS724G U 0 20 Y Y 1 F N +F0 "U" -200 450 50 H V C CNN +F1 "ITS724G" 250 450 50 H V C CNN +F2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" 0 -400 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS ITS716G ITS711L1 +$FPLIST + SOIC*7.5x12.8mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 400 300 -400 0 1 10 f +X VBB 1 0 500 100 D 50 50 1 1 W +X VBB 10 0 500 100 D 50 50 1 1 P N +X VBB 11 0 500 100 D 50 50 1 1 P N +X VBB 12 0 500 100 D 50 50 1 1 P N +X OUT4 13 400 -300 100 L 50 50 1 1 E +X OUT3 14 400 -100 100 L 50 50 1 1 E +X VBB 15 0 500 100 D 50 50 1 1 P N +X VBB 16 0 500 100 D 50 50 1 1 P N +X OUT2 17 400 100 100 L 50 50 1 1 E +X OUT1 18 400 300 100 L 50 50 1 1 E +X VBB 19 0 500 100 D 50 50 1 1 P N +X GND1/2 2 -100 -500 100 U 50 50 1 1 W +X VBB 20 0 500 100 D 50 50 1 1 P N +X IN1 3 -400 0 100 R 50 50 1 1 I +X ST1/2 4 -400 300 100 R 50 50 1 1 C +X IN2 5 -400 -100 100 R 50 50 1 1 I +X GND3/4 6 0 -500 100 U 50 50 1 1 W +X IN3 7 -400 -200 100 R 50 50 1 1 I +X ST3/4 8 -400 200 100 R 50 50 1 1 C +X IN4 9 -400 -300 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IXDN609PI +# +DEF IXDN609PI U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "IXDN609PI" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 400 200 -400 0 1 10 f +X VCC 1 -300 300 100 R 50 50 1 1 W +X IN 2 -300 100 100 R 50 50 1 1 I +X NC 3 -300 -100 100 R 50 50 1 1 N +X GND 4 -300 -300 100 R 50 50 1 1 W +X GND 5 300 -300 100 L 50 50 1 1 W +X OUT 6 300 -100 100 L 50 50 1 1 O +X OUT 7 300 100 100 L 50 50 1 1 O +X VCC 8 300 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# L6491 +# +DEF L6491 U 0 20 Y Y 1 F N +F0 "U" -300 600 50 H V C CNN +F1 "L6491" 300 600 50 H V C CNN +F2 "Package_SO:SO-14_3.9x8.65mm_P1.27mm" 0 -900 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SO*3.9x8.65mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -500 300 500 0 1 10 f +X ~LIN 1 -400 100 100 R 50 50 1 1 I +X CP+ 10 400 -300 100 L 50 50 1 1 I +X NC 11 300 -200 100 L 50 50 1 1 N N +X OUT 12 400 0 100 L 50 50 1 1 I +X HVG 13 400 100 100 L 50 50 1 1 O +X BOOT 14 400 300 100 L 50 50 1 1 P +X ~SD~/OD 2 -400 -100 100 R 50 50 1 1 I +X HIN 3 -400 200 100 R 50 50 1 1 I +X VCC 4 -100 600 100 D 50 50 1 1 W +X DT 5 -400 -200 100 R 50 50 1 1 I +X SGND 6 -100 -600 100 U 50 50 1 1 W +X PGND 7 0 -600 100 U 50 50 1 1 W +X LVG 8 400 -100 100 L 50 50 1 1 O +X CP- 9 400 -400 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LM5109ASD +# +DEF LM5109ASD U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "LM5109ASD" 0 450 50 H V C CNN +F2 "Package_SON:WSON-8_4x4mm_P0.8mm" 0 -600 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS LM5109BSD +$FPLIST + WSON*4x4mm*P0.8mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X HI 2 -300 -100 100 R 50 50 1 1 I +X LI 3 -300 -200 100 R 50 50 1 1 I +X VSS 4 -300 -300 100 R 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X HS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 -100 100 L 50 50 1 1 O +X HB 8 300 300 100 L 50 50 1 1 P +X VSS 9 -300 -300 100 R 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# LM5109MA +# +DEF LM5109MA U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "LM5109MA" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN +F3 "" 0 0 50 H I C CNN +ALIAS LM5109AMA LM5109BMA +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 -300 300 100 R 50 50 1 1 W +X HI 2 -300 -100 100 R 50 50 1 1 I +X LI 3 -300 -200 100 R 50 50 1 1 I +X VSS 4 -300 -300 100 R 50 50 1 1 W +X LO 5 300 -300 100 L 50 50 1 1 O +X HS 6 300 -200 100 L 50 50 1 1 P +X HO 7 300 -100 100 L 50 50 1 1 O +X HB 8 300 300 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LTC4440EMS8 +# +DEF LTC4440EMS8 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "LTC4440EMS8" -50 350 50 H V L CNN +F2 "Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.68x1.88mm" 0 -600 50 H I C CNN +F3 "" -100 450 50 H I C CNN +ALIAS LTC4440IMS8 +$FPLIST + MSOP*1EP*3x3mm*P0.65mm* +$ENDFPLIST +DRAW +S -300 300 300 -200 0 1 10 f +X INP 1 -400 0 100 R 50 50 1 1 I +X GND 2 -100 -300 100 U 50 50 1 1 W +X VCC 3 -100 400 100 D 50 50 1 1 W +X GND 4 0 -300 100 U 50 50 1 1 W +X NC 5 -200 -200 100 U 50 50 1 1 N N +X BOOST 6 400 200 100 L 50 50 1 1 I +X TG 7 400 0 100 L 50 50 1 1 O +X TS 8 400 -100 100 L 50 50 1 1 I +X PAD 9 100 -300 100 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LTC4440ES6 +# +DEF LTC4440ES6 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "LTC4440ES6" -50 350 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-6" 0 -400 50 H I C CNN +F3 "" -100 450 50 H I C CNN +ALIAS LTC4440IS6 +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -300 300 300 -200 0 1 10 f +X VCC 1 -100 400 100 D 50 50 1 1 W +X GND 2 0 -300 100 U 50 50 1 1 W +X INP 3 -400 0 100 R 50 50 1 1 I +X TS 4 400 -100 100 L 50 50 1 1 I +X TG 5 400 0 100 L 50 50 1 1 O +X BOOST 6 400 200 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# MAX15012AxSA +# +DEF MAX15012AxSA U 0 20 Y Y 1 F N +F0 "U" 100 525 50 H V C CNN +F1 "MAX15012AxSA" 300 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS MAX15013AxSA +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X BST 2 300 300 100 L 50 50 1 1 W +X DH 3 300 200 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X IN_H 5 -300 0 100 R 50 50 1 1 I +X IN_L 6 -300 -100 100 R 50 50 1 1 I +X GND 7 0 -500 100 U 50 50 1 1 W +X DL 8 300 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MAX15012BxSA +# +DEF MAX15012BxSA U 0 20 Y Y 1 F N +F0 "U" 100 525 50 H V C CNN +F1 "MAX15012BxSA" 300 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS MAX15013BxSA +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X BST 2 300 300 100 L 50 50 1 1 W +X DH 3 300 200 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X IN_H 5 -300 0 100 R 50 50 1 1 I +X ~IN_L 6 -300 -100 100 R 50 50 1 1 I +X GND 7 0 -500 100 U 50 50 1 1 W +X DL 8 300 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MAX15012CxSA +# +DEF MAX15012CxSA U 0 20 Y Y 1 F N +F0 "U" 100 525 50 H V C CNN +F1 "MAX15012CxSA" 300 450 50 H V C CNN +F2 "Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm" 0 -700 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS MAX15013CxSA +$FPLIST + SOIC*1EP*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X BST 2 300 300 100 L 50 50 1 1 W +X DH 3 300 200 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X IN_H 5 -300 0 100 R 50 50 1 1 I +X IN_L 6 -300 -100 100 R 50 50 1 1 I +X GND 7 0 -500 100 U 50 50 1 1 W +X DL 8 300 -300 100 L 50 50 1 1 O +X EP 9 -100 -500 100 U 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MAX15012DxSA +# +DEF MAX15012DxSA U 0 20 Y Y 1 F N +F0 "U" 100 525 50 H V C CNN +F1 "MAX15012DxSA" 300 450 50 H V C CNN +F2 "Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.514x3.2mm" 0 -700 50 H I C CIN +F3 "" 0 -550 50 H I C CNN +ALIAS MAX15013DxSA +$FPLIST + SOIC*1EP*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 -400 200 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X BST 2 300 300 100 L 50 50 1 1 W +X DH 3 300 200 100 L 50 50 1 1 O +X HS 4 300 -200 100 L 50 50 1 1 P +X IN_H 5 -300 0 100 R 50 50 1 1 I +X ~IN_L 6 -300 -100 100 R 50 50 1 1 I +X GND 7 0 -500 100 U 50 50 1 1 W +X DL 8 300 -300 100 L 50 50 1 1 O +X EP 9 -100 -500 100 U 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MCP1415 +# +DEF MCP1415 U 0 20 Y Y 1 F N +F0 "U" -200 250 50 H V L CNN +F1 "MCP1415" 50 250 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-5" 0 -600 50 H I C CIN +F3 "" -200 250 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -200 200 300 -200 0 1 10 f +X NC 1 300 -100 100 L 50 50 1 1 N N +X Vdd 2 0 300 100 D 50 50 1 1 W +X IN 3 -300 0 100 R 50 50 1 1 I +X GND 4 0 -300 100 U 50 50 1 1 W +X ~OUT 5 400 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MCP1415R +# +DEF MCP1415R U 0 20 Y Y 1 F N +F0 "U" -200 250 50 H V L CNN +F1 "MCP1415R" 50 250 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-5" 0 -600 50 H I C CIN +F3 "" -200 250 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -200 200 300 -200 0 1 10 f +X NC 1 300 -100 100 L 50 50 1 1 N N +X GND 2 0 -300 100 U 50 50 1 1 W +X IN 3 -300 0 100 R 50 50 1 1 I +X ~OUT 4 400 0 100 L 50 50 1 1 O +X Vdd 5 0 300 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# MCP1416 +# +DEF MCP1416 U 0 20 Y Y 1 F N +F0 "U" -200 250 50 H V L CNN +F1 "MCP1416" 50 250 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-5" 0 -400 50 H I C CIN +F3 "" -200 250 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -200 200 300 -200 0 1 10 f +X NC 1 300 -100 100 L 50 50 1 1 N N +X Vdd 2 0 300 100 D 50 50 1 1 W +X IN 3 -300 0 100 R 50 50 1 1 I +X GND 4 0 -300 100 U 50 50 1 1 W +X OUT 5 400 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# MCP1416R +# +DEF MCP1416R U 0 20 Y Y 1 F N +F0 "U" -200 250 50 H V L CNN +F1 "MCP1416R" 50 250 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-5" 0 -400 50 H I C CIN +F3 "" -200 250 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -200 200 300 -200 0 1 10 f +X NC 1 300 -100 100 L 50 50 1 1 N N +X GND 2 0 -300 100 U 50 50 1 1 W +X IN 3 -300 0 100 R 50 50 1 1 I +X OUT 4 400 0 100 L 50 50 1 1 O +X Vdd 5 0 300 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# MCP14A0303xMNY +# +DEF MCP14A0303xMNY U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MCP14A0303xMNY" 50 350 50 H V L CNN +F2 "Package_DFN_QFN:WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm" 0 750 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + WDFN*1EP*3x2mm*P0.5mm*EP1.3x1.4mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X ENA 1 -400 200 100 R 50 50 1 1 I +X INA 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X INB 4 -400 -100 100 R 50 50 1 1 I +X ~OUTB 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUTA 7 400 100 100 L 50 50 1 1 O +X ENB 8 -400 -200 100 R 50 50 1 1 I +X GND 9 0 -400 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# MCP14A0304xMNY +# +DEF MCP14A0304xMNY U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MCP14A0304xMNY" 50 350 50 H V L CNN +F2 "Package_DFN_QFN:WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm" 0 750 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + WDFN*1EP*3x2mm*P0.5mm*EP1.3x1.4mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X ENA 1 -400 200 100 R 50 50 1 1 I +X INA 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X INB 4 -400 -100 100 R 50 50 1 1 I +X OUTB 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X OUTA 7 400 100 100 L 50 50 1 1 O +X ENB 8 -400 -200 100 R 50 50 1 1 I +X GND 9 0 -400 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# MCP14A0305xMNY +# +DEF MCP14A0305xMNY U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MCP14A0305xMNY" 50 350 50 H V L CNN +F2 "Package_DFN_QFN:WDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm" 0 750 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + WDFN*1EP*3x2mm*P0.5mm*EP1.3x1.4mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X ENA 1 -400 200 100 R 50 50 1 1 I +X INA 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X INB 4 -400 -100 100 R 50 50 1 1 I +X OUTB 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUTA 7 400 100 100 L 50 50 1 1 O +X ENB 8 -400 -200 100 R 50 50 1 1 I +X GND 9 0 -400 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# MCP14A0901xMNY +# +DEF MCP14A0901xMNY U 0 20 Y Y 1 F N +F0 "U" -200 300 50 H V L CNN +F1 "MCP14A0901xMNY" 100 300 50 H V L CNN +F2 "Package_DFN_QFN:TDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm" 0 750 50 H I C CNN +F3 "" 0 -200 50 H I C CNN +ALIAS MCP14A1201xMNY +$FPLIST + TDFN*1EP*3x2mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -200 200 200 0 1 10 f +X VDD 1 0 300 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X EN 3 -300 -100 100 R 50 50 1 1 I +X GND 4 0 -300 100 U 50 50 1 1 W +X GND 5 0 -300 100 U 50 50 1 1 P N +X ~OUT 6 300 0 100 L 50 50 1 1 O +X ~OUT 7 300 0 100 L 50 50 1 1 P N +X VDD 8 0 300 100 D 50 50 1 1 P N +X GND 9 0 -300 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# MCP14A0902xMNY +# +DEF MCP14A0902xMNY U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MCP14A0902xMNY" 50 350 50 H V L CNN +F2 "Package_DFN_QFN:TDFN-8-1EP_3x2mm_P0.5mm_EP1.3x1.4mm" 0 750 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +ALIAS MCP14A1202xMNY +$FPLIST + TDFN*1EP*3x2mm*P0.5mm* +$ENDFPLIST +DRAW +S -200 -200 200 200 1 1 10 f +X VDD 1 0 300 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X EN 3 -300 -100 100 R 50 50 1 1 I +X GND 4 0 -300 100 U 50 50 1 1 W +X GND 5 0 -300 100 U 50 50 1 1 P N +X OUT 6 300 0 100 L 50 50 1 1 O +X OUT 7 300 0 100 L 50 50 1 1 P N +X VDD 8 0 300 100 D 50 50 1 1 P N +X GND 9 0 -300 100 U 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# MIC4426 +# +DEF MIC4426 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MIC4426" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*3.9x4.9mm*P1.27mm* + MSOP*P0.65mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X ~OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# MIC4427 +# +DEF MIC4427 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MIC4427" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*3.9x4.9mm*P1.27mm* + MSOP*P0.65mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# MIC4428 +# +DEF MIC4428 U 0 20 Y Y 1 F N +F0 "U" -300 350 50 H V L CNN +F1 "MIC4428" 50 350 50 H V L CNN +F2 "" 0 -300 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +$FPLIST + DIP*W7.62mm* + SOIC*3.9x4.9mm*P1.27mm* + MSOP*P0.65mm* +$ENDFPLIST +DRAW +S -300 -300 300 300 0 1 10 f +X NC 1 -300 0 100 R 50 50 1 1 N N +X IN_A 2 -400 100 100 R 50 50 1 1 I +X GND 3 0 -400 100 U 50 50 1 1 W +X IN_B 4 -400 -100 100 R 50 50 1 1 I +X OUT_B 5 400 -100 100 L 50 50 1 1 O +X V+ 6 0 400 100 D 50 50 1 1 W +X ~OUT_A 7 400 100 100 L 50 50 1 1 O +X NC 8 300 0 100 L 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# MIC4604YM +# +DEF MIC4604YM U 0 20 Y Y 1 F N +F0 "U" -350 -350 50 H V R CNN +F1 "MIC4604YM" -350 -450 50 H V R CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" -100 300 50 H I C CNN +F3 "" 0 400 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -500 300 400 0 1 10 f +X VDD 1 0 500 100 D 50 50 1 1 W +X HB 2 400 300 100 L 50 50 1 1 P +X HO 3 400 -200 100 L 50 50 1 1 O +X HS 4 400 -300 100 L 50 50 1 1 P +X HI 5 -400 300 100 R 50 50 1 1 I +X LI 6 -400 200 100 R 50 50 1 1 I +X VSS 7 0 -600 100 U 50 50 1 1 W +X LO 8 400 -400 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# NCD5702 +# +DEF NCD5702 U 0 20 Y Y 1 F N +F0 "U" -200 550 50 H V R CNN +F1 "NCD5702" 50 550 50 H V L CNN +F2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 100 50 H I C CNN +$FPLIST + SOIC*3.9x9.9*P1.27mm* +$ENDFPLIST +DRAW +S -300 500 300 -500 0 1 10 f +X EN 1 -400 0 100 R 50 50 1 1 I +X VCC 10 0 600 100 D 50 50 1 1 W +X VOH 11 400 200 100 L 50 50 1 1 E +X VOL 12 400 0 100 L 50 50 1 1 C +X GND 13 100 -600 100 U 50 50 1 1 W +X VEE 14 0 -600 100 U 50 50 1 1 W +X VEEA 15 -100 -600 100 U 50 50 1 1 W +X CLAMP 16 400 -200 100 L 50 50 1 1 C +X VIN 2 -400 200 100 R 50 50 1 1 I +X VREF 3 -400 400 100 R 50 50 1 1 w +X ~FLT 4 -400 -200 100 R 50 50 1 1 C +X GNDA 5 -200 -600 100 U 50 50 1 1 W +X NC 6 -300 300 100 R 50 50 1 1 N N +X RSVD 7 400 -300 100 L 50 50 1 1 P +X NC 8 -300 100 100 R 50 50 1 1 N N +X DESAT 9 400 400 100 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# NCV8402xST +# +DEF NCV8402xST Q 0 0 Y N 1 F N +F0 "Q" 200 350 50 H V R CNN +F1 "NCV8402xST" -450 350 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-223" 0 -280 50 H I C CNN +F3 "" 300 0 50 H I C CNN +$FPLIST + SOT?223* +$ENDFPLIST +DRAW +C -300 0 11 1 1 0 F +C -25 -230 11 1 1 0 F +C -25 0 11 1 1 0 F +C 100 0 11 1 1 0 F +C 265 0 111 1 1 10 N +C 300 -230 11 1 1 0 F +C 300 -155 11 1 1 0 F +C 300 -70 11 1 1 0 F +C 300 70 11 1 1 0 F +C 300 150 11 1 1 0 F +T 0 -60 -135 21 0 0 0 Limit Normal 0 C C +T 0 -50 -90 21 0 0 0 "Temp & Current" Normal 0 C C +S -400 300 400 -300 0 0 0 f +S -235 20 -90 -20 0 0 0 N +S -200 -50 100 -180 0 1 0 N +P 2 0 0 0 300 100 300 -300 N +P 2 0 0 0 300 100 300 300 N +P 3 0 0 0 -25 -50 -25 -25 -25 0 N +P 3 0 0 0 100 0 -90 0 -35 0 N +P 3 0 0 0 100 0 100 150 300 150 N +P 3 0 0 0 300 -230 -25 -230 -25 -180 N +P 4 0 0 0 -25 -230 -300 -230 -300 0 -240 0 N +P 2 0 1 0 -300 0 -400 0 N +P 2 0 1 0 300 -155 105 -155 N +P 2 1 1 0 100 0 210 0 N +P 2 1 1 0 230 -70 300 -70 N +P 2 1 1 10 230 -50 230 -90 N +P 2 1 1 0 230 0 300 0 N +P 2 1 1 10 230 20 230 -20 N +P 2 1 1 0 230 70 300 70 N +P 2 1 1 10 230 90 230 50 N +P 2 1 1 0 300 -70 300 -100 N +P 2 1 1 0 300 -70 300 0 N +P 2 1 1 0 300 100 300 70 N +P 3 1 1 10 210 75 210 -75 210 -75 N +P 4 1 1 0 -320 -70 -315 -75 -285 -75 -280 -80 N +P 4 1 1 0 -300 -145 -285 -120 -315 -120 -300 -145 N +P 4 1 1 0 -300 -75 -315 -100 -285 -100 -300 -75 N +P 4 1 1 0 -280 -150 -285 -145 -315 -145 -320 -140 N +P 4 1 1 0 80 120 85 115 115 115 120 110 N +P 4 1 1 0 100 45 115 70 85 70 100 45 N +P 4 1 1 0 100 115 85 90 115 90 100 115 N +P 4 1 1 0 120 40 115 45 85 45 80 50 N +P 4 1 1 0 240 0 280 15 280 -15 240 0 F +P 4 1 1 0 300 -70 330 -70 330 70 300 70 N +P 4 1 1 0 310 20 315 15 345 15 350 10 N +P 4 1 1 0 330 15 315 -10 345 -10 330 15 N +X G 1 -500 0 100 R 50 50 1 1 I +X D 2 300 400 100 D 50 50 1 1 P N +X S 3 300 -400 100 U 50 50 1 1 P +X D 4 300 400 100 D 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PE29101 +# +DEF PE29101 U 0 20 Y Y 1 F N +F0 "U" -300 650 50 H V C CNN +F1 "PE29101" 250 650 50 H V C CNN +F2 "Package_CSP:pSemi_CSP-16_1.64x2.04mm_P0.4mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + pSemi*CSP*1.64x2.04mm*P0.4mm* +$ENDFPLIST +DRAW +S 400 600 -400 -600 0 1 10 f +X HSGpd 1 500 100 100 L 50 50 1 1 O +X LSO 10 -500 -100 100 R 50 50 1 1 O +X GND 11 0 -700 100 U 50 50 1 1 W +X LSGpd 12 500 -400 100 L 50 50 1 1 O +X LSS 13 500 -500 100 L 50 50 1 1 P +X LSB 14 500 -200 100 L 50 50 1 1 I +X VDD 15 0 700 100 D 50 50 1 1 W +X RDHL 16 -500 -400 100 R 50 50 1 1 P +X HSS 2 500 0 100 L 50 50 1 1 P +X HSB 3 500 300 100 L 50 50 1 1 I +X VDDSYNC 4 500 500 100 L 50 50 1 1 P +X RDLH 5 -500 -300 100 R 50 50 1 1 P +X HSGpu 6 500 200 100 L 50 50 1 1 O +X ~EN 7 -500 100 100 R 50 50 1 1 I +X IN 8 -500 300 100 R 50 50 1 1 I +X LSGpu 9 500 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PE29102 +# +DEF PE29102 U 0 20 Y Y 1 F N +F0 "U" -300 650 50 H V C CNN +F1 "PE29102" 250 650 50 H V C CNN +F2 "Package_CSP:pSemi_CSP-16_1.64x2.04mm_P0.4mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + pSemi*CSP*1.64x2.04mm*P0.4mm* +$ENDFPLIST +DRAW +S 400 600 -400 -600 0 1 10 f +X HSGpd 1 500 100 100 L 50 50 1 1 O +X PHCTL 10 -500 -100 100 R 50 50 1 1 I +X GND 11 0 -700 100 U 50 50 1 1 W +X LSGpd 12 500 -400 100 L 50 50 1 1 O +X LSS 13 500 -500 100 L 50 50 1 1 P +X LSB 14 500 -200 100 L 50 50 1 1 I +X VDD 15 0 700 100 D 50 50 1 1 W +X RDHL 16 -500 -400 100 R 50 50 1 1 P +X HSS 2 500 0 100 L 50 50 1 1 P +X HSB 3 500 300 100 L 50 50 1 1 I +X NC 4 400 500 100 L 50 50 1 1 N N +X RDLH 5 -500 -300 100 R 50 50 1 1 P +X HSGpu 6 500 200 100 L 50 50 1 1 O +X ~EN 7 -500 100 100 R 50 50 1 1 I +X IN 8 -500 300 100 R 50 50 1 1 I +X LSGpu 9 500 -300 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PM8834 +# +DEF PM8834 U 0 20 Y Y 1 F N +F0 "U" -300 450 50 H V L CNN +F1 "PM8834" 500 450 50 H V R CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 -400 300 400 0 1 10 f +X EN1 1 -400 300 100 R 50 50 1 1 I +X PWM1 2 -400 200 100 R 50 50 1 1 I +X GND 3 0 -500 100 U 50 50 1 1 W +X PWM2 4 -400 -100 100 R 50 50 1 1 I +X OUT2 5 400 -100 100 L 50 50 1 1 O +X VCC 6 0 500 100 D 50 50 1 1 W +X OUT1 7 400 100 100 L 50 50 1 1 O +X EN2 8 -400 0 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PM8834M +# +DEF PM8834M U 0 20 Y Y 1 F N +F0 "U" -300 450 50 H V L CNN +F1 "PM8834M" 500 450 50 H V R CNN +F2 "Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.95x2.15mm" -100 -800 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + MSOP*1EP*3x3mm*P0.65mm* +$ENDFPLIST +DRAW +S -300 -400 300 400 0 1 10 f +X EN1 1 -400 300 100 R 50 50 1 1 I +X PWM1 2 -400 200 100 R 50 50 1 1 I +X GND 3 100 -500 100 U 50 50 1 1 W +X PWM2 4 -400 -100 100 R 50 50 1 1 I +X OUT2 5 400 -100 100 L 50 50 1 1 O +X VCC 6 0 500 100 D 50 50 1 1 W +X OUT1 7 400 100 100 L 50 50 1 1 O +X EN2 8 -400 0 100 R 50 50 1 1 I +X GND 9 -100 -500 100 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +# SM72295MA +# +DEF SM72295MA U 0 20 Y Y 1 F N +F0 "U" 250 1050 50 H V L CNN +F1 "SM72295MA" 250 950 50 H V L CNN +F2 "Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm" 1050 -950 50 H I C CIN +F3 "" -50 -400 50 H I C CNN +$FPLIST + SOIC*7.5x17.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -500 -900 500 900 0 1 10 f +X SIA 1 -600 700 100 R 50 50 1 1 I +X PGOOD 10 600 -600 100 L 50 50 1 1 C +X BOUT 11 -600 -500 100 R 50 50 1 1 O +X IOUT 12 -600 -700 100 R 50 50 1 1 P +X SOB 13 600 600 100 L 50 50 1 1 I +X SIB 14 600 700 100 L 50 50 1 1 I +X OVP 15 600 -700 100 L 50 50 1 1 C +X OVS 16 -600 400 100 R 50 50 1 1 I +X VDD 17 -100 1000 100 D 50 50 1 1 W +X HSA 18 600 300 100 L 50 50 1 1 P +X HOA 19 600 200 100 L 50 50 1 1 O +X SOA 2 -600 600 100 R 50 50 1 1 I +X HBA 20 600 400 100 L 50 50 1 1 P +X VCCA 21 0 1000 100 D 50 50 1 1 W +X LOA 22 600 100 100 L 50 50 1 1 O +X PGND 23 100 -1000 100 U 50 50 1 1 W +X LOB 24 600 -400 100 L 50 50 1 1 O +X VCCB 25 100 1000 100 D 50 50 1 1 W +X HBB 26 600 -100 100 L 50 50 1 1 P +X HOB 27 600 -300 100 L 50 50 1 1 O +X HSB 28 600 -200 100 L 50 50 1 1 P +X IIN 3 -600 -600 100 R 50 50 1 1 P +X BIN 4 -600 -400 100 R 50 50 1 1 O +X AGND 5 -100 -1000 100 U 50 50 1 1 W +X LIA 6 -600 -100 100 R 50 50 1 1 I +X HIA 7 -600 200 100 R 50 50 1 1 I +X HIB 8 -600 100 100 R 50 50 1 1 I +X LIB 9 -600 -200 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# STGAP1AS +# +DEF STGAP1AS U 0 20 Y Y 1 F N +F0 "U" -400 800 50 H V C CNN +F1 "STGAP1AS" 400 800 50 H V C CNN +F2 "Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm" 0 -1300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*7.5x15.4mm*P1.27mm* +$ENDFPLIST +DRAW +S -400 -700 400 700 0 1 10 f +X GND 1 -200 -800 100 U 50 50 1 1 W +X DIAG1 10 -500 -200 100 R 50 50 1 1 C +X ~SD 11 -500 -500 100 R 50 50 1 1 I +X GND 12 -200 -800 100 U 50 50 1 1 P N +X GNDISO 13 0 -800 100 U 50 50 1 1 W +X VL 14 100 -800 100 U 50 50 1 1 W +X VREGISO 15 500 400 100 L 50 50 1 1 w +X SENSE 16 500 -500 100 L 50 50 1 1 I +X VH 17 100 800 100 D 50 50 1 1 W +X DESAT 18 500 100 100 L 50 50 1 1 P +X VCECLAMP 19 500 200 100 L 50 50 1 1 I +X SDO 2 -500 500 100 R 50 50 1 1 O +X GON 20 500 -100 100 L 50 50 1 1 O +X GOFF 21 500 -200 100 L 50 50 1 1 O +X CLAMP 22 500 -400 100 L 50 50 1 1 O +X VL 23 100 -800 100 U 50 50 1 1 P N +X ASC 24 500 -600 100 L 50 50 1 1 I +X SDI 3 -500 400 100 R 50 50 1 1 I +X ~CS 4 -500 300 100 R 50 50 1 1 I +X CK 5 -500 200 100 R 50 50 1 1 I +X VREG 6 500 500 100 L 50 50 1 1 w +X VDD 7 -200 800 100 D 50 50 1 1 W +X IN-/DIAG2 8 -500 -100 100 R 50 50 1 1 B +X IN+ 9 -500 0 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# STGAP2SCM +# +DEF STGAP2SCM U 0 20 Y Y 1 F N +F0 "U" -400 350 50 H V L CNN +F1 "STGAP2SCM" 150 350 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -400 -300 400 300 0 1 10 f +X VDD 1 -100 400 100 D 50 50 1 1 W +X IN+ 2 -500 100 100 R 50 50 1 1 I +X IN- 3 -500 -100 100 R 50 50 1 1 I +X GND 4 -100 -400 100 U 50 50 1 1 W +X VH 5 100 400 100 D 50 50 1 1 W +X GOUT 6 500 100 100 L 50 50 1 1 O +X CLAMP 7 500 -100 100 L 50 50 1 1 O +X GNDISO 8 100 -400 100 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +# STGAP2SM +# +DEF STGAP2SM U 0 20 Y Y 1 F N +F0 "U" -400 350 50 H V L CNN +F1 "STGAP2SM" 150 350 50 H V L CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -400 -300 400 300 0 1 10 f +X VDD 1 -100 400 100 D 50 50 1 1 W +X IN+ 2 -500 100 100 R 50 50 1 1 I +X IN- 3 -500 -100 100 R 50 50 1 1 I +X GND 4 -100 -400 100 U 50 50 1 1 W +X VH 5 100 400 100 D 50 50 1 1 W +X GON 6 500 100 100 L 50 50 1 1 O +X GOFF 7 500 -100 100 L 50 50 1 1 O +X GNDISO 8 100 -400 100 U 50 50 1 1 W +ENDDRAW +ENDDEF +# +# TC4421 +# +DEF TC4421 U 0 20 Y Y 1 F N +F0 "U" -350 250 50 H V C CNN +F1 "TC4421" 250 250 50 H V C CNN +F2 "Package_DIP:DIP-8-N6_W7.62mm" 0 -800 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -400 200 400 -200 0 1 10 f +X VDD 1 0 300 100 D 50 50 1 1 W +X INPUT 2 -500 0 100 R 50 50 1 1 I +X NC 3 -200 -200 100 U 50 50 1 1 N N +X GND 4 0 -300 100 U 50 50 1 1 W +X GND 5 0 -300 100 U 50 50 1 1 P N +X ~OUTPUT 6 500 0 100 L 50 50 1 1 O +X ~OUTPUT 7 500 0 100 L 50 50 1 1 P N +X VDD 8 0 300 100 D 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# TC4422 +# +DEF TC4422 U 0 20 Y Y 1 F N +F0 "U" -350 250 50 H V C CNN +F1 "TC4422" 250 250 50 H V C CNN +F2 "Package_DIP:DIP-8-N6_W7.62mm" 0 -800 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +S -400 200 400 -200 0 1 10 f +X VDD 1 0 300 100 D 50 50 1 1 W +X INPUT 2 -500 0 100 R 50 50 1 1 I +X NC 3 -200 -200 100 U 50 50 1 1 N N +X GND 4 0 -300 100 U 50 50 1 1 W +X GND 5 0 -300 100 U 50 50 1 1 P N +X OUTPUT 6 500 0 100 L 50 50 1 1 O +X OUTPUT 7 500 0 100 L 50 50 1 1 P N +X VDD 8 0 300 100 D 50 50 1 1 P N +ENDDRAW +ENDDEF +# +# TLP250 +# +DEF TLP250 U 0 20 Y N 1 F N +F0 "U" 0 500 50 H V C CNN +F1 "TLP250" 0 400 50 H V C CNN +F2 "Package_DIP:DIP-8_W7.62mm" 0 -400 50 H I C CIN +F3 "" -90 5 50 H I L CNN +$FPLIST + DIP*W7.62mm* +$ENDFPLIST +DRAW +C 200 -300 10 0 1 0 F +C 200 0 10 0 1 0 F +C 200 300 10 0 1 0 F +C 260 0 10 0 1 0 F +S -300 350 300 -350 0 1 10 f +S 25 250 25 250 0 1 0 N +S 25 250 25 300 0 1 0 N +S 200 50 200 -50 0 1 0 N +P 2 0 1 10 -225 -25 -175 -25 N +P 2 0 1 10 -25 25 -75 25 N +P 2 0 1 0 120 -150 50 -150 N +P 2 0 1 0 120 150 50 150 N +P 2 0 1 0 125 -175 200 -250 N +P 2 0 1 0 125 175 200 250 N +P 2 0 1 0 200 -250 200 -300 N +P 2 0 1 0 200 -50 125 -125 F +P 2 0 1 0 200 0 260 0 N +P 2 0 1 0 200 50 125 125 F +P 2 0 1 0 200 250 200 300 N +P 2 0 1 0 300 300 25 300 N +P 3 0 1 0 -50 -25 -50 -100 0 -100 N +P 3 0 1 0 -50 25 -50 100 0 100 N +P 3 0 1 0 25 -250 25 -300 300 -300 N +P 3 0 1 20 125 -225 125 -75 125 -75 N +P 3 0 1 20 125 225 125 75 125 75 N +P 4 0 1 0 -300 300 -200 300 -200 -300 -300 -300 N +P 4 0 1 10 -200 -25 -225 25 -175 25 -200 -25 F +P 4 0 1 10 -50 25 -25 -25 -75 -25 -50 25 F +P 4 0 1 0 300 100 260 100 260 -100 300 -100 N +P 5 0 1 0 -150 -20 -100 -20 -115 -25 -115 -15 -100 -20 N +P 5 0 1 0 -150 20 -100 20 -115 15 -115 25 -100 20 N +P 5 0 1 0 50 250 50 -250 0 -250 0 250 50 250 N +P 5 0 1 0 145 85 165 105 185 65 145 85 145 85 F +P 5 0 1 0 195 -75 175 -55 155 -95 195 -75 195 -75 F +X NC 1 -300 100 100 R 50 50 1 1 N N +X A 2 -400 300 100 R 50 50 1 1 P +X C 3 -400 -300 100 R 50 50 1 1 P +X NC 4 -300 -100 100 R 50 50 1 1 N N +X VEE 5 400 -300 100 L 50 50 1 1 W +X VO 6 400 100 100 L 50 50 1 1 O +X VO 7 400 -100 100 L 50 50 1 1 O +X VCC 8 400 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# UCC21520DW +# +DEF UCC21520DW U 0 20 Y Y 1 F N +F0 "U" 0 650 50 H V C CNN +F1 "UCC21520DW" 0 550 50 H V C CNN +F2 "Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm" 0 -550 50 H I C CNN +F3 "" 0 -50 50 H I C CNN +ALIAS UCC21520ADW +$FPLIST + SOIC*7.5x10.3mm*P1.27mm* +$ENDFPLIST +DRAW +T 900 -130 0 25 0 0 0 "Logic Input" Normal 0 C C +S 40 -250 -40 -350 0 0 0 N +S 40 350 -40 250 0 0 0 N +S -150 450 -100 -450 0 1 0 N +S 400 500 -400 -500 0 1 0 f +P 2 0 0 0 -25 250 -25 200 N +P 2 0 0 0 -25 400 -25 350 N +P 2 0 0 0 -25 475 -25 425 N +P 2 0 0 0 -10 -300 -100 -300 N +P 2 0 0 10 -10 -270 -10 -330 N +P 2 0 0 0 -10 300 -100 300 N +P 2 0 0 10 -10 330 -10 270 N +P 2 0 0 0 10 -300 70 -300 N +P 2 0 0 10 10 -270 10 -330 N +P 2 0 0 0 10 300 70 300 N +P 2 0 0 10 10 330 10 270 N +P 2 0 0 0 25 250 25 200 N +P 2 0 0 0 25 350 25 400 N +P 2 0 0 0 25 425 25 475 N +P 2 0 0 0 100 -25 50 -25 N +P 2 0 0 0 100 25 50 25 N +P 2 0 0 0 160 -300 130 -300 N +P 2 0 0 0 160 300 130 300 N +P 2 0 0 0 175 -25 125 -25 N +P 2 0 0 0 175 25 125 25 N +P 2 0 0 0 250 -25 200 -25 N +P 2 0 0 0 250 25 200 25 N +P 2 0 0 0 325 -25 275 -25 N +P 2 0 0 0 325 25 275 25 N +P 2 0 0 0 400 -25 350 -25 N +P 2 0 0 0 400 25 350 25 N +P 3 0 0 0 160 -400 100 -400 100 -330 N +P 3 0 0 0 160 -200 100 -200 100 -270 N +P 3 0 0 0 160 200 100 200 100 270 N +P 3 0 0 0 160 400 100 400 100 330 N +P 4 0 0 0 130 -300 70 -360 70 -240 130 -300 N +P 4 0 0 0 130 300 70 240 70 360 130 300 N +P 2 0 1 0 -150 -400 -180 -400 N +P 2 0 1 0 -150 -300 -180 -300 N +P 2 0 1 0 -150 -100 -180 -100 N +P 2 0 1 0 -150 0 -180 0 N +P 2 0 1 0 -150 100 -180 100 N +P 2 0 1 0 -150 400 -180 400 N +P 2 0 1 0 -25 -425 -25 -475 N +P 2 0 1 0 -25 -350 -25 -400 N +P 2 0 1 0 -25 -200 -25 -250 N +P 2 0 1 0 -25 -125 -25 -175 N +P 2 0 1 0 -25 -50 -25 -100 N +P 2 0 1 0 -25 25 -25 -25 N +P 2 0 1 0 -25 100 -25 50 N +P 2 0 1 0 -25 175 -25 125 N +P 2 0 1 0 25 -425 25 -475 N +P 2 0 1 0 25 -350 25 -400 N +P 2 0 1 0 25 -200 25 -250 N +P 2 0 1 0 25 -125 25 -175 N +P 2 0 1 0 25 -50 25 -100 N +P 2 0 1 0 25 25 25 -25 N +P 2 0 1 0 25 100 25 50 N +P 2 0 1 0 25 175 25 125 N +X INA 1 -500 100 100 R 50 50 1 1 I +X OUTB 10 500 -300 100 L 50 50 1 1 O +X VDDB 11 500 -200 100 L 50 50 1 1 W +X NC 12 400 -100 100 L 50 50 1 1 N N +X NC 13 400 100 100 L 50 50 1 1 N N +X VSSA 14 500 200 100 L 50 50 1 1 W +X OUTA 15 500 300 100 L 50 50 1 1 O +X VDDA 16 500 400 100 L 50 50 1 1 W +X INB 2 -500 0 100 R 50 50 1 1 I +X VCCI 3 -500 400 100 R 50 50 1 1 W +X GND 4 -500 -400 100 R 50 50 1 1 W +X DIS 5 -500 -100 100 R 50 50 1 1 I +X DT 6 -500 -300 100 R 50 50 1 1 P +X NC 7 -400 -200 100 R 50 50 1 1 N N +X VCCI 8 -500 400 100 R 50 50 1 1 P N +X VSSB 9 500 -400 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# UCC27714D +# +DEF UCC27714D U 0 20 Y Y 1 F N +F0 "U" -300 450 50 H V L CNN +F1 "UCC27714D" 50 450 50 H V L CNN +F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 -100 50 H I C CNN +$FPLIST + SOIC*3.9x8.7mm*P1.27mm* +$ENDFPLIST +DRAW +S -300 400 300 -400 0 1 10 f +X HI 1 -400 300 100 R 50 50 1 1 I +X NC 10 -300 -200 100 R 50 50 1 1 N N +X HS 11 400 0 100 L 50 50 1 1 P +X HO 12 400 100 100 L 50 50 1 1 O +X HB 13 400 300 100 L 50 50 1 1 I +X NC 14 -300 -300 100 R 50 50 1 1 N N +X LI 2 -400 200 100 R 50 50 1 1 I +X VSS 3 0 -500 100 U 50 50 1 1 W +X EN/NC 4 -400 100 100 R 50 50 1 1 I +X COM 5 400 -300 100 L 50 50 1 1 P +X LO 6 400 -200 100 L 50 50 1 1 O +X VDD 7 0 500 100 D 50 50 1 1 W +X NC 8 -300 0 100 R 50 50 1 1 N N +X NC 9 -300 -100 100 R 50 50 1 1 N N +ENDDRAW +ENDDEF +# +# ZXGD3001E6 +# +DEF ZXGD3001E6 U 0 20 Y Y 1 F N +F0 "U" -350 250 50 H V C CNN +F1 "ZXGD3001E6" 400 -300 50 H V C CNN +F2 "Package_TO_SOT_SMD:SOT-23-6" 0 -500 50 H I C CNN +F3 "" -350 250 50 H I C CNN +ALIAS ZXGD3004E6 ZXGD3002E6 ZXGD3003E6 +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -400 200 400 -200 0 1 10 f +X VCC 1 0 300 100 D 50 50 1 1 W +X IN1 2 -500 100 100 R 50 50 1 1 I +X GND 3 0 -300 100 U 50 50 1 1 W +X SINK 4 500 -100 100 L 50 50 1 1 C +X IN2 5 -500 -100 100 R 50 50 1 1 I +X SOURCE 6 500 100 100 L 50 50 1 1 E +ENDDRAW +ENDDEF +# +# ZXGD3006E6 +# +DEF ZXGD3006E6 U 0 20 Y Y 1 F N +F0 "U" 100 350 50 H V L CNN +F1 "ZXGD3006E6" 100 250 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-23-6" 0 500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -200 200 300 -200 0 1 10 f +X VCC 1 0 300 100 D 50 50 1 1 W +X IN 2 -300 0 100 R 50 50 1 1 I +X VEE 3 0 -300 100 U 50 50 1 1 W +X SINK 4 400 -100 100 L 50 50 1 1 C +X NC 5 300 100 100 L 50 50 1 1 N N +X SRC 6 400 0 100 L 50 50 1 1 E +ENDDRAW +ENDDEF +# +# ZXGD3009E6 +# +DEF ZXGD3009E6 U 0 20 Y Y 1 F N +F0 "U" -350 250 50 H V C CNN +F1 "ZXGD3009E6" 400 -300 50 H V C CNN +F2 "Package_TO_SOT_SMD:SOT-23-6" 0 -500 50 H I C CNN +F3 "" -350 250 50 H I C CNN +$FPLIST + SOT?23* +$ENDFPLIST +DRAW +S -400 200 400 -200 0 1 10 f +X VCC 1 0 300 100 D 50 50 1 1 W +X IN 2 -500 0 100 R 50 50 1 1 I +X VEE 3 0 -300 100 U 50 50 1 1 W +X SINK 4 500 -100 100 L 50 50 1 1 C +X NC 5 400 0 100 L 50 50 1 1 N N +X SOURCE 6 500 100 100 L 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/hw/fp-info-cache b/hw/fp-info-cache new file mode 100644 index 0000000..7dc6485 --- /dev/null +++ b/hw/fp-info-cache @@ -0,0 +1,701 @@ +163500692101241 +Capacitor_SMD +CP_Elec_3x5.3 +SMT capacitor, aluminium electrolytic, 3x5.3, Cornell Dubilier Electronics +Capacitor Electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_3x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 3.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x3 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 4.0x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.3 +SMD capacitor, aluminum electrolytic, Vishay, 4.0x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.4 +SMD capacitor, aluminum electrolytic, Panasonic A5 / Nichicon, 4.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 4.0x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_4x5.8 +SMD capacitor, aluminum electrolytic, Panasonic, 4.0x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x3 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x4.4 +SMD capacitor, aluminum electrolytic, Panasonic B45, 5.0x4.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.3 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 5.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 5.0x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.8 +SMD capacitor, aluminum electrolytic, Panasonic, 5.0x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_5x5.9 +SMD capacitor, aluminum electrolytic, Panasonic B6, 5.0x5.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x3 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x3.9 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x3.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x4.5 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x4.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x4.9 +SMD capacitor, aluminum electrolytic, Panasonic C5, 6.3x4.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.2 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.2mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.3 +SMD capacitor, aluminum electrolytic, Cornell Dubilier, 6.3x5.3mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.4 +SMD capacitor, aluminum electrolytic, Panasonic C55, 6.3x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.4_Nichicon +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 6.3x5.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.8 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x5.8mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x5.9 +SMD capacitor, aluminum electrolytic, Panasonic C6, 6.3x5.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x7.7 +SMD capacitor, aluminum electrolytic, Nichicon, 6.3x7.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_6.3x9.9 +SMD capacitor, aluminum electrolytic, Panasonic C10, 6.3x9.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x5.4 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x5.4mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.2 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x6.2mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.5 +SMD capacitor, aluminum electrolytic, Rubycon, 8.0x6.5mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.7 +SMD capacitor, aluminum electrolytic, United Chemi-Con, 8.0x6.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x6.9 +SMD capacitor, aluminum electrolytic, Panasonic E7, 8.0x6.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x10 +SMD capacitor, aluminum electrolytic, Nichicon, 8.0x10mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x10.5 +SMD capacitor, aluminum electrolytic, Vishay 0810, 8.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_8x11.9 +SMD capacitor, aluminum electrolytic, Panasonic E12, 8.0x11.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x7.7 +SMD capacitor, aluminum electrolytic, Nichicon, 10.0x7.7mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x7.9 +SMD capacitor, aluminum electrolytic, Panasonic F8, 10.0x7.9mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x10 +SMD capacitor, aluminum electrolytic, Nichicon, 10.0x10.0mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x10.5 +SMD capacitor, aluminum electrolytic, Vishay 1010, 10.0x10.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x12.5 +SMD capacitor, aluminum electrolytic, Vishay 1012, 10.0x12.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x12.6 +SMD capacitor, aluminum electrolytic, Panasonic F12, 10.0x12.6mm +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_10x14.3 +SMD capacitor, aluminum electrolytic, Vishay 1014, 10.0x14.3mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_16x17.5 +SMD capacitor, aluminum electrolytic, Vishay 1616, 16.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_16x22 +SMD capacitor, aluminum electrolytic, Vishay 1621, 16.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_18x17.5 +SMD capacitor, aluminum electrolytic, Vishay 1816, 18.0x17.5mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +CP_Elec_18x22 +SMD capacitor, aluminum electrolytic, Vishay 1821, 18.0x22.0mm, http://www.vishay.com/docs/28395/150crz.pdf +capacitor electrolytic +0 +2 +2 +Capacitor_SMD +C_0201_0603Metric +Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +capacitor +0 +4 +2 +Capacitor_SMD +C_0201_0603Metric_Pad0.64x0.40mm_HandSolder +Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +4 +2 +Capacitor_SMD +C_0402_1005Metric +Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0402_1005Metric_Pad0.74x0.62mm_HandSolder +Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_0504_1310Metric +Capacitor SMD 0504 (1310 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0504_1310Metric_Pad0.83x1.28mm_HandSolder +Capacitor SMD 0504 (1310 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_0603_1608Metric +Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0603_1608Metric_Pad1.08x0.95mm_HandSolder +Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_0805_2012Metric +Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_0805_2012Metric_Pad1.18x1.45mm_HandSolder +Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_01005_0402Metric +Capacitor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +capacitor +0 +4 +2 +Capacitor_SMD +C_01005_0402Metric_Pad0.57x0.30mm_HandSolder +Capacitor SMD 01005 (0402 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: http://www.vishay.com/docs/20056/crcw01005e3.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +4 +2 +Capacitor_SMD +C_1206_3216Metric +Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1206_3216Metric_Pad1.33x1.80mm_HandSolder +Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1210_3225Metric +Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1210_3225Metric_Pad1.33x2.70mm_HandSolder +Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1812_4532Metric +Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1812_4532Metric_Pad1.57x3.40mm_HandSolder +Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_1825_4564Metric +Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_1825_4564Metric_Pad1.57x6.80mm_HandSolder +Capacitor SMD 1825 (4564 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2220_5650Metric +Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2220_5650Metric_Pad1.97x5.40mm_HandSolder +Capacitor SMD 2220 (5650 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_2225_5664Metric +Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_2225_5664Metric_Pad1.80x6.60mm_HandSolder +Capacitor SMD 2225 (5664 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_3640_9110Metric +Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor +0 +2 +2 +Capacitor_SMD +C_3640_9110Metric_Pad2.10x10.45mm_HandSolder +Capacitor SMD 3640 (9110 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size from: http://datasheets.avx.com/AVX-HV_MLCC.pdf), generated with kicad-footprint-generator +capacitor handsolder +0 +2 +2 +Capacitor_SMD +C_Elec_3x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 3.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_4x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_4x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 4.0x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_5x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_5x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 5.0x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x5.8 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x5.8mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_6.3x7.7 +SMD capacitor, aluminum electrolytic nonpolar, 6.3x7.7mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x5.4 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x5.4mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x6.2 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x6.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_8x10.2 +SMD capacitor, aluminum electrolytic nonpolar, 8.0x10.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Elec_10x10.2 +SMD capacitor, aluminum electrolytic nonpolar, 10.0x10.2mm +capacitor electrolyic nonpolar +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZB4-A +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZB4 TZB4-A +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZB4-B +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZB4 TZB4-A +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZC3 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZC3 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZR1 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZR1 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZW4 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZW4 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Murata_TZY2 +trimmer capacitor SMD horizontal, http://www.murata.com/~/media/webrenewal/support/library/catalog/products/capacitor/trimmer/t13e.ashx?la=en-gb + Murata TZY2 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Sprague-Goodman_SGC3 +trimmer capacitor SMD horizontal, http://media.wix.com/ugd/d86717_38d9821e12823a7aa9cef38c6c2a73cc.pdf + Sprague Goodman SGC3 +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JN +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JN +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JQ +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JQ +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JR +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JR +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JV +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JV +0 +2 +2 +Capacitor_SMD +C_Trimmer_Voltronics_JZ +trimmer capacitor SMD horizontal, http://www.knowlescapacitors.com/File%20Library/Voltronics/English/GlobalNavigation/Products/Trimmer%20Capacitors/CerChipTrimCap.pdf + Voltronics JR +0 +2 +2 diff --git a/hw/fzzt-cache.lib b/hw/fzzt-cache.lib new file mode 100644 index 0000000..5b3b67c --- /dev/null +++ b/hw/fzzt-cache.lib @@ -0,0 +1,279 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# Connector_Conn_01x01_Female +# +DEF Connector_Conn_01x01_Female J 0 40 Y N 1 F N +F0 "J" 0 100 50 H V C CNN +F1 "Connector_Conn_01x01_Female" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:* +$ENDFPLIST +DRAW +A 0 0 20 901 -901 1 1 6 N 0 20 0 -20 +P 2 1 1 6 -50 0 -20 0 N +X Pin_1 1 -200 0 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Connector_Conn_01x04_Female +# +DEF Connector_Conn_01x04_Female J 0 40 Y N 1 F N +F0 "J" 0 200 50 H V C CNN +F1 "Connector_Conn_01x04_Female" 0 -300 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Connector*:*_1x??_* +$ENDFPLIST +DRAW +A 0 -200 20 901 -901 1 1 6 N 0 -180 0 -220 +A 0 -100 20 901 -901 1 1 6 N 0 -80 0 -120 +A 0 0 20 901 -901 1 1 6 N 0 20 0 -20 +A 0 100 20 901 -901 1 1 6 N 0 120 0 80 +P 2 1 1 6 -50 -200 -20 -200 N +P 2 1 1 6 -50 -100 -20 -100 N +P 2 1 1 6 -50 0 -20 0 N +P 2 1 1 6 -50 100 -20 100 N +X Pin_1 1 -200 100 150 R 50 50 1 1 P +X Pin_2 2 -200 0 150 R 50 50 1 1 P +X Pin_3 3 -200 -100 150 R 50 50 1 1 P +X Pin_4 4 -200 -200 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_C +# +DEF Device_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "Device_C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_Crystal_GND24 +# +DEF Device_Crystal_GND24 Y 0 40 Y N 1 F N +F0 "Y" 125 200 50 H V L CNN +F1 "Device_Crystal_GND24" 125 125 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Crystal* +$ENDFPLIST +DRAW +S -45 100 45 -100 0 1 12 N +P 2 0 1 0 -100 0 -80 0 N +P 2 0 1 20 -80 -50 -80 50 N +P 2 0 1 0 0 -150 0 -140 N +P 2 0 1 0 0 140 0 150 N +P 2 0 1 20 80 -50 80 50 N +P 2 0 1 0 80 0 100 0 N +P 4 0 1 0 -100 -90 -100 -140 100 -140 100 -90 N +P 4 0 1 0 -100 90 -100 140 100 140 100 90 N +X 1 1 -150 0 50 R 50 50 1 1 P +X 2 2 0 200 50 D 50 50 1 1 P +X 3 3 150 0 50 L 50 50 1 1 P +X 4 4 0 -200 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_D +# +DEF Device_D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "Device_D" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 0 1 10 -50 50 -50 -50 N +P 2 0 1 0 50 0 -50 0 N +P 4 0 1 10 50 50 50 -50 -50 0 50 50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Device_R +# +DEF Device_R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "Device_R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Oscillator_Si5351A-B-GT +# +DEF Oscillator_Si5351A-B-GT U 0 20 Y Y 1 F N +F0 "U" -350 450 50 H V C CNN +F1 "Oscillator_Si5351A-B-GT" -500 -500 50 H V C CNN +F2 "Package_SO:MSOP-10_3x3mm_P0.5mm" 0 -800 50 H I C CNN +F3 "" -350 -100 50 H I C CNN +$FPLIST + MSOP*3x3mm*P0.5mm* +$ENDFPLIST +DRAW +S -400 400 400 -400 0 1 10 f +X VDD 1 -100 500 100 D 50 50 1 1 W +X CLK0 10 500 200 100 L 50 50 1 1 O +X XA 2 -500 300 100 R 50 50 1 1 I +X XB 3 -500 100 100 R 50 50 1 1 I +X SCL 4 -500 -200 100 R 50 50 1 1 I +X SDA 5 -500 -300 100 R 50 50 1 1 B +X CLK2 6 500 -200 100 L 50 50 1 1 O +X VDDO 7 100 500 100 D 50 50 1 1 W +X GND 8 0 -500 100 U 50 50 1 1 W +X CLK1 9 500 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Regulator_Linear_LD1117S33TR_SOT223 +# +DEF Regulator_Linear_LD1117S33TR_SOT223 U 0 10 Y Y 1 F N +F0 "U" -150 125 50 H V C CNN +F1 "Regulator_Linear_LD1117S33TR_SOT223" 0 125 50 H V L CNN +F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN +F3 "" 100 -250 50 H I C CNN +ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0 +$FPLIST + SOT?223*TabPin2* +$ENDFPLIST +DRAW +S -200 -200 200 75 0 1 10 f +X GND 1 0 -300 100 U 50 50 1 1 W +X VO 2 300 0 100 L 50 50 1 1 w +X VI 3 -300 0 100 R 50 50 1 1 W +ENDDRAW +ENDDEF +# +# Switch_SW_Push +# +DEF Switch_SW_Push SW 0 40 N N 1 F N +F0 "SW" 50 100 50 H V L CNN +F1 "Switch_SW_Push" 0 -60 50 H V C CNN +F2 "" 0 200 50 H I C CNN +F3 "" 0 200 50 H I C CNN +DRAW +C -80 0 20 0 1 0 N +C 80 0 20 0 1 0 N +P 2 0 1 0 0 50 0 120 N +P 2 0 1 0 100 50 -100 50 N +X 1 1 -200 0 100 R 50 50 0 1 P +X 2 2 200 0 100 L 50 50 0 1 P +ENDDRAW +ENDDEF +# +# cesco_STM32G031J6Mx +# +DEF cesco_STM32G031J6Mx U 0 40 Y Y 1 F N +F0 "U" 0 0 50 H V C CNN +F1 "cesco_STM32G031J6Mx" 0 0 50 H V C CNN +F2 "Package_SO:SO-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +S -800 -100 850 -750 0 1 0 N +X PB7,8,9/PC14 1 -900 -200 100 R 50 50 1 1 B +X VDD/VDDA 2 -900 -350 100 R 50 50 1 1 W +X VSS/VSSA 3 -900 -500 100 R 50 50 1 1 W +X PA0,1/PF2/NRST 4 -900 -650 100 R 50 50 1 1 B +X A8/A11/PA9 5 950 -650 100 L 50 50 1 1 B +X PA12[PA10] 6 950 -500 100 L 50 50 1 1 B +X PA13 7 950 -350 100 L 50 50 1 1 B +X PB5,6/PA14,15 8 950 -200 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# fzzt-rescue_IXDN609PI-ixdn609pi +# +DEF fzzt-rescue_IXDN609PI-ixdn609pi U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "fzzt-rescue_IXDN609PI-ixdn609pi" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 400 200 -400 0 1 10 f +X VCC 1 -300 300 100 R 50 50 1 1 W +X IN 2 -300 100 100 R 50 50 1 1 I +X NC 3 -300 -100 100 R 50 50 1 1 N +X GND 4 -300 -300 100 R 50 50 1 1 W +X GND 5 300 -300 100 L 50 50 1 1 W +X OUT 6 300 -100 100 L 50 50 1 1 O +X OUT 7 300 100 100 L 50 50 1 1 O +X VCC 8 300 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +# power_+12V +# +DEF power_+12V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+12V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +12V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_+3.3V +# +DEF power_+3.3V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "power_+3.3V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS +3.3V +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# power_GND +# +DEF power_GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "power_GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/hw/fzzt-rescue.dcm b/hw/fzzt-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/hw/fzzt-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/hw/fzzt-rescue.lib b/hw/fzzt-rescue.lib new file mode 100644 index 0000000..35178d6 --- /dev/null +++ b/hw/fzzt-rescue.lib @@ -0,0 +1,27 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# IXDN609PI-ixdn609pi +# +DEF IXDN609PI-ixdn609pi U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "IXDN609PI-ixdn609pi" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 400 200 -400 0 1 10 f +X VCC 1 -300 300 100 R 50 50 1 1 W +X IN 2 -300 100 100 R 50 50 1 1 I +X NC 3 -300 -100 100 R 50 50 1 1 N +X GND 4 -300 -300 100 R 50 50 1 1 W +X GND 5 300 -300 100 L 50 50 1 1 W +X OUT 6 300 -100 100 L 50 50 1 1 O +X OUT 7 300 100 100 L 50 50 1 1 O +X VCC 8 300 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/hw/fzzt.kicad_pcb b/hw/fzzt.kicad_pcb new file mode 100644 index 0000000..5c84905 --- /dev/null +++ b/hw/fzzt.kicad_pcb @@ -0,0 +1,1130 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.99.0+really5.1.12+dfsg1-1) + + (general + (thickness 1.6) + (drawings 4) + (tracks 163) + (zones 0) + (modules 21) + (nets 16) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (user_trace_width 0.5) + (user_trace_width 1) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +3V3) + (net 3 "Net-(SW1-Pad2)") + (net 4 "Net-(U2-Pad10)") + (net 5 "Net-(U2-Pad9)") + (net 6 "Net-(U2-Pad3)") + (net 7 "Net-(U2-Pad2)") + (net 8 +12V) + (net 9 "Net-(J1-Pad1)") + (net 10 "Net-(J2-Pad1)") + (net 11 "Net-(R1-Pad2)") + (net 12 "Net-(R2-Pad2)") + (net 13 "Net-(C1-Pad1)") + (net 14 "Net-(J6-Pad4)") + (net 15 "Net-(J6-Pad3)") + + (net_class Default "Questo è il gruppo di collegamenti predefinito" + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +12V) + (add_net +3V3) + (add_net GND) + (add_net "Net-(C1-Pad1)") + (add_net "Net-(J1-Pad1)") + (add_net "Net-(J2-Pad1)") + (add_net "Net-(J6-Pad3)") + (add_net "Net-(J6-Pad4)") + (add_net "Net-(R1-Pad2)") + (add_net "Net-(R2-Pad2)") + (add_net "Net-(SW1-Pad2)") + (add_net "Net-(U2-Pad10)") + (add_net "Net-(U2-Pad2)") + (add_net "Net-(U2-Pad3)") + (add_net "Net-(U2-Pad9)") + ) + + (module Capacitor_SMD:C_1812_4532Metric (layer F.Cu) (tedit 5F68FEEE) (tstamp 61D41F81) + (at 86.85 45.075 180) + (descr "Capacitor SMD 1812 (4532 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags capacitor) + (path /61E06150) + (attr smd) + (fp_text reference C5 (at 0 -2.65) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220n (at 0 2.65) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.25 1.6) (end -2.25 -1.6) (layer F.Fab) (width 0.1)) + (fp_line (start -2.25 -1.6) (end 2.25 -1.6) (layer F.Fab) (width 0.1)) + (fp_line (start 2.25 -1.6) (end 2.25 1.6) (layer F.Fab) (width 0.1)) + (fp_line (start 2.25 1.6) (end -2.25 1.6) (layer F.Fab) (width 0.1)) + (fp_line (start -1.161252 -1.71) (end 1.161252 -1.71) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.161252 1.71) (end 1.161252 1.71) (layer F.SilkS) (width 0.12)) + (fp_line (start -3 1.95) (end -3 -1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3 -1.95) (end 3 -1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3 -1.95) (end 3 1.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3 1.95) (end -3 1.95) (layer F.CrtYd) (width 0.05)) + (pad 2 smd roundrect (at 2.05 0 180) (size 1.4 3.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.178571) + (net 13 "Net-(C1-Pad1)")) + (pad 1 smd roundrect (at -2.05 0 180) (size 1.4 3.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.178571) + (net 1 GND)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1812_4532Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder (layer F.Cu) (tedit 5F68FEEE) (tstamp 61D2D22D) + (at 66.225 52.625) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "resistor handsolder") + (path /61BEE388) + (attr smd) + (fp_text reference R2 (at 0 -1.82) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 5k6 (at 0 1.82) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.45 1.12) (end -2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 -1.12) (end 2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 -1.12) (end 2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 1.12) (end -2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 12 "Net-(R2-Pad2)")) + (pad 1 smd roundrect (at -1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5677) + (at 69.7625 38.2 180) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /61C2BA36) + (attr smd) + (fp_text reference C3 (at 0 -1.85) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 150n (at 0 1.85) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 180) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 180) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 61D3F292) + (at 75.245 51.23 270) + (descr "surface-mounted straight pin header, 1x04, 2.54mm pitch, single row, style 1 (pin 1 left)") + (tags "Surface mounted pin header SMD 1x04 2.54mm single row style1 pin1 left") + (path /61DE3E97) + (attr smd) + (fp_text reference J6 (at 0 -6.14 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x04_Female (at 0 6.14 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.27 5.08) (end -1.27 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -0.32 -5.08) (end 1.27 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 5.08) (end -1.27 -4.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -4.13) (end -0.32 -5.08) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -5.08) (end 1.27 5.08) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -4.13) (end -2.54 -4.13) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 -4.13) (end -2.54 -3.49) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 -3.49) (end -1.27 -3.49) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 0.95) (end -2.54 0.95) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 0.95) (end -2.54 1.59) (layer F.Fab) (width 0.1)) + (fp_line (start -2.54 1.59) (end -1.27 1.59) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.59) (end 2.54 -1.59) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 -1.59) (end 2.54 -0.95) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 -0.95) (end 1.27 -0.95) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 3.49) (end 2.54 3.49) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 3.49) (end 2.54 4.13) (layer F.Fab) (width 0.1)) + (fp_line (start 2.54 4.13) (end 1.27 4.13) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 -5.14) (end 1.33 -5.14) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 5.14) (end 1.33 5.14) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 -5.14) (end 1.33 -2.03) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -4.57) (end -2.85 -4.57) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -5.14) (end -1.33 -4.57) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 4.57) (end 1.33 5.14) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 -0.51) (end 1.33 3.05) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -3.05) (end -1.33 0.51) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 2.03) (end -1.33 5.14) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.45 -5.6) (end -3.45 5.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.45 5.6) (end 3.45 5.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 5.6) (end 3.45 -5.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.45 -5.6) (end -3.45 -5.6) (layer F.CrtYd) (width 0.05)) + (pad 4 smd rect (at 1.655 3.81 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(J6-Pad4)")) + (pad 2 smd rect (at 1.655 -1.27 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 3 smd rect (at -1.655 1.27 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask) + (net 15 "Net-(J6-Pad3)")) + (pad 1 smd rect (at -1.655 -3.81 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_TO_SOT_SMD:SOT-223-3_TabPin2 (layer F.Cu) (tedit 5A02FF57) (tstamp 61D3A92F) + (at 70.575 32.525 180) + (descr "module CMS SOT223 4 pins") + (tags "CMS SOT") + (path /61DBDBE5) + (attr smd) + (fp_text reference U5 (at 0 -4.5) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value LD1117S33TR_SOT223 (at 0 4.5) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.85 -3.35) (end 1.85 3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.85 3.35) (end 1.85 3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -4.1 -3.41) (end 1.91 -3.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.85 -3.35) (end 1.85 -3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.85 3.41) (end 1.91 3.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.85 -2.35) (end -1.85 3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.85 -2.35) (end -0.85 -3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -4.4 -3.6) (end -4.4 3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.4 3.6) (end 4.4 3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.4 3.6) (end 4.4 -3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.4 -3.6) (end -4.4 -3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.91 -3.41) (end 1.91 -2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.91 3.41) (end 1.91 2.15) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 1 smd rect (at -3.15 -2.3 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 3 smd rect (at -3.15 2.3 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(C1-Pad1)")) + (pad 2 smd rect (at -3.15 0 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 2 smd rect (at 3.15 0 180) (size 2 3.8) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-223.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Button_Switch_SMD:SW_SPST_CK_RS282G05A3 (layer F.Cu) (tedit 5A7A67D2) (tstamp 61BD3C07) + (at 64.8 41.25 90) + (descr https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf) + (tags "SPST button tactile switch") + (path /61C14AD4) + (attr smd) + (fp_text reference SW1 (at 0 -2.6 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SW_Push (at 0 3 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 3 -1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end -3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end 3 -1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end -1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3.06 1.85) (end -3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 1.85) (end -3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 -1.85) (end 3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.06 -1.85) (end 3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.75 1) (end -1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 1) (end -1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 -1) (end 1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start -1.75 -1) (end 1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start -4.9 -2.05) (end 4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 -2.05) (end 4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 2.05) (end -4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.9 2.05) (end -4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2.6 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 2 smd rect (at 3.9 0 90) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 3 "Net-(SW1-Pad2)")) + (pad 1 smd rect (at -3.9 0 90) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_CK_RS282G05A3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Diode_SMD:D_3220_8050Metric_Pad2.65x5.15mm_HandSolder (layer F.Cu) (tedit 5F68FEF0) (tstamp 61D3822D) + (at 86.575 32.625) + (descr "Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator") + (tags "diode handsolder") + (path /61D9D085) + (attr smd) + (fp_text reference D1 (at 0 -3.52) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value D (at 0 3.52) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 4.85 2.82) (end -4.85 2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.85 -2.82) (end 4.85 2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.85 -2.82) (end 4.85 -2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.85 2.82) (end -4.85 -2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.86 2.835) (end 4 2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start -4.86 -2.835) (end -4.86 2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start 4 -2.835) (end -4.86 -2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start 4 2.5) (end 4 -2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -4 2.5) (end 4 2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -4 -1.5) (end -4 2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -2.5) (end -4 -1.5) (layer F.Fab) (width 0.1)) + (fp_line (start 4 -2.5) (end -3 -2.5) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 2 smd roundrect (at 3.275 0) (size 2.65 5.15) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.09433999999999999) + (net 8 +12V)) + (pad 1 smd roundrect (at -3.275 0) (size 2.65 5.15) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.09433999999999999) + (net 13 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_3220_8050Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D34121) + (at 94.325 44.65) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D73449) + (attr virtual) + (fp_text reference J5 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MOSFETGND (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 1 GND)) + ) + + (module Crystal:Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering (layer F.Cu) (tedit 5A0FD1B2) (tstamp 61D3179C) + (at 77.75 40.2875) + (descr "crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package") + (tags "SMD SMT crystal hand-soldering") + (path /61D4D30B) + (attr smd) + (fp_text reference Y1 (at 0 -2.95) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Crystal_GND24 (at 0 2.95) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.8 -2.2) (end -2.8 -2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.8 2.2) (end 2.8 -2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.8 2.2) (end 2.8 2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.8 -2.2) (end -2.8 2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.7 2.15) (end 2.7 2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.7 -2.15) (end -2.7 2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.6 0.25) (end -0.6 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.15) (end -1.5 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 1.15) (end -1.6 -1.15) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 1.25) (end -1.6 1.15) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 1.25) (end -1.5 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 1.15) (end 1.5 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -1.15) (end 1.6 1.15) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -1.25) (end 1.6 -1.15) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -1.25) (end 1.5 -1.25) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.7 0.7) (thickness 0.105))) + ) + (pad 4 smd rect (at -1.45 -1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 3 smd rect (at 1.45 -1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(U2-Pad3)")) + (pad 2 smd rect (at 1.45 1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 1 smd rect (at -1.45 1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(U2-Pad2)")) + (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D30632) + (at 94.275 32.975) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D4A334) + (attr virtual) + (fp_text reference J4 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 8 +12V)) + ) + + (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 61D39FB7) + (at 85.3 39.69) + (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SOIC SO") + (path /6170CD01) + (attr smd) + (fp_text reference U3 (at 0 -3.4) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value IXDN609PI (at 0 3.4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.98 0.98) (thickness 0.15))) + ) + (fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end -3.45 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.975 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 2.45) (end -1.95 -1.475) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 -1.475) (end -0.975 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -3.7 -2.7) (end -3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 13 "Net-(C1-Pad1)")) + (pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 4 "Net-(U2-Pad10)")) + (pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 "Net-(J1-Pad1)")) + (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 "Net-(J1-Pad1)")) + (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 13 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5655) + (at 90.25 39.4625 270) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /617245F7) + (attr smd) + (fp_text reference C1 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 13 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 61BD2D92) + (at 85.05 50.255) + (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SOIC SO") + (path /6170DA36) + (attr smd) + (fp_text reference U4 (at 0 -3.4) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value IXDN609PI (at 0 3.4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.98 0.98) (thickness 0.15))) + ) + (fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end -3.45 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.975 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 2.45) (end -1.95 -1.475) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 -1.475) (end -0.975 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -3.7 -2.7) (end -3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 13 "Net-(C1-Pad1)")) + (pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 5 "Net-(U2-Pad9)")) + (pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 "Net-(J2-Pad1)")) + (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 "Net-(J2-Pad1)")) + (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 13 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D33C2A) + (at 78.075 34.275) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D33D93) + (attr virtual) + (fp_text reference J3 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 1 GND)) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D2EC39) + (at 94.3 50.475) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61C2A1B5) + (attr virtual) + (fp_text reference J2 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 10 "Net-(J2-Pad1)")) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D2ECD8) + (at 94.325 39.475) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61C293CA) + (attr virtual) + (fp_text reference J1 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 9 "Net-(J1-Pad1)")) + ) + + (module Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder (layer F.Cu) (tedit 5F68FEEE) (tstamp 61D2D21C) + (at 66.25 49.975) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "resistor handsolder") + (path /61BED99B) + (attr smd) + (fp_text reference R1 (at 0 -1.82) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 5k6 (at 0 1.82) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.45 1.12) (end -2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 -1.12) (end 2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 -1.12) (end 2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 1.12) (end -2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 11 "Net-(R1-Pad2)")) + (pad 1 smd roundrect (at -1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61D2D999) + (at 73.75 40.5375 90) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /61C2AF29) + (attr smd) + (fp_text reference C4 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 150n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 90) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 90) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5666) + (at 90.225 50.0625 270) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /617264A4) + (attr smd) + (fp_text reference C2 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 13 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SO:MSOP-10_3x3mm_P0.5mm (layer F.Cu) (tedit 5A02F25C) (tstamp 61D2F9FE) + (at 78.075 44.725) + (descr "10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.5") + (path /61BD2F46) + (attr smd) + (fp_text reference U2 (at 0 -2.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Si5351A-B-GT (at 0 2.6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.6 0.6) (thickness 0.15))) + ) + (fp_line (start -0.5 -1.5) (end 1.5 -1.5) (layer F.Fab) (width 0.15)) + (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.Fab) (width 0.15)) + (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.Fab) (width 0.15)) + (fp_line (start -1.5 1.5) (end -1.5 -0.5) (layer F.Fab) (width 0.15)) + (fp_line (start -1.5 -0.5) (end -0.5 -1.5) (layer F.Fab) (width 0.15)) + (fp_line (start -3.15 -1.85) (end -3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.15 -1.85) (end 3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.15 -1.85) (end 3.15 -1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.15 1.85) (end 3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.675 -1.675) (end -1.675 -1.45) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.675 -1.675) (end 1.675 -1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.675 1.675) (end 1.675 1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 1.675) (end -1.675 1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 -1.675) (end 1.675 -1.675) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 1.675) (end 1.675 1.675) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 -1.45) (end -2.9 -1.45) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -2.2 -1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 2 smd rect (at -2.2 -0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(U2-Pad2)")) + (pad 3 smd rect (at -2.2 0) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(U2-Pad3)")) + (pad 4 smd rect (at -2.2 0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(R2-Pad2)")) + (pad 5 smd rect (at -2.2 1) (size 1.4 0.3) (layers F.Cu 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(width 0.25) (layer F.Cu) (net 11)) + (segment (start 69.085 45.55) (end 69.41001 45.22499) (width 0.25) (layer F.Cu) (net 11) (status 10)) + (segment (start 69.085 46.425) (end 69.085 45.55) (width 0.25) (layer F.Cu) (net 11) (status 30)) + (segment (start 69.085 48.69) (end 69.085 46.425) (width 0.5) (layer F.Cu) (net 11) (status 20)) + (segment (start 67.8 49.975) (end 69.085 48.69) (width 0.5) (layer F.Cu) (net 11) (status 10)) + (segment (start 74.611391 44.774981) (end 75.06141 45.225) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 68.590021 44.77498) (end 74.611391 44.774981) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 75.06141 45.225) (end 75.875 45.225) (width 0.25) (layer F.Cu) (net 12) (status 20)) + (segment (start 67.815 45.55) (end 68.590021 44.77498) (width 0.25) (layer F.Cu) (net 12) (status 10)) + (segment (start 67.815 46.425) (end 67.815 45.55) (width 0.25) (layer F.Cu) (net 12) (status 30)) + (segment (start 66.69999 51.54999) (end 67.775 52.625) (width 0.5) (layer F.Cu) (net 12) (status 20)) + (segment (start 66.69999 47.54001) (end 66.69999 51.54999) (width 0.5) (layer F.Cu) (net 12)) + (segment (start 67.815 46.425) (end 66.69999 47.54001) (width 0.5) (layer F.Cu) (net 12) (status 10)) + (segment (start 90.135 37.785) (end 90.25 37.9) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 87.525 37.785) (end 90.135 37.785) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 90.075 48.35) (end 90.225 48.5) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 87.525 48.35) (end 90.075 48.35) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 90.225 48.5) (end 90.6 48.5) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 90.6 48.5) (end 91.475 47.625) (width 0.5) (layer F.Cu) (net 13) (status 10)) + (segment (start 91.125001 37.024999) (end 90.25 37.9) (width 0.5) (layer F.Cu) (net 13) (status 20)) + (segment (start 96.685001 37.024999) (end 91.125001 37.024999) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 96.775001 37.114999) (end 96.685001 37.024999) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 96.775001 47.010001) (end 96.775001 37.114999) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 96.160002 47.625) (end 96.775001 47.010001) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 91.475 47.625) (end 96.160002 47.625) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 87.525 37.785) (end 82.575 37.785) (width 0.5) (layer F.Cu) (net 13) (status 30)) + (segment (start 80.995 30.32) (end 83.3 32.625) (width 1) (layer F.Cu) (net 13) (status 20)) + (segment (start 73.875 30.32) (end 80.995 30.32) (width 1) (layer F.Cu) (net 13) (status 10)) + (segment (start 83.3 32.625) (end 87.175 36.5) (width 1) (layer F.Cu) (net 13) (status 10)) + (segment (start 88.85 36.5) (end 90.25 37.9) (width 1) (layer F.Cu) (net 13) (status 20)) + (segment (start 87.175 36.5) (end 88.85 36.5) (width 1) (layer F.Cu) (net 13)) + (segment (start 84.8 48.15) (end 85 48.35) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 84.8 45.075) (end 84.8 48.15) (width 0.5) (layer F.Cu) (net 13) (status 10)) + (segment (start 85 48.35) (end 82.575 48.35) (width 0.5) (layer F.Cu) (net 13) (status 20)) + (segment (start 87.525 48.35) (end 85 48.35) (width 0.5) (layer F.Cu) (net 13) (status 10)) + (segment (start 70.355 52.005) (end 71.435 53.085) (width 0.5) (layer F.Cu) (net 14) (status 20)) + (segment (start 70.355 46.425) (end 70.355 52.005) (width 0.5) (layer F.Cu) (net 14) (status 10)) + (segment (start 71.625 47.425) (end 73.975 49.775) (width 0.5) (layer F.Cu) (net 15) (status 20)) + (segment (start 71.625 46.425) (end 71.625 47.425) (width 0.5) (layer F.Cu) (net 15) (status 10)) + +) diff --git a/hw/fzzt.kicad_pcb-bak b/hw/fzzt.kicad_pcb-bak new file mode 100644 index 0000000..9d3485d --- /dev/null +++ b/hw/fzzt.kicad_pcb-bak @@ -0,0 +1,1086 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.99.0+really5.1.12+dfsg1-1) + + (general + (thickness 1.6) + (drawings 4) + (tracks 167) + (zones 0) + (modules 20) + (nets 15) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.5) + (user_trace_width 0.5) + (user_trace_width 1) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +3V3) + (net 3 "Net-(SW1-Pad2)") + (net 4 "Net-(U2-Pad10)") + (net 5 "Net-(U2-Pad9)") + (net 6 "Net-(U2-Pad3)") + (net 7 "Net-(U2-Pad2)") + (net 8 +12V) + (net 9 "Net-(J1-Pad1)") + (net 10 "Net-(J2-Pad1)") + (net 11 "Net-(R1-Pad2)") + (net 12 "Net-(R2-Pad2)") + (net 13 "Net-(SW2-Pad2)") + (net 14 "Net-(C1-Pad1)") + + (net_class Default "Questo è il gruppo di collegamenti predefinito" + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +12V) + (add_net +3V3) + (add_net GND) + (add_net "Net-(C1-Pad1)") + (add_net "Net-(J1-Pad1)") + (add_net "Net-(J2-Pad1)") + (add_net "Net-(R1-Pad2)") + (add_net "Net-(R2-Pad2)") + (add_net "Net-(SW1-Pad2)") + (add_net "Net-(SW2-Pad2)") + (add_net "Net-(U1-Pad4)") + (add_net "Net-(U1-Pad8)") + (add_net "Net-(U2-Pad10)") + (add_net "Net-(U2-Pad2)") + (add_net "Net-(U2-Pad3)") + (add_net "Net-(U2-Pad6)") + (add_net "Net-(U2-Pad9)") + (add_net "Net-(U3-Pad3)") + (add_net "Net-(U4-Pad3)") + ) + + (module Package_TO_SOT_SMD:SOT-223-3_TabPin2 (layer F.Cu) (tedit 5A02FF57) (tstamp 61D3A92F) + (at 70.575 32.525 180) + (descr "module CMS SOT223 4 pins") + (tags "CMS SOT") + (path /61DBDBE5) + (attr smd) + (fp_text reference U5 (at 0 -4.5) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value LD1117S33TR_SOT223 (at 0 4.5) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (fp_line (start 1.91 3.41) (end 1.91 2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.91 -3.41) (end 1.91 -2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.4 -3.6) (end -4.4 -3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.4 3.6) (end 4.4 -3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.4 3.6) (end 4.4 3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.4 -3.6) (end -4.4 3.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.85 -2.35) (end -0.85 -3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.85 -2.35) (end -1.85 3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.85 3.41) (end 1.91 3.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.85 -3.35) (end 1.85 -3.35) (layer F.Fab) (width 0.1)) + (fp_line (start -4.1 -3.41) (end 1.91 -3.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.85 3.35) (end 1.85 3.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.85 -3.35) (end 1.85 3.35) (layer F.Fab) (width 0.1)) + (pad 1 smd rect (at -3.15 -2.3 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 3 smd rect (at -3.15 2.3 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 14 "Net-(C1-Pad1)")) + (pad 2 smd rect (at -3.15 0 180) (size 2 1.5) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 2 smd rect (at 3.15 0 180) (size 2 3.8) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Package_TO_SOT_SMD.3dshapes/SOT-223.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Button_Switch_SMD:SW_SPST_CK_RS282G05A3 (layer F.Cu) (tedit 5A7A67D2) (tstamp 61D3393E) + (at 75.475 51.825 180) + (descr https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf) + (tags "SPST button tactile switch") + (path /61D66A37) + (attr smd) + (fp_text reference SW2 (at 0 -2.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SW_Push (at 0 3) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -4.9 2.05) (end -4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 2.05) (end -4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 -2.05) (end 4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.9 -2.05) (end 4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1) (end 1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 -1) (end 1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 1) (end -1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start -1.75 1) (end -1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start -3.06 -1.85) (end 3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 -1.85) (end 3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 1.85) (end -3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.06 1.85) (end -3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.5 0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end -1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end 3 -1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end -3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start 3 -1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (pad 2 smd rect (at 3.9 0 180) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 13 "Net-(SW2-Pad2)")) + (pad 1 smd rect (at -3.9 0 180) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_CK_RS282G05A3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Button_Switch_SMD:SW_SPST_CK_RS282G05A3 (layer F.Cu) (tedit 5A7A67D2) (tstamp 61BD3C07) + (at 64.8 41.25 90) + (descr https://www.mouser.com/ds/2/60/RS-282G05A-SM_RT-1159762.pdf) + (tags "SPST button tactile switch") + (path /61C14AD4) + (attr smd) + (fp_text reference SW1 (at 0 -2.6 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SW_Push (at 0 3 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.6 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -4.9 2.05) (end -4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 2.05) (end -4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.9 -2.05) (end 4.9 2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.9 -2.05) (end 4.9 -2.05) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1) (end 1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 -1) (end 1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start 1.75 1) (end -1.75 1) (layer F.Fab) (width 0.1)) + (fp_line (start -1.75 1) (end -1.75 -1) (layer F.Fab) (width 0.1)) + (fp_line (start -3.06 -1.85) (end 3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 -1.85) (end 3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.06 1.85) (end -3.06 1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.06 1.85) (end -3.06 -1.85) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.5 0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end 1.5 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -0.8) (end 1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 -0.8) (end -1.5 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end 3 -1.8) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -1.8) (end -3 1.8) (layer F.Fab) (width 0.1)) + (fp_line (start 3 -1.8) (end 3 1.8) (layer F.Fab) (width 0.1)) + (pad 2 smd rect (at 3.9 0 90) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 3 "Net-(SW1-Pad2)")) + (pad 1 smd rect (at -3.9 0 90) (size 1.5 1.5) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Button_Switch_SMD.3dshapes/SW_SPST_CK_RS282G05A3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Diode_SMD:D_3220_8050Metric_Pad2.65x5.15mm_HandSolder (layer F.Cu) (tedit 5F68FEF0) (tstamp 61D3822D) + (at 86.575 32.625) + (descr "Diode SMD 3220 (8050 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size from: http://datasheets.avx.com/schottky.pdf), generated with kicad-footprint-generator") + (tags "diode handsolder") + (path /61D9D085) + (attr smd) + (fp_text reference D1 (at 0 -3.52) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value D (at 0 3.52) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 4 -2.5) (end -3 -2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -3 -2.5) (end -4 -1.5) (layer F.Fab) (width 0.1)) + (fp_line (start -4 -1.5) (end -4 2.5) (layer F.Fab) (width 0.1)) + (fp_line (start -4 2.5) (end 4 2.5) (layer F.Fab) (width 0.1)) + (fp_line (start 4 2.5) (end 4 -2.5) (layer F.Fab) (width 0.1)) + (fp_line (start 4 -2.835) (end -4.86 -2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start -4.86 -2.835) (end -4.86 2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start -4.86 2.835) (end 4 2.835) (layer F.SilkS) (width 0.12)) + (fp_line (start -4.85 2.82) (end -4.85 -2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start -4.85 -2.82) (end 4.85 -2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.85 -2.82) (end 4.85 2.82) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.85 2.82) (end -4.85 2.82) (layer F.CrtYd) (width 0.05)) + (pad 2 smd roundrect (at 3.275 0) (size 2.65 5.15) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.09433999999999999) + (net 8 +12V)) + (pad 1 smd roundrect (at -3.275 0) (size 2.65 5.15) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.09433999999999999) + (net 14 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Diode_SMD.3dshapes/D_3220_8050Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D34121) + (at 94.325 44.65) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D73449) + (attr virtual) + (fp_text reference J5 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value MOSFETGND (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 1 GND)) + ) + + (module Crystal:Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering (layer F.Cu) (tedit 5A0FD1B2) (tstamp 61D3179C) + (at 77.75 40.2875) + (descr "crystal Epson Toyocom TSX-3225 series https://support.epson.biz/td/api/doc_check.php?dl=brief_fa-238v_en.pdf, hand-soldering, 3.2x2.5mm^2 package") + (tags "SMD SMT crystal hand-soldering") + (path /61D4D30B) + (attr smd) + (fp_text reference Y1 (at 0 -2.95) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Crystal_GND24 (at 0 2.95) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.7 0.7) (thickness 0.105))) + ) + (fp_line (start -1.5 -1.25) (end 1.5 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 -1.25) (end 1.6 -1.15) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -1.15) (end 1.6 1.15) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 1.15) (end 1.5 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.5 1.25) (end -1.5 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.5 1.25) (end -1.6 1.15) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 1.15) (end -1.6 -1.15) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -1.15) (end -1.5 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.25) (end -0.6 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start -2.7 -2.15) (end -2.7 2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.7 2.15) (end 2.7 2.15) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.8 -2.2) (end -2.8 2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.8 2.2) (end 2.8 2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.8 2.2) (end 2.8 -2.2) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.8 -2.2) (end -2.8 -2.2) (layer F.CrtYd) (width 0.05)) + (pad 4 smd rect (at -1.45 -1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 3 smd rect (at 1.45 -1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(U2-Pad3)")) + (pad 2 smd rect (at 1.45 1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 1 smd rect (at -1.45 1.0875) (size 2.1 1.725) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(U2-Pad2)")) + (model ${KISYS3DMOD}/Crystal.3dshapes/Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D30632) + (at 94.275 32.975) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D4A334) + (attr virtual) + (fp_text reference J4 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 8 +12V)) + ) + + (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 61D39FB7) + (at 85.3 39.69) + (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SOIC SO") + (path /6170CD01) + (attr smd) + (fp_text reference U3 (at 0 -3.4) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value IXDN609PI (at 0 3.4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end -3.45 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.975 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 2.45) (end -1.95 -1.475) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 -1.475) (end -0.975 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -3.7 -2.7) (end -3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.98 0.98) (thickness 0.15))) + ) + (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 14 "Net-(C1-Pad1)")) + (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 "Net-(J1-Pad1)")) + (pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 9 "Net-(J1-Pad1)")) + (pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 4 "Net-(U2-Pad10)")) + (pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 14 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5655) + (at 90.25 39.4625 270) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /617245F7) + (attr smd) + (fp_text reference C1 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 14 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 61BD2D92) + (at 85.05 50.255) + (descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SOIC SO") + (path /6170DA36) + (attr smd) + (fp_text reference U4 (at 0 -3.4) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value IXDN609PI (at 0 3.4) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start 0 -2.56) (end -3.45 -2.56) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.975 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 2.45) (end -1.95 -1.475) (layer F.Fab) (width 0.1)) + (fp_line (start -1.95 -1.475) (end -0.975 -2.45) (layer F.Fab) (width 0.1)) + (fp_line (start -3.7 -2.7) (end -3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.98 0.98) (thickness 0.15))) + ) + (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 14 "Net-(C1-Pad1)")) + (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 "Net-(J2-Pad1)")) + (pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 10 "Net-(J2-Pad1)")) + (pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 1 GND)) + (pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)) + (pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 5 "Net-(U2-Pad9)")) + (pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25) + (net 14 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D33C2A) + (at 78.075 34.275) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61D33D93) + (attr virtual) + (fp_text reference J3 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 1 GND)) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D2EC39) + (at 94.3 50.475) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61C2A1B5) + (attr virtual) + (fp_text reference J2 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 10 "Net-(J2-Pad1)")) + ) + + (module TestPoint:TestPoint_Pad_4.0x4.0mm (layer F.Cu) (tedit 5A0F774F) (tstamp 61D2ECD8) + (at 94.325 39.475) + (descr "SMD rectangular pad as test Point, square 4.0mm side length") + (tags "test point SMD pad rectangle square") + (path /61C293CA) + (attr virtual) + (fp_text reference J1 (at 0 -2.898) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Conn_01x01_Female (at 0 3.1) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 0 -2.9) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.2 -2.2) (end 2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 -2.2) (end 2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 2.2 2.2) (end -2.2 2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.2 2.2) (end -2.2 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.5 -2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.5 -2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end 2.5 -2.5) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.5 2.5) (end -2.5 2.5) (layer F.CrtYd) (width 0.05)) + (pad 1 smd rect (at 0 0) (size 4 4) (layers F.Cu F.Mask) + (net 9 "Net-(J1-Pad1)")) + ) + + (module Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder (layer F.Cu) (tedit 5F68FEEE) (tstamp 61D2D22D) + (at 67.075 52.6) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "resistor handsolder") + (path /61BEE388) + (attr smd) + (fp_text reference R2 (at 0 -1.82) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 5k6 (at 0 1.82) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.45 1.12) (end -2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 -1.12) (end 2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 -1.12) (end 2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 1.12) (end -2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 12 "Net-(R2-Pad2)")) + (pad 1 smd roundrect (at -1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder (layer F.Cu) (tedit 5F68FEEE) (tstamp 61D2D21C) + (at 67.125 50.05) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "resistor handsolder") + (path /61BED99B) + (attr smd) + (fp_text reference R1 (at 0 -1.82) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 5k6 (at 0 1.82) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2.45 1.12) (end -2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.45 -1.12) (end 2.45 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 -1.12) (end 2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.45 1.12) (end -2.45 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -0.727064 0.91) (end 0.727064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.727064 -0.91) (end 0.727064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 11 "Net-(R1-Pad2)")) + (pad 1 smd roundrect (at -1.55 0) (size 1.3 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.192308) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61D2D999) + (at 73.75 40.5375 90) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /61C2AF29) + (attr smd) + (fp_text reference C4 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 150n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 90) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 90) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5677) + (at 69.9625 39.525 180) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /61C2BA36) + (attr smd) + (fp_text reference C3 (at 0 -1.85) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 150n (at 0 1.85) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 180) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 180) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder (layer F.Cu) (tedit 5F68FEEF) (tstamp 61BD5666) + (at 90.225 50.0625 270) + (descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (path /617264A4) + (attr smd) + (fp_text reference C2 (at 0 -1.85 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 220n (at 0 1.85 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.711252 -0.91) (end 0.711252 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.711252 0.91) (end 0.711252 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.48 1.15) (end -2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.48 -1.15) (end 2.48 -1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 -1.15) (end 2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.48 1.15) (end -2.48 1.15) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 2 smd roundrect (at 1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 1 GND)) + (pad 1 smd roundrect (at -1.5625 0 270) (size 1.325 1.8) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.188679) + (net 14 "Net-(C1-Pad1)")) + (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SO:MSOP-10_3x3mm_P0.5mm (layer F.Cu) (tedit 5A02F25C) (tstamp 61D2F9FE) + (at 78.075 44.725) + (descr "10-Lead Plastic Micro Small Outline Package (MS) [MSOP] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SSOP 0.5") + (path /61BD2F46) + (attr smd) + (fp_text reference U2 (at 0 -2.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Si5351A-B-GT (at 0 2.6) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.5 -1.5) (end 1.5 -1.5) (layer F.Fab) (width 0.15)) + (fp_line (start 1.5 -1.5) (end 1.5 1.5) (layer F.Fab) (width 0.15)) + (fp_line (start 1.5 1.5) (end -1.5 1.5) (layer F.Fab) (width 0.15)) + (fp_line (start -1.5 1.5) (end -1.5 -0.5) (layer F.Fab) (width 0.15)) + (fp_line (start -1.5 -0.5) (end -0.5 -1.5) (layer F.Fab) (width 0.15)) + (fp_line (start -3.15 -1.85) (end -3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.15 -1.85) (end 3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.15 -1.85) (end 3.15 -1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.15 1.85) (end 3.15 1.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.675 -1.675) (end -1.675 -1.45) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.675 -1.675) (end 1.675 -1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.675 1.675) (end 1.675 1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 1.675) (end -1.675 1.375) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 -1.675) (end 1.675 -1.675) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 1.675) (end 1.675 1.675) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.675 -1.45) (end -2.9 -1.45) (layer F.SilkS) (width 0.15)) + (fp_text user %R (at 0 0) (layer F.Fab) + (effects (font (size 0.6 0.6) (thickness 0.15))) + ) + (pad 10 smd rect (at 2.2 -1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 "Net-(U2-Pad10)")) + (pad 9 smd rect (at 2.2 -0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 5 "Net-(U2-Pad9)")) + (pad 8 smd rect (at 2.2 0) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 1 GND)) + (pad 7 smd rect (at 2.2 0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (pad 6 smd rect (at 2.2 1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -2.2 1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 11 "Net-(R1-Pad2)")) + (pad 4 smd rect (at -2.2 0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 12 "Net-(R2-Pad2)")) + (pad 3 smd rect (at -2.2 0) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 6 "Net-(U2-Pad3)")) + (pad 2 smd rect (at -2.2 -0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 "Net-(U2-Pad2)")) + (pad 1 smd rect (at -2.2 -1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 +3V3)) + (model ${KISYS3DMOD}/Package_SO.3dshapes/MSOP-10_3x3mm_P0.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Package_SO:SO-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 61BD2D3F) + (at 69.845 44.9 270) + (descr "SO, 8 Pin (https://www.nxp.com/docs/en/data-sheet/PCF8523.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py") + (tags "SO SO") + (path /61BD7233) + (attr smd) + (fp_text reference U1 (at 0 -3.4 90) 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46.27499) (width 0.25) (layer F.Cu) (net 11)) + (segment (start 69.21 46.6) (end 69.53501 46.27499) (width 0.25) (layer F.Cu) (net 11)) + (segment (start 69.21 47.475) (end 69.21 46.6) (width 0.25) (layer F.Cu) (net 11)) + (segment (start 75.74998 45.725) (end 75.875 45.725) (width 0.25) (layer F.Cu) (net 11)) + (segment (start 75.19999 46.27499) (end 75.74998 45.725) (width 0.25) (layer F.Cu) (net 11)) + (segment (start 69.21 49.515) (end 69.21 47.475) (width 0.5) (layer F.Cu) (net 11)) + (segment (start 68.675 50.05) (end 69.21 49.515) (width 0.5) (layer F.Cu) (net 11)) + (segment (start 74.775 45.225) (end 75.875 45.225) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 74.17502 45.82498) (end 74.775 45.225) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 68.71502 45.82498) (end 74.17502 45.82498) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 67.94 46.6) (end 68.71502 45.82498) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 67.94 47.475) (end 67.94 46.6) (width 0.25) (layer F.Cu) (net 12)) + (segment (start 67.57499 51.54999) (end 68.625 52.6) (width 0.5) (layer F.Cu) (net 12)) + (segment (start 67.57499 47.84001) (end 67.57499 51.54999) (width 0.5) (layer F.Cu) (net 12)) + (segment (start 67.94 47.475) (end 67.57499 47.84001) (width 0.5) (layer F.Cu) (net 12)) + (segment (start 70.48 50.73) (end 71.575 51.825) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 70.48 47.475) (end 70.48 50.73) (width 0.5) (layer F.Cu) (net 13)) + (segment (start 80.995 30.32) (end 83.3 32.625) (width 1) (layer F.Cu) (net 14)) + (segment (start 73.875 30.32) (end 80.995 30.32) (width 1) (layer F.Cu) (net 14)) + (segment (start 83.3 32.625) (end 87.175 36.5) (width 1) (layer F.Cu) (net 14)) + (segment (start 88.85 36.5) (end 90.25 37.9) (width 1) (layer F.Cu) (net 14)) + (segment (start 87.175 36.5) (end 88.85 36.5) (width 1) (layer F.Cu) (net 14)) + +) diff --git a/hw/fzzt.pro b/hw/fzzt.pro new file mode 100644 index 0000000..7865cfd --- /dev/null +++ b/hw/fzzt.pro @@ -0,0 +1,240 @@ +update=lun 3 gen 2022, 14:40:39 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[pcbnew] +version=1 +PageLayoutDescrFile= +LastNetListRead= +CopperLayerCount=2 +BoardThickness=1.6 +AllowMicroVias=0 +AllowBlindVias=0 +RequireCourtyardDefinitions=0 +ProhibitOverlappingCourtyards=1 +MinTrackWidth=0.2 +MinViaDiameter=0.4 +MinViaDrill=0.3 +MinMicroViaDiameter=0.2 +MinMicroViaDrill=0.09999999999999999 +MinHoleToHole=0.25 +TrackWidth1=0.25 +TrackWidth2=0.5 +TrackWidth3=1 +ViaDiameter1=0.8 +ViaDrill1=0.4 +dPairWidth1=0.2 +dPairGap1=0.25 +dPairViaGap1=0.25 +SilkLineWidth=0.12 +SilkTextSizeV=1 +SilkTextSizeH=1 +SilkTextSizeThickness=0.15 +SilkTextItalic=0 +SilkTextUpright=1 +CopperLineWidth=0.2 +CopperTextSizeV=1.5 +CopperTextSizeH=1.5 +CopperTextThickness=0.3 +CopperTextItalic=0 +CopperTextUpright=1 +EdgeCutLineWidth=0.05 +CourtyardLineWidth=0.05 +OthersLineWidth=0.15 +OthersTextSizeV=1 +OthersTextSizeH=1 +OthersTextSizeThickness=0.15 +OthersTextItalic=0 +OthersTextUpright=1 +SolderMaskClearance=0 +SolderMaskMinWidth=0 +SolderPasteClearance=0 +SolderPasteRatio=-0 +[pcbnew/Layer.F.Cu] +Name=F.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.In1.Cu] +Name=In1.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In2.Cu] +Name=In2.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In3.Cu] +Name=In3.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In4.Cu] +Name=In4.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In5.Cu] +Name=In5.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In6.Cu] +Name=In6.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In7.Cu] +Name=In7.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In8.Cu] +Name=In8.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In9.Cu] +Name=In9.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In10.Cu] +Name=In10.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In11.Cu] +Name=In11.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In12.Cu] +Name=In12.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In13.Cu] +Name=In13.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In14.Cu] +Name=In14.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In15.Cu] +Name=In15.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In16.Cu] +Name=In16.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In17.Cu] +Name=In17.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In18.Cu] +Name=In18.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In19.Cu] +Name=In19.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In20.Cu] +Name=In20.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In21.Cu] +Name=In21.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In22.Cu] +Name=In22.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In23.Cu] +Name=In23.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In24.Cu] +Name=In24.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In25.Cu] +Name=In25.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In26.Cu] +Name=In26.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In27.Cu] +Name=In27.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In28.Cu] +Name=In28.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In29.Cu] +Name=In29.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.In30.Cu] +Name=In30.Cu +Type=0 +Enabled=0 +[pcbnew/Layer.B.Cu] +Name=B.Cu +Type=0 +Enabled=1 +[pcbnew/Layer.B.Adhes] +Enabled=1 +[pcbnew/Layer.F.Adhes] +Enabled=1 +[pcbnew/Layer.B.Paste] +Enabled=1 +[pcbnew/Layer.F.Paste] +Enabled=1 +[pcbnew/Layer.B.SilkS] +Enabled=1 +[pcbnew/Layer.F.SilkS] +Enabled=1 +[pcbnew/Layer.B.Mask] +Enabled=1 +[pcbnew/Layer.F.Mask] +Enabled=1 +[pcbnew/Layer.Dwgs.User] +Enabled=1 +[pcbnew/Layer.Cmts.User] +Enabled=1 +[pcbnew/Layer.Eco1.User] +Enabled=1 +[pcbnew/Layer.Eco2.User] +Enabled=1 +[pcbnew/Layer.Edge.Cuts] +Enabled=1 +[pcbnew/Layer.Margin] +Enabled=1 +[pcbnew/Layer.B.CrtYd] +Enabled=1 +[pcbnew/Layer.F.CrtYd] +Enabled=1 +[pcbnew/Layer.B.Fab] +Enabled=1 +[pcbnew/Layer.F.Fab] +Enabled=1 +[pcbnew/Layer.Rescue] +Enabled=0 +[pcbnew/Netclasses] +[pcbnew/Netclasses/Default] +Name=Default +Clearance=0.2 +TrackWidth=0.25 +ViaDiameter=0.8 +ViaDrill=0.4 +uViaDiameter=0.3 +uViaDrill=0.1 +dPairWidth=0.2 +dPairGap=0.25 +dPairViaGap=0.25 diff --git a/hw/fzzt.sch b/hw/fzzt.sch new file mode 100644 index 0000000..77a64a4 --- /dev/null +++ b/hw/fzzt.sch @@ -0,0 +1,618 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L fzzt-rescue:IXDN609PI-ixdn609pi U3 +U 1 1 6170CD01 +P 8100 3300 +F 0 "U3" H 8100 3867 50 0000 C CNN +F 1 "IXDN609PI" H 8100 3776 50 0000 C CNN +F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 8100 2800 50 0001 C CNN +F 3 "" H 8100 3300 50 0001 C CNN + 1 8100 3300 + 1 0 0 -1 +$EndComp +$Comp +L fzzt-rescue:IXDN609PI-ixdn609pi U4 +U 1 1 6170DA36 +P 8100 4600 +F 0 "U4" H 8100 5167 50 0000 C CNN +F 1 "IXDN609PI" H 8100 5076 50 0000 C CNN +F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 8100 4100 50 0001 C CNN +F 3 "" H 8100 4600 50 0001 C CNN + 1 8100 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3750 7100 3200 +Wire Wire Line + 7100 3200 7800 3200 +Wire Wire Line + 7100 4500 7800 4500 +Wire Wire Line + 8400 3200 8850 3200 +Wire Wire Line + 8400 4500 8850 4500 +$Comp +L Device:C C1 +U 1 1 617245F7 +P 7500 3450 +F 0 "C1" H 7615 3496 50 0000 L CNN +F 1 "220n" H 7615 3405 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 7538 3300 50 0001 C CNN +F 3 "~" H 7500 3450 50 0001 C CNN + 1 7500 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 3300 7500 3000 +Wire Wire Line + 7500 3000 7700 3000 +Wire Wire Line + 7500 3600 7700 3600 +$Comp +L power:GND #PWR0105 +U 1 1 61726114 +P 7500 3600 +F 0 "#PWR0105" H 7500 3350 50 0001 C CNN +F 1 "GND" H 7505 3427 50 0000 C CNN +F 2 "" H 7500 3600 50 0001 C CNN +F 3 "" H 7500 3600 50 0001 C CNN + 1 7500 3600 + 1 0 0 -1 +$EndComp +Connection ~ 7500 3600 +$Comp +L Device:C C2 +U 1 1 617264A4 +P 7500 4750 +F 0 "C2" H 7615 4796 50 0000 L CNN +F 1 "220n" H 7615 4705 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 7538 4600 50 0001 C CNN +F 3 "~" H 7500 4750 50 0001 C CNN + 1 7500 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 4600 7500 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50 0000 L CNN +F 2 "TestPoint:TestPoint_Pad_4.0x4.0mm" H 3800 2300 50 0001 C CNN +F 3 "" H 3800 2300 50 0001 C CNN + 1 3800 2300 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR0114 +U 1 1 61C42002 +P 4450 2600 +F 0 "#PWR0114" H 4450 2350 50 0001 C CNN +F 1 "GND" H 4455 2427 50 0000 C CNN +F 2 "" H 4450 2600 50 0001 C CNN +F 3 "" H 4450 2600 50 0001 C CNN + 1 4450 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:+3.3V #PWR0115 +U 1 1 61C425A8 +P 4750 2300 +F 0 "#PWR0115" H 4750 2150 50 0001 C CNN +F 1 "+3.3V" V 4765 2428 50 0000 L CNN +F 2 "" H 4750 2300 50 0001 C CNN +F 3 "" H 4750 2300 50 0001 C CNN + 1 4750 2300 + 0 1 -1 0 +$EndComp +Wire Wire Line + 6050 3050 6250 3050 +Connection ~ 6050 3050 +$Comp +L Device:R R1 +U 1 1 61BED99B +P 4550 3200 +F 0 "R1" H 4620 3246 50 0000 L CNN +F 1 "5k6" H 4620 3155 50 0000 L CNN +F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder" V 4480 3200 50 0001 C CNN +F 3 "~" H 4550 3200 50 0001 C CNN + 1 4550 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R2 +U 1 1 61BEE388 +P 4850 3200 +F 0 "R2" H 4920 3246 50 0000 L CNN +F 1 "5k6" H 4920 3155 50 0000 L CNN +F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder" V 4780 3200 50 0001 C CNN +F 3 "~" H 4850 3200 50 0001 C CNN + 1 4850 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3050 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 4850 3050 5750 3050 +Wire Wire Line + 4550 3350 4550 4100 +Wire Wire Line + 7700 3600 7700 3800 +Wire Wire Line + 7700 3800 8400 3800 +Wire Wire Line + 8400 3800 8400 3750 +Connection ~ 7700 3600 +Wire Wire Line + 7700 3600 7800 3600 +Wire Wire Line + 7700 3000 7700 2650 +Wire Wire Line + 7700 2650 8400 2650 +Wire Wire Line + 8400 2650 8400 3000 +Connection ~ 7700 3000 +Wire Wire Line + 7700 3000 7800 3000 +Wire Wire Line + 4850 4250 5200 4250 +Wire Wire Line + 5200 4250 5200 4150 +Wire Wire Line + 5200 4150 5650 4150 +Connection ~ 4850 4250 +Wire Wire Line + 4550 4100 5400 4100 +Wire Wire Line + 5400 4100 5400 4250 +Wire Wire Line + 5400 4250 5650 4250 +Connection ~ 4550 4100 +$Comp +L Connector:Conn_01x01_Female J3 +U 1 1 61D33D93 +P 4250 1750 +F 0 "J3" H 4278 1776 50 0000 L CNN +F 1 "Conn_01x01_Female" H 4278 1685 50 0000 L CNN +F 2 "TestPoint:TestPoint_Pad_4.0x4.0mm" H 4250 1750 50 0001 C CNN +F 3 "~" H 4250 1750 50 0001 C CNN + 1 4250 1750 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0103 +U 1 1 61D34201 +P 4050 1750 +F 0 "#PWR0103" H 4050 1500 50 0001 C CNN +F 1 "GND" H 4055 1577 50 0000 C CNN +F 2 "" H 4050 1750 50 0001 C CNN +F 3 "" H 4050 1750 50 0001 C CNN + 1 4050 1750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7700 4900 7700 5100 +Wire Wire Line + 7700 5100 8400 5100 +Wire Wire Line + 8400 5100 8400 4900 +Connection ~ 7700 4900 +Wire Wire Line + 7700 4900 7800 4900 +Wire Wire Line + 8400 4300 8400 4050 +Wire Wire Line + 8400 3950 7700 3950 +Wire Wire Line + 7700 3950 7700 4300 +Connection ~ 7700 4300 +Wire Wire Line + 7700 4300 7800 4300 +$Comp +L power:+12V #PWR0104 +U 1 1 61D49F63 +P 4050 1500 +F 0 "#PWR0104" H 4050 1350 50 0001 C CNN +F 1 "+12V" V 4065 1628 50 0000 L CNN +F 2 "TestPoint:TestPoint_Pad_4.0x4.0mm" H 4050 1500 50 0001 C CNN +F 3 "" H 4050 1500 50 0001 C CNN + 1 4050 1500 + 0 -1 -1 0 +$EndComp +$Comp +L Connector:Conn_01x01_Female J4 +U 1 1 61D4A334 +P 4250 1500 +F 0 "J4" H 4278 1526 50 0000 L CNN +F 1 "Conn_01x01_Female" H 4278 1435 50 0000 L CNN +F 2 "TestPoint:TestPoint_Pad_4.0x4.0mm" H 4250 1500 50 0001 C CNN +F 3 "~" H 4250 1500 50 0001 C CNN + 1 4250 1500 + 1 0 0 -1 +$EndComp +$Comp +L Device:Crystal_GND24 Y1 +U 1 1 61D4D30B +P 5250 3750 +F 0 "Y1" V 5204 3994 50 0000 L CNN +F 1 "Crystal_GND24" V 5295 3994 50 0000 L CNN +F 2 "Crystal:Crystal_SMD_SeikoEpson_TSX3225-4Pin_3.2x2.5mm_HandSoldering" H 5250 3750 50 0001 C CNN +F 3 "~" H 5250 3750 50 0001 C CNN + 1 5250 3750 + 0 1 1 0 +$EndComp +$Comp +L power:GND #PWR0116 +U 1 1 61D52ADC +P 5050 3750 +F 0 "#PWR0116" H 5050 3500 50 0001 C CNN +F 1 "GND" H 5055 3577 50 0000 C CNN +F 2 "" H 5050 3750 50 0001 C CNN +F 3 "" H 5050 3750 50 0001 C CNN + 1 5050 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5450 3750 5450 3550 +Wire Wire Line + 5450 3550 5050 3550 +Wire Wire Line + 5050 3550 5050 3750 +Wire Wire Line + 4850 3350 4850 4250 +Connection ~ 5050 3750 +$Comp +L Connector:Conn_01x01_Female J5 +U 1 1 61D73449 +P 9100 3800 +F 0 "J5" H 9128 3826 50 0000 L CNN +F 1 "MOSFETGND" H 9128 3735 50 0000 L CNN +F 2 "TestPoint:TestPoint_Pad_4.0x4.0mm" H 9100 3800 50 0001 C CNN +F 3 "~" H 9100 3800 50 0001 C CNN + 1 9100 3800 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0119 +U 1 1 61D7344F +P 8900 3800 +F 0 "#PWR0119" H 8900 3550 50 0001 C CNN +F 1 "GND" H 8905 3627 50 0000 C CNN +F 2 "" H 8900 3800 50 0001 C CNN +F 3 "" H 8900 3800 50 0001 C CNN + 1 8900 3800 + 1 0 0 -1 +$EndComp +$Comp +L Device:D D1 +U 1 1 61D9D085 +P 4000 2300 +F 0 "D1" H 4000 2083 50 0000 C CNN +F 1 "D" H 4000 2174 50 0000 C CNN +F 2 "Diode_SMD:D_3220_8050Metric_Pad2.65x5.15mm_HandSolder" H 4000 2300 50 0001 C CNN +F 3 "~" H 4000 2300 50 0001 C CNN + 1 4000 2300 + -1 0 0 1 +$EndComp +Wire Wire Line + 3800 2300 3850 2300 +Wire Wire Line + 7500 4300 7250 4300 +Wire Wire Line + 7250 4300 7250 3000 +Wire Wire Line + 7250 3000 7500 3000 +Connection ~ 7500 4300 +Connection ~ 7500 3000 +Wire Wire Line + 4150 2300 4150 2000 +Wire Wire Line + 4150 2000 7250 2000 +Wire Wire Line + 7250 2000 7250 3000 +Connection ~ 7250 3000 +$Comp +L Regulator_Linear:LD1117S33TR_SOT223 U5 +U 1 1 61DBDBE5 +P 4450 2300 +F 0 "U5" H 4450 2542 50 0000 C CNN +F 1 "LD1117S33TR_SOT223" H 4450 2451 50 0000 C CNN +F 2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" H 4450 2500 50 0001 C CNN +F 3 "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/CD00000544.pdf" H 4550 2050 50 0001 C CNN + 1 4450 2300 + 1 0 0 -1 +$EndComp +Connection ~ 4150 2300 +$Comp +L Connector:Conn_01x04_Female J6 +U 1 1 61DE3E97 +P 3300 3100 +F 0 "J6" V 3238 2812 50 0000 R CNN +F 1 "Conn_01x04_Female" V 3147 2812 50 0000 R CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical_SMD_Pin1Left" H 3300 3100 50 0001 C CNN +F 3 "~" H 3300 3100 50 0001 C CNN + 1 3300 3100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4400 3350 4400 3800 +Wire Wire Line + 3500 3300 3500 3450 +Wire Wire Line + 3500 3450 4450 3450 +Wire Wire Line + 4450 3450 4450 3950 +Wire Wire Line + 4450 3950 4400 3950 +Wire Wire Line + 3400 3300 3400 3350 +$Comp +L power:+3.3V #PWR0108 +U 1 1 61DF1B00 +P 3300 3300 +F 0 "#PWR0108" H 3300 3150 50 0001 C CNN +F 1 "+3.3V" H 3315 3473 50 0000 C CNN +F 2 "" H 3300 3300 50 0001 C CNN +F 3 "" H 3300 3300 50 0001 C CNN + 1 3300 3300 + -1 0 0 1 +$EndComp +$Comp +L power:GND #PWR0109 +U 1 1 61DF2496 +P 3200 3300 +F 0 "#PWR0109" H 3200 3050 50 0001 C CNN +F 1 "GND" H 3205 3127 50 0000 C CNN +F 2 "" H 3200 3300 50 0001 C CNN +F 3 "" H 3200 3300 50 0001 C CNN + 1 3200 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3350 4400 3350 +Wire Wire Line + 8400 3750 8600 3750 +Connection ~ 8400 3750 +Wire Wire Line + 8400 3750 8400 3600 +Wire Wire Line + 8600 4050 8400 4050 +Connection ~ 8400 4050 +Wire Wire Line + 8400 4050 8400 3950 +$Comp +L Device:C C5 +U 1 1 61E06150 +P 8600 3900 +F 0 "C5" H 8715 3946 50 0000 L CNN +F 1 "220n" H 8715 3855 50 0000 L CNN +F 2 "Capacitor_SMD:C_1812_4532Metric" H 8638 3750 50 0001 C CNN +F 3 "~" H 8600 3900 50 0001 C CNN + 1 8600 3900 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/hw/fzzt.sch-bak b/hw/fzzt.sch-bak new file mode 100644 index 0000000..11f54be --- /dev/null +++ b/hw/fzzt.sch-bak @@ -0,0 +1,443 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L fzzt-rescue:IXDN609PI-ixdn609pi U3 +U 1 1 6170CD01 +P 8100 3300 +F 0 "U3" H 8100 3867 50 0000 C CNN +F 1 "IXDN609PI" H 8100 3776 50 0000 C CNN +F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 8100 2800 50 0001 C CNN +F 3 "" H 8100 3300 50 0001 C CNN + 1 8100 3300 + 1 0 0 -1 +$EndComp +$Comp +L fzzt-rescue:IXDN609PI-ixdn609pi U4 +U 1 1 6170DA36 +P 8100 4600 +F 0 "U4" H 8100 5167 50 0000 C CNN +F 1 "IXDN609PI" H 8100 5076 50 0000 C CNN +F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 8100 4100 50 0001 C CNN +F 3 "" H 8100 4600 50 0001 C CNN + 1 8100 4600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7100 3750 7100 3200 +Wire Wire Line + 7100 3200 7800 3200 +Wire Wire Line + 7100 4500 7800 4500 +Wire Wire Line + 8400 3200 8850 3200 +Wire Wire Line + 8400 4500 8850 4500 +$Comp +L Device:C C1 +U 1 1 617245F7 +P 7500 3450 +F 0 "C1" H 7615 3496 50 0000 L CNN +F 1 "220n" H 7615 3405 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 7538 3300 50 0001 C CNN +F 3 "~" H 7500 3450 50 0001 C CNN + 1 7500 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 3300 7500 3000 +Wire Wire Line + 7500 3000 7700 3000 +Wire Wire Line + 7500 3600 7700 3600 +$Comp +L power:GND #PWR0105 +U 1 1 61726114 +P 7500 3600 +F 0 "#PWR0105" H 7500 3350 50 0001 C CNN +F 1 "GND" H 7505 3427 50 0000 C CNN +F 2 "" H 7500 3600 50 0001 C CNN +F 3 "" H 7500 3600 50 0001 C CNN + 1 7500 3600 + 1 0 0 -1 +$EndComp +Connection ~ 7500 3600 +$Comp +L Device:C C2 +U 1 1 617264A4 +P 7500 4750 +F 0 "C2" H 7615 4796 50 0000 L CNN +F 1 "220n" H 7615 4705 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 7538 4600 50 0001 C CNN +F 3 "~" H 7500 4750 50 0001 C CNN + 1 7500 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 4600 7500 4300 +Wire Wire Line + 7500 4300 7800 4300 +Wire Wire Line + 7500 4900 7800 4900 +$Comp +L power:GND #PWR0106 +U 1 1 617281DD +P 7500 4900 +F 0 "#PWR0106" H 7500 4650 50 0001 C CNN +F 1 "GND" H 7505 4727 50 0000 C CNN +F 2 "" H 7500 4900 50 0001 C CNN +F 3 "" H 7500 4900 50 0001 C CNN + 1 7500 4900 + 1 0 0 -1 +$EndComp +Connection ~ 7500 4900 +Wire Wire Line + 8400 4700 8400 4500 +Connection ~ 8400 4500 +Wire Wire Line + 8400 3400 8400 3200 +Connection ~ 8400 3200 +$Comp +L Oscillator:Si5351A-B-GT U2 +U 1 1 61BD2F46 +P 6150 3950 +F 0 "U2" H 6150 3361 50 0000 C CNN +F 1 "Si5351A-B-GT" H 6150 3270 50 0000 C CNN +F 2 "Package_SO:MSOP-10_3x3mm_P0.5mm" H 6150 3150 50 0001 C CNN +F 3 "https://www.silabs.com/documents/public/data-sheets/Si5351-B.pdf" H 5800 3850 50 0001 C CNN + 1 6150 3950 + 1 0 0 -1 +$EndComp +$Comp +L cesco:STM32G031J6Mx U1 +U 1 1 61BD7233 +P 3450 3600 +F 0 "U1" H 3475 3665 50 0000 C CNN +F 1 "STM32G031J6Mx" H 3475 3574 50 0000 C CNN +F 2 "Package_SO:SO-8_3.9x4.9mm_P1.27mm" H 3450 3600 50 0001 C CNN +F 3 "" H 3450 3600 50 0001 C CNN + 1 3450 3600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6650 3750 7100 3750 +Wire Wire Line + 6650 3950 7100 3950 +Wire Wire Line + 7100 3950 7100 4500 +Wire Wire Line + 4400 4250 4850 4250 +Wire Wire Line + 4400 4100 4550 4100 +$Comp +L power:+3.3V #PWR0107 +U 1 1 61C06B8F +P 2250 3300 +F 0 "#PWR0107" H 2250 3150 50 0001 C CNN +F 1 "+3.3V" H 2265 3473 50 0000 C CNN +F 2 "" H 2250 3300 50 0001 C CNN +F 3 "" H 2250 3300 50 0001 C CNN + 1 2250 3300 + 1 0 0 -1 +$EndComp +$Comp +L power:+12V #PWR0108 +U 1 1 61C0789A +P 7500 3000 +F 0 "#PWR0108" H 7500 2850 50 0001 C CNN +F 1 "+12V" H 7515 3173 50 0000 C CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical" H 7500 3000 50 0001 C CNN +F 3 "" H 7500 3000 50 0001 C CNN + 1 7500 3000 + 1 0 0 -1 +$EndComp +Connection ~ 7500 3000 +$Comp +L power:+12V #PWR0109 +U 1 1 61C0CC6C +P 7500 4300 +F 0 "#PWR0109" H 7500 4150 50 0001 C CNN +F 1 "+12V" H 7515 4473 50 0000 C CNN +F 2 "" H 7500 4300 50 0001 C CNN +F 3 "" H 7500 4300 50 0001 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +Connection ~ 7500 4300 +$Comp +L power:+3.3V #PWR0110 +U 1 1 61C0D708 +P 5750 3050 +F 0 "#PWR0110" H 5750 2900 50 0001 C CNN +F 1 "+3.3V" H 5765 3223 50 0000 C CNN +F 2 "" H 5750 3050 50 0001 C CNN +F 3 "" H 5750 3050 50 0001 C CNN + 1 5750 3050 + 1 0 0 -1 +$EndComp +$Comp +L Switch:SW_Push SW1 +U 1 1 61C14AD4 +P 2400 3500 +F 0 "SW1" V 2354 3648 50 0000 L CNN +F 1 "SW_Push" V 2445 3648 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" H 2400 3700 50 0001 C CNN +F 3 "~" H 2400 3700 50 0001 C CNN + 1 2400 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 2250 3300 2400 3300 +Wire Wire Line + 2250 3300 2250 3700 +Wire Wire Line + 2250 3950 2550 3950 +Connection ~ 2250 3300 +Wire Wire Line + 2400 3700 2400 3800 +Wire Wire Line + 2400 3800 2550 3800 +$Comp +L power:GND #PWR0111 +U 1 1 61C16FEF +P 2250 4100 +F 0 "#PWR0111" H 2250 3850 50 0001 C CNN +F 1 "GND" H 2255 3927 50 0000 C CNN +F 2 "" H 2250 4100 50 0001 C CNN +F 3 "" H 2250 4100 50 0001 C CNN + 1 2250 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2250 4100 2550 4100 +$Comp +L power:GND #PWR0112 +U 1 1 61C17CF1 +P 6150 4450 +F 0 "#PWR0112" H 6150 4200 50 0001 C CNN +F 1 "GND" H 6155 4277 50 0000 C CNN +F 2 "" H 6150 4450 50 0001 C CNN +F 3 "" H 6150 4450 50 0001 C CNN + 1 6150 4450 + 1 0 0 -1 +$EndComp +$Comp +L Device:Crystal Y1 +U 1 1 61C18A07 +P 5250 3750 +F 0 "Y1" V 5296 3881 50 0000 L CNN +F 1 "25MHz" V 5205 3881 50 0000 L CNN +F 2 "Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm" H 5250 3750 50 0001 C CNN +F 3 "~" H 5250 3750 50 0001 C CNN + 1 5250 3750 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5650 3600 5650 3650 +Wire Wire Line + 5250 3900 5650 3900 +Wire Wire Line + 5650 3900 5650 3850 +Wire Wire Line + 5250 3600 5650 3600 +$Comp +L Connector:Conn_01x01_Female J1 +U 1 1 61C293CA +P 9050 3200 +F 0 "J1" H 9078 3226 50 0000 L CNN +F 1 "Conn_01x01_Female" H 9078 3135 50 0000 L CNN +F 2 "Connector_PinSocket_2.54mm:PinSocket_1x01_P2.54mm_Vertical" H 9050 3200 50 0001 C CNN +F 3 "~" H 9050 3200 50 0001 C CNN + 1 9050 3200 + 1 0 0 -1 +$EndComp +$Comp +L Connector:Conn_01x01_Female J2 +U 1 1 61C2A1B5 +P 9050 4500 +F 0 "J2" H 9078 4526 50 0000 L CNN +F 1 "Conn_01x01_Female" H 9078 4435 50 0000 L CNN +F 2 "Connector_PinSocket_2.54mm:PinSocket_1x01_P2.54mm_Vertical" H 9050 4500 50 0001 C CNN +F 3 "~" H 9050 4500 50 0001 C CNN + 1 9050 4500 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C4 +U 1 1 61C2AF29 +P 5750 3200 +F 0 "C4" H 5865 3246 50 0000 L CNN +F 1 "150n" H 5865 3155 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 5788 3050 50 0001 C CNN +F 3 "~" H 5750 3200 50 0001 C CNN + 1 5750 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:C C3 +U 1 1 61C2BA36 +P 1750 3850 +F 0 "C3" H 1865 3896 50 0000 L CNN +F 1 "150n" H 1865 3805 50 0000 L CNN +F 2 "Capacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder" H 1788 3700 50 0001 C CNN +F 3 "~" H 1750 3850 50 0001 C CNN + 1 1750 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 3700 2250 3700 +Connection ~ 2250 3700 +Wire Wire Line + 2250 3700 2250 3950 +$Comp +L power:GND #PWR0101 +U 1 1 61C2CAF4 +P 1750 4000 +F 0 "#PWR0101" H 1750 3750 50 0001 C CNN +F 1 "GND" H 1755 3827 50 0000 C CNN +F 2 "" H 1750 4000 50 0001 C CNN +F 3 "" H 1750 4000 50 0001 C CNN + 1 1750 4000 + 1 0 0 -1 +$EndComp +$Comp +L power:GND #PWR0102 +U 1 1 61C30EE8 +P 5750 3350 +F 0 "#PWR0102" H 5750 3100 50 0001 C CNN +F 1 "GND" H 5755 3177 50 0000 C CNN +F 2 "" H 5750 3350 50 0001 C CNN +F 3 "" H 5750 3350 50 0001 C CNN + 1 5750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5750 3050 6050 3050 +Wire Wire Line + 6050 3050 6050 3450 +Connection ~ 5750 3050 +Wire Wire Line + 6250 3450 6250 3050 +$Comp +L Regulator_Linear:LM1117-3.3 U5 +U 1 1 61C40422 +P 4450 2300 +F 0 "U5" H 4450 2542 50 0000 C CNN +F 1 "LM1117-3.3" H 4450 2451 50 0000 C CNN +F 2 "Package_TO_SOT_SMD:TO-252-3_TabPin2" H 4450 2300 50 0001 C CNN +F 3 "http://www.ti.com/lit/ds/symlink/lm1117.pdf" H 4450 2300 50 0001 C CNN + 1 4450 2300 + 1 0 0 -1 +$EndComp +$Comp +L power:+12V #PWR0113 +U 1 1 61C412FB +P 4150 2300 +F 0 "#PWR0113" H 4150 2150 50 0001 C CNN +F 1 "+12V" V 4165 2428 50 0000 L CNN +F 2 "Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical" H 4150 2300 50 0001 C CNN +F 3 "" H 4150 2300 50 0001 C CNN + 1 4150 2300 + 0 -1 -1 0 +$EndComp +$Comp +L power:GND #PWR0114 +U 1 1 61C42002 +P 4450 2600 +F 0 "#PWR0114" H 4450 2350 50 0001 C CNN +F 1 "GND" H 4455 2427 50 0000 C CNN +F 2 "" H 4450 2600 50 0001 C CNN +F 3 "" H 4450 2600 50 0001 C CNN + 1 4450 2600 + 1 0 0 -1 +$EndComp +$Comp +L power:+3.3V #PWR0115 +U 1 1 61C425A8 +P 4750 2300 +F 0 "#PWR0115" H 4750 2150 50 0001 C CNN +F 1 "+3.3V" V 4765 2428 50 0000 L CNN +F 2 "" H 4750 2300 50 0001 C CNN +F 3 "" H 4750 2300 50 0001 C CNN + 1 4750 2300 + 0 1 -1 0 +$EndComp +Wire Wire Line + 6050 3050 6250 3050 +Connection ~ 6050 3050 +$Comp +L Device:R R? +U 1 1 61BED99B +P 4550 3200 +F 0 "R?" H 4620 3246 50 0000 L CNN +F 1 "5k6" H 4620 3155 50 0000 L CNN +F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder" V 4480 3200 50 0001 C CNN +F 3 "~" H 4550 3200 50 0001 C CNN + 1 4550 3200 + 1 0 0 -1 +$EndComp +$Comp +L Device:R R? +U 1 1 61BEE388 +P 4850 3200 +F 0 "R?" H 4920 3246 50 0000 L CNN +F 1 "5k6" H 4920 3155 50 0000 L CNN +F 2 "Resistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder" V 4780 3200 50 0001 C CNN +F 3 "~" H 4850 3200 50 0001 C CNN + 1 4850 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 3050 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 4850 3050 5750 3050 +Wire Wire Line + 4550 3350 4550 4100 +Wire Wire Line + 4850 3350 4850 4250 +Wire Wire Line + 7700 3600 7700 3800 +Wire Wire Line + 7700 3800 8400 3800 +Wire Wire Line + 8400 3800 8400 3600 +Connection ~ 7700 3600 +Wire Wire Line + 7700 3600 7800 3600 +Wire Wire Line + 7700 3000 7700 2650 +Wire Wire Line + 7700 2650 8400 2650 +Wire Wire Line + 8400 2650 8400 3000 +Connection ~ 7700 3000 +Wire Wire Line + 7700 3000 7800 3000 +Wire Wire Line + 4850 4250 5200 4250 +Wire Wire Line + 5200 4250 5200 4150 +Wire Wire Line + 5200 4150 5650 4150 +Connection ~ 4850 4250 +Wire Wire Line + 4550 4100 5400 4100 +Wire Wire Line + 5400 4100 5400 4250 +Wire Wire Line + 5400 4250 5650 4250 +Connection ~ 4550 4100 +$EndSCHEMATC diff --git a/hw/ixdn609pi.dcm b/hw/ixdn609pi.dcm new file mode 100644 index 0000000..8fa19c9 --- /dev/null +++ b/hw/ixdn609pi.dcm @@ -0,0 +1,10 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP IXDN609PI +D 9-Ampere Low-Side +Ultrafast MOSFET Driver +K Gate Driver +F http://www.onsemi.com/pub/Collateral/FAN7842-D.pdf +$ENDCMP +# +#End Doc Library diff --git a/hw/ixdn609pi.lib b/hw/ixdn609pi.lib new file mode 100644 index 0000000..1e3fb06 --- /dev/null +++ b/hw/ixdn609pi.lib @@ -0,0 +1,27 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# IXDN609PI +# +DEF IXDN609PI U 0 20 Y Y 1 F N +F0 "U" 0 550 50 H V C CNN +F1 "IXDN609PI" 0 450 50 H V C CNN +F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + SOIC*3.9x4.9mm*P1.27mm* +$ENDFPLIST +DRAW +S -200 400 200 -400 0 1 10 f +X VCC 1 -300 300 100 R 50 50 1 1 W +X IN 2 -300 100 100 R 50 50 1 1 I +X NC 3 -300 -100 100 R 50 50 1 1 N +X GND 4 -300 -300 100 R 50 50 1 1 W +X GND 5 300 -300 100 L 50 50 1 1 W +X OUT 6 300 -100 100 L 50 50 1 1 O +X OUT 7 300 100 100 L 50 50 1 1 O +X VCC 8 300 300 100 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/hw/sym-lib-table b/hw/sym-lib-table new file mode 100644 index 0000000..37de98c --- /dev/null +++ b/hw/sym-lib-table @@ -0,0 +1,4 @@ +(sym_lib_table + (lib (name ixdn609pi)(type Legacy)(uri ${KIPRJMOD}/ixdn609pi.lib)(options "")(descr "")) + (lib (name fzzt-rescue)(type Legacy)(uri ${KIPRJMOD}/fzzt-rescue.lib)(options "")(descr "")) +) diff --git a/note.txt b/note.txt new file mode 100644 index 0000000..f298688 --- /dev/null +++ b/note.txt @@ -0,0 +1,14 @@ +https://www.researchgate.net/figure/Proposed-push-pull-Class-E-PA_fig1_3451465 + +# driver +http://www.classeradio.com/driver.htm + +ZXGD3006E6TA 40V 10A GATE DRIVER IN SOT26 +IXDD414PI 14A Low-Side Ultrafast MOSFET Driver in DIP8 (obsoleto) +IXDN614PI 14A DIP8 2,09 € +IXDN614CI 14A TO220 4,11 € +IXDN609CI 9A Low-Side TO220 2,57 € +IXDN609PI 9A Low-Side DIP-8 1,40 € (presi) + +# mosfet +STF5N60M2 600V 3,7A Rdson 1,4Ω, Ciss 165Ω (presi) diff --git a/squero/.mxproject b/squero/.mxproject new file mode 100644 index 0000000..c03d220 --- /dev/null +++ b/squero/.mxproject @@ -0,0 +1,25 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm7.h; + +[PreviousUsedMakefileFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32g0xx_it.c;Core/Src/stm32g0xx_hal_msp.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;Core/Src/system_stm32g0xx.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;Core/Src/system_stm32g0xx.c;;; +HeaderPath=Drivers/STM32G0xx_HAL_Driver/Inc;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32G0xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_HAL_DRIVER;STM32G031xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=3 +HeaderFiles#0=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Inc/stm32g0xx_it.h +HeaderFiles#1=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Inc/stm32g0xx_hal_conf.h +HeaderFiles#2=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Inc +HeaderFiles=; +SourceFileListSize=3 +SourceFiles#0=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Src/stm32g0xx_it.c +SourceFiles#1=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Src/stm32g0xx_hal_msp.c +SourceFiles#2=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=/home/fra/Documenti/tech/sviluppo/telecom/radio/squero/squero/Core/Src +SourceFiles=; + diff --git a/squero/Core/Inc/main.h b/squero/Core/Inc/main.h new file mode 100644 index 0000000..fd9df66 --- /dev/null +++ b/squero/Core/Inc/main.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define UP_Pin GPIO_PIN_14 +#define UP_GPIO_Port GPIOC +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/squero/Core/Inc/si5351.h b/squero/Core/Inc/si5351.h new file mode 100644 index 0000000..f862683 --- /dev/null +++ b/squero/Core/Inc/si5351.h @@ -0,0 +1,330 @@ +/**************************************************************************/ +/*! + @file Adafruit_SI5351.h + @author K. Townsend (Adafruit Industries) + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2014, Adafruit Industries + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ +#ifndef _SI5351_H_ +#define _SI5351_H_ + + +extern I2C_HandleTypeDef hi2c2; +#include "si5351_errors.h" +#include "si5351_asserts.h" + + +#define SI5351_ADDRESS (0x60) // Assumes ADDR pin = low +#define SI5351_READBIT (0x01) + +#define USE_FULL_ASSERT (0x01) + +/* Test setup from SI5351 ClockBuilder + * ----------------------------------- + * XTAL: 25 MHz + * Channel 0: 120.00 MHz + * Channel 1: 12.00 MHz + * Channel 2: 13.56 MHz + */ +static const uint8_t m_si5351_regs_15to92_149to170[100][2] = +{ + { 15, 0x00 }, /* Input source = crystal for PLLA and PLLB */ + { 16, 0x4F }, /* CLK0 Control: 8mA drive, Multisynth 0 as CLK0 source, Clock not inverted, Source = PLLA, Multisynth 0 in integer mode, clock powered up */ + { 17, 0x4F }, /* CLK1 Control: 8mA drive, Multisynth 1 as CLK1 source, Clock not inverted, Source = PLLA, Multisynth 1 in integer mode, clock powered up */ + { 18, 0x6F }, /* CLK2 Control: 8mA drive, Multisynth 2 as CLK2 source, Clock not inverted, Source = PLLB, Multisynth 2 in integer mode, clock powered up */ + { 19, 0x80 }, /* CLK3 Control: Not used ... clock powered down */ + { 20, 0x80 }, /* CLK4 Control: Not used ... clock powered down */ + { 21, 0x80 }, /* CLK5 Control: Not used ... clock powered down */ + { 22, 0x80 }, /* CLK6 Control: Not used ... clock powered down */ + { 23, 0x80 }, /* CLK7 Control: Not used ... clock powered down */ + { 24, 0x00 }, /* Clock disable state 0..3 (low when disabled) */ + { 25, 0x00 }, /* Clock disable state 4..7 (low when disabled) */ + /* PLL_A Setup */ + { 26, 0x00 }, + { 27, 0x05 }, + { 28, 0x00 }, + { 29, 0x0C }, + { 30, 0x66 }, + { 31, 0x00 }, + { 32, 0x00 }, + { 33, 0x02 }, + /* PLL_B Setup */ + { 34, 0x02 }, + { 35, 0x71 }, + { 36, 0x00 }, + { 37, 0x0C }, + { 38, 0x1A }, + { 39, 0x00 }, + { 40, 0x00 }, + { 41, 0x86 }, + /* Multisynth Setup */ + { 42, 0x00 }, + { 43, 0x01 }, + { 44, 0x00 }, + { 45, 0x01 }, + { 46, 0x00 }, + { 47, 0x00 }, + { 48, 0x00 }, + { 49, 0x00 }, + { 50, 0x00 }, + { 51, 0x01 }, + { 52, 0x00 }, + { 53, 0x1C }, + { 54, 0x00 }, + { 55, 0x00 }, + { 56, 0x00 }, + { 57, 0x00 }, + { 58, 0x00 }, + { 59, 0x01 }, + { 60, 0x00 }, + { 61, 0x18 }, + { 62, 0x00 }, + { 63, 0x00 }, + { 64, 0x00 }, + { 65, 0x00 }, + { 66, 0x00 }, + { 67, 0x00 }, + { 68, 0x00 }, + { 69, 0x00 }, + { 70, 0x00 }, + { 71, 0x00 }, + { 72, 0x00 }, + { 73, 0x00 }, + { 74, 0x00 }, + { 75, 0x00 }, + { 76, 0x00 }, + { 77, 0x00 }, + { 78, 0x00 }, + { 79, 0x00 }, + { 80, 0x00 }, + { 81, 0x00 }, + { 82, 0x00 }, + { 83, 0x00 }, + { 84, 0x00 }, + { 85, 0x00 }, + { 86, 0x00 }, + { 87, 0x00 }, + { 88, 0x00 }, + { 89, 0x00 }, + { 90, 0x00 }, + { 91, 0x00 }, + { 92, 0x00 }, + /* Misc Config Register */ + { 149, 0x00 }, + { 150, 0x00 }, + { 151, 0x00 }, + { 152, 0x00 }, + { 153, 0x00 }, + { 154, 0x00 }, + { 155, 0x00 }, + { 156, 0x00 }, + { 157, 0x00 }, + { 158, 0x00 }, + { 159, 0x00 }, + { 160, 0x00 }, + { 161, 0x00 }, + { 162, 0x00 }, + { 163, 0x00 }, + { 164, 0x00 }, + { 165, 0x00 }, + { 166, 0x00 }, + { 167, 0x00 }, + { 168, 0x00 }, + { 169, 0x00 }, + { 170, 0x00 } +}; + +/* See http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf for registers 26..41 */ +enum +{ + SI5351_REGISTER_0_DEVICE_STATUS = 0, + SI5351_REGISTER_1_INTERRUPT_STATUS_STICKY = 1, + SI5351_REGISTER_2_INTERRUPT_STATUS_MASK = 2, + SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL = 3, + SI5351_REGISTER_9_OEB_PIN_ENABLE_CONTROL = 9, + SI5351_REGISTER_15_PLL_INPUT_SOURCE = 15, + SI5351_REGISTER_16_CLK0_CONTROL = 16, + SI5351_REGISTER_17_CLK1_CONTROL = 17, + SI5351_REGISTER_18_CLK2_CONTROL = 18, + SI5351_REGISTER_19_CLK3_CONTROL = 19, + SI5351_REGISTER_20_CLK4_CONTROL = 20, + SI5351_REGISTER_21_CLK5_CONTROL = 21, + SI5351_REGISTER_22_CLK6_CONTROL = 22, + SI5351_REGISTER_23_CLK7_CONTROL = 23, + SI5351_REGISTER_24_CLK3_0_DISABLE_STATE = 24, + SI5351_REGISTER_25_CLK7_4_DISABLE_STATE = 25, + SI5351_REGISTER_42_MULTISYNTH0_PARAMETERS_1 = 42, + SI5351_REGISTER_43_MULTISYNTH0_PARAMETERS_2 = 43, + SI5351_REGISTER_44_MULTISYNTH0_PARAMETERS_3 = 44, + SI5351_REGISTER_45_MULTISYNTH0_PARAMETERS_4 = 45, + SI5351_REGISTER_46_MULTISYNTH0_PARAMETERS_5 = 46, + SI5351_REGISTER_47_MULTISYNTH0_PARAMETERS_6 = 47, + SI5351_REGISTER_48_MULTISYNTH0_PARAMETERS_7 = 48, + SI5351_REGISTER_49_MULTISYNTH0_PARAMETERS_8 = 49, + SI5351_REGISTER_50_MULTISYNTH1_PARAMETERS_1 = 50, + SI5351_REGISTER_51_MULTISYNTH1_PARAMETERS_2 = 51, + SI5351_REGISTER_52_MULTISYNTH1_PARAMETERS_3 = 52, + SI5351_REGISTER_53_MULTISYNTH1_PARAMETERS_4 = 53, + SI5351_REGISTER_54_MULTISYNTH1_PARAMETERS_5 = 54, + SI5351_REGISTER_55_MULTISYNTH1_PARAMETERS_6 = 55, + SI5351_REGISTER_56_MULTISYNTH1_PARAMETERS_7 = 56, + SI5351_REGISTER_57_MULTISYNTH1_PARAMETERS_8 = 57, + SI5351_REGISTER_58_MULTISYNTH2_PARAMETERS_1 = 58, + SI5351_REGISTER_59_MULTISYNTH2_PARAMETERS_2 = 59, + SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3 = 60, + SI5351_REGISTER_61_MULTISYNTH2_PARAMETERS_4 = 61, + SI5351_REGISTER_62_MULTISYNTH2_PARAMETERS_5 = 62, + SI5351_REGISTER_63_MULTISYNTH2_PARAMETERS_6 = 63, + SI5351_REGISTER_64_MULTISYNTH2_PARAMETERS_7 = 64, + SI5351_REGISTER_65_MULTISYNTH2_PARAMETERS_8 = 65, + SI5351_REGISTER_66_MULTISYNTH3_PARAMETERS_1 = 66, + SI5351_REGISTER_67_MULTISYNTH3_PARAMETERS_2 = 67, + SI5351_REGISTER_68_MULTISYNTH3_PARAMETERS_3 = 68, + SI5351_REGISTER_69_MULTISYNTH3_PARAMETERS_4 = 69, + SI5351_REGISTER_70_MULTISYNTH3_PARAMETERS_5 = 70, + SI5351_REGISTER_71_MULTISYNTH3_PARAMETERS_6 = 71, + SI5351_REGISTER_72_MULTISYNTH3_PARAMETERS_7 = 72, + SI5351_REGISTER_73_MULTISYNTH3_PARAMETERS_8 = 73, + SI5351_REGISTER_74_MULTISYNTH4_PARAMETERS_1 = 74, + SI5351_REGISTER_75_MULTISYNTH4_PARAMETERS_2 = 75, + SI5351_REGISTER_76_MULTISYNTH4_PARAMETERS_3 = 76, + SI5351_REGISTER_77_MULTISYNTH4_PARAMETERS_4 = 77, + SI5351_REGISTER_78_MULTISYNTH4_PARAMETERS_5 = 78, + SI5351_REGISTER_79_MULTISYNTH4_PARAMETERS_6 = 79, + SI5351_REGISTER_80_MULTISYNTH4_PARAMETERS_7 = 80, + SI5351_REGISTER_81_MULTISYNTH4_PARAMETERS_8 = 81, + SI5351_REGISTER_82_MULTISYNTH5_PARAMETERS_1 = 82, + SI5351_REGISTER_83_MULTISYNTH5_PARAMETERS_2 = 83, + SI5351_REGISTER_84_MULTISYNTH5_PARAMETERS_3 = 84, + SI5351_REGISTER_85_MULTISYNTH5_PARAMETERS_4 = 85, + SI5351_REGISTER_86_MULTISYNTH5_PARAMETERS_5 = 86, + SI5351_REGISTER_87_MULTISYNTH5_PARAMETERS_6 = 87, + SI5351_REGISTER_88_MULTISYNTH5_PARAMETERS_7 = 88, + SI5351_REGISTER_89_MULTISYNTH5_PARAMETERS_8 = 89, + SI5351_REGISTER_90_MULTISYNTH6_PARAMETERS = 90, + SI5351_REGISTER_91_MULTISYNTH7_PARAMETERS = 91, + SI5351_REGISTER_092_CLOCK_6_7_OUTPUT_DIVIDER = 92, + SI5351_REGISTER_165_CLK0_INITIAL_PHASE_OFFSET = 165, + SI5351_REGISTER_166_CLK1_INITIAL_PHASE_OFFSET = 166, + SI5351_REGISTER_167_CLK2_INITIAL_PHASE_OFFSET = 167, + SI5351_REGISTER_168_CLK3_INITIAL_PHASE_OFFSET = 168, + SI5351_REGISTER_169_CLK4_INITIAL_PHASE_OFFSET = 169, + SI5351_REGISTER_170_CLK5_INITIAL_PHASE_OFFSET = 170, + SI5351_REGISTER_177_PLL_RESET = 177, + SI5351_REGISTER_183_CRYSTAL_INTERNAL_LOAD_CAPACITANCE = 183 +}; + +typedef enum +{ + SI5351_PLL_A = 0, + SI5351_PLL_B, +} si5351PLL_t; + +typedef enum +{ + SI5351_CRYSTAL_LOAD_6PF = (1<<6), + SI5351_CRYSTAL_LOAD_8PF = (2<<6), + SI5351_CRYSTAL_LOAD_10PF = (3<<6) +} si5351CrystalLoad_t; + +typedef enum +{ + SI5351_CRYSTAL_FREQ_24MHZ = (24000000), + SI5351_CRYSTAL_FREQ_25MHZ = (25000000), + SI5351_CRYSTAL_FREQ_27MHZ = (27000000) +} si5351CrystalFreq_t; + +typedef enum +{ + SI5351_MULTISYNTH_DIV_4 = 4, + SI5351_MULTISYNTH_DIV_6 = 6, + SI5351_MULTISYNTH_DIV_8 = 8 +} si5351MultisynthDiv_t; + +typedef enum +{ + SI5351_R_DIV_1 = 0, + SI5351_R_DIV_2 = 1, + SI5351_R_DIV_4 = 2, + SI5351_R_DIV_8 = 3, + SI5351_R_DIV_16 = 4, + SI5351_R_DIV_32 = 5, + SI5351_R_DIV_64 = 6, + SI5351_R_DIV_128 = 7, +} si5351RDiv_t; + +typedef struct +{ + uint8_t initialised; + si5351CrystalFreq_t crystalFreq; + si5351CrystalLoad_t crystalLoad; + uint32_t crystalPPM; + uint8_t plla_configured; + uint32_t plla_freq; + uint8_t pllb_configured; + uint32_t pllb_freq; + uint32_t ms0_freq; + uint32_t ms1_freq; + uint32_t ms2_freq; + uint32_t ms0_r_div; + uint32_t ms1_r_div; + uint32_t ms2_r_div; +} si5351Config_t; + + + + err_t si5351_Init(void); + err_t si5351_setupPLL(si5351PLL_t pll, uint8_t mult, uint32_t num, uint32_t denom); + err_t si5351_setupPLLInt(si5351PLL_t pll, uint8_t mult); + err_t si5351_setupMultisynth(uint8_t output, si5351PLL_t pllSource, uint32_t div, uint32_t num, uint32_t denom); + err_t si5351_setupMultisynthInt(uint8_t output, si5351PLL_t pllSource, si5351MultisynthDiv_t div); + err_t si5351_enableOutputs(uint8_t enabled); + err_t si5351_setupRdiv(uint8_t output, si5351RDiv_t div); + + +extern si5351Config_t m_si5351Config; + + err_t si5351_write8(uint8_t reg, uint8_t value); + err_t si5351_read8(uint8_t reg, uint8_t *value); + +#endif + +/* + + The VCO frequency can only be from 600 MHz to 900 MHz. Yes, over-clocking is possible, and so in under-clocking, to extend the output frequency range beyond 2,3 kHz to 200 MHz. But let’s leave this for now. + The FMD ratio can be from 15 + 0/1 048 575 and to 90 + 0/1 048 575, i.e. a = 15, b = 0 and c = 1 048 575 to a = 90, b = 0 and c = 1 048 575. Please remember that c can never be zero (0), as this will violate fundamental math principles. + The OMD ratio can be 4 and from 6 to 2048. Please remember that f can never be zero (0), as this will violate fundamental math principles. + The R divider can only be 1, 2, 4, 8, 16, 32, 64 or 128. + If the output frequency is above 150 MHz d is always 4. + If the output frequency is below 500 kHz R should be used, i.e. higher than 1. + +https://www.rfzero.net/documentation/tools/si5351a-frequency-tool/ +*/ diff --git a/squero/Core/Inc/si5351_asserts.h b/squero/Core/Inc/si5351_asserts.h new file mode 100644 index 0000000..5c8924f --- /dev/null +++ b/squero/Core/Inc/si5351_asserts.h @@ -0,0 +1,84 @@ +/**************************************************************************/ +/*! + @file si5351_asserts.h + @author K. Townsend (Adafruit Industries) + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2014, Adafruit Industries + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ +#ifndef _ASSERTS_H_ +#define _ASSERTS_H_ + +#include "si5351_errors.h" + +/**************************************************************************/ +/*! + @brief Checks the condition, and if the assert fails the supplied + returnValue will be returned in the calling function. + + @code + // Make sure 'addr' is within range + ASSERT(addr <= MAX_ADDR, ERROR_ADDRESSOUTOFRANGE); + @endcode +*/ +/**************************************************************************/ +#define ASSERT(condition, returnValue) \ + do{\ + if (!(condition)) {\ + return (returnValue);\ + }\ + }while(0) + +/**************************************************************************/ +/*! + @brief Checks the supplied \ref err_t value (sts), and if it is + not equal to \ref ERROR_NONE the sts value will be returned. + + @details + This macro is useful to check if a function returned an error without + bloating your own code with endless "if (error) {...}". + + @code + // If anything other than ERROR_NONE is returned by si5351a + // this macro will log the error and exit the function returning the + // error_t value. + ASSERT_STATUS(si5351_Init()); + @endcode +*/ +/**************************************************************************/ +#define ASSERT_STATUS(sts) \ + do{\ + err_t status = (sts);\ + if (ERROR_NONE != status) {\ + return status;\ + }\ + } while(0) + +#endif diff --git a/squero/Core/Inc/si5351_errors.h b/squero/Core/Inc/si5351_errors.h new file mode 100644 index 0000000..5753b12 --- /dev/null +++ b/squero/Core/Inc/si5351_errors.h @@ -0,0 +1,67 @@ +/**************************************************************************/ +/*! + @file errors.h + @author K. Townsend (Adafruit Industries) + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2014, Adafruit Industries + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ +#ifndef _ERRORS_H_ +#define _ERRORS_H_ + +typedef enum +{ + /*======================================================================= + GENERIC ERRORS 0x0000 .. 0x00FF + ----------------------------------------------------------------------- + These error codes can be used anywhere in the system + -----------------------------------------------------------------------*/ + ERROR_NONE = 0x0, /**< Indicates no error occurred */ + ERROR_OPERATIONTIMEDOUT = 0x1, /**< Operation timed out before completion */ + ERROR_ADDRESSOUTOFRANGE = 0x2, /**< The supplied address is out of range */ + ERROR_BUFFEROVERFLOW = 0x3, /**< The proposed action will cause a buffer overflow */ + ERROR_INVALIDPARAMETER = 0x4, /**< An invalid parameter value was provided */ + ERROR_DEVICENOTINITIALISED = 0x5, /**< Attempting to execute a function on an uninitialised peripheral */ + ERROR_UNEXPECTEDVALUE = 0x6, /**< An unexpected value was found inside a function */ + /*=======================================================================*/ + + + /*======================================================================= + I2C ERRORS 0x0100 .. 0x010F + ----------------------------------------------------------------------- + Errors related to the I2C bus + -----------------------------------------------------------------------*/ + ERROR_I2C_DEVICENOTFOUND = 0x101, /**< Device didn't ACK after an I2C transfer */ + ERROR_I2C_NOACK = 0x102, /**< No ACK signal received during an I2C transfer */ + ERROR_I2C_TIMEOUT = 0x103, /**< Device timed out waiting for response (missing pullups?) */ + /*=======================================================================*/ +} err_t; + +#endif diff --git a/squero/Core/Inc/stm32g0xx_hal_conf.h b/squero/Core/Inc/stm32g0xx_hal_conf.h new file mode 100644 index 0000000..c05f5fa --- /dev/null +++ b/squero/Core/Inc/stm32g0xx_hal_conf.h @@ -0,0 +1,351 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CONF_H +#define STM32G0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u +#define USE_HAL_HCD_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_PCD_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ +#endif + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief External clock source for I2S2 peripheral + * This value is used by the RCC HAL module to compute the I2S2 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S2_CLOCK_VALUE) + #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/ +#endif /* EXTERNAL_I2S2_CLOCK_VALUE */ +#endif + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g0xx_hal_adc.h" +#include "stm32g0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32g0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g0xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32g0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CONF_H */ diff --git a/squero/Core/Inc/stm32g0xx_it.h b/squero/Core/Inc/stm32g0xx_it.h new file mode 100644 index 0000000..fa21540 --- /dev/null +++ b/squero/Core/Inc/stm32g0xx_it.h @@ -0,0 +1,62 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G0xx_IT_H +#define __STM32G0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G0xx_IT_H */ diff --git a/squero/Core/Src/main.c b/squero/Core/Src/main.c new file mode 100644 index 0000000..50d9cd8 --- /dev/null +++ b/squero/Core/Src/main.c @@ -0,0 +1,295 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include "si5351.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +I2C_HandleTypeDef hi2c2; + +/* USER CODE BEGIN PV */ +uint32_t frequenza; + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_I2C2_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_I2C2_Init(); + /* USER CODE BEGIN 2 */ + frequenza = 1359000; + HAL_Delay(100); + si5351_Init(); + HAL_Delay(500); + CalcRegisters(frequenza); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + + +// HAL_I2C_Master_Transmit(&hi2c2, ((uint16_t)0x60)<<1, "ciao", 4, HAL_MAX_DELAY); + // da 24 a 36 +/* + a = 24; + b = 28437; + c = 1048562; + d = 442; + e = 0; + f = 1; + */ +/* + si5351_setupPLL(SI5351_PLL_A, a, b, c); + HAL_Delay(10); + si5351_setupMultisynth(0, SI5351_PLL_A, d, e, f); + HAL_Delay(10); + si5351_setupRdiv(0, SI5351_R_DIV_1); + HAL_Delay(10); + + si5351_setupMultisynth(1, SI5351_PLL_A, d, e, f); + HAL_Delay(10); + si5351_setupRdiv(1, SI5351_R_DIV_1); + HAL_Delay(10); +*/ + if(HAL_GPIO_ReadPin(UP_GPIO_Port, UP_Pin)){ + frequenza += 9000; + if(frequenza > 1800000) frequenza = 585000; + CalcRegisters(frequenza); + } + + // 2a volta serve per avere fase non casuale +// si5351_setupPLL(SI5351_PLL_A, 24, 28437, 1048562); + +/* + si5351_setupPLL(SI5351_PLL_B, 28, 7012, 390625); + si5351_setupMultisynth(2, SI5351_PLL_B, 1336, 0, 1); + si5351_setupRdiv(2, SI5351_R_DIV_16); +*/ + + si5351_enableOutputs(0xFF); + HAL_Delay(100); + + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief I2C2 Initialization Function + * @param None + * @retval None + */ +static void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + hi2c2.Init.Timing = 0x00303D5B; + hi2c2.Init.OwnAddress1 = 0; + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c2.Init.OwnAddress2 = 0; + hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + { + Error_Handler(); + } + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + + /*Configure GPIO pin : PC14 */ + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/squero/Core/Src/si5351.c b/squero/Core/Src/si5351.c new file mode 100644 index 0000000..461b5bb --- /dev/null +++ b/squero/Core/Src/si5351.c @@ -0,0 +1,713 @@ +/**************************************************************************/ +/*! + @file si5351.c + + @author K. Townsend (Adafruit Industries) + + @brief Driver for the SI5351 160MHz Clock Gen + + @section REFERENCES + + Si5351A/B/C Datasheet: + http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf + + Manually Generating an Si5351 Register Map: + http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2014, Adafruit Industries + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ +#include "main.h" +// CHANGE THIS FOR YOUR CHIP +#include "stm32g0xx_hal.h" +// #include "i2c.h" +#include +#include "si5351.h" + +// extern I2C_HandleTypeDef hi2c2; +si5351Config_t m_si5351Config; +/**************************************************************************/ +/*! + Initializes I2C and configures the breakout (call this function before + doing anything else) +*/ +/**************************************************************************/ +err_t si5351_Init(void) +{ + + /*! + Constructor + */ + m_si5351Config.initialised = 0; + m_si5351Config.crystalFreq = SI5351_CRYSTAL_FREQ_24MHZ; + m_si5351Config.crystalLoad = SI5351_CRYSTAL_LOAD_10PF; + m_si5351Config.crystalPPM = 30; + m_si5351Config.plla_configured = 0; + m_si5351Config.plla_freq = 0; + m_si5351Config.pllb_configured = 0; + m_si5351Config.pllb_freq = 0; + m_si5351Config.ms0_freq = 0; + m_si5351Config.ms1_freq = 0; + m_si5351Config.ms2_freq = 0; + m_si5351Config.ms0_r_div = 0; + m_si5351Config.ms1_r_div = 0; + m_si5351Config.ms2_r_div = 0; + + + + /* Disable all outputs setting CLKx_DIS high */ + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, 0xFF)); + + /* Power down all output drivers */ + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_16_CLK0_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + + /* Set the load capacitance for the XTAL */ + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_183_CRYSTAL_INTERNAL_LOAD_CAPACITANCE, + m_si5351Config.crystalLoad)); + + /* Set interrupt masks as required (see Register 2 description in AN619). + By default, ClockBuilder Desktop sets this register to 0x18. + Note that the least significant nibble must remain 0x8, but the most + significant nibble may be modified to suit your needs. */ + + /* Reset the PLL config fields just in case we call init again */ + m_si5351Config.plla_configured = 0; + m_si5351Config.plla_freq = 0; + m_si5351Config.pllb_configured = 0; + m_si5351Config.pllb_freq = 0; + + /* All done! */ + m_si5351Config.initialised = 1; + + return ERROR_NONE; +} + + +/**************************************************************************/ +/*! + @brief Sets the multiplier for the specified PLL using integer values + + @param pll The PLL to configure, which must be one of the following: + - SI5351_PLL_A + - SI5351_PLL_B + @param mult The PLL integer multiplier (must be between 15 and 90) +*/ +/**************************************************************************/ +err_t si5351_setupPLLInt(si5351PLL_t pll, uint8_t mult) +{ + return si5351_setupPLL(pll, mult, 0, 1); +} + +/**************************************************************************/ +/*! + @brief Sets the multiplier for the specified PLL + + @param pll The PLL to configure, which must be one of the following: + - SI5351_PLL_A + - SI5351_PLL_B + @param mult The PLL integer multiplier (must be between 15 and 90) + @param num The 20-bit numerator for fractional output (0..1,048,575). + Set this to '0' for integer output. + @param denom The 20-bit denominator for fractional output (1..1,048,575). + Set this to '1' or higher to avoid divider by zero errors. + + @section PLL Configuration + + fVCO is the PLL output, and must be between 600..900MHz, where: + + fVCO = fXTAL * (a+(b/c)) + + fXTAL = the crystal input frequency + a = an integer between 15 and 90 + b = the fractional numerator (0..1,048,575) + c = the fractional denominator (1..1,048,575) + + NOTE: Try to use integers whenever possible to avoid clock jitter + (only use the a part, setting b to '0' and c to '1'). + + See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf +*/ +/**************************************************************************/ +err_t si5351_setupPLL(si5351PLL_t pll, + uint8_t mult, + uint32_t num, + uint32_t denom) +{ + uint32_t P1; /* PLL config register P1 */ + uint32_t P2; /* PLL config register P2 */ + uint32_t P3; /* PLL config register P3 */ + + /* Basic validation */ + ASSERT( m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED ); + ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + + /* Feedback Multisynth Divider Equation + * + * where: a = mult, b = num and c = denom + * + * P1 register is an 18-bit value using following formula: + * + * P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512 + * + * P2 register is a 20-bit value using the following formula: + * + * P2[19:0] = 128 * num - denom * floor(128*(num/denom)) + * + * P3 register is a 20-bit value using the following formula: + * + * P3[19:0] = denom + */ + + /* Set the main PLL config registers */ + if (num == 0) + { + /* Integer mode */ + P1 = 128 * mult - 512; + P2 = num; + P3 = denom; + } + else + { + /* Fractional mode */ + P1 = (uint32_t)(128 * mult + floor(128 * ((float)num/(float)denom)) - 512); + P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + P3 = denom; + } + + /* Get the appropriate starting point for the PLL registers */ + uint8_t baseaddr = (pll == SI5351_PLL_A ? 26 : 34); + + /* The datasheet is a nightmare of typos and inconsistencies here! */ + ASSERT_STATUS( si5351_write8( baseaddr, (P3 & 0x0000FF00) >> 8)); + ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) )); + ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + + /* Reset both PLLs */ + ASSERT_STATUS( si5351_write8(SI5351_REGISTER_177_PLL_RESET, (1<<7) | (1<<5) )); + + /* Store the frequency settings for use with the Multisynth helper */ + if (pll == SI5351_PLL_A) + { + float fvco = m_si5351Config.crystalFreq * (mult + ( (float)num / (float)denom )); + m_si5351Config.plla_configured = 1; //true + m_si5351Config.plla_freq = (uint32_t)floor(fvco); + } + else + { + float fvco = m_si5351Config.crystalFreq * (mult + ( (float)num / (float)denom )); + m_si5351Config.pllb_configured = 1; //true + m_si5351Config.pllb_freq = (uint32_t)floor(fvco); + } + + return ERROR_NONE; +} + +/**************************************************************************/ +/*! + @brief Configures the Multisynth divider using integer output. + + @param output The output channel to use (0..2) + @param pllSource The PLL input source to use, which must be one of: + - SI5351_PLL_A + - SI5351_PLL_B + @param div The integer divider for the Multisynth output, + which must be one of the following values: + - SI5351_MULTISYNTH_DIV_4 + - SI5351_MULTISYNTH_DIV_6 + - SI5351_MULTISYNTH_DIV_8 +*/ +/**************************************************************************/ +err_t si5351_setupMultisynthInt(uint8_t output, + si5351PLL_t pllSource, + si5351MultisynthDiv_t div) +{ + return si5351_setupMultisynth(output, pllSource, div, 0, 1); +} + + +err_t si5351_setupRdiv(uint8_t output, si5351RDiv_t div) { + ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + + uint8_t Rreg, regval, rDiv; + + if (output == 0) Rreg = SI5351_REGISTER_44_MULTISYNTH0_PARAMETERS_3; + if (output == 1) Rreg = SI5351_REGISTER_52_MULTISYNTH1_PARAMETERS_3; + if (output == 2) Rreg = SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3; + + si5351_read8(Rreg, ®val); + + regval &= 0x0F; + uint8_t divider = div; + divider &= 0x07; + divider <<= 4; + regval |= divider; + si5351_write8(Rreg, regval); + + switch(div) + { + case 0: + rDiv = 1; + break; + + case 1: + rDiv = 2; + break; + + case 2: + rDiv = 4; + break; + + case 3: + rDiv = 8; + break; + + case 4: + rDiv = 16; + break; + + case 5: + rDiv = 32; + break; + + case 6: + rDiv = 64; + break; + + case 7: + rDiv = 128; + break; + } + + switch(output) + { + case 0: + m_si5351Config.ms0_r_div = rDiv; + break; + + case 1: + m_si5351Config.ms1_r_div = rDiv; + break; + + case 2: + m_si5351Config.ms2_r_div = rDiv; + break; + } + + return ERROR_NONE; +} + +/**************************************************************************/ +/*! + @brief Configures the Multisynth divider, which determines the + output clock frequency based on the specified PLL input. + + @param output The output channel to use (0..2) + @param pllSource The PLL input source to use, which must be one of: + - SI5351_PLL_A + - SI5351_PLL_B + @param div The integer divider for the Multisynth output. + If pure integer values are used, this value must + be one of: + - SI5351_MULTISYNTH_DIV_4 + - SI5351_MULTISYNTH_DIV_6 + - SI5351_MULTISYNTH_DIV_8 + If fractional output is used, this value must be + between 8 and 900. + @param num The 20-bit numerator for fractional output + (0..1,048,575). Set this to '0' for integer output. + @param denom The 20-bit denominator for fractional output + (1..1,048,575). Set this to '1' or higher to + avoid divide by zero errors. + + @section Output Clock Configuration + + The multisynth dividers are applied to the specified PLL output, + and are used to reduce the PLL output to a valid range (500kHz + to 160MHz). The relationship can be seen in this formula, where + fVCO is the PLL output frequency and MSx is the multisynth + divider: + + fOUT = fVCO / MSx + + Valid multisynth dividers are 4, 6, or 8 when using integers, + or any fractional values between 8 + 1/1,048,575 and 900 + 0/1 + + The following formula is used for the fractional mode divider: + + a + b / c + + a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) + or 8..900 in fractional mode (MSx_INT=0). + b = The fractional numerator (0..1,048,575) + c = The fractional denominator (1..1,048,575) + + @note Try to use integers whenever possible to avoid clock jitter + + @note For output frequencies > 150MHz, you must set the divider + to 4 and adjust to PLL to generate the frequency (for example + a PLL of 640 to generate a 160MHz output clock). This is not + yet supported in the driver, which limits frequencies to + 500kHz .. 150MHz. + + @note For frequencies below 500kHz (down to 8kHz) Rx_DIV must be + used, but this isn't currently implemented in the driver. +*/ +/**************************************************************************/ +err_t si5351_setupMultisynth(uint8_t output, + si5351PLL_t pllSource, + uint32_t div, + uint32_t num, + uint32_t denom) +{ + uint32_t P1; /* Multisynth config register P1 */ + uint32_t P2; /* Multisynth config register P2 */ + uint32_t P3; /* Multisynth config register P3 */ + + /* Basic validation */ + ASSERT( m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED); + ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + //ASSERT( div < 901, ERROR_INVALIDPARAMETER); /* Divider integer value */ + //ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + //ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + //ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + + + /* Make sure the requested PLL has been initialised */ + if (pllSource == SI5351_PLL_A) + { + ASSERT(m_si5351Config.plla_configured = 1, ERROR_INVALIDPARAMETER); + } + else + { + ASSERT(m_si5351Config.pllb_configured = 1, ERROR_INVALIDPARAMETER); + } + + /* Output Multisynth Divider Equations + * + * where: a = div, b = num and c = denom + * + * P1 register is an 18-bit value using following formula: + * + * P1[17:0] = 128 * a + floor(128*(b/c)) - 512 + * + * P2 register is a 20-bit value using the following formula: + * + * P2[19:0] = 128 * b - c * floor(128*(b/c)) + * + * P3 register is a 20-bit value using the following formula: + * + * P3[19:0] = c + */ + + /* Set the main PLL config registers */ + if (num == 0) + { + /* Integer mode */ + P1 = 128 * div - 512; + P2 = num; + P3 = denom; + } + else + { + /* Fractional mode */ + P1 = (uint32_t)(128 * div + floor(128 * ((float)num/(float)denom)) - 512); + P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + P3 = denom; + } + + /* Get the appropriate starting point for the PLL registers */ + uint8_t baseaddr = 0; + switch (output) + { + case 0: + baseaddr = SI5351_REGISTER_42_MULTISYNTH0_PARAMETERS_1; + break; + case 1: + baseaddr = SI5351_REGISTER_50_MULTISYNTH1_PARAMETERS_1; + break; + case 2: + baseaddr = SI5351_REGISTER_58_MULTISYNTH2_PARAMETERS_1; + break; + } + + /* Set the MSx config registers */ + si5351_write8( baseaddr, (P3 & 0x0000FF00) >> 8); + si5351_write8( baseaddr+1, (P3 & 0x000000FF)); + si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16); /* ToDo: Add DIVBY4 (>150MHz) and R0 support (<500kHz) later */ + si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8); + si5351_write8( baseaddr+4, (P1 & 0x000000FF)); + si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ); + si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + si5351_write8( baseaddr+7, (P2 & 0x000000FF)); + + + if (pllSource == SI5351_PLL_A) + { + float fvco = m_si5351Config.plla_freq / (div + ( (float)num / (float)denom )); + switch (output) + { + case 0: + m_si5351Config.ms0_freq = (uint32_t)floor(fvco); + break; + case 1: + m_si5351Config.ms1_freq = (uint32_t)floor(fvco); + break; + case 2: + m_si5351Config.ms2_freq = (uint32_t)floor(fvco); + break; + } + } + else + { + float fvco = m_si5351Config.pllb_freq / (div + ( (float)num / (float)denom)); + switch (output) + { + case 0: + m_si5351Config.ms0_freq = (uint32_t)floor(fvco); + break; + case 1: + m_si5351Config.ms1_freq = (uint32_t)floor(fvco); + break; + case 2: + m_si5351Config.ms2_freq = (uint32_t)floor(fvco); + break; + } + } + + + + /* Configure the clk control and enable the output */ + uint8_t clkControlReg = 0x0F; /* 8mA drive strength, MS0 as CLK0 source, Clock not inverted, powered up */ + // controfase + if(output == 1) clkControlReg = 0x1F; + + if (pllSource == SI5351_PLL_B) clkControlReg |= (1 << 5); /* Uses PLLB */ + if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + switch (output) + { + case 0: + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_16_CLK0_CONTROL, clkControlReg)); + break; + case 1: + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, clkControlReg)); + break; + case 2: + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, clkControlReg)); + break; + } + + return ERROR_NONE; +} + +/**************************************************************************/ +/*! + @brief Enables or disables all clock outputs +*/ +/**************************************************************************/ +err_t si5351_enableOutputs(uint8_t enabled) +{ + /* Make sure we've called init first */ + ASSERT(m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED); + + /* Enabled desired outputs (see Register 3) */ + ASSERT_STATUS(si5351_write8(SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, enabled ? 0x00: 0xFF)); + + return ERROR_NONE; +} + +/* ---------------------------------------------------------------------- */ +/* PRUVATE FUNCTIONS */ +/* ---------------------------------------------------------------------- */ + +/**************************************************************************/ +/*! + @brief Writes a register and an 8 bit value over I2C +*/ +/**************************************************************************/ +err_t si5351_write8 (uint8_t reg, uint8_t value) +{ + HAL_StatusTypeDef status = HAL_OK; + + while (HAL_I2C_IsDeviceReady(&hi2c2, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } + + status = HAL_I2C_Mem_Write(&hi2c2, // i2c handle + (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned + (uint8_t)reg, // register address + I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses + (uint8_t*)(&value), // write returned data to this variable + 1, // how many bytes to expect returned + 100); // timeout + + return ERROR_NONE; +} + +/**************************************************************************/ +/*! + @brief Reads an 8 bit value over I2C +*/ +/**************************************************************************/ +err_t si5351_read8(uint8_t reg, uint8_t *value) +{ + HAL_StatusTypeDef status = HAL_OK; + + while (HAL_I2C_IsDeviceReady(&hi2c2, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } + + status = HAL_I2C_Mem_Read(&hi2c2, // i2c handle + (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned + (uint8_t)reg, // register address + I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses + (uint8_t*)(&value), // write returned data to this variable + 1, // how many bytes to expect returned + 100); // timeout + + return ERROR_NONE; +} + + +void CalcRegisters(uint32_t fout){ + fout *= 2; + uint8_t *regs; + uint32_t fref = SI5351_CRYSTAL_FREQ_24MHZ; // The reference frequency + + // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1 + uint32_t d = 4; + uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY4 = 0xC0, see datasheet 4.1.3 + int msx_divby4 = 0; + int rx_div = 0; + int r = 1; + + if (fout > 150e6) + msx_divby4 = 0x0C; // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3 + else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datasheet 4.2.2. In reality this means > 292 968,75 Hz when d = 2048 + { + int rd = 0; + while ((r < 128) && (r * fout < 292969UL)) + { + r <<= 1; + rd++; + } + rx_div = rd << 4; + + d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum + if (d % 2) // Make d even to reduce spurious and phase noise/jitter, see datasheet 4.1.2.1. + d++; + + if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even d value + d += 2; + } + else // 292968 Hz <= fout <= 150 MHz + { + d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum + if (d < 6) + d = 6; + else if (d % 2) // Make d even to reduce phase noise/jitter, see datasheet 4.1.2.1. + d++; + + if (d * fout < 600e6) // VCO frequency to low check and maintain an even d value + d += 2; + } + msx_p1 = 128 * d - 512; + + uint32_t fvco = (uint32_t) d * r * fout; + + // Calc Feedback Multisynth Divider + double fmd = (double)fvco / fref; // The FMD value has been found + int a = fmd; // a is the integer part of the FMD value + + double b_c = (double)fmd - a; // Get b/c + uint32_t c = 1048575UL; + uint32_t b = (double)b_c * c; + if (b > 0) + { + c = (double)b / b_c + 0.5; // Improves frequency precision in some cases + if (c > 1048575UL) + c = 1048575UL; + } + + + si5351_setupPLL(SI5351_PLL_A, a, b, c); + HAL_Delay(10); + si5351_setupMultisynth(0, SI5351_PLL_A, d, 0, 1); + HAL_Delay(10); + si5351_setupRdiv(0, SI5351_R_DIV_2); + HAL_Delay(10); + + si5351_setupMultisynth(1, SI5351_PLL_A, d, 0, 1); + HAL_Delay(10); + si5351_setupRdiv(1, SI5351_R_DIV_2); + HAL_Delay(10); + + + // 2a volta serve per avere fase non casuale + si5351_setupPLL(SI5351_PLL_A, a, b, c); + + + uint32_t msnx_p1 = 128 * a + 128 * b / c - 512; // See datasheet 3.2 + uint32_t msnx_p2 = 128 * b - c * (128 * b / c); + uint32_t msnx_p3 = c; + + // Feedback Multisynth Divider registers + regs[0] = (msnx_p3 >> 8) & 0xFF; + regs[1] = msnx_p3 & 0xFF; + regs[2] = (msnx_p1 >> 16) & 0x03; + regs[3] = (msnx_p1 >> 8) & 0xFF; + regs[4] = msnx_p1 & 0xFF; + regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F); + regs[6] = (msnx_p2 >> 8) & 0xFF; + regs[7] = msnx_p2 & 0xFF; + + // Output Multisynth Divider registers + regs[8] = 0; // (msx_p3 >> 8) & 0xFF + regs[9] = 1; // msx_p3 & 0xFF + regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03); + regs[11] = (msx_p1 >> 8) & 0xFF; + regs[12] = msx_p1 & 0xFF; + regs[13] = 0; // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0F + regs[14] = 0; // (msx_p2 >> 8) & 0xFF + regs[15] = 0; // msx_p2 & 0xFF + + return; +} diff --git a/squero/Core/Src/stm32g0xx_hal_msp.c b/squero/Core/Src/stm32g0xx_hal_msp.c new file mode 100644 index 0000000..10f181e --- /dev/null +++ b/squero/Core/Src/stm32g0xx_hal_msp.c @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief I2C MSP Initialization +* This function configures the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspInit 0 */ + + /* USER CODE END I2C2_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**I2C2 GPIO Configuration + PA11 [PA9] ------> I2C2_SCL + PA12 [PA10] ------> I2C2_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF6_I2C2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + __HAL_RCC_I2C2_CLK_ENABLE(); + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + } + +} + +/** +* @brief I2C MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hi2c: I2C handle pointer +* @retval None +*/ +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) +{ + if(hi2c->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspDeInit 0 */ + + /* USER CODE END I2C2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C2_CLK_DISABLE(); + + /**I2C2 GPIO Configuration + PA11 [PA9] ------> I2C2_SCL + PA12 [PA10] ------> I2C2_SDA + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + + /* USER CODE BEGIN I2C2_MspDeInit 1 */ + + /* USER CODE END I2C2_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + diff --git a/squero/Core/Src/stm32g0xx_it.c b/squero/Core/Src/stm32g0xx_it.c new file mode 100644 index 0000000..2e2ec76 --- /dev/null +++ b/squero/Core/Src/stm32g0xx_it.c @@ -0,0 +1,146 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + diff --git a/squero/Core/Src/system_stm32g0xx.c b/squero/Core/Src/system_stm32g0xx.c new file mode 100644 index 0000000..c8c9be7 --- /dev/null +++ b/squero/Core/Src/system_stm32g0xx.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_1: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h b/squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h new file mode 100644 index 0000000..89c9ee9 --- /dev/null +++ b/squero/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h @@ -0,0 +1,7876 @@ +/** + ****************************************************************************** + * @file stm32g031xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g031xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g031xx + * @{ + */ + +#ifndef STM32G031xx_H +#define STM32G031xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g031xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI line 16 */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + LPTIM1_IRQn = 17, /*!< LPTIM1 global Interrupts */ + LPTIM2_IRQn = 18, /*!< LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + LPUART1_IRQn = 29, /*!< LPUART1 globlal Interrupts (combined with EXTI 28) */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED8[17];/*!< Reserved8, Address offset: 0x3C--0x7C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ +#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM28_Pos (28U) +#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ +#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ +#define EXTI_IMR1_IM29_Pos (29U) +#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ +#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ +#define EXTI_IMR1_IM30_Pos (30U) +#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ +#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0xF2A9FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xF2A9FFFF */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM28_Pos (28U) +#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ +#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ +#define EXTI_EMR1_EM29_Pos (29U) +#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ +#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ +#define EXTI_EMR1_EM30_Pos (30U) +#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ +#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */ +#define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */ +#define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk +#define FLASH_ACR_DBG_SWEN_Pos (18U) +#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */ +#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_RDERR_Pos (14U) +#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ +#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_RDERRIE_Pos (26U) +#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_SEC_PROT_Pos (28U) +#define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */ +#define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_BOR_EN_Pos (8U) +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk +#define FLASH_OPTR_BORR_LEV_Pos (9U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORF_LEV_Pos (11U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_nRST_SHDW_Pos (15U) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk +#define FLASH_OPTR_NRST_MODE_Pos (27U) +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_IRHEN_Pos (29U) +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk + +/****************** Bits definition for FLASH_PCROP1ASR register ************/ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1AER register ************/ +#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk +#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + +/****************** Bits definition for FLASH_PCROP1BSR register ************/ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk + +/****************** Bits definition for FLASH_PCROP1BER register ************/ +#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk + + +/****************** Bits definition for FLASH_SECR register *****************/ +#define FLASH_SECR_SEC_SIZE_Pos (0U) +#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */ +#define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk +#define FLASH_SECR_BOOT_LOCK_Pos (16U) +#define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ +#define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/squero/Drivers/CMSIS/Include/cmsis_armclang.h b/squero/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..478f75b --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/squero/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/squero/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..1b5a965 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/squero/Drivers/CMSIS/Include/cmsis_compiler.h b/squero/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..21a2c71 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/squero/Drivers/CMSIS/Include/cmsis_gcc.h b/squero/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..1e08e7e --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/squero/Drivers/CMSIS/Include/cmsis_iccarm.h b/squero/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..7af7562 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/squero/Drivers/CMSIS/Include/cmsis_version.h b/squero/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..3174cf6 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/squero/Drivers/CMSIS/Include/core_armv81mml.h b/squero/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8cee930 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_armv8mbl.h b/squero/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..266f180 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_armv8mml.h b/squero/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..ba5d83f --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm0.h b/squero/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..70e4505 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm0plus.h b/squero/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..fe7b424 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm1.h b/squero/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..44c2a49 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm23.h b/squero/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..49f4a5b --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm3.h b/squero/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..1f69e8b --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm33.h b/squero/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..2f1d98e --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm35p.h b/squero/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..7d34367 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm4.h b/squero/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..90c2a72 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_cm7.h b/squero/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..3da3c43 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_sc000.h b/squero/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..f315013 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/core_sc300.h b/squero/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..ad031f2 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/squero/Drivers/CMSIS/Include/mpu_armv7.h b/squero/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..337eb65 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/squero/Drivers/CMSIS/Include/mpu_armv8.h b/squero/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..2fe28b6 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/squero/Drivers/CMSIS/Include/tz_context.h b/squero/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..d4c1474 --- /dev/null +++ b/squero/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/squero/Drivers/CMSIS/LICENSE.txt b/squero/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..c0ee812 --- /dev/null +++ b/squero/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#endif +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h new file mode 100644 index 0000000..7e896a2 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h @@ -0,0 +1,839 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_H +#define STM32G0xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_conf.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Break Break + * @{ + */ +#define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */ +#if defined(SYSCFG_CFGR2_PVDL) +#define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#endif /* SYSCFG_CFGR2_PVDL */ +#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */ +#define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +#if defined(SYSCFG_CDEN_SUPPORT) +/** @defgroup SYSCFG_ClampingDiode Clamping Diode + * @{ + */ +#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */ +#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */ +#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */ +#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */ +#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */ +#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */ +#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */ +#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */ + +/** + * @} + */ +#endif /* SYSCFG_CDEN_SUPPORT */ + +/** @defgroup HAL_Pin_remapping Pin remapping + * @{ + */ +/* Only available on cut2.0 */ +#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ +#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ +/** + * @} + */ + +/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ +#if defined(USART4) +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */ +#else +#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ +#endif /* USART4 */ + +/** + * @} + */ + +/** @defgroup HAL_IR_POL_SEL IR output polarity selection + * @{ + */ +#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ +#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V. + This requires VDDA equal to or higher than 2.4 V. */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V. + This requires VDDA equal to or higher than 2.8 V. */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ +#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */ +#if defined (I2C3) +#define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */ +#endif /* I2C3 */ + +/** + * @} + */ +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration + * @{ + */ +#define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */ +#define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */ + +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @{ + */ +#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ + +#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG) /*!< WWDG has expired .... */ +#if defined (PWR_PVD_SUPPORT) +#define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */ +#endif /* PWR_PVD_SUPPORT */ +#if defined (PWR_PVM_SUPPORT) +#define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT) /*!< Power voltage monitor Interrupt .... */ +#endif /* PWR_PVM_SUPPORT */ +#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[19] Interrupt */ +#define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[21] interrupt .... */ +#define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */ +#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ +#if defined (CRS) +#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */ +#endif /*CRS */ +#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ +#if defined (UCPD1) +#define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1) /*!< UCPD1 Interrupt */ +#endif /* UCPD1 */ +#if defined (UCPD2) +#define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2) /*!< UCPD2 Interrupt */ +#endif /* UCPD2 */ +#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx) +#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ +#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */ +#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1) /*!< DMAMUX1 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ +#if defined(DMA1_Channel7) +#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ +#endif /* DMA1_Channel7 */ +#if defined (DMA2) +#define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1) /*!< DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2) /*!< DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3) /*!< DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4) /*!< DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5) /*!< DMA2 Channel 5 Interrupt */ +#endif /* DMA2 */ +#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ +#if defined (COMP1) +#define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */ +#endif /* COMP1 */ +#if defined (COMP2) +#define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */ +#endif /* COMP2 */ +#if defined (COMP3) +#define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3) /*!< COMP3 Interrupt -> exti[1x] */ +#endif /* COMP3 */ +#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */ +#if defined (TIM2) +#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */ +#endif /* TIM2 */ +#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ +#if defined (TIM4) +#define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB) /*!< TIM4 Interrupt */ +#endif /* TIM4 */ +#if defined(TIM6) +#define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */ +#endif /* TIM6 */ +#if defined(DAC1) +#define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC) /*!< DAC Interrupt */ +#endif /* DAC1 */ +#if defined(LPTIM1) +#define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[29] */ +#endif /* LPTIM1 */ +#if defined(TIM7) +#define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */ +#endif /* TIM7 */ +#if defined(LPTIM2) +#define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[30] */ +#endif /* LPTIM2 */ +#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ +#if defined(TIM15) +#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */ +#endif /* TIM15 */ +#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ +#if defined (FDCAN1) || defined (FDCAN2) +#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0) /*!< FDCAN1_IT0 Interrupt */ +#define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0) /*!< FDCAN2_IT0 Interrupt */ +#endif /* FDCAN1 || FDCAN2 */ +#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ +#if defined (FDCAN1) || defined (FDCAN2) +#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1) /*!< FDCAN1_IT1 Interrupt */ +#define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1) /*!< FDCAN2_IT1 Interrupt */ +#endif /* FDCAN1 || FDCAN2 */ +#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt -> exti[24] */ +#if defined (I2C3) +#define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB) /*!< I2C3 Interrupt -> exti[22] */ +#endif /* I2C3 */ +#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ +#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */ +#if defined (SPI3) +#define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3) /*!< SPI3 Interrupt */ +#endif /* SPI3 */ +#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */ +#if defined (LPUART2) +#define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[26] */ +#endif /* LPUART2 */ +#if defined(USART3) +#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */ +#endif /* USART3 */ +#if defined(USART4) +#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 Interrupt .... */ +#endif /* USART4 */ +#if defined (LPUART1) +#define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/ +#endif /* LPUART1 */ +#if defined (USART5) +#define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB) /*!< USART5 Interrupt .... */ +#endif /* USART5 */ +#if defined (USART6) +#define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB) /*!< USART6 Interrupt .... */ +#endif /* USART6 */ +#if defined (CEC) +#define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC) /*!< CEC Interrupt -> exti[27] */ +#endif /* CEC */ +#if defined (RNG) +#define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */ +#endif /* RNG */ +#if defined (AES) +#define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */ +#endif /* AES */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze and Unfreeze Peripherals in Debug mode + */ +#if defined(DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */ + +#if defined(DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#endif /* DBG_APB_FZ1_DBG_RTC_STOP */ + +#if defined(DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */ + +#if defined(DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */ + +#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */ + +#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */ + +#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) +#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */ + +#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) +#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** + * @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0)) + +/** + * @brief Return the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values @ref SYSCFG_BootMode + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) + + +/** @brief SYSCFG Break Cortex-M0+ Lockup lock. + * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +#if defined(SYSCFG_CFGR2_PVDL) +/** @brief SYSCFG Break PVD lock. + * Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked only by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) +#endif /* SYSCFG_CFGR2_PVDL */ + +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17 + * @note The selected configuration is locked and can only be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL) + +/** @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF) + +/** @brief Set the PEF bit to clear the SRAM Parity Error Flag. + */ +#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + +#if defined(SYSCFG_CDEN_SUPPORT) +/** @brief Clamping Diode on specific pins enable/disable macros + * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode + */ +#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + SET_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) + +#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) +#endif /* SYSCFG_CDEN_SUPPORT */ + +/** @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + */ +#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) \ + (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU)) + +/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register + * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ + SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ + }while(0U) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) + +/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register + * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ + SET_BIT(SYSCFG->CFGR1,(__SEL__));\ + }while(0U) + +/** + * @brief Return the IROut Polarity mode as configured by user. + * @retval The IROut polarity as configured by user. The returned value can be one + * of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) + +/** @brief Break input to TIM1/15/16/17 capability enable/disable macros + * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break + */ +#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) + +#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ +#if defined (PWR_PVD_SUPPORT) +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ + ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ + ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) +#else +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ + ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) +#endif /* PWR_PVD_SUPPORT */ + +#if defined(SYSCFG_CDEN_SUPPORT) +#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \ + (((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \ + (((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \ + (((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \ + (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \ + (((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \ + (((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \ + (((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2)) +#endif /* SYSCFG_CDEN_SUPPORT */ + +#if defined (USART4) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#else +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) +#endif /* USART4 */ +#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ + ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) + +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \ + ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \ + ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE))) +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +#if defined(VREFBUF) +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif /* VREFBUF */ + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ + ((RMP) == SYSCFG_REMAP_PA12) || \ + ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions + * @{ + */ + +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ + +#if defined(VREFBUF) +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#endif /* VREFBUF */ + +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); +#if defined(SYSCFG_CDEN_SUPPORT) +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig); +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig); +#endif /* SYSCFG_CDEN_SUPPORT */ +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery); +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h new file mode 100644 index 0000000..c6062c4 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h @@ -0,0 +1,387 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CORTEX_H +#define STM32G0xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. + */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h new file mode 100644 index 0000000..0931d4f --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DEF +#define STM32G0xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handles State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handles "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handles "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((packed)) + #endif /* __packed */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +/* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ +#elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +/* ARM Compiler */ +#if defined (__CC_ARM) /* ARM Compiler V5 */ +#define __ALIGN_BEGIN __align(4U) +/* IAR Compiler */ +#elif defined (__ICCARM__) +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __CC_ARM || __ARMCC_VERSION */ + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __CC_ARM || __ARMCC_VERSION */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h new file mode 100644 index 0000000..4affc2f --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h @@ -0,0 +1,803 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DMA_H +#define STM32G0xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_dma.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified channel. + This parameter can be a value of @ref DMA_request */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + +#if defined(DMA2) + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + +#endif /* DMA2 */ + uint32_t ChannelIndex; /*!< DMA Channel Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ + +/** + * @} + */ + +/** @defgroup DMA_request DMA request + * @{ + */ +#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ +#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ +#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ +#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ +#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ +#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ +#if defined(AES) +#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ +#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ +#endif /* AES */ +#if defined(DAC1) +#define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */ +#define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */ +#endif /* DAC1 */ +#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ +#if defined(LPUART1) +#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ +#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ +#endif /* LPUART1 */ +#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ +#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */ +#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ +#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ +#endif /* TIM2 */ +#define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */ +#define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ +#if defined(TIM6) +#define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ +#endif /* TIM6 */ +#if defined(TIM7) +#define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ +#endif /* TIM7 */ +#if defined(TIM15) +#define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ +#define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ +#define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ +#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ +#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM /*!< DMAMUX TIM17 COM request */ +#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ +#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ +#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ +#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ +#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ +#define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ +#define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ +#if defined(UCPD1) +#define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */ +#define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */ +#endif/* UCPD1 */ +#if defined(UCPD2) +#define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */ +#define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */ +#endif /* UCPD2 */ + +#if defined(I2C3) +#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ +#endif /* I2C3 */ + +#if defined(LPUART2) +#define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ +#define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ +#endif /* LPUART2 */ + +#if defined(SPI3) +#define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ +#endif /* SPI3 */ + +#if defined(TIM4) +#define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2 /*!< DMAMUX TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3 /*!< DMAMUX TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */ +#define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */ +#define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */ +#endif /* TIM4 */ + +#if defined(USART5) +#define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */ +#define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */ +#endif /* USART5 */ + +#if defined(USART6) +#define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */ +#define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */ +#endif /* USART6 */ + + +#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ +#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ +#define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ +#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ +#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ +#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ +#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ +#if defined(DMA1_Channel6) +#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#else +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + DMA_FLAG_GI5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(DMA2) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) +#else /* DMA1 */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) +#endif /* DMA2 */ + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval None + */ +#if defined(DMA2) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) +#else /* DMA1 */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) +#endif /* DMA2 */ + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32g0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h new file mode 100644 index 0000000..df43225 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h @@ -0,0 +1,280 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DMA_EX_H +#define STM32G0xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_dmamux.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE */ + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +} HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */ +#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */ +#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */ +#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */ +#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */ +#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */ +#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */ +#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */ +#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */ +#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */ +#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */ +#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */ +#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */ +#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line1 3 */ +#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line1 4 */ +#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line1 5 */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2 /*!< Synchronization signal from DMAMUX channel2 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */ +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */ +#endif /* LPTIM2 */ +#define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */ + +#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2 /*!< Request signal generation from DMAMUX channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */ +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */ +#endif /* LPTIM2 */ +#define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */ + +#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC))) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN))) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h new file mode 100644 index 0000000..b67db28 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h @@ -0,0 +1,389 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_EXTI_H +#define STM32G0xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) +#if defined(COMP1) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) +#else +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#endif /* COMP1 */ +#if defined(COMP2) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) +#else +#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u) +#endif /* COMP2 */ +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u) +#if defined(COMP3) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) +#else +#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) +#endif /* COMP3 */ +#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) +#if defined(RCC_CCIPR_I2C2SEL) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) +#else +#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u) +#endif /* RCC_CCIPR_I2C2SEL */ +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#if defined(RCC_CCIPR_USART3SEL) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#else +#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) +#endif /* RCC_CCIPR_USART3SEL */ +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#if defined(RCC_CCIPR_USART2SEL) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) +#else +#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(CEC) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) +#else +#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) +#endif /* CEC */ +#if defined(LPUART1) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#else +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#endif /* LPUART1 */ +#if defined(LPTIM1) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) +#else +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) +#else +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#endif /* LPTIM2 */ +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) +#if defined(UCPD1) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u) +#else +#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u) +#else +#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u) +#endif /* UCPD2 */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u) +#else +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#endif /* STM32G0C1xx || STM32G0B1xx */ +#if defined(LPUART2) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) +#else +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#endif /* LPUART2 */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined(GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif /* GPIOE */ +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define EXTI_LINE_NB 37uL +#elif defined(STM32G0B0xx) +#define EXTI_LINE_NB 37uL +#elif defined(STM32G081xx) || defined(STM32G071xx) +#define EXTI_LINE_NB 34uL +#elif defined(STM32G070xx) +#define EXTI_LINE_NB 34uL +#elif defined(STM32G041xx) || defined(STM32G031xx) +#define EXTI_LINE_NB 32uL +#else +#define EXTI_LINE_NB 32uL +#endif /* STM32G0C1xx || STM32G0B1xx */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__MODE__) ((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__MODE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOF)) +#endif /* GPIOE */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h new file mode 100644 index 0000000..05bf99b --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h @@ -0,0 +1,1036 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_FLASH_H +#define STM32G0xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Banks; /*!< Select bank to erase. + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled + This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of + @ref FLASH_OB_USER_BOR_ENABLE(*), + @ref FLASH_OB_USER_BOR_LEVEL(*), + @ref FLASH_OB_USER_RESET_CONFIG(*), + @ref FLASH_OB_USER_nRST_STOP, + @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN(*), + @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, + @ref FLASH_OB_USER_SRAM_PARITY, + @ref FLASH_OB_USER_BANK_SWAP(*), + @ref FLASH_OB_USER_DUAL_BANK(*), + @ref FLASH_OB_USER_nBOOT_SEL, + @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + @note (*) availability depends on devices */ +#if defined(FLASH_PCROP_SUPPORT) + uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). + This parameter must be a combination of @ref FLASH_OB_PCROP_ZONE + and @ref FLASH_OB_PCROP_RDP. Note that once set, Pcrop erase on RDP level 1 regression + (PCROP_RDP bit) can not be reset. It will be reset by mass erase */ + uint32_t PCROP1AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t PCROP2AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */ + uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address. + This parameter must be a value between [0] and [FLASH_PAGE_NB], + [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t SecSize2; /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address. + This parameter must be a value between [0] and [FLASH_PAGE_NB], + [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +#endif /* FLASH_DBANK_SUPPORT */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Banks; /* Internal variable to save current bank selected during erase in IT context */ + uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 + to unlock the FLASH registers access */ +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 + to allow option bytes operations */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 0x00000000UL /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +/** + * @} + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#define FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos) /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos) /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos) /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos) /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos) /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos) /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos) /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos) /*!< FLASH Fast programming data miss error flag */ +#define FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos) /*!< FLASH Fast programming error flag */ +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos) /*!< FLASH PCROP read error flag */ +#endif /* FLASH_PCROP_SUPPORT */ +#define FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos) /*!< FLASH Option validity error flag */ +#define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos) /*!< FLASH Operation Busy flag for Bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos) /*!< FLASH Operation Busy flag for Bank 2 */ +#endif /* FLASH_DBANK_SUPPORT */ +#define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /*!< FLASH Operation Busy flag - legacy name for single bank */ +#define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos) /*!< FLASH Configuration Busy flag */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos) /*!< FLASH Programming/erase operation suspended */ +#endif /* FLASH_DBANK_SUPPORT */ +#define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos) /*!< FLASH ECC correction on bank 1 */ +#define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos) /*!< FLASH ECC detection on bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos) /*!< FLASH ECC correction on bank 2 */ +#define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos) /*!< FLASH ECC detection on bank 2 */ +#endif /* FLASH_DBANK_SUPPORT */ +#define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1 /*!< FLASH ECC correction - legacy name for single bank */ +#define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1 /*!< FLASH ECC detection - legacy name for single bank */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos) /*!< Error Interrupt source */ +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos) /*!< PCROP Read Error Interrupt source*/ +#endif /* FLASH_PCROP_SUPPORT */ +#define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction on Bank 1 Interrupt source */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos) /*!< ECC Correction on Bank 2 Interrupt source */ +#endif /* FLASH_DBANK_SUPPORT */ +#define FLASH_IT_ECCC FLASH_IT_ECCC1 /*!< ECC Correction - legacy name for single bank */ +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_SR_EOP +#define HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_SR_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR +#if defined(FLASH_PCROP_SUPPORT) +#define HAL_FLASH_ERROR_RD FLASH_SR_RDERR +#endif /* FLASH_PCROP_SUPPORT */ +#define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR +#define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only */ +#define FLASH_TYPEERASE_MASS FLASH_CR_MER1 /*!< Flash mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASH_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 FLASH_CR_MER1 /*!< Bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_BANK_2 FLASH_CR_MER2 /*!< Bank 2 */ +#endif /* FLASH_DBANK_SUPPORT */ +/** + * @} + */ + + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 row double-word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Type FLASH Option Bytes Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#if defined(FLASH_PCROP_SUPPORT) +#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ +#endif /* FLASH_PCROP_SUPPORT */ +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + +#if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_PCROP | OPTIONBYTE_SEC) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */ +#endif /* FLASH_PCROP_SUPPORT && FLASH_SECURABLE_MEMORY_SUPPORT */ +/** + * @} + */ + +/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area + * @{ + */ +#define OB_WRPAREA_ZONE_A 0x00000001U /*!< Flash Zone A */ +#define OB_WRPAREA_ZONE_B 0x00000002U /*!< Flash Zone B */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_WRPAREA_ZONE2_A 0x00000004U /*!< Flash Bank 2 Zone A */ +#define OB_WRPAREA_ZONE2_B 0x00000008U /*!< Flash Bank 2 Zone B */ +#endif /* FLASH_DBANK_SUPPORT */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0x000000AAU +#define OB_RDP_LEVEL_1 0x000000BBU +#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 + it is no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type + * @{ + */ +#if defined(PWR_BOR_SUPPORT) +#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */ +#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */ +#endif /* PWR_BOR_SUPPORT */ +#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ +#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ +#if defined(PWR_SHDW_SUPPORT) +#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ +#endif /* PWR_SHDW_SUPPORT */ +#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ +#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK /*!< Swap bank memory addresses */ +#define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK /*!< Select single or dual bank (depending of device memory size) */ +#endif /* FLASH_DBANK_SUPPORT */ +#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity check control */ +#define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL /*!< Boot Selection */ +#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< nBoot1 configuration */ +#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBoot0 configuration */ +#if defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /*!< Reset pin configuration */ +#endif /* GPIO_NRST_CONFIG_SUPPORT */ +#if defined(FLASH_OPTR_IRHEN) +#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ +#endif /* FLASH_OPTR_IRHEN */ + +#if defined(FLASH_DBANK_SUPPORT) +#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_nRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else +#define OB_USER_ALL ( OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */ +#else +#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_nRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else +#define OB_USER_ALL ( OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */ +#endif /* FLASH_DBANK_SUPPORT */ +/** + * @} + */ + +#if defined(PWR_BOR_SUPPORT) +/** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable + * @{ + */ +#define OB_BOR_DISABLE 0x00000000U /*!< BOR Reset set to default */ +#define OB_BOR_ENABLE FLASH_OPTR_BOR_EN /*!< Use option byte to define BOR thresholds */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level + * @{ + */ +#define OB_BOR_LEVEL_FALLING_0 0x00000000U /*!< BOR falling level 1 with threshold around 2.0V */ +#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /*!< BOR falling level 2 with threshold around 2.2V */ +#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /*!< BOR falling level 3 with threshold around 2.5V */ +#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with threshold around 2.8V */ +#define OB_BOR_LEVEL_RISING_0 0x00000000U /*!< BOR rising level 1 with threshold around 2.1V */ +#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /*!< BOR rising level 2 with threshold around 2.3V */ +#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /*!< BOR rising level 3 with threshold around 2.6V */ +#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with threshold around 2.9V */ +/** + * @} + */ +#endif /* PWR_BOR_SUPPORT */ + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ +#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ +#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ +/** + * @} + */ + +#if defined(PWR_SHDW_SUPPORT) +/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown + * @{ + */ +#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ +#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ +/** + * @} + */ +#endif /* PWR_SHDW_SUPPORT */ + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ +#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ +#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ +#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type + * @{ + */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ +#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ + +#if defined(FLASH_DBANK_SUPPORT) +/** @defgroup FLASH_OB_USER_BANK_SWAP FLASH Option Bytes User bank swap Type + * @{ + */ +#define OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U /*!< Enable bank swap */ +#define OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK /*!< Disable bank swap */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_DUAL_BANK FLASH Option Bytes User dual bank enable Type + * @{ + */ +#define OB_USER_DUALBANK_DISABLE 0x00000000U /*!< Disable dual bank */ +#define OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK /*!< Enable dual bank */ +/** + * @} + */ +#endif /* FLASH_DBANK_SUPPORT */ + +/** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity + * @{ + */ +#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< Sram parity enable */ +#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection + * @{ + */ +#define OB_BOOT0_FROM_PIN 0x00000000U /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */ +#define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL /*!< BOOT0 signal is defined by nBOOT0 option bit */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type + * @{ + */ +#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ +#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit + * @{ + */ +#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ +#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ +/** + * @} + */ + +#if defined(GPIO_NRST_CONFIG_SUPPORT) +/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit + * @{ + */ +#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */ +#define OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode mode only */ +#define OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */ +/** + * @} + */ +#endif /* GPIO_NRST_CONFIG_SUPPORT */ + +#if defined(FLASH_OPTR_IRHEN) +/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit + * @{ + */ +#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ +/** + * @} + */ +#endif /* FLASH_OPTR_IRHEN */ + +#if defined(FLASH_PCROP_SUPPORT) +/** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE + * @{ + */ +#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ +#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_PCROP_ZONE2_A 0x00000004U /*!< PCROP Bank 2 Zone A */ +#define OB_PCROP_ZONE2_B 0x00000008U /*!< PCROP Bank 2 Zone B */ +#endif /* FLASH_DBANK_SUPPORT */ +/** + * @} + */ + +/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 */ +#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase). + Once this bit is set only, it will be reset by mass erase */ +/** + * @} + */ +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +/** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock + * @{ + */ +#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U /*!< Boot entry is free */ +#define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK /*!< Boot entry is forced to Flash or System Flash */ +/** + * @} + */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Reset the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0U) +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be one of the following values : + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1 + * @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank + * @note (*) availability depends on devices + * @retval none + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#endif /* FLASH_DBANK_SUPPORT */ + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be one of the following values : + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1 + * @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank + * @note (*) availability depends on devices + * @retval none + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#endif /* FLASH_DBANK_SUPPORT */ + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values : + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag(*) + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_BSY1 FLASH bank 1 write/erase operations in progress flag + * @arg @ref FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*) + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag - legacy name for single bank + * @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used. + * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1 + * @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank + * @note (*) availability depends on devices + * @retval The state of FLASH_FLAG (SET or RESET). + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)) +#endif /* FLASH_DBANK_SUPPORT */ + +/** + * @brief Clear the FLASH pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be one of the following values : + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1 + * @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank + * @note (*) availability depends on devices + * @retval None + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R = (1uL << ((__FLAG__) & 0x1Fu)); } \ + } while(0U) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + } while(0U) +#endif /* FLASH_DBANK_SUPPORT */ +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32g0xx_hal_flash_ex.h" +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types --------------------------------------------------------*/ +/** @defgroup FLASH_Private_types FLASH Private Types + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE + +#if defined(FLASH_DBANK_SUPPORT) +#define OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U) /*!< Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence */ +#define FLASH_SALES_TYPE_Pos (24U) +#define FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos) /*!< 0x000001E0 */ +#define FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos) /*!< 0x01000000 */ +#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /*!< 0x02000000 */ +#define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE)) +#define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK)) +#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U)\ + || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U) +#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */ +#else /* FLASH_DBANK_SUPPORT */ +#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */ +#endif /* FLASH_DBANK_SUPPORT */ + +#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */ +#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ +#define FLASH_TYPENONE 0x00000000U /*!< No programming Procedure On Going */ + +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ +#else +#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD) +#else +#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP) +#endif /* FLASH_DBANK_SUPPORT */ + +/* Internal defines for HAL macro usage */ +#define FLASH_FLAG_REG_POS 16u +#define FLASH_FLAG_SR_ID 1u +#define FLASH_FLAG_CR_ID 2u +#define FLASH_FLAG_ECCR1_ID 4u +#define FLASH_FLAG_ECCR2_ID 8u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + +#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL))) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) +#endif /* FLASH_DBANK_SUPPORT */ + +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) + +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U)\ + && ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\ + || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) + +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) + +#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB) + +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_BANK(__BANK__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__BANK__) == FLASH_BANK_1) || \ + ((__BANK__) == FLASH_BANK_2) || \ + ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \ + ((__BANK__) == FLASH_BANK_1)) +#else +#define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1) +#endif /* FLASH_DBANK_SUPPORT */ + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ + ((__VALUE__) == FLASH_TYPEERASE_MASS)) + +#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) + +#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \ + (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) + +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_WRPAREA(__VALUE__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \ + ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))) +#else +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A)\ + || ((__VALUE__) == OB_WRPAREA_ZONE_B)) +#endif /* FLASH_DBANK_SUPPORT */ + +#define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \ + (((__TYPE__) & ~OB_USER_ALL) == 0x00U)) + +#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U) + +#if defined(FLASH_PCROP_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_PCROP_CONFIG(__CONFIG__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \ + OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)) +#else +#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__)\ + & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U) +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\ + || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) + +#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U)) +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1) || \ + ((__LATENCY__) == FLASH_LATENCY_2)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h new file mode 100644 index 0000000..240bfba --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_FLASH_EX_H +#define STM32G0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check + * @{ + */ +#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ +#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +void HAL_FLASHEx_EnableDebugger(void); +void HAL_FLASHEx_DisableDebugger(void); +uint32_t HAL_FLASHEx_FlashEmptyCheck(void); +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks); +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */ +#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) +void FLASH_PageErase(uint32_t Banks, uint32_t Page); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h new file mode 100644 index 0000000..2173307 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h @@ -0,0 +1,364 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_GPIO_H +#define STM32G0xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line rising pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line falling pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32g0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h new file mode 100644 index 0000000..5957cbb --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_GPIO_EX_H +#define STM32G0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ +#if defined (STM32G0C1xx) || defined (STM32G0B1xx) +/*------------------------- STM32G0C1xx / STM32G0B1xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF0_UCPD1 ((uint8_t)0x00) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF0_UCPD2 ((uint8_t)0x00) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPTIM2 ((uint8_t)0x01) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_LPUART2 ((uint8_t)0x01) /*!< LPUART2 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF1_UCPD1 ((uint8_t)0x01) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF1_UCPD2 ((uint8_t)0x01) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< USB Alternate Function mapping */ + + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_FDCAN1 ((uint8_t)0x03) /*!< FDCAN1 Alternate Function mapping */ +#define GPIO_AF3_FDCAN2 ((uint8_t)0x03) /*!< FDCAN2 Alternate Function mapping */ +#define GPIO_AF3_LPUART2 ((uint8_t)0x03) /*!< LPUART2 Alternate Function mapping */ +#define GPIO_AF3_USART5 ((uint8_t)0x03) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF3_USART6 ((uint8_t)0x03) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF3_MCO2 ((uint8_t)0x03) /*!< MCO2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< CRS Alternate Function mapping */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_USART6 ((uint8_t)0x04) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF4_UCPD1 ((uint8_t)0x04) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF4_UCPD2 ((uint8_t)0x04) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF6_UCPD2 ((uint8_t)0x06) /*!< UCPD2 Alternate Function mapping */ +#define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07) /*!< COMP3 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF8_USART5 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF9_SPI3 ((uint8_t)0x09) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF9_TIM4 ((uint8_t)0x09) /*!< TIM4 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_LPUART2 ((uint8_t)0x0A) /*!< LPUART2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A) + +#endif /* STM32G0C1xx || STM32G0B1xx */ + +#if defined (STM32G0B0xx) +/*------------------------- STM32G0B0xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< USB Alternate Function mapping */ + + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_USART5 ((uint8_t)0x03) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF3_USART6 ((uint8_t)0x03) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF3_MCO2 ((uint8_t)0x03) /*!< MCO2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< CRS Alternate Function mapping */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_USART6 ((uint8_t)0x04) /*!< USART6 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF8_USART5 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF9_SPI3 ((uint8_t)0x09) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF9_TIM4 ((uint8_t)0x09) /*!< TIM4 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x09) + +#endif /* STM32G0B0xx */ + + +#if defined (STM32G081xx) || defined (STM32G071xx) +/*------------------------- STM32G081xx / STM32G071xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< CEC Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_UCPD1 ((uint8_t)0x00) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF0_UCPD2 ((uint8_t)0x00) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< CEC Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF1_UCPD1 ((uint8_t)0x01) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF1_UCPD2 ((uint8_t)0x01) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF3_UCPD2 ((uint8_t)0x03) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_UCPD1 ((uint8_t)0x04) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF4_UCPD2 ((uint8_t)0x04) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF6_UCPD2 ((uint8_t)0x06) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G081xx || STM32G071xx */ + +#if defined (STM32G070xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G070xx */ + +#if defined (STM32G051xx) || defined (STM32G061xx) +/*------------------------- STM32G061xx / STM32G051xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G051xx || STM32G061xx */ + +#if defined (STM32G050xx) +/*------------------------- STM32G050xx --------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G050xx */ + +#if defined (STM32G031xx) || defined (STM32G041xx) +/*------------------------- STM32G041xx / STM32G031xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G031xx || STM32G041xx */ + +#if defined (STM32G030xx) +/*------------------------- STM32G030xx --------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G030xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index +* @{ + */ +#if defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 5uL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL : 5uL) +#endif /* GPIOE */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h new file mode 100644 index 0000000..fc1feaa --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_I2C_H +#define STM32G0xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32g0xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32g0xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h new file mode 100644 index 0000000..5ada411 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h @@ -0,0 +1,180 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_I2C_EX_H +#define STM32G0xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */ +#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_CFGR1_I2C3_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32g0xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_I2C_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h new file mode 100644 index 0000000..c8daa14 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_PWR_H +#define STM32G0xx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#endif /* PWR_CR3_EWUP3 */ +#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#endif /* PWR_CR3_EWUP3 */ +#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif /* PWR_CR3_EWUP5*/ +#define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */ +#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */ +#endif /* PWR_CR3_EWUP3 */ +#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */ +/** + * @} + */ + +/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection + * @{ + */ +#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ +#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ +#if defined(PWR_SHDW_SUPPORT) +#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ +#endif /* PWR_SHDW_SUPPORT */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000u) /*!< Regulator in main mode */ +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#define PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2) /*!< Wakeup event on wakeup pin 2 */ +#if defined(PWR_CR3_EWUP3) +#define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3) /*!< Wakeup event on wakeup pin 3 */ +#endif /* PWR_CR3_EWUP3 */ +#define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4) /*!< Wakeup event on wakeup pin 4 */ +#if defined(PWR_CR3_EWUP5) +#define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5) /*!< Wakeup event on wakeup pin 5 */ +#endif /* PWR_CR3_EWUP5 */ +#define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6) /*!< Wakeup event on wakeup pin 6 */ +#define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF) /*!< Wakeup event on all wakeup pin */ +#define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF) /*!< Standby flag */ +#define PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI) /*!< Wakeup on internal wakeup line */ +#define PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY) /*!< Flash ready */ +#define PWR_FLAG_REGLPS (0x00020000u | PWR_SR2_REGLPS) /*!< Regulator Low Power started */ +#define PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF) /*!< Regulator Low Power flag */ +#if defined(PWR_PVD_SUPPORT) +#define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO) /*!< Power Voltage Detector output */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB) /*!< Power Voltage Monitoring output */ +#endif /* PWR_PVM_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. (*) + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_SB: StandBy Flag. Indicates that the system + * entered StandBy mode. + * @arg PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is + * detected on the internal wakeup line. + * OR a combination of following values: + * @arg PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash + * can be used or not + * @arg PWR_FLAG_REGLPS: Low Power Regulator Started. Indicates whether + * or not the low-power regulator is ready. + * @arg PWR_FLAG_REGLPF: Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. + * @if defined(STM32G081xx) + * @arg PWR_FLAG_PVDO: Power Voltage Detector Output. Indicates whether + * VDD voltage is below or above the selected PVD threshold. + * @endif + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) & 0x00010000u) ?\ + ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\ + ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u))) + +/** @brief Clear a specific PWR flag. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. (*) + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_WUF: Encompasses all Wake Up Flags. + * @arg PWR_FLAG_SB: Standby Flag. Indicates that the system + * entered Standby mode. + * @retval None + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->SCR = (__FLAG__)) + +/** + * @} + */ + +/* Private constants-------------------------------------------------------*/ +/** @defgroup PWR_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants + * @{ + */ +#define PWR_WUP_POLARITY_SHIFT 0x08u /*!< Internal constant used to retrieve wakeup pin polariry */ +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_WAKEUP_PIN(PIN) ((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \ + (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32g0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h new file mode 100644 index 0000000..e192c2b --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h @@ -0,0 +1,643 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_PWR_EX_H +#define STM32G0xx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVM_Mode. */ +} PWR_PVMTypeDef; +#endif /* PWR_PVM_SUPPORT */ + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value or a combination of + @ref PWR_PVD_detection_level. */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +#endif /* PWR_PVD_SUPPORT */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels + * @note see datasheet for selection voltage value + * @{ + */ +#define PWR_PVDLEVEL_RISING_0 (0x00000000u) /*!< PVD threshold level 0 for rising detection */ +#define PWR_PVDLEVEL_RISING_1 (PWR_CR2_PVDRT_0) /*!< PVD threshold level 1 for rising detection */ +#define PWR_PVDLEVEL_RISING_2 (PWR_CR2_PVDRT_1) /*!< PVD threshold level 2 for rising detection */ +#define PWR_PVDLEVEL_RISING_3 (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1) /*!< PVD threshold level 3 for rising detection */ +#define PWR_PVDLEVEL_RISING_4 (PWR_CR2_PVDRT_2) /*!< PVD threshold level 4 for rising detection */ +#define PWR_PVDLEVEL_RISING_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /*!< PVD threshold level 5 for rising detection */ +#define PWR_PVDLEVEL_RISING_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /*!< PVD threshold level 6 for rising detection */ +#define PWR_PVDLEVEL_FALLING_0 (0x00000000u) /*!< PVD threshold level 0 for falling detection */ +#define PWR_PVDLEVEL_FALLING_1 (PWR_CR2_PVDFT_0) /*!< PVD threshold level 1 for falling detection */ +#define PWR_PVDLEVEL_FALLING_2 (PWR_CR2_PVDFT_1) /*!< PVD threshold level 2 for falling detection */ +#define PWR_PVDLEVEL_FALLING_3 (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1) /*!< PVD threshold level 3 for falling detection */ +#define PWR_PVDLEVEL_FALLING_4 (PWR_CR2_PVDFT_2) /*!< PVD threshold level 4 for falling detection */ +#define PWR_PVDLEVEL_FALLING_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /*!< PVD threshold level 5 for falling detection */ +#define PWR_PVDLEVEL_FALLING_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /*!< PVD threshold level 6 for falling detection */ +#define PWR_PVDLEVEL_0 (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0) /*!< same PVD threshold level 0 on rising & falling */ +#define PWR_PVDLEVEL_1 (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1) /*!< same PVD threshold level 1 on rising & falling */ +#define PWR_PVDLEVEL_2 (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2) /*!< same PVD threshold level 2 on rising & falling */ +#define PWR_PVDLEVEL_3 (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3) /*!< same PVD threshold level 3 on rising & falling */ +#define PWR_PVDLEVEL_4 (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4) /*!< same PVD threshold level 4 on rising & falling */ +#define PWR_PVDLEVEL_5 (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5) /*!< same PVD threshold level 5 on rising & falling */ +#define PWR_PVDLEVEL_6 (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6) /*!< same PVD threshold level 6 on rising & falling */ +#define PWR_PVDLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /*!< External input analog voltage (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000u) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001u) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002u) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003u) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVD (EXTI_IMR1_IM16) /*!< External interrupt line 16 connected to PVD */ +/** + * @} + */ + +/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line + * @{ + */ +#define PWR_EVENT_LINE_PVD (EXTI_EMR1_EM16) /*!< Event line 16 connected to PVD */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_PVM_SUPPORT) +/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type + * @{ + */ +#define PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */ +/** + * @} + */ +/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode + * @{ + */ +#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ +/** @defgroup PWR_PVM_EXTI_LINE PWR PVM external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34) /*!< External interrupt line 34 connected to PVM */ +/** + * @} + */ + +/** @defgroup PWR_PVM_EVENT_LINE PWR PVM event line + * @{ + */ +#define PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34) /*!< Event line 34 connected to PVM */ +/** + * @} + */ +#endif /* PWR_PVM_SUPPORT */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Bit_Number GPIO bit position + * @brief for I/O pull up/down setting in standby/shutdown mode + * @{ + */ +#define PWR_GPIO_BIT_0 PWR_PUCRB_PU0 /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 PWR_PUCRB_PU1 /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 PWR_PUCRB_PU2 /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 PWR_PUCRB_PU3 /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 PWR_PUCRB_PU4 /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 PWR_PUCRB_PU5 /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 PWR_PUCRB_PU6 /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 PWR_PUCRB_PU7 /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 PWR_PUCRB_PU8 /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 PWR_PUCRB_PU9 /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 PWR_PUCRB_PU10 /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 PWR_PUCRB_PU11 /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 PWR_PUCRB_PU12 /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 PWR_PUCRB_PU13 /*!< GPIO port I/O pin 13 */ +#define PWR_GPIO_BIT_14 PWR_PUCRB_PU14 /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_15 PWR_PUCRB_PU15 /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Port GPIO Port + * @{ + */ +#define PWR_GPIO_A (0x00000000u) /*!< GPIO port A */ +#define PWR_GPIO_B (0x00000001u) /*!< GPIO port B */ +#define PWR_GPIO_C (0x00000002u) /*!< GPIO port C */ +#define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */ +#if defined (GPIOE) +#define PWR_GPIO_E (0x00000004u) /*!< GPIO port E */ +#endif /* GPIOE */ +#define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */ +/** + * @} + */ + +/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes + * @{ + */ +#define PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN /*!< Enable Flash power down in low power run mode */ +#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP /*!< Enable Flash power down in low power sleep mode */ +#define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP /*!< Enable Flash power down in stop mode */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ +/** + * @} + */ + +/** @addtogroup PWR_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */ +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Rising flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Falling flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD) +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Disable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Rising flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG() (EXTI->RPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Falling flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() (EXTI->FPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM) +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ +#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \ + ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \ + (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u)) +#if defined (GPIOE) +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_D) || \ + ((__GPIO__) == PWR_GPIO_E) || \ + ((__GPIO__) == PWR_GPIO_F)) +#else +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_D) || \ + ((__GPIO__) == PWR_GPIO_F)) +#endif /* GPIOE */ + +#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \ + (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u)) + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) + +#if defined(PWR_PVD_SUPPORT) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u) + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING) || \ + ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_PVM_SUPPORT) +#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB) + +#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) +#endif /* PWR_PVM_SUPPORT */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); +void HAL_PWREx_DisableBatteryCharging(void); +#if defined(PWR_CR3_ENB_ULP) +void HAL_PWREx_EnablePORMonitorSampling(void); +void HAL_PWREx_DisablePORMonitorSampling(void); +#endif /* PWR_CR3_ENB_ULP */ +void HAL_PWREx_EnableInternalWakeUpLine(void); +void HAL_PWREx_DisableInternalWakeUpLine(void); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); +#if defined(PWR_CR3_RRS) +void HAL_PWREx_EnableSRAMRetention(void); +void HAL_PWREx_DisableSRAMRetention(void); +#endif /* PWR_CR3_RRS */ +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +#if defined(PWR_PVD_SUPPORT) +/* Power voltage detection configuration functions ****************************/ +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWREx_EnablePVD(void); +void HAL_PWREx_DisablePVD(void); +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_PVM_SUPPORT) +/* Power voltage monitoring configuration functions ***************************/ +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +void HAL_PWREx_EnablePVMUSB(void); +void HAL_PWREx_DisablePVMUSB(void); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#endif /* PWR_PVM_SUPPORT */ + +/* Low Power modes configuration functions ************************************/ +void HAL_PWREx_EnableLowPowerRunMode(void); +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); +#if defined(PWR_SHDW_SUPPORT) +void HAL_PWREx_EnterSHUTDOWNMode(void); +#endif /* PWR_SHDW_SUPPORT */ + +#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) +void HAL_PWREx_PVD_PVM_IRQHandler(void); +void HAL_PWREx_PVD_PVM_Rising_Callback(void); +void HAL_PWREx_PVD_PVM_Falling_Callback(void); +#elif defined(PWR_PVD_SUPPORT) +void HAL_PWREx_PVD_IRQHandler(void); +void HAL_PWREx_PVD_Rising_Callback(void); +void HAL_PWREx_PVD_Falling_Callback(void); +#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h new file mode 100644 index 0000000..52ab595 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h @@ -0,0 +1,3138 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_RCC_H +#define STM32G0xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_rcc.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ +/* Defines used for Flags */ +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U +#if defined(RCC_HSI48_SUPPORT) +#define CRRCR_REG_INDEX 4U +#endif /* RCC_HSI48_SUPPORT */ + +#define RCC_FLAG_MASK 0x1FU + +/* Define used for IS_RCC_CLOCKTYPE() */ +#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#else +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#endif /* RCC_HSI48_SUPPORT */ + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) +#endif /* RCC_HSI48_SUPPORT */ + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) + +#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ + ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ + ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ + ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \ + ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \ + ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \ + ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8)) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) + +#if defined(RCC_PLLQ_SUPPORT) +#define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) +#endif /* RCC_PLLQ_SUPPORT */ + +#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ + & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(RCC_MCO2_SUPPORT) +#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) ) +#else +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) +#endif /* RCC_MCO2_SUPPORT */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) +#elif defined(STM32G0B0xx) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) +#else +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#endif /* STM32G0C1xx || STM32G0B1xx */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \ + ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \ + ((__DIV__) == RCC_MCODIV_1024)) +#else +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_MCO2_SUPPORT) +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) +#else +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) +#endif /* RCC_HSI48_SUPPORT */ +#define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ + ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ + ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \ + ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \ + ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \ + ((__DIV__) == RCC_MCO2DIV_1024)) + +#endif /* RCC_MCO2_SUPPORT */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ + + uint32_t PLLP; /*!< PLLP: PLL Division factor. + User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + +#if defined(RCC_PLLQ_SUPPORT) + uint32_t PLLQ; /*!< PLLQ: PLL Division factor. + User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ +#endif /* RCC_PLLQ_SUPPORT */ + + uint32_t PLLR; /*!< PLLR: PLL Division for the main system clock. + User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI16. + This parameter can be a value of @ref RCC_HSI_Div */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_HSI48_SUPPORT) + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices). + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_HSI48_SUPPORT */ + + RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a combination of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Div HSI Div + * @{ + */ +#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ +#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ +#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ +#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ +#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ +#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ +#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ +#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ +/** + * @} + */ + +/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider + * @{ + */ +#define RCC_PLLM_DIV1 0x00000000U /*!< PLLM division factor = 8 */ +#define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0 /*!< PLLM division factor = 2 */ +#define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1 /*!< PLLM division factor = 3 */ +#define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 4 */ +#define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2 /*!< PLLM division factor = 5 */ +#define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 6 */ +#define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLLM division factor = 7 */ +#define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0 /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1 /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2 /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3 /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4 /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3) /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */ +/** + * @} + */ + +#if defined(RCC_PLLQ_SUPPORT) +/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider + * @{ + */ +#define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0 /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1 /*!< PLLQ division factor = 3 */ +#define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2 /*!< PLLQ division factor = 5 */ +#define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< PLLQ division factor = 7 */ +#define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 8 */ +/** * @} + */ +#endif /* RCC_PLLQ_SUPPORT */ + +/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider + * @{ + */ +#define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0 /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1 /*!< PLLR division factor = 3 */ +#define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2 /*!< PLLR division factor = 5 */ +#define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< PLLR division factor = 7 */ +#define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */ +/** * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output PLL Clock Output + * @{ + */ +#define RCC_PLLPCLK RCC_PLLCFGR_PLLPEN /*!< PLLPCLK selection from main PLL */ +#if defined(RCC_PLLQ_SUPPORT) +#define RCC_PLLQCLK RCC_PLLCFGR_PLLQEN /*!< PLLQCLK selection from main PLL */ +#endif /* RCC_PLLQ_SUPPORT */ +#define RCC_PLLRCLK RCC_PLLCFGR_PLLREN /*!< PLLRCLK selection from main PLL */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1 /*!< PLL selection as system clock */ +#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ +#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1 /*!< PLL used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source APB Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#if defined(RCC_MCO2_SUPPORT) +#define RCC_MCO2 0x00000001U /*!< MCO2 index */ +#endif /* RCC_MCO2_SUPPORT */ + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_CFGR_MCOSEL_3) +#define RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ +#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ +#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ +#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ +#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ +#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ +#define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ +#define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ +#define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0) /*!< HSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0) /*!< PLLCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler + * @{ + */ +#define RCC_MCO2DIV_1 0x00000000U /*!< MCO2 not divided */ +#define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ +#define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ +#define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ +#define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ +#define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ +#define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ +#define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ +#define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */ +#define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */ +#define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */ +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ +#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ + +#if defined(RCC_HSI48_SUPPORT) +/* Flags in the CR register */ +#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ +#endif /* RCC_HSI48_SUPPORT */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ + +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration + * @{ + */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#endif /* DMA2 */ + + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* RNG */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* AES */ + +#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable + * @brief Enable or disable the IO Ports clock. + * @note After reset, the IO ports clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* GPIOE */ + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM2 */ + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM4 */ + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRS */ + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* SPI3 */ + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART5 */ + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART6 */ + +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPUART1 */ + +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPUART2 */ + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* I2C3 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* CEC */ + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* UCPD1 */ + +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* UCPD2 */ + +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FDCAN1 || FDCAN2 */ + +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* DAC1 */ + +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPTIM2 */ + +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM15 */ + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) +#endif /* DAC1 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) +#endif /* LPTIM2 */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) +#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET) +#endif /* AES */ + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status + * @brief Check whether the IO Port clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET) + + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U) +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U) +#endif /* FDCAN1 || FDCAN2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U) +#endif /* UCPD2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U) +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U) +#endif /* FDCAN1 || FDCAN2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U) +#endif /* UCPD2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#if defined(DMA2) +#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) +#if defined(RNG) +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) +#endif /* AES */ + +#define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) +#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#if defined(DMA2) +#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) +#if defined(RNG) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset + * @brief Force or release IO Port reset. + * @{ + */ +#define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) + +#define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined(TIM4) +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) +#if defined(CRS) +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#if defined(SPI3) +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#if defined(USART5) +#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#if defined(I2C3) +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) +#if defined(DAC1) +#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) +#endif /* LPTIM1 */ +#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) +#if defined(TIM2) +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined(TIM4) +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) +#if defined(CRS) +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#if defined(SPI3) +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#if defined(USART5) +#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#if defined(I2C3) +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) +#if defined(DAC1) +#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) +#endif /* LPTIM1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable + * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) +#endif /* AES */ +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) +#endif /* AES */ + +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable + * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. + * @note IOPORT clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) +#endif /* FDCAN1) || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) +#endif /* LPTIM1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET) +#endif /* AES */ +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET) +#endif /* AES */ + +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status + * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) + + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) + + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) + + +/** + * @} + */ + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** + * @} + */ + +/** @defgroup RCC_Clock_Configuration RCC Clock Configuration + * @{ + */ + +/** @brief Macros to enable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macros to disable the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 127. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** @brief Macro to configure the HSISYS clock. + * @param __HSIDIV__ specifies the HSI16 division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 + * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 + * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 + * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 + * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 + * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 + * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 + * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 + */ +#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0U) + +#if defined(RCC_HSI48_SUPPORT) +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) + +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup RCC_RTC_Clock_Configuration + * @{ + */ + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ + +/** + * @} + */ + +/** @addtogroup RCC_Clock_Configuration + * @{ + */ + +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a value of RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency + * of 16 MHz to limit PLL jitter. + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) + +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a value of RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency + * of 16 MHz to limit PLL jitter. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. + * This parameter must be a number between 8 and 86. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 64 and 344 MHz. + * + * @param __PLLP__ specifies the division factor for ADC clock. + * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. + * + * @param __PLLQ__ specifies the division factor for RBG & HS Timers clocks.(1) + * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider + * @note (1)__PLLQ__ parameter availability depends on devices + * @note If the USB FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the RNG needs a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @param __PLLR__ specifies the division factor for the main system clock. + * This parameter must be a value of RCC_PLLR_Clock_Divider + * @note You have to set the PLL parameters correctly to not exceed 64MHZ. + * @retval None + */ +#if defined(RCC_PLLQ_SUPPORT) +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLQ__) | \ + (uint32_t) (__PLLR__))) +#else +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLR__))) +#endif /* RCC_PLLQ_SUPPORT */ +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) + +/** + * @brief Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @note Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot + * be stopped if used as System Clock. + * @note (*) RCC_PLLQCLK availability depends on devices + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLLPCLK This clock is used to generate the clock for the ADC. + * @if defined(STM32G081xx) + * @arg @ref RCC_PLLQCLK This Clock is used to generate the clock for the High Speed Timers, + * and the random analog generator (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @note Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot + * be stopped if used as System Clock. + * @note (*) RCC_PLLQCLK availability depends on devices + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLLPCLK This clock may be used to generate the clock for the ADC, I2S1. + * @if defined(STM32G081xx) + * @arg @ref RCC_PLLQCLK This Clock may be used to generate the clock for the High Speed Timers, + * and RNG (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. + * This parameter can be one of the following values: + * @arg RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1. + * @if defined(STM32G081xx) + * @arg RCC_PLLQCLK This Clock may be used to generate the clock for the HS Timers, + * the RNG (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval SET / RESET + * @note (*) RCC_PLLQCLK availability depends on devices + */ +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + +/** @brief Macro to configure the Microcontroller output clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source + @if STM32G0C1xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + @endif + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + @if STM32G0C1xx + * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256 + * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512 + * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024 + @endif + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +#if defined(RCC_MCO2_SUPPORT) +/** @brief Macro to configure the Microcontroller output clock 2. + * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled + * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee + * @arg @ref RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source + @if STM32G0C1xx + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48 + @endif + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2DIV_1 MCO2 clock source is divided by 1 + * @arg @ref RCC_MCO2DIV_2 MCO2 clock source is divided by 2 + * @arg @ref RCC_MCO2DIV_4 MCO2 clock source is divided by 4 + * @arg @ref RCC_MCO2DIV_8 MCO2 clock source is divided by 8 + * @arg @ref RCC_MCO2DIV_16 MCO2 clock source is divided by 16 + * @arg @ref RCC_MCO2DIV_32 MCO2 clock source is divided by 32 + * @arg @ref RCC_MCO2DIV_64 MCO2 clock source is divided by 64 + * @arg @ref RCC_MCO2DIV_128 MCO2 clock source is divided by 128 + * @arg @ref RCC_MCO2DIV_256 MCO2 clock source is divided by 256 + * @arg @ref RCC_MCO2DIV_512 MCO2 clock source is divided by 512 + * @arg @ref RCC_MCO2DIV_1024 MCO2 clock source is divided by 1024 + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#endif /* RCC_MCO2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear RCC interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#if defined(RCC_HSI48_SUPPORT) +#define __HAL_RCC_GET_FLAG(__FLAG__) \ + (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) +#else +#define __HAL_RCC_GET_FLAG(__FLAG__) \ + (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32g0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_EnableLSECSS(void); +void HAL_RCC_DisableLSECSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +uint32_t HAL_RCC_GetResetSource(void); +/* LSE & HSE CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_LSECSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h new file mode 100644 index 0000000..fc85384 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h @@ -0,0 +1,1593 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_RCC_EX_H +#define STM32G0xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ +#if defined(RCC_CCIPR_USART2SEL) + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ +#endif /* LPUART1 */ + +#if defined(LPUART2) + uint32_t Lpuart2ClockSelection; /*!< Specifies LPUART2 clock source + This parameter can be a value of @ref RCCEx_LPUART2_Clock_Source */ +#endif /* LPUART2 */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + +#if defined(RCC_CCIPR_I2C2SEL) + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ +#endif /* RCC_CCIPR_I2C2SEL */ + + uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source + This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ +#if defined(RCC_CCIPR2_I2S2SEL) + uint32_t I2s2ClockSelection; /*!< Specifies I2S2 clock source + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ +#endif /* RCC_CCIPR2_I2S2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#endif /* RCC_CCIPR_LPTIM2SEL */ +#if defined(RNG) + uint32_t RngClockSelection; /*!< Specifies RNG clock source + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ +#endif /* RNG */ + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ +#if defined(CEC) + uint32_t CecClockSelection; /*!< Specifies CEC Clock clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ +#endif /* CEC */ +#if defined(RCC_CCIPR_TIM1SEL) + uint32_t Tim1ClockSelection; /*!< Specifies TIM1 Clock clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + uint32_t Tim15ClockSelection; /*!< Specifies TIM15 Clock clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ +#endif /* RCC_CCIPR_TIM15SEL */ + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(RCC_CCIPR2_USBSEL) + uint32_t UsbClockSelection; /*!< Specifies USB Clock clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(FDCAN1) || defined(FDCAN2) + uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source + This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ +#endif /* FDCAN1 || FDCAN2 */ +} RCC_PeriphCLKInitTypeDef; + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +} RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x7F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +} RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U +#if defined(RCC_CCIPR_USART2SEL) +#define RCC_PERIPHCLK_USART2 0x00000002U +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) +#define RCC_PERIPHCLK_USART3 0x00000004U +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(LPUART1) +#define RCC_PERIPHCLK_LPUART1 0x00000010U +#endif /* LPUART1 */ +#define RCC_PERIPHCLK_I2C1 0x00000020U +#if defined(RCC_CCIPR_I2C2SEL) +#define RCC_PERIPHCLK_I2C2 0x00000040U +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) +#define RCC_PERIPHCLK_LPTIM2 0x00000400U +#endif /* RCC_CCIPR_LPTIM2SEL */ +#define RCC_PERIPHCLK_I2S1 0x00000800U +#if defined(LPUART2) +#define RCC_PERIPHCLK_LPUART2 0x00001000U +#endif /* LPUART2 */ +#if defined(RCC_CCIPR2_I2S2SEL) +#define RCC_PERIPHCLK_I2S2 0x00002000U +#endif /* RCC_CCIPR2_I2S2SEL */ +#define RCC_PERIPHCLK_ADC 0x00004000U +#define RCC_PERIPHCLK_RTC 0x00020000U +#if defined(RCC_CCIPR_RNGSEL) +#define RCC_PERIPHCLK_RNG 0x00040000U +#endif /* RCC_CCIPR_RNGSEL */ +#if defined(RCC_CCIPR_CECSEL) +#define RCC_PERIPHCLK_CEC 0x00080000U +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR_TIM1SEL) +#define RCC_PERIPHCLK_TIM1 0x00200000U +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) +#define RCC_PERIPHCLK_TIM15 0x00400000U +#endif /* RCC_CCIPR_TIM15SEL */ +#if defined(RCC_CCIPR2_USBSEL) +#define RCC_PERIPHCLK_USB 0x01000000U +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(FDCAN1) || defined(FDCAN2) +#define RCC_PERIPHCLK_FDCAN 0x02000000U +#endif /* FDCAN1 || FDCAN2 */ +/** + * @} + */ + + +/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART1 clock */ +/** + * @} + */ + +#if defined(RCC_CCIPR_USART2SEL) +/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 /*!< SYSCLK clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 /*!< HSI clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) /*!< LSE clock selected as USART2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) +/** @defgroup RCCEx_USART3_Clock_Source RCC USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 /*!< SYSCLK clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 /*!< HSI clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) /*!< LSE clock selected as USART3 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) +/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) /*!< LSE clock selected as LPUART1 clock */ +/** + * @} + */ +#endif /* LPUART1 */ + +#if defined(LPUART2) +/** @defgroup RCCEx_LPUART2_Clock_Source RCC LPUART2 Clock Source + * @{ + */ +#define RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0 /*!< SYSCLK clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1 /*!< HSI clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1) /*!< LSE clock selected as LPUART2 clock */ +/** + * @} + */ +#endif /* LPUART2 */ + +/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /*!< HSI clock selected as I2C1 clock */ +/** + * @} + */ + +#if defined(RCC_CCIPR_I2C2SEL) +/** @defgroup RCCEx_I2C2_Clock_Source RCC I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 /*!< SYSCLK clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /*!< HSI clock selected as I2C2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_I2C2SEL */ + +/** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ +#else +#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +#if defined(RCC_CCIPR2_I2S2SEL) +/** @defgroup RCCEx_I2S2_Clock_Source RCC I2S2 Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0 /*!< PLL "P" selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1 /*!< HSI clock selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL /*!< External I2S clock source selected as I2S2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock selected as LPTimer 1 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +/** @defgroup RCCEx_LPTIM2_Clock_Source RCC LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 /*!< LSI clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 /*!< HSI clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL /*!< LSE clock selected as LPTimer 2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(RNG) +/** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_NONE 0x00000000U /*!< No clock selected */ +#define RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator divided by 8 clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK selected as RNG clock */ +#define RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1) /*!< PLL "Q" selected as RNG clock */ + +/** + * @} + */ + +/** @defgroup RCCEx_RNG_Division_factor RCC RNG Division factor + * @{ + */ +#define RCC_RNGCLK_DIV1 0x00000000U /*!< RNG clock not divided */ +#define RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */ +#define RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */ +#define RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1) /*!< RNG clock divided by 8 */ + +/** + * @} + */ +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCCEx_FDCAN_Clock_Source RCC FDCAN Clock Source + * @{ + */ +#define RCC_FDCANCLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as FDCAN clock */ +#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" selected as FDCAN clock */ +#define RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock selected as FDCAN clock */ + +/** + * @} + */ +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RCC_CCIPR2_USBSEL) +/** @defgroup RCCEx_USB_Clock_Source USB Clock Source + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_USBCLKSOURCE_HSI48 0x00000000U /*!< HSI48 oscillator clock selected as USB clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< HSE oscillator clock selected as USB clock */ +#define RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL "Q" selected as USB clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_USBSEL */ + +/** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source + * @{ + */ + +#define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0 /*!< PLL "P" (PLLADC) used as ADC clock */ +#define RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as default CEC clock */ +#define RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCCEx_TIM1_Clock_Source RCC TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 1 clock */ +#define RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL /*!< PLL "Q" clock selected as Timer 1 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @defgroup RCCEx_TIM15_Clock_Source RCC TIM15 Clock Source + * @{ + */ +#define RCC_TIM15CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 15 clock */ +#define RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL /*!< PLL "Q" clock selected as Timer 15 clock */ + +/** + * @} + */ +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) + +#if defined(RCC_CCIPR_I2C2SEL) +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) +#endif /* RCC_CCIPR_I2C2SEL */ + +/** @brief Macro to configure the I2S1 clock (I2S1CLK). + * + * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) +#else +#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** @brief Macro to get the I2S1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL))) +#else +#define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_CCIPR2_I2S2SEL) +/** @brief Macro to configure the I2S2 clock (I2S2CLK). + * + * @param __I2S2_CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__)) + +/** @brief Macro to get the I2S2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock + */ +#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL))) +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) + +#if defined(RCC_CCIPR_USART2SEL) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(RCC_CCIPR_LPUART1SEL) +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) +#endif /* RCC_CCIPR_LPUART1SEL */ + +#if defined(RCC_CCIPR_LPUART2SEL) +/** @brief Macro to configure the LPUART2 clock (LPUART2CLK). + * + * @param __LPUART2_CLKSOURCE__ specifies the LPUART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock + */ +#define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) + +/** @brief Macro to get the LPUART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock + */ +#define __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL))) +#endif /* RCC_CCIPR_LPUART2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(CEC) +/** @brief Macro to configure the CEC clock (CECCLK). + * + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief Macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 Clock selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL))) +#endif /* CEC */ + +#if defined(RNG) +/** @brief Macro to configure the RNG clock. + * + * + * @param __RNG_CLKSOURCE__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divided by 8 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System Clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__)) + +/** @brief Macro to get the RNG clock. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divide by 8 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL))) + +/** @brief Macro to configure the RNG clock. + * + * + * @param __RNG_CLKDIV__ specifies the RNG clock division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided + * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 + * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 + * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 + */ +#define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__)) + +/** @brief Macro to get the RNG clock division factor. + * @retval The division factor can be one of the following values: + * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided + * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 + * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 + * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 + */ +#define __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV))) +#endif /* RNG */ + +/** @brief Macro to configure the ADC interface clock + * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) + +#if defined(RCC_CCIPR_TIM1SEL) +/** @brief Macro to configure the TIM1 interface clock + * @param __TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock + * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock + */ +#define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__)) + +/** @brief Macro to get the TIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock + * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock + */ +#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL))) +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @brief Macro to configure the TIM15 interface clock + * @param __TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock + * @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock + */ +#define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__)) + +/** @brief Macro to get the TIM15 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock + * @arg @ref RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock + */ +#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL))) +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(RCC_CCIPR2_USBSEL) +/** @brief Macro to configure the USB interface clock + * @param __USB_CLKSOURCE__ specifies the USB digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock (*) + * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock (*) + * (*) Feature not available on all devices + */ +#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) +#endif /* RCC_CCIPR2_USBSEL */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @brief Macro to configure the FDCAN interface clock + * @param __FDCAN_CLKSOURCE__ specifies the FDCAN digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock + * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock + * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL))) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(CRS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +#endif /* CRS */ + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#if defined(STM32G0C1xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G0B1xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G0B0xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#elif defined(STM32G081xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) +#elif defined(STM32G071xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G070xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#elif defined(STM32G061xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G051xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G041xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + +#elif defined(STM32G031xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + +#elif defined(STM32G030xx) || defined(STM32G050xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32G0C1xx */ + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + +#if defined(RCC_CCIPR_USART2SEL) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) +#endif /* LPUART1 */ + +#if defined(LPUART2) +#define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI)) +#endif /* LPUART2 */ + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + +#if defined(RCC_CCIPR_I2C2SEL) +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + +#endif /* RCC_CCIPR_I2C2SEL */ + +#define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) + +#if defined(RCC_CCIPR2_I2S2SEL) +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT)) +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) + +#if defined(RNG) +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) +#define IS_RCC_RNGDIV(__DIV__) \ + (((__DIV__) == RCC_RNGCLK_DIV1) || \ + ((__DIV__) == RCC_RNGCLK_DIV2) || \ + ((__DIV__) == RCC_RNGCLK_DIV4) || \ + ((__DIV__) == RCC_RNGCLK_DIV8)) +#endif /* RNG */ + +#if defined(CEC) +#define IS_RCC_CECCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \ + ((__SOURCE__) == RCC_CECCLKSOURCE_LSE)) +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) + +#endif /* FDCAN1 */ + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CCIPR_TIM1SEL) +#define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1)) +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +#define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1)) +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h new file mode 100644 index 0000000..f8e5c18 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h @@ -0,0 +1,2439 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_TIM_H +#define STM32G0xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x10000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x20000000U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ +#elif defined(COMP1) && defined(COMP2) +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP1 && COMP2 && COMP3 */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR1 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#if defined(USB_BASE) +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#endif /* USB_BASE */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#if defined(USB_BASE) +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#endif /* USB_BASE */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#elif defined(COMP1) && defined(COMP2) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP1 && COMP2 && COMP3 */ + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#if defined(USB_BASE) +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#else +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#endif /* USB_BASE */ + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#if defined(PWR_PVD_SUPPORT) +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#else +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#endif /* PWR_PVD_SUPPORT */ + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32g0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h new file mode 100644 index 0000000..8d5ac31 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_TIM_EX_H +#define STM32G0xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ +} TIMEx_BreakInputConfigTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#if defined(COMP3) +#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#if defined(TIM2) +#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#define TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */ +#if defined(COMP3) +#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */ +#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */ +#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#endif /* TIM2 */ +#if defined(TIM3) +#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ +#define TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#endif /* TIM3 */ +#if defined(TIM4) +#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */ +#define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#endif /* TIM4 */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#if defined(COMP1) && defined(COMP2) +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */ +#endif /* COMP3 */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ + +#if defined(TIM2) +#define TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */ +#define TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */ +#define TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ +#endif /* TIM2 */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ + +#if defined(TIM4) +#define TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ +#endif /* TIM4 */ + +#define TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */ +#define TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */ +#define TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */ +#define TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */ +#endif + +#if defined(TIM15) +#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */ +#endif /* TIM15 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */ +#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */ +#endif /* RCC_MCO2_SUPPORT */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */ +#if defined(RCC_HSI48_SUPPORT) +#define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */ +#endif /* RCC_HSI48_SUPPORT */ +#define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */ +#define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */ +#endif /* RCC_MCO2_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3)) +#elif defined(COMP1) && defined(COMP2) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) +#endif /* COMP1 && COMP2 && COMP3 */ + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h new file mode 100644 index 0000000..71833f2 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h @@ -0,0 +1,2272 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_DMA_H +#define STM32G0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" +#include "stm32g0xx_ll_dmamux.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6_BASE) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /* DMA1_Channel6_BASE */ +#if defined(DMA1_Channel7_BASE) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), +#endif /* DMA1_Channel7_BASE */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ +#endif /* DMA1_Channel7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else /* DMA1 */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif /* DMA2 */ + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined(DMA2) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined(DMA2) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +#endif /* DMA1_Channel7 */ +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +#endif /* DMA1_Channel7 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h new file mode 100644 index 0000000..9994383 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h @@ -0,0 +1,1828 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_DMAMUX_H +#define STM32G0xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004UL + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#endif /* DMAMUX1_Channel6 */ +#if defined(DMA2) +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#endif /* DMA2 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#endif /* DMAMUX1_Channel6 */ +#if defined(DMA2) +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#endif /* DMA2 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */ +#if defined(AES) +#define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */ +#endif /* AES */ +#if defined(DAC1) +#define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U /*!< DMAMUX DAC_CH2 request */ +#endif /* DAC1 */ +#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU /*!< DMAMUX I2C2 TX request */ +#if defined(LPUART1) +#define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU /*!< DMAMUX LPUART1 TX request */ +#endif /* LPUART1 */ +#define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 0x00000013U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U /*!< DMAMUX TIM1 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */ +#define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */ +#endif /* TIM2 */ +#define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM6) +#define LL_DMAMUX_REQ_TIM6_UP 0x00000026U /*!< DMAMUX TIM6 UP request */ +#endif /* TIM6 */ +#if defined(TIM7) +#define LL_DMAMUX_REQ_TIM7_UP 0x00000027U /*!< DMAMUX TIM7 UP request */ +#endif /* TIM7 */ +#if defined(TIM15) +#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */ +#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */ +#endif /* TIM15 */ +#define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU /*!< DMAMUX TIM16 COM request */ +#define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_COM 0x00000030U /*!< DMAMUX TIM17 COM request */ +#define LL_DMAMUX_REQ_TIM17_UP 0x00000031U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_USART1_RX 0x00000032U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */ +#endif /* USART3 */ +#if defined(USART4) +#define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */ +#define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */ +#endif /* USART4 */ +#if defined(UCPD1) +#define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU /*!< DMAMUX UCPD1 RX request */ +#define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU /*!< DMAMUX UCPD1 TX request */ +#endif /* UCPD1 */ +#if defined(UCPD2) +#define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU /*!< DMAMUX UCPD2 RX request */ +#define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU /*!< DMAMUX UCPD2 TX request */ +#endif /* UCPD2 */ + +#if defined(I2C3) +#define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU /*!< DMAMUX I2C3 TX request */ +#endif /* I2C3 */ + +#if defined(LPUART2) +#define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U /*!< DMAMUX LPUART2 RX request */ +#define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U /*!< DMAMUX LPUART2 TX request */ +#endif /* LPUART2 */ + +#if defined(SPI3) +#define LL_DMAMUX_REQ_SPI3_RX 0x00000042U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 0x00000043U /*!< DMAMUX SPI3 TX request */ +#endif /* SPI3 */ + +#if defined(TIM4) +#define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 0x00000045U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 0x00000046U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U /*!< DMAMUX TIM4 TRIG request */ +#define LL_DMAMUX_REQ_TIM4_UP 0x00000049U /*!< DMAMUX TIM4 UP request */ +#endif /* TIM4 */ + +#if defined(USART5) +#define LL_DMAMUX_REQ_USART5_RX 0x0000004AU /*!< DMAMUX USART5 RX request */ +#define LL_DMAMUX_REQ_USART5_TX 0x0000004BU /*!< DMAMUX USART5 TX request */ +#endif /* USART5 */ + +#if defined(USART6) +#define LL_DMAMUX_REQ_USART6_RX 0x0000004CU /*!< DMAMUX USART6 RX request */ +#define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */ +#endif /* USART6 */ + +#if defined(STM32G0C1xx)||defined(STM32G0B1xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX +#elif defined(STM32G0B0xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX +#elif defined(STM32G081xx)||defined(STM32G071xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_UCPD2_TX +#elif defined(STM32G070xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX +#else +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART2_TX +#endif /* STM32G0C1xx || STM32G0B1xx */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#endif /* DMAMUX1_Channel6 */ +#if defined(DMA2) +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#endif /* DMA2 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */ +#endif /* LPTIM2 */ +#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */ +#endif /* LPTIM2 */ +#define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +#if defined(DMAMUX1_Channel5) +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel6 */ +#if defined(DMAMUX1_Channel7) +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel7 */ +#if defined(DMAMUX1_Channel8) +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel8 */ +#if defined(DMAMUX1_Channel9) +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel9 */ +#if defined(DMAMUX1_Channel10) +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel10 */ +#if defined(DMAMUX1_Channel11) +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +#endif /* DMAMUX1_Channel11 */ +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +#if defined(DMAMUX1_Channel5) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +#endif /* DMAMUX1_Channel5 */ +#if defined(DMAMUX1_Channel6) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +#endif /* DMAMUX1_Channel6 */ +#if defined(DMAMUX1_Channel7) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +#endif /* DMAMUX1_Channel7 */ +#if defined(DMAMUX1_Channel8) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +#endif /* DMAMUX1_Channel8 */ +#if defined(DMAMUX1_Channel9) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +#endif /* DMAMUX1_Channel9 */ +#if defined(DMAMUX1_Channel10) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +#endif /* DMAMUX1_Channel10 */ +#if defined(DMAMUX1_Channel11) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +#endif /* DMAMUX1_Channel11 */ +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_DMAMUX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h new file mode 100644 index 0000000..7808368 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h @@ -0,0 +1,3886 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_RCC_H +#define STM32G0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if defined(RCC_HSI48_SUPPORT) +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSI_DIV HSI division factor + * @{ + */ +#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */ +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */ +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */ +#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */ +#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */ +#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */ +#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */ +#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_CFGR_MCOSEL_3) +#define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */ +#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */ +#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */ +#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ +#define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ +#define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */ +#endif /* RCC_CFGR_MCOPRE_3 */ +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection + * @{ + */ +#define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< HSI16 selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< Main PLL "R" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLL "P" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0) /*!< PLL "Q" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1) /*!< RTC Clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler + * @{ + */ +#define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ +#define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ +#define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ +#define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ +#define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ +#define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */ +#define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */ +#define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */ +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(LPUART1) || defined(LPUART2) +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#if defined(LPUART2) +#define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) /*!< SYSCLK clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) /*!< HSI clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) /*!< LSE clock used as LPUART2 clock source */ +#endif /* LPUART2 */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) /*!< SYSCLK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) /*!< LSE clock used as LPUART1 clock source */ +/** + * @} + */ +#endif /* LPUART1 || LPUART2 */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */ +#endif /* RCC_CCIPR_I2C2SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1) /*!< HSI clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL) /*!< External clock used as I2S1 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0) /*!< PLL clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1) /*!< HSI clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL) /*!< External clock used as I2S2 clock source */ +#else +#define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @} + */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM1 clock source */ +#define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PLL used as TIM1 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE + * @{ + */ +#define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM15 clock source */ +#define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /*!< PLL used as TIM15 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */ +/** + * @} + */ +#endif /* LPTIM1 && LPTIM2*/ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */ + +/** + * @} + */ +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 oscillator clock used as FDCAN clock */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" oscillator clock used as FDCAN clock */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock used as FDCAN clock */ + +/** + * @} + */ +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */ +#define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK divided by 1 used as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL /*!< PLL used as RNG clock */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor + * @{ + */ +#define LL_RCC_RNG_CLK_DIV1 0x00000000U /*!< RNG clock not divided */ +#define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */ +#define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */ +#define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV /*!< RNG clock divided by 8 */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< PLL clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL clock used as USB clock source */ +/** + * @} + */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0 /*!< PLL used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(LPUART1) +/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ +#if defined(LPUART2) +#define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */ +#endif /* LPUART2 */ +/** + * @} + */ +#endif /* LPUART1 */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */ +#endif /* RCC_CCIPR_I2C2SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */ +#define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */ +#else +#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */ +#if defined(RCC_CCIPR_TIM15SEL) +#define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */ +#endif /* RCC_CCIPR_TIM15SEL */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */ +#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ +/** + * @} + */ +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL /*!< FDCAN Clock source selection */ +/** + * @} + */ +#endif /* FDCAN1 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor + * @{ + */ +#define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV /*!< RNG Clock division factor */ +/** + * @} + */ +#endif /* RNG */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor (PLLM) + * @{ + */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */ +/** + * @} + */ + +#if defined(RCC_PLLQ_SUPPORT) +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLQ_SUPPORT */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) + +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S2 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + +#if defined(RNG) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* RNG */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on TIM1 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#if defined(TIM15) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* TIM15 */ +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on FDCAN domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on USB domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the HSISYS frequency + * @param __HSIDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval HSISYS clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI in stop mode is enabled + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Set HSI16 division factor + * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @param HSIDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); +} +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @brief Get HSI16 Division factor + * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO1 MCO1 + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*) + * + * (*) value not defined in all devices. + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_32 + * @arg @ref LL_RCC_MCO1_DIV_64 + * @arg @ref LL_RCC_MCO1_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_LL_EF_MCO2 MCO2 + * @{ + */ + +/** + * @brief Configure MCO2 + * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n + * CFGR MCO2PRE LL_RCC_ConfigMCO2 + * @note feature not available in all devices. + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSI + * @arg @ref LL_RCC_MCO2SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @arg @ref LL_RCC_MCO2SOURCE_LSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK + * @arg @ref LL_RCC_MCO2SOURCE_RTCCLK + * @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP + * + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_16 + * @arg @ref LL_RCC_MCO2_DIV_32 + * @arg @ref LL_RCC_MCO2_DIV_64 + * @arg @ref LL_RCC_MCO2_DIV_128 + * @arg @ref LL_RCC_MCO2_DIV_256 + * @arg @ref LL_RCC_MCO2_DIV_512 + * @arg @ref LL_RCC_MCO2_DIV_1024 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +#if defined(LPUART1) +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @rmtoll CCIPR LPUART2SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU)); +} +#endif /* LPUART1 */ + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU)); +} + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Configure TIMx clock source + * @rmtoll CCIPR TIMxSEL LL_RCC_SetTIMClockSource + * @param TIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1 + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1 + * @endif + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16)); +} +#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CCIPR CECSEL LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource); +} +#endif /* CEC */ + +#if defined(RCC_CCIPR_RNGDIV) +/** + * @brief Configure RNG division factor + * @rmtoll CCIPR RNGDIV LL_RCC_SetRNGClockDiv + * @param RNGxDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLK_DIV1 + * @arg @ref LL_RCC_RNG_CLK_DIV2 + * @arg @ref LL_RCC_RNG_CLK_DIV4 + * @arg @ref LL_RCC_RNG_CLK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv); +} +#endif /* RNG */ + +#if defined (RCC_CCIPR_RNGSEL) +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8 + * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_HSE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined (FDCAN1) || defined (FDCAN2) +/** + * @brief Configure FDCAN clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource); +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR2 I2SxSEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU)); +} + +#else +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +} + +#if defined (LPUART2) || defined (LPUART1) +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource\n + * CCIPR LPUART2SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U)); +} +#endif /* LPUART2 || LPUART1 */ + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource\n + * CCIPR I2C2SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U)); +} + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Get TIMx clock source + * @rmtoll CCIPR TIMxSEL LL_RCC_GetTIMClockSource + * @param TIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE + * @arg @ref LL_RCC_TIM15_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1 + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1 + * @endif + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx); +} +#endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined (RCC_CCIPR_CECSEL) +/** + * @brief Get CEC clock source + * @rmtoll CCIPR CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, CECx)); +} +#endif /* CEC */ + +#if defined(RCC_CCIPR2_FDCANSEL) +/** + * @brief Get FDCAN clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx)); +} +#endif /* RCC_CCIPR2_FDCANSEL */ + +#if defined(RNG) +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8 + * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +} +#endif /* RNG */ + +#if defined(RNG) +/** + * @brief Get RNGx clock division factor + * @rmtoll CCIPR RNGDIV LL_RCC_GetRNGClockDiv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLK_DIV1 + * @arg @ref LL_RCC_RNG_CLK_DIV2 + * @arg @ref LL_RCC_RNG_CLK_DIV4 + * @arg @ref LL_RCC_RNG_CLK_DIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Get USBx clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx)); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR2 I2S1SEL LL_RCC_GetI2SClockSource\n + * CCIPR2 I2S2SEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U)); +} +#else +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2S1SEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); +} + +/** + * @brief Configure PLL used for ADC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: I2S1) + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} + +/** + * @brief Configure PLL used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: ADC) + * @note This can be selected for I2S1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S1 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Configure PLL used for I2S2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: ADC) + * @note This can be selected for I2S2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Configure PLL used for RNG domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for RNG + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Configure PLL used for FDCAN domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for FDCAN + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_FDCAN + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure PLL used for USB domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for USB + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_USB + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Configure PLL used for TIM1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: RNG, TIM15) + * @note This can be selected for TIM1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM1 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +/** + * @brief Configure PLL used for TIM15 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: RNG, TIM1) + * @note This can be selected for TIM15 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM15 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RCC_PLLQ_SUPPORT && TIM15 */ + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 8 and 86 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @note used for PLLPCLK (ADC & I2S clock) + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} +#endif /* RCC_PLLQ_SUPPORT */ + +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Enable PLL output mapped on ADC domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC + * @note User shall check that PLL enable is not done through + * other functions (ex: I2S1) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Disable PLL output mapped on ADC domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: I2S1) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Enable PLL output mapped on I2S domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S1 + * @note User shall check that PLL enable is not done through + * other functions (ex: ADC) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Enable PLL output mapped on I2S2 domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S2 + * @note User shall check that PLL enable is not done through + * other functions (ex: ADC) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** + * @brief Disable PLL output mapped on I2S1 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Disable PLL output mapped on I2S2 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Enable PLL output mapped on RNG domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on RNG domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Enable PLL output mapped on FDCAN domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_FDCAN + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on FDCAN domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_FDCAN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Enable PLL output mapped on USB domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_USB + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on USB domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_USB + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Enable PLL output mapped on TIM1 domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM1 + * @note User shall check that PLL enable is not done through + * other functions (ex: RNG, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on TIM1 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +/** + * @brief Enable PLL output mapped on TIM15 domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM15 + * @note User shall check that PLL enable is not done through + * other functions (ex: RNG, TIM1) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on TIM15 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG, TIM1) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RCC_PLLQ_SUPPORT && TIM15 */ + +/** + * @brief Enable PLL output mapped on SYSCLK domain + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Disable PLL output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, Main PLL should be 0 + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @} + */ + + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Option byte reset is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR or POR/PDR reset is set or not. + * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(LPUART1) || defined(LPUART2) +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +#endif /* LPUART1 */ +#if defined(LPTIM1) && defined(LPTIM2) +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#endif /* LPTIM1 && LPTIM2 */ +#if defined(RNG) +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#endif /* RNG */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(FDCAN1) || defined(FDCAN2) +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +#endif /* FDCAN1 */ +uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); +uint32_t LL_RCC_GetRTCClockFreq(void); +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/License.md b/squero/Drivers/STM32G0xx_HAL_Driver/License.md new file mode 100644 index 0000000..e881f98 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2018 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c new file mode 100644 index 0000000..e56cd43 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c @@ -0,0 +1,759 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32G0xx HAL Driver version number + */ +#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32G0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32G0xx_HAL_VERSION_RC)) + +#if defined(VREFBUF) +#define VREFBUF_TIMEOUT_VALUE 10U /*!< 10 ms */ +#endif /* VREFBUF */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @brief HAL Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch and the Instruction cache, + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file + * stm32g0xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Configure Flash prefetch, Instruction cache */ + /* Default configuration at reset is: */ + /* - Prefetch disabled */ + /* - Instruction cache enabled */ + +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + __HAL_RCC_IOP_FORCE_RESET(); + __HAL_RCC_IOP_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32G0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @brief SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Pin remap + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disable the I/O analog switch voltage booster + (+) Enable/Disable dead battery behavior(*) + (+) Configure Clamping Diode on specific pins(*) + (*) Feature not available on all devices + +@endverbatim + * @{ + */ +#if defined(VREFBUF) +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_VoltageScale + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_HighImpedance + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @note VrefBuf voltage scale is calibrated in production for each device, + * using voltage scale 1. This calibration value is loaded + * as default trimming value at device power up. + * This trimming value can be fine tuned for voltage scales 0 and 1 + * using this function. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} +#endif /* VREFBUF */ + +/** + * @brief Enable the I/O analog switch voltage booster + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the remap on PA11_PA12 + * @param PinRemap specifies which pins have to be remapped + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + SET_BIT(SYSCFG->CFGR1, PinRemap); +} + +/** + * @brief Disable the remap on PA11_PA12 + * @param PinRemap specifies which pins will behave normally + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + CLEAR_BIT(SYSCFG->CFGR1, PinRemap); +} + +#if defined(SYSCFG_CDEN_SUPPORT) +/** + * @brief Enable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be enabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + SET_BIT(SYSCFG->CFGR2, PinConfig); +} + +/** + * @brief Disable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be disabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + CLEAR_BIT(SYSCFG->CFGR2, PinConfig); +} +#endif /* SYSCFG_CDEN_SUPPORT */ + +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +/** + * @brief Strobe configuration of GPIO depending on UCPDx dead battery settings + * @param ConfigDeadBattery specifies on which pins to make effective or not Dead Battery sw configuration + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_UCPD1_STROBE + * @arg @ref SYSCFG_UCPD2_STROBE + * @retval None + */ +void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery) +{ + assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery)); + + /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */ + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery); +} +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c new file mode 100644 index 0000000..6f99df3 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c @@ -0,0 +1,417 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex M0+ exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32g0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if (__MPU_PRESENT == 1U) +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0U) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c new file mode 100644 index 0000000..59fb0d3 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c @@ -0,0 +1,1191 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX + thanks to: + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(); + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function to register callbacks with HAL_DMA_RegisterCallback(). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ +#if defined(DMA2) + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; +#endif /* DMA2 */ + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + hdma->Init.PeriphInc | hdma->Init.MemInc | \ + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Compute the channel index */ +#if defined(DMA2) + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; +#endif /* DMA2 */ + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral handle */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + +#if defined(DMA2) + while ((hdma->DmaBaseAddress->ISR & temp) == 0U) + { + if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } +#else + while (0U == __HAL_DMA_GET_FLAG(hdma, temp)) + { + if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU)))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } +#endif /* DMA2 */ + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + /*Check for DMAMUX Request generator (if used) overrun status */ + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ +#if defined(DMA2) + uint32_t flag_it = hdma->DmaBaseAddress->ISR; +#else + uint32_t flag_it = DMA1->ISR; +#endif /* DMA2 */ + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + return; +} + +/** + * @brief Register callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback Pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + + + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + /* Return the DMA error code */ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif /* DMA2 */ + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number; + +#if defined(DMA2) + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + } +#else + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; +#endif /* DMA2 */ + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c new file mode 100644 index 0000000..1b2b909 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG(hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID), \ + (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos))); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if (hdma->DMAmuxRequestGen == 0U) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if (hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c new file mode 100644 index 0000000..eaa2e36 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c @@ -0,0 +1,672 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + EXTI->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + EXTI->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameterd */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c new file mode 100644 index 0000000..11c543a --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c @@ -0,0 +1,723 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Prefetch on I-Code + (+) 32 cache lines of 4*64 bits on I-Code + (+) Error code correction (ECC) : Data in flash are 72-bits word + (8 bits added per double word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32G0xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: double word and fast program (full row programming) + (++) There are two modes of programming: + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions: + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache + (+) Reset the Instruction cache + (+) Enable/Disable the Flash power-down during low-power run and sleep modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = FLASH_TYPENONE, \ + .Address = 0U, \ + .Banks = 0U, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program double word or fast program of a row at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program depending on the TypeProgram: + * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG or FSTPG Bit */ + CLEAR_BIT(FLASH->CR, TypeProgram); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program double word or fast program of a row at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program depending on the TypeProgram: + * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Enable End of Operation and Error interrupts */ + FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + } + + /* return status */ + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param; + uint32_t error; + + /* Save flash errors. */ + error = (FLASH->SR & FLASH_SR_ERRORS); + + /* A] Set parameter for user or error callbacks */ + /* check operation was a program or erase */ + if ((pFlash.ProcedureOnGoing & FLASH_TYPEERASE_MASS) != 0x00U) + { + /* return bank number */ + param = pFlash.Banks; + } + else + { + /* Clear operation only for page erase or program */ + CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); + + if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U) + { + /* return address being programmed */ + param = pFlash.Address; + } + else + { + /* return page number being erased */ + param = pFlash.Page; + } + } + + /* B] Check errors */ + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* clear error flags */ + FLASH->SR = FLASH_SR_ERRORS; + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + + /* Error callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* C] Check FLASH End of Operation flag */ + if ((FLASH->SR & FLASH_SR_EOP) != 0x00U) + { + /* Clear FLASH End of Operation pending bit */ + FLASH->SR = FLASH_SR_EOP; + + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase*/ + if (pFlash.NbPagesToErase != 0x00U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Banks, pFlash.Page); + } + else + { + /* No more pages to erase: stop erase pages procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + } + else + { + /*Stop the ongoing procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + + /* User callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) + { + /* Disable End of Operation and Error interrupts */ + FLASH->CR &= ~(FLASH_CR_EOPIE | FLASH_CR_ERRIE); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page which has been erased + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* verify Flash is unlock */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* verify option bytes are unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U) + { + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); + + /* verify option bytes are locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP Operation error + * @arg @ref HAL_FLASH_ERROR_PROG Programming error + * @arg @ref HAL_FLASH_ERROR_WRP Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ Size error + * @arg @ref HAL_FLASH_ERROR_PGS Programming sequence error + * @arg @ref HAL_FLASH_ERROR_MIS Fast programming data miss error + * @arg @ref HAL_FLASH_ERROR_FAST Fast programming error + * @arg @ref HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*) + * @arg @ref HAL_FLASH_ERROR_OPTV Option validity error + * @arg @ref HAL_FLASH_ERROR_ECCD two ECC errors have been detected + * @note (*) availability depends on devices + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t error; + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + uint32_t timeout = HAL_GetTick() + Timeout; + + /* Wait if any operation is ongoing */ +#if defined(FLASH_DBANK_SUPPORT) + error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); +#else + error = FLASH_SR_BSY1; +#endif /* FLASH_DBANK_SUPPORT */ + + while ((FLASH->SR & error) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + /* check flash errors */ + error = (FLASH->SR & FLASH_SR_ERRORS); + + /* Clear SR register */ + FLASH->SR = FLASH_SR_CLEAR; + + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode = error; + return HAL_ERROR; + } + + /* Wait for control register to be written */ + timeout = HAL_GetTick() + Timeout; + + while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Program double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Program first word */ + *(uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} + +/** + * @brief Fast program a 32 row double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. + * @retval None + */ +static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 0; + uint32_t dest = Address; + uint32_t src = DataAddress; + uint32_t primask_bit; + + /* Set FSTPG bit */ + SET_BIT(FLASH->CR, FLASH_CR_FSTPG); + + /* Enter critical section: row programming should not be longer than 7 ms */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Fast Program : 64 words */ + while (index < 64U) + { + *(uint32_t *)dest = *(uint32_t *)src; + src += 4U; + dest += 4U; + index++; + } + + /* wait for BSY1 in order to be sure that flash operation is ended befoire + allowing prefetch in flash. Timeout does not return status, as it will + be anyway done later */ + +#if defined(FLASH_DBANK_SUPPORT) + while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U) +#else + while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) +#endif /* FLASH_DBANK_SUPPORT */ + { + } + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c new file mode 100644 index 0000000..d187dac --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c @@ -0,0 +1,1310 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32G0xx + devices contains the following additional features + + (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write + capability (RWW) + (+) Single bank memory organization + (+) PCROP protection + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32G0xx devices. It includes + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase page, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the PCROP protection + (++) Set Securable memory area and boot entry point + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get Securable memory area and boot entry point information + + (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and + HAL_FLASHEx_DisableDebugger. + + (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck. + and modify this setting (for flash loader purpose e.g.) using + HAL_FLASHEx_ForceFlashEmpty. + + (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t Banks); +void FLASH_FlushCaches(void); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +#if defined(FLASH_PCROP_SUPPORT) +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, + uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, + uint32_t *PCROP1AEndAddr); +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); +#if defined(FLASH_DBANK_SUPPORT) +static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr); +static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr); +static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr); +static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr); +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2); +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2); +#else +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize); +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize); +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @param[out] PageError Pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased) + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { +#if !defined(FLASH_DBANK_SUPPORT) + /* For single bank product force Banks to Bank 1 */ + pEraseInit->Banks = FLASH_BANK_1; +#endif /* FLASH_DBANK_SUPPORT */ + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Proceed to Mass Erase */ + FLASH_MassErase(pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) + { + /* Start erase page */ + FLASH_PageErase(pEraseInit->Banks, index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = index; + break; + } + } + + /* If operation is completed or interrupted, disable the Page Erase Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* save procedure for interrupt treatment */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { +#if !defined(FLASH_DBANK_SUPPORT) + /* For single bank product force Banks to Bank 1 */ + pEraseInit->Banks = FLASH_BANK_1; +#endif /* FLASH_DBANK_SUPPORT */ + /* Store Bank number */ + pFlash.Banks = pEraseInit->Banks; + + /* Enable End of Operation and Error interrupts */ + FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Set Page to 0 for Interrupt callback management */ + pFlash.Page = 0; + + /* Proceed to Mass Erase */ + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /*Erase 1st page and wait for IT */ + FLASH_PageErase(pEraseInit->Banks, pEraseInit->Page); + } + } + + /* return status */ + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account only + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + * - a Power On Reset + * - an exit from Standby or Shutdown mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + uint32_t optr; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); + } + + /* Option register */ + if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER)) + { + /* Fully modify OPTR register with RDP & user data */ + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U) + { + /* Only modify RDP so get current user data */ + optr = FLASH_OB_GetUser(); + FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U) + { + /* Only modify user so get current RDP level */ + optr = FLASH_OB_GetRDP(); + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + } + else + { + /* nothing to do */ + } + +#if defined(FLASH_PCROP_SUPPORT) + /* PCROP Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U) + { + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); + + if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U) + { + /* Configure the 1A Proprietary code readout protection */ + FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U) + { + /* Configure the 1B Proprietary code readout protection */ + FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); + } + +#if defined(FLASH_DBANK_SUPPORT) + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_A) != 0x00U) + { + /* Configure the 2A Proprietary code readout protection */ + FLASH_OB_PCROP2AConfig(pOBInit->PCROP2AStartAddr, pOBInit->PCROP2AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_B) != 0x00U) + { + /* Configure the 2B Proprietary code readout protection */ + FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr); + } +#endif /* FLASH_DBANK_SUPPORT */ + } +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + /* Securable Memory Area Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U) + { +#if defined(FLASH_DBANK_SUPPORT) + /* Configure the securable memory area protection */ + FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize, pOBInit->SecSize2); +#else + /* Configure the securable memory area protection */ + FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); +#endif /* FLASH_DBANK_SUPPORT */ + } +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @note warning: this API only read flash register, it does not reflect any + * change that would have been programmed between previous Option byte + * loading and current call. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + * configuration information. The fields pOBInit->WRPArea should + * indicate which area is requested for the WRP. + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_ALL; + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + pOBInit->USERType = OB_USER_ALL; + +#if defined(FLASH_PCROP_SUPPORT) + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr)); + FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); +#if defined(FLASH_DBANK_SUPPORT) + FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr)); + FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B); +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) + /* Get the Securable Memory Area protection */ + FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize), &(pOBInit->SecSize2)); +#else + /* Get the Securable Memory Area protection */ + FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize)); +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +} + +#if defined(FLASH_ACR_DBG_SWEN) +/** + * @brief Enable Debugger. + * @note After calling this API, flash interface allow debugger intrusion. + * @retval None + */ +void HAL_FLASHEx_EnableDebugger(void) +{ + FLASH->ACR |= FLASH_ACR_DBG_SWEN; +} + + +/** + * @brief Disable Debugger. + * @note After calling this API, Debugger is disabled: it is no more possible to + * break, see CPU register, etc... + * @retval None + */ +void HAL_FLASHEx_DisableDebugger(void) +{ + FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; +} +#endif /* FLASH_ACR_DBG_SWEN */ + +/** + * @brief Flash Empty check + * @note This API checks if first location in Flash is programmed or not. + * This check is done once by Option Byte Loader. + * @retval 0 if 1st location is not programmed else + */ +uint32_t HAL_FLASHEx_FlashEmptyCheck(void) +{ + return ((FLASH->ACR & FLASH_ACR_PROGEMPTY)); +} + + +/** + * @brief Force Empty check value. + * @note Allows to modify program empty check value in order to force this + * infrmation in Flash Interface, for all next reset that do not launch + * Option Byte Loader. + * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check + * @retval None + */ +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty) +{ + uint32_t acr; + assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + + acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY); + FLASH->ACR = (acr | FlashEmpty); +} + + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +/** + * @brief Securable memory area protection enable + * @param Banks Select Bank to be secured. + * This parameter can be a value of @ref FLASH_Banks + * @note On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1. + * @note This API locks Securable memory area which is defined in SEC_SIZE option byte + * (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking + * Secsize). + * @note SEC_PROT bit can only be set, it will be reset by system reset. + * @retval None + */ +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks) +{ +#if defined(FLASH_DBANK_SUPPORT) + assert_param(IS_FLASH_BANK(Banks)); + + if (Banks == (FLASH_BANK_2 | FLASH_BANK_1)) + { + FLASH->CR |= (FLASH_CR_SEC_PROT2 | FLASH_CR_SEC_PROT); + } + else if (Banks == FLASH_BANK_2) + { + FLASH->CR |= FLASH_CR_SEC_PROT2; + } + else +#else + UNUSED(Banks); +#endif /* FLASH_DBANK_SUPPORT */ + { + FLASH->CR |= FLASH_CR_SEC_PROT; + } +} +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory. + * @param Banks: Banks to be erased + * This parameter can be a combination of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased* + * @note (*) availability depends on devices + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Set the Mass Erase Bit and start bit */ + FLASH->CR |= (FLASH_CR_STRT | Banks); +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Banks: Banks to be erased + * This parameter can one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased* + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in Flash - 1) + * @note (*) availability depends on devices + * @retval None + */ +void FLASH_PageErase(uint32_t Banks, uint32_t Page) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_FLASH_PAGE(Page)); + + /* Get configuration register, then clear page number */ + tmp = (FLASH->CR & ~FLASH_CR_PNB); + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if page has to be erased in bank 1 or 2 */ + if (Banks != FLASH_BANK_1) + { + tmp |= FLASH_CR_BKER; + } + else + { + tmp &= ~FLASH_CR_BKER; + } +#endif /* FLASH_DBANK_SUPPORT */ + + /* Set page number, Page Erase bit & Start bit */ + FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); +} + +/** + * @brief Flush the instruction cache. + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } +} + + +/** + * @brief Configure the write protection of the desired pages. + * @note When WRP is active in a zone, it cannot be erased or programmed. + * Consequently, a software mass erase cannot be performed if one zone + * is write-protected. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @param WRPArea Specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + * @note (*) availability depends on devices + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash Bank - 1) + * @param WRDPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash Bank - 1) + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRDPEndOffset)); + + /* Configure the write protected area */ + if (WRPArea == OB_WRPAREA_ZONE_A) + { + FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); + } +#if defined(FLASH_DBANK_SUPPORT) + else if (WRPArea == OB_WRPAREA_ZONE2_A) + { + FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_ZONE2_B) + { + FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); + } +#endif /* FLASH_DBANK_SUPPORT */ + else + { + FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); + } +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @param[in] WRPArea Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + * @note (*) availability depends on devices + * @param[out] WRPStartOffset Specifies the address where to copied the start page + * of the write protected area + * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of + * the write protected area + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_ZONE_A) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); + } +#if defined(FLASH_DBANK_SUPPORT) + else if (WRPArea == OB_WRPAREA_ZONE2_A) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos); + } + else if (WRPArea == OB_WRPAREA_ZONE2_B) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos); + } +#endif /* FLASH_DBANK_SUPPORT */ + else + { + *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); + } +} + +/** + * @brief Set user & RDP configuration + * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible + * to go back to level 1 or 0 !!! + * @param UserType The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * @param UserConfig The FLASH User Option Bytes values. + * This parameter can be a combination of: + * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + * @arg @ref FLASH_OB_USER_nRST_STOP + * @arg @ref FLASH_OB_USER_nRST_STANDBY + * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + * @arg @ref FLASH_OB_USER_IWDG_SW + * @arg @ref FLASH_OB_USER_IWDG_STOP + * @arg @ref FLASH_OB_USER_IWDG_STANDBY + * @arg @ref FLASH_OB_USER_WWDG_SW + * @arg @ref FLASH_OB_USER_SRAM_PARITY + * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + * @arg @ref FLASH_OB_USER_nBOOT_SEL + * @arg @ref FLASH_OB_USER_nBOOT1 + * @arg @ref FLASH_OB_USER_nBOOT0 + * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Memory Read protection + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note (*) availability depends on devices + * @retval None + */ +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) +{ + uint32_t optr; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + assert_param(IS_OB_USER_CONFIG(UserType, UserConfig)); + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + optr = FLASH->OPTR; + optr &= ~(UserType | FLASH_OPTR_RDP); + FLASH->OPTR = (optr | UserConfig | RDPLevel); +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This return value can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdplvl; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values. It will be a combination of all the following values: + * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + * @arg @ref FLASH_OB_USER_nRST_STOP + * @arg @ref FLASH_OB_USER_nRST_STANDBY + * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + * @arg @ref FLASH_OB_USER_IWDG_SW + * @arg @ref FLASH_OB_USER_IWDG_STOP + * @arg @ref FLASH_OB_USER_IWDG_STANDBY + * @arg @ref FLASH_OB_USER_WWDG_SW + * @arg @ref FLASH_OB_USER_SRAM_PARITY + * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + * @arg @ref FLASH_OB_USER_nBOOT_SEL + * @arg @ref FLASH_OB_USER_nBOOT1 + * @arg @ref FLASH_OB_USER_nBOOT0 + * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + * @note (*) availability depends on devices + */ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL); + return user; +} + +#if defined(FLASH_PCROP_SUPPORT) +/** + * @brief Configure the 1A Proprietary code readout protection & erase configuration on RDP regression. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) + * on RDP level 1 regression. + * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t pcrop1aend; + uint32_t ropbase; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AEndAddr)); + + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif /* FLASH_DBANK_SUPPORT */ + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AEndAddr)); + + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* get pcrop 1A end register */ + pcrop1aend = FLASH->PCROP1AER; + + /* Configure the Proprietary code readout protection offset */ + if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U) + { + /* Compute offset depending on pcrop granularity */ + startoffset = ((PCROP1AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone A start offset */ + FLASH->PCROP1ASR = startoffset; + + /* Set Zone A end offset */ + pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END; + pcrop1aend |= endoffset; + } + + /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ + if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U) + { + pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; + } + + /* set 1A End register */ + FLASH->PCROP1AER = pcrop1aend; +} + +/** + * @brief Configure the 1B Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPB_STRT and PCROPB_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BEndAddr)); + + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif /* FLASH_DBANK_SUPPORT */ + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BEndAddr)); + + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP1BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone B start offset */ + FLASH->PCROP1BSR = startoffset; + /* Set Zone B end offset */ + FLASH->PCROP1BER = endoffset; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option. + * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address + * of the 1A Proprietary code readout protection + * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of + * the 1A Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif /* FLASH_DBANK_SUPPORT */ + { + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT); + *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AStartAddr += ropbase; + + pcrop = FLASH->PCROP1AER; + *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); + + *PCROPConfig &= ~OB_PCROP_RDP_ERASE; + *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP); +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address + * of the 1B Proprietary code readout protection + * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of + * the 1B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif /* FLASH_DBANK_SUPPORT */ + { + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT); + *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BStartAddr += ropbase; + + pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END); + *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} + +#if defined(FLASH_DBANK_SUPPORT) +/** + * @brief Configure the 2A Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP2AStartAddr Specifies the Zone 2A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP2AEndAddr Specifies the Zone 2A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP2AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AEndAddr)); + + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AEndAddr)); + + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP2AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP2AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone A start offset */ + FLASH->PCROP2ASR = startoffset; + /* Set Zone A end offset */ + FLASH->PCROP2AER = endoffset; +} + +/** + * @brief Configure the 2B Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROP_STRT and PCROP_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP2BStartAddr Specifies the Zone 2B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP2BEndAddr Specifies the Zone 2B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP2BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BEndAddr)); + + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BEndAddr)); + + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP2BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP2BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone B start offset */ + FLASH->PCROP2BSR = startoffset; + /* Set Zone B end offset */ + FLASH->PCROP2BER = endoffset; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP2AStartAddr [out] Specifies the address where to copied the start address + * of the 2A Proprietary code readout protection + * @param PCROP2AEndAddr [out] Specifies the address where to copied the end address of + * the 2A Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP2ASR & FLASH_PCROP2ASR_PCROP2A_STRT); + *PCROP2AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2AStartAddr += ropbase; + + pcrop = (FLASH->PCROP2AER & FLASH_PCROP2AER_PCROP2A_END); + *PCROP2AEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP2BStartAddr [out] Specifies the address where to copied the start address + * of the 2B Proprietary code readout protection + * @param PCROP2BEndAddr [out] Specifies the address where to copied the end address of + * the 2B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP2BSR & FLASH_PCROP2BSR_PCROP2B_STRT); + *PCROP2BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2BStartAddr += ropbase; + + pcrop = (FLASH->PCROP2BER & FLASH_PCROP2BER_PCROP2B_END); + *PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +/** + * @brief Configure Securable Memory area feature. + * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced + * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH Flash selected as unique entry boot + * @param SecSize specifies number of pages to protect as securable memory area, starting from + * beginning of Bank1 (page 0). + * @param SecSize2 specifies number of pages to protect as securable memory area, starting from + * beginning of Bank2 (page 0). + * @retval None + */ +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2) +{ + uint32_t secmem; + + /* Check the parameters */ + assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + assert_param(IS_OB_SEC_SIZE(SecSize)); + + if ((FLASH_BANK_NB == 2U)) + { + assert_param(IS_OB_SEC_SIZE(SecSize2)); + } + + /* Set securable memory area configuration */ + secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE | FLASH_SECR_SEC_SIZE2)); + FLASH->SECR = (secmem | BootEntry | SecSize | (SecSize2 << FLASH_SECR_SEC_SIZE2_Pos)); +} + +/** + * @brief Return the FLASH Securable memory area protection Option Bytes value. + * @param BootEntry specifies boot scheme configuration + * @param SecSize specifies number of pages to protect as secure memory area, starting from + * beginning of Bank1 (page 0). + * @param SecSize2 specifies number of pages to protect as secure memory area, starting from + * beginning of Bank2 (page 0). + * @retval None + */ +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2) +{ + uint32_t secmem = FLASH->SECR; + + *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + *SecSize = (secmem & FLASH_SECR_SEC_SIZE); + *SecSize2 = (secmem & FLASH_SECR_SEC_SIZE2) >> FLASH_SECR_SEC_SIZE2_Pos; +} + +#else +/** + * @brief Configure Securable Memory area feature. + * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced + * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot + * @param SecSize specifies number of pages to protect as securable memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) +{ + uint32_t secmem; + + /* Check the parameters */ + assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + assert_param(IS_OB_SEC_SIZE(SecSize)); + + /* Set securable memory area configuration */ + secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE)); + FLASH->SECR = (secmem | BootEntry | SecSize); +} + +/** + * @brief Return the FLASH Securable memory area protection Option Bytes value. + * @param BootEntry specifies boot scheme configuration + * @param SecSize specifies number of pages to protect as secure memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize) +{ + uint32_t secmem = FLASH->SECR; + + *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + *SecSize = (secmem & FLASH_SECR_SEC_SIZE); +} +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c new file mode 100644 index 0000000..1444420 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c @@ -0,0 +1,551 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16u) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + temp = EXTI->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (8u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + EXTI->EXTICR[position >> 2u] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = EXTI->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (8u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (8u * (position & 0x03u)); + EXTI->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c new file mode 100644 index 0000000..d1d801d --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c @@ -0,0 +1,6796 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() + @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Slave_Seq_Transmit_IT() + or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Slave_Seq_Receive_IT() + or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + @ref HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + @ref HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + @ref HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + @ref HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + @ref HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + [..] + Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + or @ref HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hi2c); + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Normal use case for Transmitter mode */ + /* A NACK is generated to confirm the end of transfer */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + return HAL_ERROR; + } + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + uint32_t tickstart; + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if a NACK is detected */ + if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + return HAL_OK; +} + +/** + * @brief This function handles Acknowledge failed detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + /* In case of Soft End condition, generate the STOP condition */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + /* Wait until STOP Flag is reset */ + /* AutoEnd should be initiate after AF */ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c new file mode 100644 index 0000000..828ae18 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32G0xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c new file mode 100644 index 0000000..9a451c4 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c @@ -0,0 +1,545 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + [..] + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pins are used to wakeup the system from Standby mode or + Shutdown mode. WakeUp pins polarity can be set to configure event + detection on high level (rising edge) or low level (falling edge). + + *** Low Power mode configuration *** + ===================================== + [..] + The devices feature 7 low-power modes: + (+) Low-power run mode: core and peripherals are running at low frequency. + Regulator is in low power mode. + (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running, + regulator is main mode. + (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running + and regulator in low power mode. + (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is + main mode. + (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator + off, low power regulator on. + (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is + disable. + (+) Shutdown mode: all clocks are stopped except LSE, regulator is + disable. + + *** Low-power run mode *** + ========================== + [..] + (+) Entry: (from main run mode) + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after + having decreased the system clock below 2 MHz. + (+) Exit: + (++) clear LPR bit then wait for REGLPF bit to be reset with + HAL_PWREx_DisableLowPowerRunMode() API. Only then can the + system clock frequency be increased above 2 MHz. + + *** Sleep mode / Low-power sleep mode *** + ========================================= + [..] + (+) Entry: + The Sleep & Low-power Sleep modes are entered through + HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator + is forced to low-power mode and if exit is interrupt or event + triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low + power mode). In this case, the system clock frequency must have + been decreased below 2 MHz beforehand. + (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction + (+) WFI Exit: + (++) Any interrupt enabled in nested vectored interrupt controller (NVIC) + (+) WFE Exit: + (++) Any wakeup event if cortex is configured with SEVONPEND = 0 + (++) Interrupt even when disabled in NVIC if cortex is configured with + SEVONPEND = 1 + [..] When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. + + *** Stop 0 & Stop 1 modes *** + ============================= + [..] + (+) Entry: + The Stop modes are entered through the following APIs: + (++) HAL_PWR_EnterSTOPMode() with following settings: + (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode. + (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode. + (+) Exit (interrupt or event-triggered, specified when entering STOP mode): + (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction + (+) WFI Exit: + (++) Any EXTI line (internal or external) configured in interrupt mode + with corresponding interrupt enable in NVIC + (+) WFE Exit: + (++) Any EXTI line (internal or external) configured in event mode if + cortex is configured with SEVONPEND = 0 + (++) Any EXTI line configured in interrupt mode (even if the + corresponding EXTI Interrupt vector is disabled in the NVIC) if + cortex is configured with SEVONPEND = 0. The interrupt source can + be external interrupts or peripherals with wakeup capability. + [..] When exiting Stop, the MCU is either in Run mode or in Low-power Run mode + depending on the LPR bit setting. + + *** Standby mode *** + ==================== + [..] In Standby mode, it is possible to keep backup SRAM content (defined as + full SRAM) keeping low power regulator on. This is achievable by setting + Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases + power consumption. + Its also possible to define I/O states using APIs: + HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown & + HAL_PWREx_EnablePullUpPullDownConfig + (+) Entry: + (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by + setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + tamper event (internal & external), LSE CSS detection, reset on + NRST pin, IWDG reset & BOR reset. + [..] Exiting Standby generates a power reset: Cortex is reset and execute + Reset handler vector, all registers in the Vcore domain are set to + their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, + and Standby/Shutdown modes control) are not impacted. + + *** Shutdown mode *** + ====================== + [..] + In Shutdown mode, + voltage regulator is disabled, all clocks are off except LSE, RRS bit is + cleared. SRAM and registers contents are lost except for backup domain + registers. + (+) Entry: + (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API, + by setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + tamper event (internal & external), LSE CSS detection, reset on + NRST pin. + [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute + Reset handler vector, all registers are set to their reset value but ones + in backup domain. + +@endverbatim + * @{ + */ + +/** + * @brief Enable access to the backup domain + * (RTC & TAMP registers, backup registers, RCC BDCR register). + * @note After reset, the backup domain is protected against + * possible unwanted write accesses. All RTC & TAMP registers (backup + * registers included) and RCC BDCR register are concerned. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + + +/** + * @brief Disable access to the backup domain + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values which set + * the default polarity i.e. detection on high level (rising edge): + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly specify + * the enabled pin and the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*) + * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*) + * @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note (*) availability depends on devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); +} + + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*), + * PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + * @note (*) availability depends on devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); +} + + +/** + * @brief Enter Sleep or Low-power Sleep mode. + * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as + * in Run mode. + * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep + * mode. This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator + * in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode only. In + * case Regulator parameter is set to Low Power but MCU is in Run mode, + * we will first enter in Low-power Run mode. Therefore, user should + * take care that HCLK frequency is less than 2 MHz. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. + * To switch back to Run mode, user must call + * HAL_PWREx_DisableLowPowerRunMode() API. + * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE + * instruction. This parameter can be one of the following values: + * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep + * mode with WFI instruction + * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep + * mode with WFE instruction + * @note When WFI entry is used, tick interrupt have to be disabled if not + * desired as the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if (Regulator != PWR_MAINREGULATOR_ON) + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u) + { + HAL_PWREx_EnableLowPowerRunMode(); + } + } + else + { + /* If in low-power run mode at this point, exit it */ + if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u) + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + { + return ; + } + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + +/** + * @brief Enter Stop mode + * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with + * legacy code running on devices where only "Stop mode" is mentioned + * with main or low power regulator ON. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the HSI and the + * HSE oscillators are disabled. Some peripherals with the wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. + * SRAM and register contents are preserved. + * The BOR is available. + * The voltage regulator can be configured either in normal (Stop 0) or + * low-power mode (Stop 1). + * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock + * @note When the voltage regulator operates in low power mode (Stop 1), + * an additional startup delay is incurred when waking up. By keeping + * the internal regulator ON during Stop mode (Stop 0), the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode + * This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power + * regulator ON) + * @param STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or + * WFE instruction. This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI + * instruction. + * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE + * instruction. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + if (Regulator != PWR_MAINREGULATOR_ON) + { + /* Stop mode with Low-Power Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); + } + else + { + /* Stop mode with Main Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + } + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + + +/** + * @brief Enter Standby mode. + * @note In Standby mode, the PLL, the HSI and the HSE oscillators are + * switched off. The voltage regulator is disabled. SRAM and register + * contents are lost except for registers in the Backup domain and + * Standby circuitry. BOR is available. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention() + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Set Stand-by mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif /* __CC_ARM */ + + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Enable Sleep-On-Exit Cortex feature + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over returning to thread mode. Setting this bit is + * useful when the processor is expected to run only on interruptions + * handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disable Sleep-On-Exit Cortex feature + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enable Cortex Sev On Pending feature. + * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled + * events and all interrupts, including disabled ones can wakeup + * processor from WFE. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disable Cortex Sev On Pending feature. + * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only + * enable interrupts or events can wakeup processor from WFE + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c new file mode 100644 index 0000000..bb3422b --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c @@ -0,0 +1,1019 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U /*!< Mask for interruption yielded + by PVD threshold crossing */ +#define PVD_MODE_EVT 0x00020000U /*!< Mask for event yielded + by PVD threshold crossing */ +#define PVD_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as + PVD trigger */ +#define PVD_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as + PVD trigger */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ + +/** @defgroup PWREx_TimeOut_Value PWREx Flag Setting Time Out Value + * @{ + */ +#define PWR_REGLPF_SETTING_DELAY_6_US 6u /*!< REGLPF should rise in about 5 us plus + 2 APB clock. Taking in account max Sysclk at + 2 MHz, and rounded to upper value */ + +#define PWR_VOSF_SETTING_DELAY_6_US 6u /*!< VOSF should rise in about 5 us plus + 2 APB clock. Taking in account max Sysclk at + 16 MHz, and rounded to upper value */ +/** + * @} + */ + +/** @defgroup PWREx_Gpio_Pin_Number PWREx Gpio Pin Number + * @{ + */ +#define PWR_GPIO_PIN_NB 16u /*!< Number of gpio pin in bank */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Initialization and de-initialization functions ##### + =============================================================================== + [..] + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PVDRT[2:0] & PVDFT[2:0] bits in + PWR CR2 register). + (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 and can generate an interrupt if enabled. + (+) The PVD is stopped in Standby & Shutdown mode. + + *** PVM configuration *** + ========================= + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Enable battery charging. + * @note When VDD is present, charge the external battery on VBAT through an + * internal resistor. + * @param ResistorSelection specifies the resistor impedance. + * This parameter can be one of the following values: + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @retval None + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) +{ + uint32_t tmpreg; + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); + + /* Specify resistor selection and enable battery charging */ + tmpreg = (PWR->CR4 & ~PWR_CR4_VBRS); + PWR->CR4 = (tmpreg | ResistorSelection | PWR_CR4_VBE); +} + + +/** + * @brief Disable battery charging. + * @retval None + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + +#if defined(PWR_CR3_ENB_ULP) +/** + * @brief Enable POR Monitor sampling mode. + * @note When entering ultra low power modes (standby, shutdown) this feature + * can be enabled to reduce further consumption: Power On Reset monitor + * is then set in sampling mode, and no more in always on mode. + * @retval None + */ +void HAL_PWREx_EnablePORMonitorSampling(void) +{ + PWR->CR3 |= PWR_CR3_ENB_ULP; +} + + +/** + * @brief Disable POR Monitor sampling mode. + * @retval None + */ +void HAL_PWREx_DisablePORMonitorSampling(void) +{ + PWR->CR3 &= ~PWR_CR3_ENB_ULP; +} +#endif /* PWR_CR3_ENB_ULP */ + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the Power Voltage Detector (PVD). + * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the + PVD configuration information: threshold levels, operating mode. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level. + * @note User should take care that rising threshold is higher than falling + * one in order to avoid having always PVDO output set. + * @retval HAL_OK + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PVD level bits only according to PVDLevel value */ + MODIFY_REG(PWR->CR2, (PWR_CR2_PVDFT | PWR_CR2_PVDRT), sConfigPVD->PVDLevel); + + /* Clear any previous config, in case no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + + +/** + * @brief Enable the Power Voltage Detector (PVD). + * @retval None + */ +void HAL_PWREx_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDE); +} + + +/** + * @brief Disable the Power Voltage Detector (PVD). + * @retval None + */ +void HAL_PWREx_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @retval None + */ +void HAL_PWREx_EnableVddUSB(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_USV); +} + +/** + * @brief Disable VDDUSB supply. + * @retval None + */ +void HAL_PWREx_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_USV); +} +#endif /* PWR_PVM_SUPPORT */ + +#if defined(PWR_CR2_IOSV) +/** + * @brief Enable VDDIO2 supply. + * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + * @retval None + */ +void HAL_PWREx_EnableVddIO2(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_IOSV); +} + + +/** + * @brief Disable VDDIO2 supply. + * @retval None + */ +void HAL_PWREx_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); +} +#endif /* PWR_CR2_IOSV */ + +#if defined (PWR_PVM_SUPPORT) +/** + * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_EnablePVMUSB(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_USB); +} + +/** + * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_DisablePVMUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_USB); +} +#endif /* PWR_PVM_SUPPORT */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information. + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly + * called for each PVM used. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level and to each monitored supply. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + + /* Configure EXTI 34 interrupts if so required: + scan through PVMType to detect which PVMx is set and + configure the corresponding EXTI line accordingly. */ + switch (sConfigPVM->PVMType) + { + case PWR_PVM_USB: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM_EXTI_DISABLE_IT(); + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); + } + + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* PWR_PVM_SUPPORT */ +/** + * @brief Enable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_EnableInternalWakeUpLine(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Disable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_DisableInternalWakeUpLine(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + + case PWR_GPIO_D: + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + +#if defined(GPI0E) + case PWR_GPIO_E: + SET_BIT(PWR->PUCRE, GPIONumber); + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; +#endif /* GPI0E */ + case PWR_GPIO_F: + SET_BIT(PWR->PUCRF, GPIONumber); + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + + case PWR_GPIO_D: + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + +#if defined(GPI0E) + case PWR_GPIO_E: + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; +#endif /* GPI0E */ + case PWR_GPIO_F: + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + + case PWR_GPIO_D: + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + +#if defined(GPIOE) + case PWR_GPIO_E: + SET_BIT(PWR->PDCRE, GPIONumber); + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; +#endif /* GPI0E */ + case PWR_GPIO_F: + SET_BIT(PWR->PDCRF, GPIONumber); + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + + case PWR_GPIO_D: + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + +#if defined(GPIOE) + case PWR_GPIO_E: + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; +#endif /* GPI0E */ + case PWR_GPIO_F: + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there + * is no conflict when setting PUy or PDy bit. + * @retval None + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @retval None + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + +#if defined(PWR_CR3_RRS) +/** + * @brief Enable SRAM content retention in Standby mode. + * @note When RRS bit is set, SRAM is powered by the low-power regulator in + * Standby mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAMRetention(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_RRS); +} + + +/** + * @brief Disable SRAM content retention in Standby mode. + * @note When RRS bit is reset, SRAM is powered off in Standby mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAMRetention(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); +} +#endif /* PWR_CR3_RRS */ + +/** + * @brief Enable Flash Power Down. + * @note This API allows to enable flash power down capabilities in low power + * run, low power sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 |= PowerMode; +} + + +/** + * @brief Disable Flash Power Down. + * @note This API allows to disable flash power down capabilities in low power + * run, low power sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 &= ~PowerMode; +} + + +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + + +/** + * @brief Configure the main regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + * typical output voltage at 1.2 V, + * system frequency up to 64 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + * typical output voltage at 1.0 V, + * system frequency up to 16 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be + * cleared before returning the status. If the flag is not cleared within + * 6 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t wait_loop_index; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Modify voltage scaling range */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); + + /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* Set timeout value */ + wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; + + /* Wait until VOSF is reset */ + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + if (wait_loop_index != 0U) + { + wait_loop_index--; + } + else + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + + + +/** + * @brief Enter Low-power Run mode + * @note System clock frequency has to be decreased below 2 MHz before entering + * low power run mode + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + + +/** + * @brief Exit Low-power Run mode. + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + + /* Wait until REGLPF is reset */ + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) + { + if (wait_loop_index != 0U) + { + wait_loop_index--; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + + +#if defined(PWR_SHDW_SUPPORT) +/** + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. + * SRAM and registers contents are lost except for registers in the Backup domain. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @retval None + + * @retval None + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif /* __CC_ARM */ + + /* Request Wait For Interrupt */ + __WFI(); +} +#endif /* PWR_SHDW_SUPPORT */ + +#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + /* Check PWR PVD exti Rising flag */ + if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWREx_PVD_PVM_Rising_Callback(); + } + + /* Check PWR exti fallling flag */ + if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWREx_PVD_PVM_Falling_Callback(); + } + + /* Check PWR PVM exti Rising flag */ + if (__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVM exti pending bit */ + __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD PVM interrupt rising user callback */ + HAL_PWREx_PVD_PVM_Rising_Callback(); + } + + /* Check PWR PVM exti fallling flag */ + if (__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVM exti pending bit */ + __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM interrupt falling user callback */ + HAL_PWREx_PVD_PVM_Falling_Callback(); + } +} + +/** + * @brief PWR PVD interrupt rising callback + * @retval None + */ +__weak void HAL_PWREx_PVD_PVM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWREx_PVD_PVM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} +#elif defined(PWR_PVD_SUPPORT) +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_IRQHandler(void) +{ + /* Check PWR exti Rising flag */ + if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWREx_PVD_Rising_Callback(); + } + + /* Check PWR exti fallling flag */ + if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWREx_PVD_Falling_Callback(); + } +} + +/** + * @brief PWR PVD interrupt rising callback + * @retval None + */ +__weak void HAL_PWREx_PVD_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWREx_PVD_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} + +#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c new file mode 100644 index 0000000..50f2ad7 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c @@ -0,0 +1,1457 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + (from 8 MHz to reach 16MHz) with Flash 0 wait state. Flash prefetch buffer, + D-Cache and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses: + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (RTC, ADC, RNG, HSTIM) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_HSI48_SUPPORT */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ + +#define PLLSOURCE_NONE (0U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#if defined(RCC_MCO2_SUPPORT) +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOA +#define MCO2_PIN GPIO_PIN_10 +#endif /* RCC_MCO2_SUPPORT */ + +#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB) + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: + (++) The first output (R) is used to generate the high speed system clock (up to 64MHz). + (++) The second output(Q) is used to generate the clock for the random analog generator and HStim. + (++) The Third output (P) is used to generate the clock for the Analog to Digital Converter and I2S. + + (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched respectively to HSI or LSI and an interrupt is generated + if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCOx (microcontroller clock output): + (++) MCO1 used to output LSI, HSI48(*), HSI, LSE, HSE or main PLL clock (through a configurable prescaler) on PA8 pin. + (++) MCO2(*) used to output LSI, HSI48(*), HSI, LSE, HSE, main PLLR clock, PLLQ clock, PLLP clock, RTC clock or RTC_Wakeup (through a configurable prescaler) on PA10 pin. + (*) available on certain devices only + + [..] System, AHB and APB buses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE, LSI, LSE and main PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + + (+@) RNG(*) requires a frequency equal or lower than 48 MHz. + This clock is derived from the main PLL or HSI or System clock. + (*) available on certain devices only + + (+@) IWDG clock which is always the LSI clock. + + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 64 MHz. + Depending on the device voltage range, the maximum frequency should be + adapted accordingly. + + @endverbatim + + (++) Table 1. HCLK clock frequency. + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | + (++) |-----------------|------------------|------------------| + (++) |2WS(3 CPU cycles)| HCLK <= 64 | - | + (++) |-----------------|------------------|------------------| + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL OFF + * - AHB and APB prescaler set to 1. + * - CSS, MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + RCC->ICSCR = RCC_ICSCR_HSITRIM_6; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (HSI is selected as system clock source) */ + RCC->CFGR = 0x00000000u; + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Then again to HSEBYP in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* once PLL is OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000u; + + /* Clear all flags */ + RCC->CICR = 0xFFFFFFFFu; + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * @ref RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then to HSE On or HSE Bypass. + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then to LSE On or LSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp_sysclksrc; + uint32_t temp_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + { + if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + { + /* When HSI is used as system clock or as PLL input clock it can not be disabled */ + if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* Adjust the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Update the SystemCoreClock global variable with HSISYS value */ + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Configure the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Enable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check if LSI is used as system clock */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + { + /* When LSI is used as system clock it will not be disabled */ + if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* When the LSE is used as system clock, it is not allowed disable it */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + { + if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + } +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); +#if defined(RCC_PLLQ_SUPPORT) + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#endif /* RCC_PLLQ_SUPPORT */ + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, +#if defined(RCC_PLLQ_SUPPORT) + RCC_OscInitStruct->PLL.PLLQ, +#endif /* RCC_PLLQ_SUPPORT */ + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLLR Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Disable all PLL outputs to save power */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); + +#if defined(RCC_PLLQ_SUPPORT) + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); +#else + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); +#endif /* RCC_PLLQ_SUPPORT */ + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp_pllckcfg = RCC->PLLCFGR; + if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || +#if defined (RCC_PLLQ_SUPPORT) + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || +#endif /* RCC_PLLQ_SUPPORT */ + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the HSI frequency is set to 8 Mhz, then it reaches its default value 16 MHz. + * + * @note The HSI can be selected as system clock source after + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note The LSI can be selected as system clock source after + * in case of failure of the LSE used directly or indirectly + * as system clock (if the Clock Security System LSECSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* LSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + { + /* Check the LSI ready flag */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* LSE is selected as System Clock Source */ + else + { + /* Check the LSE ready flag */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*). + * @note PA8, PA10(*) should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32G0xx family this parameter can have only one value: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA10)(*). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48(*) + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*) + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*) + * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48(*) + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLCLK main PLLR clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_Wakeup selected as MCO2 source(*) + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @arg @ref RCC_MCO2DIV_1 no division applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_2 division by 2 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_4 division by 4 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_8 division by 8 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_16 division by 16 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_32 division by 32 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_64 division by 64 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_128 division by 128 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_256 division by 256 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_512 division by 512 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_1024 division by 1024 applied to MCO2 clock(*) + * + * (*) Feature not available on all devices of the family + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + + /* Common GPIO init parameters */ + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + } +#if defined(RCC_MCO2_SUPPORT) + else if (RCC_MCOx == RCC_MCO2) + { + assert_param(IS_RCC_MCO2DIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Alternate = GPIO_AF3_MCO2; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv)); + } +#endif /* RCC_MCO2_SUPPORT */ +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(***) + * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(****) + * @note (*) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note (***) LSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 32768 Hz). + * @note (****) LSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 32000 Hz). + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllvco, pllsource, pllr, pllm, hsidiv; + uint32_t sysclockfreq; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSISYS can be derived for HSI16 */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + + /* HSI used as system clock source */ + sysclockfreq = (HSI_VALUE / hsidiv); + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* PLL used as system clock source */ + + /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ + default: /* HSI16 used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; + break; + } + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); + sysclockfreq = pllvco / pllr; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + { + /* LSE used as system clock source */ + sysclockfreq = LSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + { + /* LSI used as system clock source */ + sysclockfreq = LSI_VALUE; + } + else + { + sysclockfreq = 0U; + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; +#else + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + RCC_OscInitStruct->HSIDiv = (RCC->CR & RCC_CR_HSIDIV); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration ---------------------------------------------*/ + if (READ_BIT(RCC->CR, RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP); +#if defined(RCC_PLLQ_SUPPORT) + RCC_OscInitStruct->PLL.PLLQ = (RCC->PLLCFGR & RCC_PLLCFGR_PLLQ); +#endif /* RCC_PLLQ_SUPPORT */ + RCC_OscInitStruct->PLL.PLLR = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR); +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Enable the LSE Clock Security System. + * @note If a failure is detected on the LSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The LSE Clock Security System Detection bit (LSECSSD in BDCR) can only be + * cleared by a backup domain reset. + * @retval None + */ +void HAL_RCC_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disable the LSE Clock Security System. + * @note After LSE failure detection, the software must disable LSECSSON + * @note The Clock Security System can only be cleared by reset otherwise. + * @retval None + */ +void HAL_RCC_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + uint32_t itflag = RCC->CIFR; + + /* Clear interrupt flags related to CSS */ + RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF)); + + /* Check RCC CSSF interrupt flag */ + if ((itflag & RCC_CIFR_CSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } + + /* Check RCC LSECSSF interrupt flag */ + if ((itflag & RCC_CIFR_LSECSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_LSECSSCallback(); + } +} + +/** + * @brief Handle the RCC HSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @brief RCC LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_LSECSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_LSECSSCallback should be implemented in the user file + */ +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c new file mode 100644 index 0000000..bb1c3e7 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c @@ -0,0 +1,1681 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */ + +#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LSCO_GPIO_PORT GPIOA +#define LSCO_PIN GPIO_PIN_2 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the @ref RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + * + * @note (1) Peripherals are not available on all devices + * @note (2) Peripherals clock selection is not available on all devices + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + FlagStatus pwrclkchanged = RESET; + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(RCC_CCIPR_USART2SEL) + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + /*-------------------------- USART3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } +#endif /* LPUART1 */ + +#if defined(LPUART2) + /*-------------------------- LPUART2 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART2CLKSOURCE(PeriphClkInit->Lpuart2ClockSelection)); + + /* Configure the LPUART clock source */ + __HAL_RCC_LPUART2_CONFIG(PeriphClkInit->Lpuart2ClockSelection); + } +#endif /* LPUART2 */ + +#if defined(RCC_CCIPR_LPTIM1SEL) + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + { + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + { + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } +#endif /* RCC_CCIPR_LPTIM2SEL */ + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(RCC_CCIPR_I2C2SEL) + /*-------------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } +#endif /* (RCC_CCIPR_I2C2SEL */ + +#if defined(RNG) + /*-------------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RNG */ + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } + +#if defined(CEC) + /*-------------------------- CEC clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* CEC */ + +#if defined(RCC_CCIPR_TIM1SEL) + /*-------------------------- TIM1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + + /* Configure the TIM1 clock source */ + __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + + if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) + /*-------------------------- TIM15 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + + /* Configure the TIM15 clock source */ + __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + + if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RCC_CCIPR_TIM15SEL */ + + /*-------------------------- I2S1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); + + /* Configure the I2S1 clock source */ + __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); + + if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } + +#if defined(RCC_CCIPR2_I2S2SEL) + /*-------------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + /*-------------------------- USB clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(FDCAN1) || defined(FDCAN2) + /*-------------------------- FDCAN clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + + /* Configure the FDCAN clock source */ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + + if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* FDCAN1 || FDCAN2 */ + + return status; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks: I2C1, I2S1, USART1, RTC, ADC, + * LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RNG (1) + * @note (1) Peripheral is not available on all devices + * @note (2) Peripheral clock selection is not available on all devices + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \ + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC ; + +#if defined(RCC_CCIPR_LPTIM1SEL) && defined(RCC_CCIPR_LPTIM2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM1; +#endif /* RCC_CCIPR_LPTIM1SEL && RCC_CCIPR_LPTIM2SEL */ +#if defined(RCC_CCIPR_RNGSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_RNG; +#endif /* RCC_CCIPR_RNGSEL */ +#if defined(RCC_CCIPR_LPUART1SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1; +#endif /* RCC_CCIPR_LPUART1SEL */ +#if defined(RCC_CCIPR_LPUART2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART2; +#endif /* RCC_CCIPR_LPUART2SEL */ +#if defined(RCC_CCIPR_CECSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR_TIM1SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; +#endif /* RCC_CCIPR_TIM15SEL */ +#if defined(RCC_CCIPR_USART2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(RCC_CCIPR_I2C2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR2_I2S2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; +#endif /* RCC_CCIPR2_I2S2SEL */ +#if defined(RCC_CCIPR2_USBSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(RCC_CCIPR2_FDCANSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN; +#endif /* RCC_CCIPR_FDCANSEL */ + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(RCC_CCIPR_USART2SEL) + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(RCC_CCIPR_LPUART1SEL) + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#endif /* RCC_CCIPR_LPUART1SEL */ +#if defined(RCC_CCIPR_LPUART2SEL) + /* Get the LPUART2 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart2ClockSelection = __HAL_RCC_GET_LPUART2_SOURCE(); +#endif /* RCC_CCIPR_LPUART2SEL */ + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#if defined(RCC_CCIPR_I2C2SEL) + /* Get the I2C2 clock source -----------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +#endif /* RCC_CCIPR_LPTIM2SEL */ +#if defined(RCC_CCIPR_TIM1SEL) + /* Get the TIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + /* Get the TIM15 clock source ---------------------------------------------*/ + PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); +#endif /* RCC_CCIPR_TIM15SEL */ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +#if defined(RCC_CCIPR_RNGSEL) + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#endif /* RCC_CCIPR_RNGSEL */ + /* Get the ADC clock source -----------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); +#if defined(RCC_CCIPR_CECSEL) + /* Get the CEC clock source -----------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR2_USBSEL) + /* Get the USB clock source -----------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(RCC_CCIPR2_FDCANSEL) + /* Get the FDCAN clock source -----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); +#endif /* RCC_CCIPR2_FDCANSEL */ + /* Get the I2S1 clock source -----------------------------------------------*/ + PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE(); +#if defined(RCC_CCIPR2_I2S2SEL) + /* Get the I2S2 clock source -----------------------------------------------*/ + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); +#endif /* RCC_CCIPR2_I2S2SEL */ +} + +/** + * @brief Return the peripheral clock frequency for peripherals with clock source from PLL + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1) + * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock(1) + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + * @note (1) Peripheral not available on all devices + * @note (2) Peripheral Clock configuration not available on all devices + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0U; + uint32_t srcclk; + uint32_t pllvco; + uint32_t plln; +#if defined(RCC_CCIPR_RNGSEL) + uint32_t rngclk; + uint32_t rngdiv; +#endif /* RCC_CCIPR_RNGSEL */ + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + if (PeriphClk == RCC_PERIPHCLK_RTC) + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) + { + frequency = HSE_VALUE / 32U; + } + /* Clock not enabled for RTC*/ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + } + else + { + /* Other external peripheral clock source than RTC */ + + /* Compute PLL clock input */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ + { + pllvco = HSI_VALUE; + } + else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ + { + pllvco = HSE_VALUE; + } + else /* No source */ + { + pllvco = 0U; + } + + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + + switch (PeriphClk) + { +#if defined(RCC_CCIPR_RNGSEL) + case RCC_PERIPHCLK_RNG: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL); + if (srcclk == RCC_RNGCLKSOURCE_HSI_DIV8) /* HSI_DIV8 ? */ + { + rngclk = HSI_VALUE / 8U; + } + else if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */ + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + rngclk = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + else if (srcclk == RCC_RNGCLKSOURCE_SYSCLK) /* SYSCLK ? */ + { + rngclk = HAL_RCC_GetSysClockFreq(); + } + else /* No clock source */ + { + rngclk = 0U; + } + + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + frequency = (rngclk / rngdiv); + + break; +#endif /* RCC_CCIPR_RNGSEL */ + case RCC_PERIPHCLK_USART1: + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK ? */ + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#if defined(RCC_CCIPR_USART2SEL) + case RCC_PERIPHCLK_USART2: + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + case RCC_PERIPHCLK_USART3: + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(RCC_CCIPR_CECSEL) + case RCC_PERIPHCLK_CEC: + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_CECCLKSOURCE_HSI_DIV488)) + { + frequency = (HSI_VALUE / 488U); + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for CEC */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_CECSEL */ + +#if defined(RCC_CCIPR_LPUART1SEL) + case RCC_PERIPHCLK_LPUART1: + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPUART1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPUART1SEL */ + +#if defined(RCC_CCIPR_LPUART2SEL) + case RCC_PERIPHCLK_LPUART2: + /* Get the current LPUART2 source */ + srcclk = __HAL_RCC_GET_LPUART2_SOURCE(); + + if (srcclk == RCC_LPUART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_LPUART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPUART2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPUART2SEL */ + + case RCC_PERIPHCLK_ADC: + + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + if (srcclk == RCC_ADCCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCCLKSOURCE_HSI) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_ADCCLKSOURCE_PLLADC) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + /* Clock not enabled for ADC */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case RCC_PERIPHCLK_I2C1: + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for I2C1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + +#if defined(RCC_CCIPR_I2C2SEL) + case RCC_PERIPHCLK_I2C2: + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for I2C2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_I2C2SEL */ + + case RCC_PERIPHCLK_I2S1: + /* Get the current I2S1 source */ + srcclk = __HAL_RCC_GET_I2S1_SOURCE(); + + if (srcclk == RCC_I2S1CLKSOURCE_PLL) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + else if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_I2S1CLKSOURCE_EXT) + { + /* External clock used.*/ + frequency = EXTERNAL_I2S1_CLOCK_VALUE; + } + /* Clock not enabled for I2S1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + +#if defined(RCC_CCIPR2_I2S2SEL) + case RCC_PERIPHCLK_I2S2: + /* Get the current I2S2 source */ + srcclk = __HAL_RCC_GET_I2S2_SOURCE(); + + if (srcclk == RCC_I2S2CLKSOURCE_PLL) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + else if (srcclk == RCC_I2S2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_I2S2CLKSOURCE_EXT) + { + /* External clock used.*/ + frequency = EXTERNAL_I2S2_CLOCK_VALUE; + } + /* Clock not enabled for I2S2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) + case RCC_PERIPHCLK_LPTIM1: + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) + case RCC_PERIPHCLK_LPTIM2: + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(RCC_CCIPR_TIM1SEL) + case RCC_PERIPHCLK_TIM1: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL); + + if (srcclk == RCC_TIM1CLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_TIM1CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) + case RCC_PERIPHCLK_TIM15: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL); + + if (srcclk == RCC_TIM15CLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_TIM15CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(RCC_CCIPR2_USBSEL) + case RCC_PERIPHCLK_USB: + + srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL); + + if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } +#if defined(RCC_HSI48_SUPPORT) + else if (srcclk == RCC_USBCLKSOURCE_HSI48) /* HSI48 ? */ + { + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + } +#endif /* RCC_HSI48_SUPPORT */ + else if (srcclk == RCC_USBCLKSOURCE_HSE) + { + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_USBSEL */ + +#if defined(RCC_CCIPR2_FDCANSEL) + case RCC_PERIPHCLK_FDCAN: + + srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL); + + if (srcclk == RCC_FDCANCLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_FDCANSEL */ + + default: + break; + } + } + + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of LSE CSS, Low speed clock output and + clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + GPIO_InitTypeDef GPIO_InitStruct; + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* LSCO Pin Clock Enable */ + LSCO_CLK_ENABLE(); + + /* Configure the LSCO pin in analog mode */ + GPIO_InitStruct.Pin = LSCO_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); + + /* Update LSCOSEL clock source in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); + + if (backupchanged == SET) + { + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Update LSCOEN bit in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable access to the backup domain */ + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); + + /* Restore previous configuration */ + if (backupchanged == SET) + { + /* Disable access to the backup domain */ + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and sychronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; /* no init needed */ + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c new file mode 100644 index 0000000..c33c4b1 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c @@ -0,0 +1,7782 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ +#define TIMx_OR1_OCREF_CLR 0x00000001U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ + CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); + break; + } +#if defined(COMP1) || defined(COMP2) || defined(COMP3) +#if defined(COMP1) && defined(COMP2) + case TIM_CLEARINPUTSOURCE_COMP1: + case TIM_CLEARINPUTSOURCE_COMP2: +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) + case TIM_CLEARINPUTSOURCE_COMP3: +#endif /* COMP3 */ + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* OCREF_CLR_INT is connected to COMPx output */ + MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource); + break; + } +#endif /* COMP1 || COMP2 || COMP3 */ + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ + CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c new file mode 100644 index 0000000..322ebc0 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c @@ -0,0 +1,2843 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } +#if defined(COMP1) && defined(COMP2) + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) + case TIM_BREAKINPUTSOURCE_COMP3: + { + bkin_enable_mask = TIM1_AF1_BKCMP3E; + bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP3P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; + break; + } +#endif /* COMP3 */ + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can take one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1: TIM1 ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2: TIM1 ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_COMP3: TIM1 ETR is connected to COMP3 output (**) + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3 + * + * For TIM2, the parameter can take one of the following values: (*) + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_COMP3: TIM2_ETR is connected to COMP3 output (**) + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO (**) + * @arg TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2 (**) + * + * For TIM3, the parameter can take one of the following values: + * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO + * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output + * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output + * @arg TIM_TIM3_ETR_COMP3 TIM3_ETR is connected to COMP3 output (**) + * + * For TIM4, the parameter can take one of the following values:(*) + * @arg TIM_TIM4_ETR_GPIO TIM4_ETR is connected to GPIO + * @arg TIM_TIM4_ETR_COMP1 TIM4_ETR is connected to COMP1 output + * @arg TIM_TIM4_ETR_COMP2 TIM4_ETR is connected to COMP2 output + * @arg TIM_TIM4_ETR_COMP3 TIM4_ETR is connected to COMP3 output (**) + * + * (*) Timer instance not available on all devices \n + * (**) Value not defined in all devices. \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_3: TI3 input channel + * @param TISelection specifies the timer input source + * + * For TIM1 this parameter can be one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO + * @arg TIM_TIM1_TI2_COMP2: TIM1 TI2 is connected to COMP2 output + * @arg TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO + * @arg TIM_TIM1_TI3_COMP3: TIM1 TI3 is connected to COMP3 output (**) + * + * For TIM2, the parameter is one of the following values: (*) + * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO + * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output + * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO + * @arg TIM_TIM2_TI3_COMP3: TIM2 TI3 is connected to COMP3 output (**) + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO + * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output + * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO + * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output (**) + * + * For TIM4, the parameter is one of the following values: (*) + * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO + * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output + * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO + * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output + * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO + * @arg TIM_TIM4_TI3_COMP3: TIM4 TI3 is connected to COMP3 output + * + * For TIM14, the parameter is one of the following values: + * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_RTC: TIM14 TI1 is connected to RTC clock + * @arg TIM_TIM14_TI1_HSE_32: TIM14 TI1 is connected to HSE div 32 + * @arg TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO + * @arg TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2 (**) + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC_WAKEUP: TIM16 TI1 is connected to TRC wakeup interrupt + * @arg TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2 (**) + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_HSI: TIM17 TI1 is connected to HSI (**) + * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 + * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO + * @arg TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2 (**) + * + * (*) Timer instance not available on all devices \n + * (**) Value not defined in all devices. \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + break; + } + + return HAL_OK; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + break; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c new file mode 100644 index 0000000..dfdf991 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_ll_dma.h" +#include "stm32g0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#if defined(DMA2) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#else +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#endif /* DMA1_Channel8 */ +#endif /* DMA2 */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_ALL + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } +#if defined(DMA2) + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } +#endif /* DMA2 */ + else + { + status = ERROR; + } + } + else + { + DMA_Channel_TypeDef *tmp; + + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + WRITE_REG(tmp->CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + WRITE_REG(tmp->CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + WRITE_REG(tmp->CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + WRITE_REG(tmp->CMAR, 0U); + + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_DMA_ClearFlag_GI4(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_DMA_ClearFlag_GI5(DMAx); + } +#if defined(DMA1_Channel6) + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } +#endif /* DMA1_Channel6 */ +#if defined(DMA1_Channel7) + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } +#endif /* DMA1_Channel7 */ + else + { + status = ERROR; + } + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: DMA_CxCR[7:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c new file mode 100644 index 0000000..91394b9 --- /dev/null +++ b/squero/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c @@ -0,0 +1,1358 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(LPUART1) && defined(LPUART2) +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE)) +#elif defined(LPUART1) +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) +#endif /* LPUART1 && LPUART2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) +#else +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(LPTIM1) || defined(LPTIM2) +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) +#endif /* LPTIM1 || LPTIM2 */ + +#if defined(RNG) +#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) +#endif /* RNG */ + +#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE)) +#else +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL) +#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE)) +#elif defined(RCC_CCIPR_TIM1SEL) +#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)) +#endif /* RCC_CCIPR_TIM1SEL */ + + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_PLL_GetFreqDomain_SYS(void); +static uint32_t RCC_PLL_GetFreqDomain_ADC(void); +static uint32_t RCC_PLL_GetFreqDomain_I2S1(void); +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +static uint32_t RCC_PLL_GetFreqDomain_I2S2(void); +static uint32_t RCC_PLL_GetFreqDomain_USB(void); +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +#if defined(FDCAN1) || defined(FDCAN2) +static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void); +#endif /* FDCAN1 || FDCAN2 */ +#if defined(RNG) +static uint32_t RCC_PLL_GetFreqDomain_RNG(void); +#endif /* RNG */ +#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL) +static uint32_t RCC_PLL_GetFreqDomain_TIM1(void); +#endif /* RCC_PLLQ_SUPPORT && RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) +static uint32_t RCC_PLL_GetFreqDomain_TIM15(void); +#endif /* RCC_CCIPR_TIM15SEL */ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + /* Set HSION bit and wait for HSI READY bit */ + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + {} + + /* Set HSITRIM bits to reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x40U); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + + /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */ + LL_RCC_WriteReg(CR, RCC_CR_HSION); + while (LL_RCC_HSE_IsReady() != 0U) + {} + LL_RCC_WriteReg(CR, RCC_CR_HSION); + + /* Wait for PLL READY bit to be reset */ + while (LL_RCC_PLL_IsReady() != 0U) + {} + + /* Reset PLLCFGR register */ + LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIER, 0x00000000U); + + /* Clear all interrupts flags */ + LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) + * or HSI_VALUE(**) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a constant defined in this file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in this file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(RCC_CCIPR_USART2SEL) + else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + else if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART3SEL */ + else + { + /* nothing to do */ + } + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + /* I2C1 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(RCC_CCIPR_I2C2SEL) + else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) + { + /* I2C2 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_I2C2SEL */ + else + { + /* nothing to do */ + } + + return i2c_frequency; +} + +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) + { + /* I2S1 CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S1_CLKSOURCE_HSI: /* I2S1 Clock is HSI */ + i2s_frequency = HSI_VALUE; + break; + + case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S1(); + } + break; + + + case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S1_CLKSOURCE_SYSCLK: /* I2S1 Clock is System Clock */ + default: + i2s_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#if defined(RCC_CCIPR2_I2S2SEL) + else if (I2SxSource == LL_RCC_I2S2_CLKSOURCE) + { + /* I2S2 CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S2_CLKSOURCE_HSI: /* I2S2 Clock is HSI */ + i2s_frequency = HSI_VALUE; + break; + + case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S2(); + } + break; + + case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /* I2S2 Clock is System Clock */ + default: + i2s_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#endif /* RCC_CCIPR2_I2S2SEL */ + else + { + } + return i2s_frequency; +} + +#if defined(LPUART1) || defined(LPUART2) +/** + * @brief Return LPUARTx clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*) + * @retval LPUART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + * (*) feature not available on all devices + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + + if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE) + { + /* LPUART1CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lpuart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ + default: + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(LPUART2) + else if (LPUARTxSource == LL_RCC_LPUART2_CLKSOURCE) + { + /* LPUART2CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART2_CLKSOURCE_SYSCLK: /* LPUART2 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART2_CLKSOURCE_HSI: /* LPUART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lpuart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART2_CLKSOURCE_LSE: /* LPUART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART2_CLKSOURCE_PCLK1: /* LPUART2 Clock is PCLK1 */ + default: + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* LPUART2 */ + else + { + } + + return lpuart_frequency; +} +#endif /* LPUART1 */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else + { + /* LPTIM2CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + + return lptim_frequency; +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Return TIMx clock frequency + * @param TIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE + * @endif + * @retval TIMx clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource) +{ + uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource)); + + if (TIMxSource == LL_RCC_TIM1_CLKSOURCE) + { + /* TIM1CLK clock frequency */ + switch (LL_RCC_GetTIMClockSource(TIMxSource)) + { + case LL_RCC_TIM1_CLKSOURCE_PLL: /* TIM1 Clock is PLLQ */ + if (LL_RCC_PLL_IsReady() == 1U) + { + tim_frequency = RCC_PLL_GetFreqDomain_TIM1(); + } + break; + + case LL_RCC_TIM1_CLKSOURCE_PCLK1: /* TIM1 Clock is PCLK1 */ + default: + tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(TIM15) + else + { + if (TIMxSource == LL_RCC_TIM15_CLKSOURCE) + { + /* TIM15CLK clock frequency */ + switch (LL_RCC_GetTIMClockSource(TIMxSource)) + { + case LL_RCC_TIM15_CLKSOURCE_PLL: /* TIM1 Clock is PLLQ */ + if (LL_RCC_PLL_IsReady() == 1U) + { + tim_frequency = RCC_PLL_GetFreqDomain_TIM15(); + } + break; + + case LL_RCC_TIM15_CLKSOURCE_PCLK1: /* TIM15 Clock is PCLK1 */ + default: + tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + } +#endif /* TIM15 */ + return tim_frequency; +} +#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */ + + +#if defined(RNG) +/** + * @brief Return RNGx clock frequency + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval RNG clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) +{ + uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t rngdiv; + + /* Check parameter */ + assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); + + /* RNGCLK clock frequency */ + switch (LL_RCC_GetRNGClockSource(RNGxSource)) + { + case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + rng_frequency = RCC_PLL_GetFreqDomain_RNG(); + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + } + break; + + case LL_RCC_RNG_CLKSOURCE_HSI_DIV8: /* HSI clock divided by 8 used as RNG clock source */ + rng_frequency = HSI_VALUE / 8U; + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + break; + case LL_RCC_RNG_CLKSOURCE_SYSCLK: /* SYSCLK clock used as RNG clock source */ + rng_frequency = RCC_GetSystemClockFreq(); + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + break; + + case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */ + default: + rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + + } + + return rng_frequency; +} +#endif /* RNG */ + +#if defined(CEC) +/** + * @brief Return CEC clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + cec_frequency = LSE_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady() == 1U) + { + cec_frequency = (HSI_VALUE / 488U); + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Return FDCANx clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval FDCANx clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource)); + + /* FDCANCLK clock frequency */ + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN_CLKSOURCE_PLL: /* FDCAN Clock is PLL "Q" Osc. */ + if (LL_RCC_PLL_IsReady() == 1U) + { + fdcan_frequency = RCC_PLL_GetFreqDomain_FDCAN(); + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_HSE: /* FDCAN Clock is HSE Osc. */ + if (LL_RCC_HSE_IsReady() == 1U) + { + fdcan_frequency = HSE_VALUE; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* FDCAN Clock is PCLK1 */ + default: + fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + + return fdcan_frequency; +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Return ADCx clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); + + /* ADCCLK clock frequency */ + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + adc_frequency = RCC_GetSystemClockFreq(); + break; + case LL_RCC_ADC_CLKSOURCE_HSI : /* HSI clock used as ADC clock source */ + adc_frequency = HSI_VALUE; + break; + + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLLP clock used as ADC clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + adc_frequency = RCC_PLL_GetFreqDomain_ADC(); + } + break; + default: + adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return adc_frequency; +} + +/** + * @brief Return RTC clock frequency + * @retval RTC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetRTCClockFreq(void) +{ + uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* RTCCLK clock frequency */ + switch (LL_RCC_GetRTCClockSource()) + { + case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */ + if (LL_RCC_LSE_IsReady() == 1U) + { + rtc_frequency = LSE_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */ + if (LL_RCC_LSI_IsReady() == 1U) + { + rtc_frequency = LSI_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE clock used as ADC clock source */ + rtc_frequency = HSE_VALUE / 32U; + break; + + case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */ + default: + rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return rtc_frequency; +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */ + if (LL_RCC_HSI48_IsReady() != 0U) + { + usb_frequency = HSI48_VALUE; + } + break; +#endif /* RCC_HSI48_SUPPORT */ + + case LL_RCC_USB_CLKSOURCE_HSE: /* HSE used as USB clock source */ + if (LL_RCC_HSE_IsReady() != 0U) + { + usb_frequency = HSE_VALUE; + } + break; + + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady() != 0U) + { + usb_frequency = RCC_PLL_GetFreqDomain_USB(); + } + break; + + default: + usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return usb_frequency; +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +static uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + frequency = (HSI_VALUE / hsidiv); + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); +} +/** + * @brief Return PLL clock frequency used for ADC domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_ADC(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + ADC Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Return PLL clock frequency used for FDCAN domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + FDCAN Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Return PLL clock frequency used for I2S1 domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_I2S1(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S1 Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Return PLL clock frequency used for I2S2 domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_I2S2(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S2 Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S2_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Return PLL clock frequency used for RNG domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_RNG(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + RNG Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Return PLL clock frequency used for USB domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_USB(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + RNG Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_USB_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL) +/** + * @brief Return PLL clock frequency used for TIM1 domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_TIM1(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + TIM1 Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_TIM1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Return PLL clock frequency used for TIM15 domain + * @retval PLL clock frequency (in Hz) + */ +static uint32_t RCC_PLL_GetFreqDomain_TIM15(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + TIM15 Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_TIM15_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RCC_CCIPR_TIM15SEL */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/squero/Makefile b/squero/Makefile new file mode 100644 index 0000000..1631208 --- /dev/null +++ b/squero/Makefile @@ -0,0 +1,194 @@ +########################################################################################################################## +# File automatically-generated by tool: [projectgenerator] version: [3.15.2] date: [Fri Dec 17 23:43:50 CET 2021] +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = squero + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -Og + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Core/Src/main.c \ +Core/Src/si5351.c \ +Core/Src/stm32g0xx_it.c \ +Core/Src/stm32g0xx_hal_msp.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c \ +Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c \ +Core/Src/system_stm32g0xx.c + +# ASM sources +ASM_SOURCES = \ +startup_stm32g031xx.s + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +ifdef GCC_PATH +CC = $(GCC_PATH)/$(PREFIX)gcc +AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy +SZ = $(GCC_PATH)/$(PREFIX)size +else +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m0plus + +# fpu +# NONE for Cortex-M0/M0+/M3 + +# float-abi + + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DUSE_HAL_DRIVER \ +-DSTM32G031xx + + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-ICore/Inc \ +-IDrivers/STM32G0xx_HAL_Driver/Inc \ +-IDrivers/STM32G0xx_HAL_Driver/Inc/Legacy \ +-IDrivers/CMSIS/Device/ST/STM32G0xx/Include \ +-IDrivers/CMSIS/Include + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf-2 +endif + + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32G031J6Mx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = +LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) +# list of ASM program objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** diff --git a/squero/STM32G031J6Mx_FLASH.ld b/squero/STM32G031J6Mx_FLASH.ld new file mode 100644 index 0000000..cd8c7f5 --- /dev/null +++ b/squero/STM32G031J6Mx_FLASH.ld @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32G031J6Mx series +** 32Kbytes FLASH and 8Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20002000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + diff --git a/squero/build/main.d b/squero/build/main.d new file mode 100644 index 0000000..2a5e624 --- /dev/null +++ b/squero/build/main.d @@ -0,0 +1,63 @@ +build/main.o: Core/Src/main.c Core/Inc/main.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h \ + Core/Inc/si5351.h Core/Inc/si5351_errors.h Core/Inc/si5351_asserts.h +Core/Inc/main.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: +Core/Inc/si5351.h: +Core/Inc/si5351_errors.h: +Core/Inc/si5351_asserts.h: diff --git a/squero/build/main.lst b/squero/build/main.lst new file mode 100644 index 0000000..5a5a778 --- /dev/null +++ b/squero/build/main.lst @@ -0,0 +1,1193 @@ +ARM GAS /tmp/ccCxCgQe.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "main.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.MX_GPIO_Init,"ax",%progbits + 16 .align 1 + 17 .arch armv6s-m + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 MX_GPIO_Init: + 24 .LFB300: + 25 .file 1 "Core/Src/main.c" + 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/main.c **** /** + 3:Core/Src/main.c **** ****************************************************************************** + 4:Core/Src/main.c **** * @file : main.c + 5:Core/Src/main.c **** * @brief : Main program body + 6:Core/Src/main.c **** ****************************************************************************** + 7:Core/Src/main.c **** * @attention + 8:Core/Src/main.c **** * + 9:Core/Src/main.c **** * Copyright (c) 2021 STMicroelectronics. + 10:Core/Src/main.c **** * All rights reserved. + 11:Core/Src/main.c **** * + 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/main.c **** * in the root directory of this software component. + 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/main.c **** * + 16:Core/Src/main.c **** ****************************************************************************** + 17:Core/Src/main.c **** */ + 18:Core/Src/main.c **** /* USER CODE END Header */ + 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 20:Core/Src/main.c **** #include "main.h" + 21:Core/Src/main.c **** + 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ + 24:Core/Src/main.c **** #include + 25:Core/Src/main.c **** #include "si5351.h" + 26:Core/Src/main.c **** + 27:Core/Src/main.c **** /* USER CODE END Includes */ + 28:Core/Src/main.c **** + 29:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 30:Core/Src/main.c **** /* USER CODE BEGIN PTD */ + 31:Core/Src/main.c **** + 32:Core/Src/main.c **** /* USER CODE END PTD */ + 33:Core/Src/main.c **** + ARM GAS /tmp/ccCxCgQe.s page 2 + + + 34:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ + 35:Core/Src/main.c **** /* USER CODE BEGIN PD */ + 36:Core/Src/main.c **** /* USER CODE END PD */ + 37:Core/Src/main.c **** + 38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 39:Core/Src/main.c **** /* USER CODE BEGIN PM */ + 40:Core/Src/main.c **** + 41:Core/Src/main.c **** /* USER CODE END PM */ + 42:Core/Src/main.c **** + 43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 44:Core/Src/main.c **** I2C_HandleTypeDef hi2c2; + 45:Core/Src/main.c **** + 46:Core/Src/main.c **** /* USER CODE BEGIN PV */ + 47:Core/Src/main.c **** uint32_t frequenza; + 48:Core/Src/main.c **** + 49:Core/Src/main.c **** /* USER CODE END PV */ + 50:Core/Src/main.c **** + 51:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 52:Core/Src/main.c **** void SystemClock_Config(void); + 53:Core/Src/main.c **** static void MX_GPIO_Init(void); + 54:Core/Src/main.c **** static void MX_I2C2_Init(void); + 55:Core/Src/main.c **** /* USER CODE BEGIN PFP */ + 56:Core/Src/main.c **** + 57:Core/Src/main.c **** /* USER CODE END PFP */ + 58:Core/Src/main.c **** + 59:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 60:Core/Src/main.c **** /* USER CODE BEGIN 0 */ + 61:Core/Src/main.c **** + 62:Core/Src/main.c **** /* USER CODE END 0 */ + 63:Core/Src/main.c **** + 64:Core/Src/main.c **** /** + 65:Core/Src/main.c **** * @brief The application entry point. + 66:Core/Src/main.c **** * @retval int + 67:Core/Src/main.c **** */ + 68:Core/Src/main.c **** int main(void) + 69:Core/Src/main.c **** { + 70:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 71:Core/Src/main.c **** + 72:Core/Src/main.c **** /* USER CODE END 1 */ + 73:Core/Src/main.c **** + 74:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 75:Core/Src/main.c **** + 76:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 77:Core/Src/main.c **** HAL_Init(); + 78:Core/Src/main.c **** + 79:Core/Src/main.c **** /* USER CODE BEGIN Init */ + 80:Core/Src/main.c **** + 81:Core/Src/main.c **** /* USER CODE END Init */ + 82:Core/Src/main.c **** + 83:Core/Src/main.c **** /* Configure the system clock */ + 84:Core/Src/main.c **** SystemClock_Config(); + 85:Core/Src/main.c **** + 86:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ + 87:Core/Src/main.c **** + 88:Core/Src/main.c **** /* USER CODE END SysInit */ + 89:Core/Src/main.c **** + 90:Core/Src/main.c **** /* Initialize all configured peripherals */ + ARM GAS /tmp/ccCxCgQe.s page 3 + + + 91:Core/Src/main.c **** MX_GPIO_Init(); + 92:Core/Src/main.c **** MX_I2C2_Init(); + 93:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 94:Core/Src/main.c **** frequenza = 1359000; + 95:Core/Src/main.c **** HAL_Delay(100); + 96:Core/Src/main.c **** si5351_Init(); + 97:Core/Src/main.c **** HAL_Delay(500); + 98:Core/Src/main.c **** CalcRegisters(frequenza); + 99:Core/Src/main.c **** /* USER CODE END 2 */ + 100:Core/Src/main.c **** + 101:Core/Src/main.c **** /* Infinite loop */ + 102:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ + 103:Core/Src/main.c **** while (1) + 104:Core/Src/main.c **** { + 105:Core/Src/main.c **** /* USER CODE END WHILE */ + 106:Core/Src/main.c **** + 107:Core/Src/main.c **** /* USER CODE BEGIN 3 */ + 108:Core/Src/main.c **** + 109:Core/Src/main.c **** + 110:Core/Src/main.c **** // HAL_I2C_Master_Transmit(&hi2c2, ((uint16_t)0x60)<<1, "ciao", 4, HAL_MAX_DELAY); + 111:Core/Src/main.c **** // da 24 a 36 + 112:Core/Src/main.c **** /* + 113:Core/Src/main.c **** a = 24; + 114:Core/Src/main.c **** b = 28437; + 115:Core/Src/main.c **** c = 1048562; + 116:Core/Src/main.c **** d = 442; + 117:Core/Src/main.c **** e = 0; + 118:Core/Src/main.c **** f = 1; + 119:Core/Src/main.c **** */ + 120:Core/Src/main.c **** /* + 121:Core/Src/main.c **** si5351_setupPLL(SI5351_PLL_A, a, b, c); + 122:Core/Src/main.c **** HAL_Delay(10); + 123:Core/Src/main.c **** si5351_setupMultisynth(0, SI5351_PLL_A, d, e, f); + 124:Core/Src/main.c **** HAL_Delay(10); + 125:Core/Src/main.c **** si5351_setupRdiv(0, SI5351_R_DIV_1); + 126:Core/Src/main.c **** HAL_Delay(10); + 127:Core/Src/main.c **** + 128:Core/Src/main.c **** si5351_setupMultisynth(1, SI5351_PLL_A, d, e, f); + 129:Core/Src/main.c **** HAL_Delay(10); + 130:Core/Src/main.c **** si5351_setupRdiv(1, SI5351_R_DIV_1); + 131:Core/Src/main.c **** HAL_Delay(10); + 132:Core/Src/main.c **** */ + 133:Core/Src/main.c **** if(HAL_GPIO_ReadPin(UP_GPIO_Port, UP_Pin)){ + 134:Core/Src/main.c **** frequenza += 9000; + 135:Core/Src/main.c **** if(frequenza > 1800000) frequenza = 585000; + 136:Core/Src/main.c **** CalcRegisters(frequenza); + 137:Core/Src/main.c **** } + 138:Core/Src/main.c **** + 139:Core/Src/main.c **** // 2a volta serve per avere fase non casuale + 140:Core/Src/main.c **** // si5351_setupPLL(SI5351_PLL_A, 24, 28437, 1048562); + 141:Core/Src/main.c **** + 142:Core/Src/main.c **** /* + 143:Core/Src/main.c **** si5351_setupPLL(SI5351_PLL_B, 28, 7012, 390625); + 144:Core/Src/main.c **** si5351_setupMultisynth(2, SI5351_PLL_B, 1336, 0, 1); + 145:Core/Src/main.c **** si5351_setupRdiv(2, SI5351_R_DIV_16); + 146:Core/Src/main.c **** */ + 147:Core/Src/main.c **** + ARM GAS /tmp/ccCxCgQe.s page 4 + + + 148:Core/Src/main.c **** si5351_enableOutputs(0xFF); + 149:Core/Src/main.c **** HAL_Delay(100); + 150:Core/Src/main.c **** + 151:Core/Src/main.c **** } + 152:Core/Src/main.c **** /* USER CODE END 3 */ + 153:Core/Src/main.c **** } + 154:Core/Src/main.c **** + 155:Core/Src/main.c **** /** + 156:Core/Src/main.c **** * @brief System Clock Configuration + 157:Core/Src/main.c **** * @retval None + 158:Core/Src/main.c **** */ + 159:Core/Src/main.c **** void SystemClock_Config(void) + 160:Core/Src/main.c **** { + 161:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 162:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 163:Core/Src/main.c **** + 164:Core/Src/main.c **** /** Configure the main internal regulator output voltage + 165:Core/Src/main.c **** */ + 166:Core/Src/main.c **** HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + 167:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 168:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. + 169:Core/Src/main.c **** */ + 170:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 171:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 172:Core/Src/main.c **** RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + 173:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 174:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 175:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 176:Core/Src/main.c **** { + 177:Core/Src/main.c **** Error_Handler(); + 178:Core/Src/main.c **** } + 179:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 180:Core/Src/main.c **** */ + 181:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 182:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; + 183:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + 184:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 185:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 186:Core/Src/main.c **** + 187:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 188:Core/Src/main.c **** { + 189:Core/Src/main.c **** Error_Handler(); + 190:Core/Src/main.c **** } + 191:Core/Src/main.c **** } + 192:Core/Src/main.c **** + 193:Core/Src/main.c **** /** + 194:Core/Src/main.c **** * @brief I2C2 Initialization Function + 195:Core/Src/main.c **** * @param None + 196:Core/Src/main.c **** * @retval None + 197:Core/Src/main.c **** */ + 198:Core/Src/main.c **** static void MX_I2C2_Init(void) + 199:Core/Src/main.c **** { + 200:Core/Src/main.c **** + 201:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 0 */ + 202:Core/Src/main.c **** + 203:Core/Src/main.c **** /* USER CODE END I2C2_Init 0 */ + 204:Core/Src/main.c **** + ARM GAS /tmp/ccCxCgQe.s page 5 + + + 205:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 1 */ + 206:Core/Src/main.c **** + 207:Core/Src/main.c **** /* USER CODE END I2C2_Init 1 */ + 208:Core/Src/main.c **** hi2c2.Instance = I2C2; + 209:Core/Src/main.c **** hi2c2.Init.Timing = 0x00303D5B; + 210:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 211:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 212:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 213:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 214:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 215:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 216:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 217:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 218:Core/Src/main.c **** { + 219:Core/Src/main.c **** Error_Handler(); + 220:Core/Src/main.c **** } + 221:Core/Src/main.c **** /** Configure Analogue filter + 222:Core/Src/main.c **** */ + 223:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 224:Core/Src/main.c **** { + 225:Core/Src/main.c **** Error_Handler(); + 226:Core/Src/main.c **** } + 227:Core/Src/main.c **** /** Configure Digital filter + 228:Core/Src/main.c **** */ + 229:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + 230:Core/Src/main.c **** { + 231:Core/Src/main.c **** Error_Handler(); + 232:Core/Src/main.c **** } + 233:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 2 */ + 234:Core/Src/main.c **** + 235:Core/Src/main.c **** /* USER CODE END I2C2_Init 2 */ + 236:Core/Src/main.c **** + 237:Core/Src/main.c **** } + 238:Core/Src/main.c **** + 239:Core/Src/main.c **** /** + 240:Core/Src/main.c **** * @brief GPIO Initialization Function + 241:Core/Src/main.c **** * @param None + 242:Core/Src/main.c **** * @retval None + 243:Core/Src/main.c **** */ + 244:Core/Src/main.c **** static void MX_GPIO_Init(void) + 245:Core/Src/main.c **** { + 26 .loc 1 245 1 view -0 + 27 .cfi_startproc + 28 @ args = 0, pretend = 0, frame = 32 + 29 @ frame_needed = 0, uses_anonymous_args = 0 + 30 0000 00B5 push {lr} + 31 .LCFI0: + 32 .cfi_def_cfa_offset 4 + 33 .cfi_offset 14, -4 + 34 0002 89B0 sub sp, sp, #36 + 35 .LCFI1: + 36 .cfi_def_cfa_offset 40 + 246:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 37 .loc 1 246 3 view .LVU1 + 38 .loc 1 246 20 is_stmt 0 view .LVU2 + 39 0004 1422 movs r2, #20 + 40 0006 0021 movs r1, #0 + ARM GAS /tmp/ccCxCgQe.s page 6 + + + 41 0008 03A8 add r0, sp, #12 + 42 000a FFF7FEFF bl memset + 43 .LVL0: + 247:Core/Src/main.c **** + 248:Core/Src/main.c **** /* GPIO Ports Clock Enable */ + 249:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 44 .loc 1 249 3 is_stmt 1 view .LVU3 + 45 .LBB4: + 46 .loc 1 249 3 view .LVU4 + 47 .loc 1 249 3 view .LVU5 + 48 000e 0E4B ldr r3, .L2 + 49 0010 596B ldr r1, [r3, #52] + 50 0012 0422 movs r2, #4 + 51 0014 1143 orrs r1, r2 + 52 0016 5963 str r1, [r3, #52] + 53 .loc 1 249 3 view .LVU6 + 54 0018 596B ldr r1, [r3, #52] + 55 001a 0A40 ands r2, r1 + 56 001c 0192 str r2, [sp, #4] + 57 .loc 1 249 3 view .LVU7 + 58 001e 019A ldr r2, [sp, #4] + 59 .LBE4: + 60 .loc 1 249 3 view .LVU8 + 250:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 61 .loc 1 250 3 view .LVU9 + 62 .LBB5: + 63 .loc 1 250 3 view .LVU10 + 64 .loc 1 250 3 view .LVU11 + 65 0020 596B ldr r1, [r3, #52] + 66 0022 0122 movs r2, #1 + 67 0024 1143 orrs r1, r2 + 68 0026 5963 str r1, [r3, #52] + 69 .loc 1 250 3 view .LVU12 + 70 0028 5B6B ldr r3, [r3, #52] + 71 002a 1A40 ands r2, r3 + 72 002c 0292 str r2, [sp, #8] + 73 .loc 1 250 3 view .LVU13 + 74 002e 029B ldr r3, [sp, #8] + 75 .LBE5: + 76 .loc 1 250 3 view .LVU14 + 251:Core/Src/main.c **** + 252:Core/Src/main.c **** /*Configure GPIO pin : PC14 */ + 253:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_14; + 77 .loc 1 253 3 view .LVU15 + 78 .loc 1 253 23 is_stmt 0 view .LVU16 + 79 0030 8023 movs r3, #128 + 80 0032 DB01 lsls r3, r3, #7 + 81 0034 0393 str r3, [sp, #12] + 254:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 82 .loc 1 254 3 is_stmt 1 view .LVU17 + 255:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 83 .loc 1 255 3 view .LVU18 + 84 .loc 1 255 24 is_stmt 0 view .LVU19 + 85 0036 0223 movs r3, #2 + 86 0038 0593 str r3, [sp, #20] + 256:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 87 .loc 1 256 3 is_stmt 1 view .LVU20 + ARM GAS /tmp/ccCxCgQe.s page 7 + + + 88 003a 03A9 add r1, sp, #12 + 89 003c 0348 ldr r0, .L2+4 + 90 003e FFF7FEFF bl HAL_GPIO_Init + 91 .LVL1: + 257:Core/Src/main.c **** + 258:Core/Src/main.c **** } + 92 .loc 1 258 1 is_stmt 0 view .LVU21 + 93 0042 09B0 add sp, sp, #36 + 94 @ sp needed + 95 0044 00BD pop {pc} + 96 .L3: + 97 0046 C046 .align 2 + 98 .L2: + 99 0048 00100240 .word 1073876992 + 100 004c 00080050 .word 1342179328 + 101 .cfi_endproc + 102 .LFE300: + 104 .section .text.Error_Handler,"ax",%progbits + 105 .align 1 + 106 .global Error_Handler + 107 .syntax unified + 108 .code 16 + 109 .thumb_func + 110 .fpu softvfp + 112 Error_Handler: + 113 .LFB301: + 259:Core/Src/main.c **** + 260:Core/Src/main.c **** /* USER CODE BEGIN 4 */ + 261:Core/Src/main.c **** + 262:Core/Src/main.c **** /* USER CODE END 4 */ + 263:Core/Src/main.c **** + 264:Core/Src/main.c **** /** + 265:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. + 266:Core/Src/main.c **** * @retval None + 267:Core/Src/main.c **** */ + 268:Core/Src/main.c **** void Error_Handler(void) + 269:Core/Src/main.c **** { + 114 .loc 1 269 1 is_stmt 1 view -0 + 115 .cfi_startproc + 116 @ Volatile: function does not return. + 117 @ args = 0, pretend = 0, frame = 0 + 118 @ frame_needed = 0, uses_anonymous_args = 0 + 119 @ link register save eliminated. + 270:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 271:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ + 272:Core/Src/main.c **** __disable_irq(); + 120 .loc 1 272 3 view .LVU23 + 121 .LBB6: + 122 .LBI6: + 123 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + ARM GAS /tmp/ccCxCgQe.s page 8 + + + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + ARM GAS /tmp/ccCxCgQe.s page 9 + + + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccCxCgQe.s page 10 + + + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors + ARM GAS /tmp/ccCxCgQe.s page 11 + + + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 124 .loc 2 207 27 view .LVU24 + 125 .LBB7: + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 126 .loc 2 209 3 view .LVU25 + 127 .syntax divided + 128 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 129 0000 72B6 cpsid i + 130 @ 0 "" 2 + 131 .thumb + 132 .syntax unified + 133 .L5: + 134 .LBE7: + 135 .LBE6: + 273:Core/Src/main.c **** while (1) + 136 .loc 1 273 3 discriminator 1 view .LVU26 + 274:Core/Src/main.c **** { + 275:Core/Src/main.c **** } + 137 .loc 1 275 3 discriminator 1 view .LVU27 + 273:Core/Src/main.c **** while (1) + 138 .loc 1 273 9 discriminator 1 view .LVU28 + 139 0002 FEE7 b .L5 + 140 .cfi_endproc + 141 .LFE301: + 143 .section .text.MX_I2C2_Init,"ax",%progbits + 144 .align 1 + 145 .syntax unified + 146 .code 16 + ARM GAS /tmp/ccCxCgQe.s page 12 + + + 147 .thumb_func + 148 .fpu softvfp + 150 MX_I2C2_Init: + 151 .LFB299: + 199:Core/Src/main.c **** + 152 .loc 1 199 1 view -0 + 153 .cfi_startproc + 154 @ args = 0, pretend = 0, frame = 0 + 155 @ frame_needed = 0, uses_anonymous_args = 0 + 156 0000 10B5 push {r4, lr} + 157 .LCFI2: + 158 .cfi_def_cfa_offset 8 + 159 .cfi_offset 4, -8 + 160 .cfi_offset 14, -4 + 208:Core/Src/main.c **** hi2c2.Init.Timing = 0x00303D5B; + 161 .loc 1 208 3 view .LVU30 + 208:Core/Src/main.c **** hi2c2.Init.Timing = 0x00303D5B; + 162 .loc 1 208 18 is_stmt 0 view .LVU31 + 163 0002 1248 ldr r0, .L13 + 164 0004 124B ldr r3, .L13+4 + 165 0006 0360 str r3, [r0] + 209:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 166 .loc 1 209 3 is_stmt 1 view .LVU32 + 209:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 167 .loc 1 209 21 is_stmt 0 view .LVU33 + 168 0008 124B ldr r3, .L13+8 + 169 000a 4360 str r3, [r0, #4] + 210:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 170 .loc 1 210 3 is_stmt 1 view .LVU34 + 210:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 171 .loc 1 210 26 is_stmt 0 view .LVU35 + 172 000c 0023 movs r3, #0 + 173 000e 8360 str r3, [r0, #8] + 211:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 174 .loc 1 211 3 is_stmt 1 view .LVU36 + 211:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 175 .loc 1 211 29 is_stmt 0 view .LVU37 + 176 0010 0122 movs r2, #1 + 177 0012 C260 str r2, [r0, #12] + 212:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 178 .loc 1 212 3 is_stmt 1 view .LVU38 + 212:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 179 .loc 1 212 30 is_stmt 0 view .LVU39 + 180 0014 0361 str r3, [r0, #16] + 213:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 181 .loc 1 213 3 is_stmt 1 view .LVU40 + 213:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 182 .loc 1 213 26 is_stmt 0 view .LVU41 + 183 0016 4361 str r3, [r0, #20] + 214:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 184 .loc 1 214 3 is_stmt 1 view .LVU42 + 214:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 185 .loc 1 214 31 is_stmt 0 view .LVU43 + 186 0018 8361 str r3, [r0, #24] + 215:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 187 .loc 1 215 3 is_stmt 1 view .LVU44 + 215:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + ARM GAS /tmp/ccCxCgQe.s page 13 + + + 188 .loc 1 215 30 is_stmt 0 view .LVU45 + 189 001a C361 str r3, [r0, #28] + 216:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 190 .loc 1 216 3 is_stmt 1 view .LVU46 + 216:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 191 .loc 1 216 28 is_stmt 0 view .LVU47 + 192 001c 0362 str r3, [r0, #32] + 217:Core/Src/main.c **** { + 193 .loc 1 217 3 is_stmt 1 view .LVU48 + 217:Core/Src/main.c **** { + 194 .loc 1 217 7 is_stmt 0 view .LVU49 + 195 001e FFF7FEFF bl HAL_I2C_Init + 196 .LVL2: + 217:Core/Src/main.c **** { + 197 .loc 1 217 6 view .LVU50 + 198 0022 0028 cmp r0, #0 + 199 0024 0CD1 bne .L10 + 223:Core/Src/main.c **** { + 200 .loc 1 223 3 is_stmt 1 view .LVU51 + 223:Core/Src/main.c **** { + 201 .loc 1 223 7 is_stmt 0 view .LVU52 + 202 0026 0021 movs r1, #0 + 203 0028 0848 ldr r0, .L13 + 204 002a FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 205 .LVL3: + 223:Core/Src/main.c **** { + 206 .loc 1 223 6 view .LVU53 + 207 002e 0028 cmp r0, #0 + 208 0030 08D1 bne .L11 + 229:Core/Src/main.c **** { + 209 .loc 1 229 3 is_stmt 1 view .LVU54 + 229:Core/Src/main.c **** { + 210 .loc 1 229 7 is_stmt 0 view .LVU55 + 211 0032 0021 movs r1, #0 + 212 0034 0548 ldr r0, .L13 + 213 0036 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 214 .LVL4: + 229:Core/Src/main.c **** { + 215 .loc 1 229 6 view .LVU56 + 216 003a 0028 cmp r0, #0 + 217 003c 04D1 bne .L12 + 237:Core/Src/main.c **** + 218 .loc 1 237 1 view .LVU57 + 219 @ sp needed + 220 003e 10BD pop {r4, pc} + 221 .L10: + 219:Core/Src/main.c **** } + 222 .loc 1 219 5 is_stmt 1 view .LVU58 + 223 0040 FFF7FEFF bl Error_Handler + 224 .LVL5: + 225 .L11: + 225:Core/Src/main.c **** } + 226 .loc 1 225 5 view .LVU59 + 227 0044 FFF7FEFF bl Error_Handler + 228 .LVL6: + 229 .L12: + 231:Core/Src/main.c **** } + ARM GAS /tmp/ccCxCgQe.s page 14 + + + 230 .loc 1 231 5 view .LVU60 + 231 0048 FFF7FEFF bl Error_Handler + 232 .LVL7: + 233 .L14: + 234 .align 2 + 235 .L13: + 236 004c 00000000 .word .LANCHOR0 + 237 0050 00580040 .word 1073764352 + 238 0054 5B3D3000 .word 3161435 + 239 .cfi_endproc + 240 .LFE299: + 242 .section .text.SystemClock_Config,"ax",%progbits + 243 .align 1 + 244 .global SystemClock_Config + 245 .syntax unified + 246 .code 16 + 247 .thumb_func + 248 .fpu softvfp + 250 SystemClock_Config: + 251 .LFB298: + 160:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 252 .loc 1 160 1 view -0 + 253 .cfi_startproc + 254 @ args = 0, pretend = 0, frame = 72 + 255 @ frame_needed = 0, uses_anonymous_args = 0 + 256 0000 00B5 push {lr} + 257 .LCFI3: + 258 .cfi_def_cfa_offset 4 + 259 .cfi_offset 14, -4 + 260 0002 93B0 sub sp, sp, #76 + 261 .LCFI4: + 262 .cfi_def_cfa_offset 80 + 161:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 263 .loc 1 161 3 view .LVU62 + 161:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 264 .loc 1 161 22 is_stmt 0 view .LVU63 + 265 0004 3822 movs r2, #56 + 266 0006 0021 movs r1, #0 + 267 0008 04A8 add r0, sp, #16 + 268 000a FFF7FEFF bl memset + 269 .LVL8: + 162:Core/Src/main.c **** + 270 .loc 1 162 3 is_stmt 1 view .LVU64 + 162:Core/Src/main.c **** + 271 .loc 1 162 22 is_stmt 0 view .LVU65 + 272 000e 1022 movs r2, #16 + 273 0010 0021 movs r1, #0 + 274 0012 6846 mov r0, sp + 275 0014 FFF7FEFF bl memset + 276 .LVL9: + 166:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 277 .loc 1 166 3 is_stmt 1 view .LVU66 + 278 0018 8020 movs r0, #128 + 279 001a 8000 lsls r0, r0, #2 + 280 001c FFF7FEFF bl HAL_PWREx_ControlVoltageScaling + 281 .LVL10: + 170:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + ARM GAS /tmp/ccCxCgQe.s page 15 + + + 282 .loc 1 170 3 view .LVU67 + 170:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 283 .loc 1 170 36 is_stmt 0 view .LVU68 + 284 0020 0223 movs r3, #2 + 285 0022 0493 str r3, [sp, #16] + 171:Core/Src/main.c **** RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + 286 .loc 1 171 3 is_stmt 1 view .LVU69 + 171:Core/Src/main.c **** RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + 287 .loc 1 171 30 is_stmt 0 view .LVU70 + 288 0024 FE33 adds r3, r3, #254 + 289 0026 0793 str r3, [sp, #28] + 172:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 290 .loc 1 172 3 is_stmt 1 view .LVU71 + 172:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 291 .loc 1 172 28 is_stmt 0 view .LVU72 + 292 0028 0023 movs r3, #0 + 293 002a 0893 str r3, [sp, #32] + 173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 294 .loc 1 173 3 is_stmt 1 view .LVU73 + 173:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 295 .loc 1 173 41 is_stmt 0 view .LVU74 + 296 002c 4022 movs r2, #64 + 297 002e 0992 str r2, [sp, #36] + 174:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 298 .loc 1 174 3 is_stmt 1 view .LVU75 + 174:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 299 .loc 1 174 34 is_stmt 0 view .LVU76 + 300 0030 0B93 str r3, [sp, #44] + 175:Core/Src/main.c **** { + 301 .loc 1 175 3 is_stmt 1 view .LVU77 + 175:Core/Src/main.c **** { + 302 .loc 1 175 7 is_stmt 0 view .LVU78 + 303 0032 04A8 add r0, sp, #16 + 304 0034 FFF7FEFF bl HAL_RCC_OscConfig + 305 .LVL11: + 175:Core/Src/main.c **** { + 306 .loc 1 175 6 view .LVU79 + 307 0038 0028 cmp r0, #0 + 308 003a 0DD1 bne .L18 + 181:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; + 309 .loc 1 181 3 is_stmt 1 view .LVU80 + 181:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1; + 310 .loc 1 181 31 is_stmt 0 view .LVU81 + 311 003c 0723 movs r3, #7 + 312 003e 0093 str r3, [sp] + 183:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 313 .loc 1 183 3 is_stmt 1 view .LVU82 + 183:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 314 .loc 1 183 34 is_stmt 0 view .LVU83 + 315 0040 0023 movs r3, #0 + 316 0042 0193 str r3, [sp, #4] + 184:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 317 .loc 1 184 3 is_stmt 1 view .LVU84 + 184:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 318 .loc 1 184 35 is_stmt 0 view .LVU85 + 319 0044 0293 str r3, [sp, #8] + 185:Core/Src/main.c **** + ARM GAS /tmp/ccCxCgQe.s page 16 + + + 320 .loc 1 185 3 is_stmt 1 view .LVU86 + 185:Core/Src/main.c **** + 321 .loc 1 185 36 is_stmt 0 view .LVU87 + 322 0046 0393 str r3, [sp, #12] + 187:Core/Src/main.c **** { + 323 .loc 1 187 3 is_stmt 1 view .LVU88 + 187:Core/Src/main.c **** { + 324 .loc 1 187 7 is_stmt 0 view .LVU89 + 325 0048 0021 movs r1, #0 + 326 004a 6846 mov r0, sp + 327 004c FFF7FEFF bl HAL_RCC_ClockConfig + 328 .LVL12: + 187:Core/Src/main.c **** { + 329 .loc 1 187 6 view .LVU90 + 330 0050 0028 cmp r0, #0 + 331 0052 03D1 bne .L19 + 191:Core/Src/main.c **** + 332 .loc 1 191 1 view .LVU91 + 333 0054 13B0 add sp, sp, #76 + 334 @ sp needed + 335 0056 00BD pop {pc} + 336 .L18: + 177:Core/Src/main.c **** } + 337 .loc 1 177 5 is_stmt 1 view .LVU92 + 338 0058 FFF7FEFF bl Error_Handler + 339 .LVL13: + 340 .L19: + 189:Core/Src/main.c **** } + 341 .loc 1 189 5 view .LVU93 + 342 005c FFF7FEFF bl Error_Handler + 343 .LVL14: + 344 .cfi_endproc + 345 .LFE298: + 347 .section .text.main,"ax",%progbits + 348 .align 1 + 349 .global main + 350 .syntax unified + 351 .code 16 + 352 .thumb_func + 353 .fpu softvfp + 355 main: + 356 .LFB297: + 69:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 357 .loc 1 69 1 view -0 + 358 .cfi_startproc + 359 @ Volatile: function does not return. + 360 @ args = 0, pretend = 0, frame = 0 + 361 @ frame_needed = 0, uses_anonymous_args = 0 + 362 0000 10B5 push {r4, lr} + 363 .LCFI5: + 364 .cfi_def_cfa_offset 8 + 365 .cfi_offset 4, -8 + 366 .cfi_offset 14, -4 + 77:Core/Src/main.c **** + 367 .loc 1 77 3 view .LVU95 + 368 0002 FFF7FEFF bl HAL_Init + 369 .LVL15: + ARM GAS /tmp/ccCxCgQe.s page 17 + + + 84:Core/Src/main.c **** + 370 .loc 1 84 3 view .LVU96 + 371 0006 FFF7FEFF bl SystemClock_Config + 372 .LVL16: + 91:Core/Src/main.c **** MX_I2C2_Init(); + 373 .loc 1 91 3 view .LVU97 + 374 000a FFF7FEFF bl MX_GPIO_Init + 375 .LVL17: + 92:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 376 .loc 1 92 3 view .LVU98 + 377 000e FFF7FEFF bl MX_I2C2_Init + 378 .LVL18: + 94:Core/Src/main.c **** HAL_Delay(100); + 379 .loc 1 94 4 view .LVU99 + 94:Core/Src/main.c **** HAL_Delay(100); + 380 .loc 1 94 14 is_stmt 0 view .LVU100 + 381 0012 174C ldr r4, .L24 + 382 0014 174B ldr r3, .L24+4 + 383 0016 2360 str r3, [r4] + 95:Core/Src/main.c **** si5351_Init(); + 384 .loc 1 95 2 is_stmt 1 view .LVU101 + 385 0018 6420 movs r0, #100 + 386 001a FFF7FEFF bl HAL_Delay + 387 .LVL19: + 96:Core/Src/main.c **** HAL_Delay(500); + 388 .loc 1 96 2 view .LVU102 + 389 001e FFF7FEFF bl si5351_Init + 390 .LVL20: + 97:Core/Src/main.c **** CalcRegisters(frequenza); + 391 .loc 1 97 2 view .LVU103 + 392 0022 FA20 movs r0, #250 + 393 0024 4000 lsls r0, r0, #1 + 394 0026 FFF7FEFF bl HAL_Delay + 395 .LVL21: + 98:Core/Src/main.c **** /* USER CODE END 2 */ + 396 .loc 1 98 2 view .LVU104 + 397 002a 2068 ldr r0, [r4] + 398 002c FFF7FEFF bl CalcRegisters + 399 .LVL22: + 400 0030 09E0 b .L23 + 401 .L22: + 136:Core/Src/main.c **** } + 402 .loc 1 136 3 view .LVU105 + 403 0032 0F4B ldr r3, .L24 + 404 0034 1868 ldr r0, [r3] + 405 0036 FFF7FEFF bl CalcRegisters + 406 .LVL23: + 407 .L21: + 148:Core/Src/main.c **** HAL_Delay(100); + 408 .loc 1 148 2 view .LVU106 + 409 003a FF20 movs r0, #255 + 410 003c FFF7FEFF bl si5351_enableOutputs + 411 .LVL24: + 149:Core/Src/main.c **** + 412 .loc 1 149 2 view .LVU107 + 413 0040 6420 movs r0, #100 + 414 0042 FFF7FEFF bl HAL_Delay + ARM GAS /tmp/ccCxCgQe.s page 18 + + + 415 .LVL25: + 103:Core/Src/main.c **** { + 416 .loc 1 103 9 view .LVU108 + 417 .L23: + 103:Core/Src/main.c **** { + 418 .loc 1 103 3 view .LVU109 + 133:Core/Src/main.c **** frequenza += 9000; + 419 .loc 1 133 2 view .LVU110 + 133:Core/Src/main.c **** frequenza += 9000; + 420 .loc 1 133 5 is_stmt 0 view .LVU111 + 421 0046 8021 movs r1, #128 + 422 0048 C901 lsls r1, r1, #7 + 423 004a 0B48 ldr r0, .L24+8 + 424 004c FFF7FEFF bl HAL_GPIO_ReadPin + 425 .LVL26: + 133:Core/Src/main.c **** frequenza += 9000; + 426 .loc 1 133 4 view .LVU112 + 427 0050 0028 cmp r0, #0 + 428 0052 F2D0 beq .L21 + 134:Core/Src/main.c **** if(frequenza > 1800000) frequenza = 585000; + 429 .loc 1 134 3 is_stmt 1 view .LVU113 + 134:Core/Src/main.c **** if(frequenza > 1800000) frequenza = 585000; + 430 .loc 1 134 13 is_stmt 0 view .LVU114 + 431 0054 064A ldr r2, .L24 + 432 0056 1368 ldr r3, [r2] + 433 0058 0849 ldr r1, .L24+12 + 434 005a 8C46 mov ip, r1 + 435 005c 6344 add r3, r3, ip + 436 005e 1360 str r3, [r2] + 135:Core/Src/main.c **** CalcRegisters(frequenza); + 437 .loc 1 135 3 is_stmt 1 view .LVU115 + 135:Core/Src/main.c **** CalcRegisters(frequenza); + 438 .loc 1 135 5 is_stmt 0 view .LVU116 + 439 0060 074A ldr r2, .L24+16 + 440 0062 9342 cmp r3, r2 + 441 0064 E5D9 bls .L22 + 135:Core/Src/main.c **** CalcRegisters(frequenza); + 442 .loc 1 135 27 is_stmt 1 discriminator 1 view .LVU117 + 135:Core/Src/main.c **** CalcRegisters(frequenza); + 443 .loc 1 135 37 is_stmt 0 discriminator 1 view .LVU118 + 444 0066 024B ldr r3, .L24 + 445 0068 064A ldr r2, .L24+20 + 446 006a 1A60 str r2, [r3] + 447 006c E1E7 b .L22 + 448 .L25: + 449 006e C046 .align 2 + 450 .L24: + 451 0070 00000000 .word .LANCHOR1 + 452 0074 98BC1400 .word 1359000 + 453 0078 00080050 .word 1342179328 + 454 007c 28230000 .word 9000 + 455 0080 40771B00 .word 1800000 + 456 0084 28ED0800 .word 585000 + 457 .cfi_endproc + 458 .LFE297: + 460 .section .text.assert_failed,"ax",%progbits + 461 .align 1 + ARM GAS /tmp/ccCxCgQe.s page 19 + + + 462 .global assert_failed + 463 .syntax unified + 464 .code 16 + 465 .thumb_func + 466 .fpu softvfp + 468 assert_failed: + 469 .LVL27: + 470 .LFB302: + 276:Core/Src/main.c **** /* USER CODE END Error_Handler_Debug */ + 277:Core/Src/main.c **** } + 278:Core/Src/main.c **** + 279:Core/Src/main.c **** #ifdef USE_FULL_ASSERT + 280:Core/Src/main.c **** /** + 281:Core/Src/main.c **** * @brief Reports the name of the source file and the source line number + 282:Core/Src/main.c **** * where the assert_param error has occurred. + 283:Core/Src/main.c **** * @param file: pointer to the source file name + 284:Core/Src/main.c **** * @param line: assert_param error line source number + 285:Core/Src/main.c **** * @retval None + 286:Core/Src/main.c **** */ + 287:Core/Src/main.c **** void assert_failed(uint8_t *file, uint32_t line) + 288:Core/Src/main.c **** { + 471 .loc 1 288 1 is_stmt 1 view -0 + 472 .cfi_startproc + 473 @ args = 0, pretend = 0, frame = 0 + 474 @ frame_needed = 0, uses_anonymous_args = 0 + 475 @ link register save eliminated. + 289:Core/Src/main.c **** /* USER CODE BEGIN 6 */ + 290:Core/Src/main.c **** /* User can add his own implementation to report the file name and line number, + 291:Core/Src/main.c **** ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + 292:Core/Src/main.c **** /* USER CODE END 6 */ + 293:Core/Src/main.c **** } + 476 .loc 1 293 1 view .LVU120 + 477 @ sp needed + 478 0000 7047 bx lr + 479 .cfi_endproc + 480 .LFE302: + 482 .global frequenza + 483 .global hi2c2 + 484 .section .bss.frequenza,"aw",%nobits + 485 .align 2 + 486 .set .LANCHOR1,. + 0 + 489 frequenza: + 490 0000 00000000 .space 4 + 491 .section .bss.hi2c2,"aw",%nobits + 492 .align 2 + 493 .set .LANCHOR0,. + 0 + 496 hi2c2: + 497 0000 00000000 .space 76 + 497 00000000 + 497 00000000 + 497 00000000 + 497 00000000 + 498 .text + 499 .Letext0: + 500 .file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 501 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 502 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + ARM GAS /tmp/ccCxCgQe.s page 20 + + + 503 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h" + 504 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h" + 505 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 506 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h" + 507 .file 10 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 508 .file 11 "Core/Inc/si5351.h" + 509 .file 12 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h" + 510 .file 13 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h" + 511 .file 14 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + 512 .file 15 "" + ARM GAS /tmp/ccCxCgQe.s page 21 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 main.c + /tmp/ccCxCgQe.s:16 .text.MX_GPIO_Init:0000000000000000 $t + /tmp/ccCxCgQe.s:23 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init + /tmp/ccCxCgQe.s:99 .text.MX_GPIO_Init:0000000000000048 $d + /tmp/ccCxCgQe.s:105 .text.Error_Handler:0000000000000000 $t + /tmp/ccCxCgQe.s:112 .text.Error_Handler:0000000000000000 Error_Handler + /tmp/ccCxCgQe.s:144 .text.MX_I2C2_Init:0000000000000000 $t + /tmp/ccCxCgQe.s:150 .text.MX_I2C2_Init:0000000000000000 MX_I2C2_Init + /tmp/ccCxCgQe.s:236 .text.MX_I2C2_Init:000000000000004c $d + /tmp/ccCxCgQe.s:243 .text.SystemClock_Config:0000000000000000 $t + /tmp/ccCxCgQe.s:250 .text.SystemClock_Config:0000000000000000 SystemClock_Config + /tmp/ccCxCgQe.s:348 .text.main:0000000000000000 $t + /tmp/ccCxCgQe.s:355 .text.main:0000000000000000 main + /tmp/ccCxCgQe.s:451 .text.main:0000000000000070 $d + /tmp/ccCxCgQe.s:461 .text.assert_failed:0000000000000000 $t + /tmp/ccCxCgQe.s:468 .text.assert_failed:0000000000000000 assert_failed + /tmp/ccCxCgQe.s:489 .bss.frequenza:0000000000000000 frequenza + /tmp/ccCxCgQe.s:496 .bss.hi2c2:0000000000000000 hi2c2 + /tmp/ccCxCgQe.s:485 .bss.frequenza:0000000000000000 $d + /tmp/ccCxCgQe.s:492 .bss.hi2c2:0000000000000000 $d + +UNDEFINED SYMBOLS +memset +HAL_GPIO_Init +HAL_I2C_Init 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zcI+eiG9&bUixHdAGeZA>5u44A1b->~R|WaMpj>YQBl>u=V3Xi3!F__AjF9hV#GD%v zyqXc4*)>xB2H~d!uM_@Tg}zSu&p zwb0vzzC!38p@#*J2~IJhJ#S#dQ7R>vW`vz{QhvMOd!_uZ1-~cw3qb=qSkFemkYE!d z>|DW!P4%E)7bENpN%^Gk6M|{MHwxY&c(33G1wSqLB|-cY=qn;^Cka^TQb;1A|skooYVff4qUKhUH6;X@N- zebs-UJJ=rdj5C7P{g)Jai4l5l5&Bj}R^F63yO51d0kdfv=XDOR^|RE(Z{?|JDwClm zy!mfpW>dkJDw|dKoKql*7eVqaF2{bI2bf%;dI+)A7Ctwy8%?=~2SwUX5UTP_d}?_v znn=wq!fln0O-%{Y$6UQCGO~o10b(h(5A&5N7@WuARxbpRJylEZCs^=`mYjEYuaXfO&>ZI!& z10&z=ZrJ6y8pMSo+KSyY^7;Cn2R(^PC*6N3F!J>!^Yk%ax8v=|=j-bL!9MDw{kt8E ze0?8*zIpJ1xV*TuzV{%XukUdX+9wpP~XO2+u_52KMqHN;Ip`H$M=xW*Y_Y^Z~aAHLv-1{u9A!50r%bD>7?ae z03+Y-cM#C`gBQeAj!WBp8F^g?S^6FH^>Id$F8eL$e0|wHxp+a96@5Nb&~;cv2cFG2 zu5{96Ze;TH{W + 52:Core/Src/si5351.c **** #include "si5351.h" + 53:Core/Src/si5351.c **** + 54:Core/Src/si5351.c **** // extern I2C_HandleTypeDef hi2c2; + 55:Core/Src/si5351.c **** si5351Config_t m_si5351Config; + 56:Core/Src/si5351.c **** /**************************************************************************/ + 57:Core/Src/si5351.c **** /*! + 58:Core/Src/si5351.c **** Initializes I2C and configures the breakout (call this function before + 59:Core/Src/si5351.c **** doing anything else) + 60:Core/Src/si5351.c **** */ + 61:Core/Src/si5351.c **** /**************************************************************************/ + 62:Core/Src/si5351.c **** err_t si5351_Init(void) + 63:Core/Src/si5351.c **** { + 64:Core/Src/si5351.c **** + 65:Core/Src/si5351.c **** /*! + 66:Core/Src/si5351.c **** Constructor + 67:Core/Src/si5351.c **** */ + 68:Core/Src/si5351.c **** m_si5351Config.initialised = 0; + 69:Core/Src/si5351.c **** m_si5351Config.crystalFreq = SI5351_CRYSTAL_FREQ_24MHZ; + 70:Core/Src/si5351.c **** m_si5351Config.crystalLoad = SI5351_CRYSTAL_LOAD_10PF; + 71:Core/Src/si5351.c **** m_si5351Config.crystalPPM = 30; + 72:Core/Src/si5351.c **** m_si5351Config.plla_configured = 0; + 73:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 74:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 75:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 76:Core/Src/si5351.c **** m_si5351Config.ms0_freq = 0; + 77:Core/Src/si5351.c **** m_si5351Config.ms1_freq = 0; + 78:Core/Src/si5351.c **** m_si5351Config.ms2_freq = 0; + 79:Core/Src/si5351.c **** m_si5351Config.ms0_r_div = 0; + 80:Core/Src/si5351.c **** m_si5351Config.ms1_r_div = 0; + 81:Core/Src/si5351.c **** m_si5351Config.ms2_r_div = 0; + 82:Core/Src/si5351.c **** + 83:Core/Src/si5351.c **** + 84:Core/Src/si5351.c **** + 85:Core/Src/si5351.c **** /* Disable all outputs setting CLKx_DIS high */ + 86:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, 0xFF)); + 87:Core/Src/si5351.c **** + 88:Core/Src/si5351.c **** /* Power down all output drivers */ + ARM GAS /tmp/ccV7ORbp.s page 3 + + + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_16_CLK0_CONTROL, 0x80)); + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 96:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 97:Core/Src/si5351.c **** + 98:Core/Src/si5351.c **** /* Set the load capacitance for the XTAL */ + 99:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_183_CRYSTAL_INTERNAL_LOAD_CAPACITANCE, + 100:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 101:Core/Src/si5351.c **** + 102:Core/Src/si5351.c **** /* Set interrupt masks as required (see Register 2 description in AN619). + 103:Core/Src/si5351.c **** By default, ClockBuilder Desktop sets this register to 0x18. + 104:Core/Src/si5351.c **** Note that the least significant nibble must remain 0x8, but the most + 105:Core/Src/si5351.c **** significant nibble may be modified to suit your needs. */ + 106:Core/Src/si5351.c **** + 107:Core/Src/si5351.c **** /* Reset the PLL config fields just in case we call init again */ + 108:Core/Src/si5351.c **** m_si5351Config.plla_configured = 0; + 109:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 110:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 111:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 112:Core/Src/si5351.c **** + 113:Core/Src/si5351.c **** /* All done! */ + 114:Core/Src/si5351.c **** m_si5351Config.initialised = 1; + 115:Core/Src/si5351.c **** + 116:Core/Src/si5351.c **** return ERROR_NONE; + 117:Core/Src/si5351.c **** } + 118:Core/Src/si5351.c **** + 119:Core/Src/si5351.c **** + 120:Core/Src/si5351.c **** /**************************************************************************/ + 121:Core/Src/si5351.c **** /*! + 122:Core/Src/si5351.c **** @brief Sets the multiplier for the specified PLL using integer values + 123:Core/Src/si5351.c **** + 124:Core/Src/si5351.c **** @param pll The PLL to configure, which must be one of the following: + 125:Core/Src/si5351.c **** - SI5351_PLL_A + 126:Core/Src/si5351.c **** - SI5351_PLL_B + 127:Core/Src/si5351.c **** @param mult The PLL integer multiplier (must be between 15 and 90) + 128:Core/Src/si5351.c **** */ + 129:Core/Src/si5351.c **** /**************************************************************************/ + 130:Core/Src/si5351.c **** err_t si5351_setupPLLInt(si5351PLL_t pll, uint8_t mult) + 131:Core/Src/si5351.c **** { + 132:Core/Src/si5351.c **** return si5351_setupPLL(pll, mult, 0, 1); + 133:Core/Src/si5351.c **** } + 134:Core/Src/si5351.c **** + 135:Core/Src/si5351.c **** /**************************************************************************/ + 136:Core/Src/si5351.c **** /*! + 137:Core/Src/si5351.c **** @brief Sets the multiplier for the specified PLL + 138:Core/Src/si5351.c **** + 139:Core/Src/si5351.c **** @param pll The PLL to configure, which must be one of the following: + 140:Core/Src/si5351.c **** - SI5351_PLL_A + 141:Core/Src/si5351.c **** - SI5351_PLL_B + 142:Core/Src/si5351.c **** @param mult The PLL integer multiplier (must be between 15 and 90) + 143:Core/Src/si5351.c **** @param num The 20-bit numerator for fractional output (0..1,048,575). + 144:Core/Src/si5351.c **** Set this to '0' for integer output. + 145:Core/Src/si5351.c **** @param denom The 20-bit denominator for fractional output (1..1,048,575). + ARM GAS /tmp/ccV7ORbp.s page 4 + + + 146:Core/Src/si5351.c **** Set this to '1' or higher to avoid divider by zero errors. + 147:Core/Src/si5351.c **** + 148:Core/Src/si5351.c **** @section PLL Configuration + 149:Core/Src/si5351.c **** + 150:Core/Src/si5351.c **** fVCO is the PLL output, and must be between 600..900MHz, where: + 151:Core/Src/si5351.c **** + 152:Core/Src/si5351.c **** fVCO = fXTAL * (a+(b/c)) + 153:Core/Src/si5351.c **** + 154:Core/Src/si5351.c **** fXTAL = the crystal input frequency + 155:Core/Src/si5351.c **** a = an integer between 15 and 90 + 156:Core/Src/si5351.c **** b = the fractional numerator (0..1,048,575) + 157:Core/Src/si5351.c **** c = the fractional denominator (1..1,048,575) + 158:Core/Src/si5351.c **** + 159:Core/Src/si5351.c **** NOTE: Try to use integers whenever possible to avoid clock jitter + 160:Core/Src/si5351.c **** (only use the a part, setting b to '0' and c to '1'). + 161:Core/Src/si5351.c **** + 162:Core/Src/si5351.c **** See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf + 163:Core/Src/si5351.c **** */ + 164:Core/Src/si5351.c **** /**************************************************************************/ + 165:Core/Src/si5351.c **** err_t si5351_setupPLL(si5351PLL_t pll, + 166:Core/Src/si5351.c **** uint8_t mult, + 167:Core/Src/si5351.c **** uint32_t num, + 168:Core/Src/si5351.c **** uint32_t denom) + 169:Core/Src/si5351.c **** { + 170:Core/Src/si5351.c **** uint32_t P1; /* PLL config register P1 */ + 171:Core/Src/si5351.c **** uint32_t P2; /* PLL config register P2 */ + 172:Core/Src/si5351.c **** uint32_t P3; /* PLL config register P3 */ + 173:Core/Src/si5351.c **** + 174:Core/Src/si5351.c **** /* Basic validation */ + 175:Core/Src/si5351.c **** ASSERT( m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED ); + 176:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 177:Core/Src/si5351.c **** ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 178:Core/Src/si5351.c **** ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 179:Core/Src/si5351.c **** ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 180:Core/Src/si5351.c **** + 181:Core/Src/si5351.c **** /* Feedback Multisynth Divider Equation + 182:Core/Src/si5351.c **** * + 183:Core/Src/si5351.c **** * where: a = mult, b = num and c = denom + 184:Core/Src/si5351.c **** * + 185:Core/Src/si5351.c **** * P1 register is an 18-bit value using following formula: + 186:Core/Src/si5351.c **** * + 187:Core/Src/si5351.c **** * P1[17:0] = 128 * mult + floor(128*(num/denom)) - 512 + 188:Core/Src/si5351.c **** * + 189:Core/Src/si5351.c **** * P2 register is a 20-bit value using the following formula: + 190:Core/Src/si5351.c **** * + 191:Core/Src/si5351.c **** * P2[19:0] = 128 * num - denom * floor(128*(num/denom)) + 192:Core/Src/si5351.c **** * + 193:Core/Src/si5351.c **** * P3 register is a 20-bit value using the following formula: + 194:Core/Src/si5351.c **** * + 195:Core/Src/si5351.c **** * P3[19:0] = denom + 196:Core/Src/si5351.c **** */ + 197:Core/Src/si5351.c **** + 198:Core/Src/si5351.c **** /* Set the main PLL config registers */ + 199:Core/Src/si5351.c **** if (num == 0) + 200:Core/Src/si5351.c **** { + 201:Core/Src/si5351.c **** /* Integer mode */ + 202:Core/Src/si5351.c **** P1 = 128 * mult - 512; + ARM GAS /tmp/ccV7ORbp.s page 5 + + + 203:Core/Src/si5351.c **** P2 = num; + 204:Core/Src/si5351.c **** P3 = denom; + 205:Core/Src/si5351.c **** } + 206:Core/Src/si5351.c **** else + 207:Core/Src/si5351.c **** { + 208:Core/Src/si5351.c **** /* Fractional mode */ + 209:Core/Src/si5351.c **** P1 = (uint32_t)(128 * mult + floor(128 * ((float)num/(float)denom)) - 512); + 210:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 211:Core/Src/si5351.c **** P3 = denom; + 212:Core/Src/si5351.c **** } + 213:Core/Src/si5351.c **** + 214:Core/Src/si5351.c **** /* Get the appropriate starting point for the PLL registers */ + 215:Core/Src/si5351.c **** uint8_t baseaddr = (pll == SI5351_PLL_A ? 26 : 34); + 216:Core/Src/si5351.c **** + 217:Core/Src/si5351.c **** /* The datasheet is a nightmare of typos and inconsistencies here! */ + 218:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr, (P3 & 0x0000FF00) >> 8)); + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 225:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + 226:Core/Src/si5351.c **** + 227:Core/Src/si5351.c **** /* Reset both PLLs */ + 228:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8(SI5351_REGISTER_177_PLL_RESET, (1<<7) | (1<<5) )); + 229:Core/Src/si5351.c **** + 230:Core/Src/si5351.c **** /* Store the frequency settings for use with the Multisynth helper */ + 231:Core/Src/si5351.c **** if (pll == SI5351_PLL_A) + 232:Core/Src/si5351.c **** { + 233:Core/Src/si5351.c **** float fvco = m_si5351Config.crystalFreq * (mult + ( (float)num / (float)denom )); + 234:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 235:Core/Src/si5351.c **** m_si5351Config.plla_freq = (uint32_t)floor(fvco); + 236:Core/Src/si5351.c **** } + 237:Core/Src/si5351.c **** else + 238:Core/Src/si5351.c **** { + 239:Core/Src/si5351.c **** float fvco = m_si5351Config.crystalFreq * (mult + ( (float)num / (float)denom )); + 240:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 241:Core/Src/si5351.c **** m_si5351Config.pllb_freq = (uint32_t)floor(fvco); + 242:Core/Src/si5351.c **** } + 243:Core/Src/si5351.c **** + 244:Core/Src/si5351.c **** return ERROR_NONE; + 245:Core/Src/si5351.c **** } + 246:Core/Src/si5351.c **** + 247:Core/Src/si5351.c **** /**************************************************************************/ + 248:Core/Src/si5351.c **** /*! + 249:Core/Src/si5351.c **** @brief Configures the Multisynth divider using integer output. + 250:Core/Src/si5351.c **** + 251:Core/Src/si5351.c **** @param output The output channel to use (0..2) + 252:Core/Src/si5351.c **** @param pllSource The PLL input source to use, which must be one of: + 253:Core/Src/si5351.c **** - SI5351_PLL_A + 254:Core/Src/si5351.c **** - SI5351_PLL_B + 255:Core/Src/si5351.c **** @param div The integer divider for the Multisynth output, + 256:Core/Src/si5351.c **** which must be one of the following values: + 257:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_4 + 258:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_6 + 259:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_8 + ARM GAS /tmp/ccV7ORbp.s page 6 + + + 260:Core/Src/si5351.c **** */ + 261:Core/Src/si5351.c **** /**************************************************************************/ + 262:Core/Src/si5351.c **** err_t si5351_setupMultisynthInt(uint8_t output, + 263:Core/Src/si5351.c **** si5351PLL_t pllSource, + 264:Core/Src/si5351.c **** si5351MultisynthDiv_t div) + 265:Core/Src/si5351.c **** { + 266:Core/Src/si5351.c **** return si5351_setupMultisynth(output, pllSource, div, 0, 1); + 267:Core/Src/si5351.c **** } + 268:Core/Src/si5351.c **** + 269:Core/Src/si5351.c **** + 270:Core/Src/si5351.c **** err_t si5351_setupRdiv(uint8_t output, si5351RDiv_t div) { + 271:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 272:Core/Src/si5351.c **** + 273:Core/Src/si5351.c **** uint8_t Rreg, regval, rDiv; + 274:Core/Src/si5351.c **** + 275:Core/Src/si5351.c **** if (output == 0) Rreg = SI5351_REGISTER_44_MULTISYNTH0_PARAMETERS_3; + 276:Core/Src/si5351.c **** if (output == 1) Rreg = SI5351_REGISTER_52_MULTISYNTH1_PARAMETERS_3; + 277:Core/Src/si5351.c **** if (output == 2) Rreg = SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3; + 278:Core/Src/si5351.c **** + 279:Core/Src/si5351.c **** si5351_read8(Rreg, ®val); + 280:Core/Src/si5351.c **** + 281:Core/Src/si5351.c **** regval &= 0x0F; + 282:Core/Src/si5351.c **** uint8_t divider = div; + 283:Core/Src/si5351.c **** divider &= 0x07; + 284:Core/Src/si5351.c **** divider <<= 4; + 285:Core/Src/si5351.c **** regval |= divider; + 286:Core/Src/si5351.c **** si5351_write8(Rreg, regval); + 287:Core/Src/si5351.c **** + 288:Core/Src/si5351.c **** switch(div) + 289:Core/Src/si5351.c **** { + 290:Core/Src/si5351.c **** case 0: + 291:Core/Src/si5351.c **** rDiv = 1; + 292:Core/Src/si5351.c **** break; + 293:Core/Src/si5351.c **** + 294:Core/Src/si5351.c **** case 1: + 295:Core/Src/si5351.c **** rDiv = 2; + 296:Core/Src/si5351.c **** break; + 297:Core/Src/si5351.c **** + 298:Core/Src/si5351.c **** case 2: + 299:Core/Src/si5351.c **** rDiv = 4; + 300:Core/Src/si5351.c **** break; + 301:Core/Src/si5351.c **** + 302:Core/Src/si5351.c **** case 3: + 303:Core/Src/si5351.c **** rDiv = 8; + 304:Core/Src/si5351.c **** break; + 305:Core/Src/si5351.c **** + 306:Core/Src/si5351.c **** case 4: + 307:Core/Src/si5351.c **** rDiv = 16; + 308:Core/Src/si5351.c **** break; + 309:Core/Src/si5351.c **** + 310:Core/Src/si5351.c **** case 5: + 311:Core/Src/si5351.c **** rDiv = 32; + 312:Core/Src/si5351.c **** break; + 313:Core/Src/si5351.c **** + 314:Core/Src/si5351.c **** case 6: + 315:Core/Src/si5351.c **** rDiv = 64; + 316:Core/Src/si5351.c **** break; + ARM GAS /tmp/ccV7ORbp.s page 7 + + + 317:Core/Src/si5351.c **** + 318:Core/Src/si5351.c **** case 7: + 319:Core/Src/si5351.c **** rDiv = 128; + 320:Core/Src/si5351.c **** break; + 321:Core/Src/si5351.c **** } + 322:Core/Src/si5351.c **** + 323:Core/Src/si5351.c **** switch(output) + 324:Core/Src/si5351.c **** { + 325:Core/Src/si5351.c **** case 0: + 326:Core/Src/si5351.c **** m_si5351Config.ms0_r_div = rDiv; + 327:Core/Src/si5351.c **** break; + 328:Core/Src/si5351.c **** + 329:Core/Src/si5351.c **** case 1: + 330:Core/Src/si5351.c **** m_si5351Config.ms1_r_div = rDiv; + 331:Core/Src/si5351.c **** break; + 332:Core/Src/si5351.c **** + 333:Core/Src/si5351.c **** case 2: + 334:Core/Src/si5351.c **** m_si5351Config.ms2_r_div = rDiv; + 335:Core/Src/si5351.c **** break; + 336:Core/Src/si5351.c **** } + 337:Core/Src/si5351.c **** + 338:Core/Src/si5351.c **** return ERROR_NONE; + 339:Core/Src/si5351.c **** } + 340:Core/Src/si5351.c **** + 341:Core/Src/si5351.c **** /**************************************************************************/ + 342:Core/Src/si5351.c **** /*! + 343:Core/Src/si5351.c **** @brief Configures the Multisynth divider, which determines the + 344:Core/Src/si5351.c **** output clock frequency based on the specified PLL input. + 345:Core/Src/si5351.c **** + 346:Core/Src/si5351.c **** @param output The output channel to use (0..2) + 347:Core/Src/si5351.c **** @param pllSource The PLL input source to use, which must be one of: + 348:Core/Src/si5351.c **** - SI5351_PLL_A + 349:Core/Src/si5351.c **** - SI5351_PLL_B + 350:Core/Src/si5351.c **** @param div The integer divider for the Multisynth output. + 351:Core/Src/si5351.c **** If pure integer values are used, this value must + 352:Core/Src/si5351.c **** be one of: + 353:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_4 + 354:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_6 + 355:Core/Src/si5351.c **** - SI5351_MULTISYNTH_DIV_8 + 356:Core/Src/si5351.c **** If fractional output is used, this value must be + 357:Core/Src/si5351.c **** between 8 and 900. + 358:Core/Src/si5351.c **** @param num The 20-bit numerator for fractional output + 359:Core/Src/si5351.c **** (0..1,048,575). Set this to '0' for integer output. + 360:Core/Src/si5351.c **** @param denom The 20-bit denominator for fractional output + 361:Core/Src/si5351.c **** (1..1,048,575). Set this to '1' or higher to + 362:Core/Src/si5351.c **** avoid divide by zero errors. + 363:Core/Src/si5351.c **** + 364:Core/Src/si5351.c **** @section Output Clock Configuration + 365:Core/Src/si5351.c **** + 366:Core/Src/si5351.c **** The multisynth dividers are applied to the specified PLL output, + 367:Core/Src/si5351.c **** and are used to reduce the PLL output to a valid range (500kHz + 368:Core/Src/si5351.c **** to 160MHz). The relationship can be seen in this formula, where + 369:Core/Src/si5351.c **** fVCO is the PLL output frequency and MSx is the multisynth + 370:Core/Src/si5351.c **** divider: + 371:Core/Src/si5351.c **** + 372:Core/Src/si5351.c **** fOUT = fVCO / MSx + 373:Core/Src/si5351.c **** + ARM GAS /tmp/ccV7ORbp.s page 8 + + + 374:Core/Src/si5351.c **** Valid multisynth dividers are 4, 6, or 8 when using integers, + 375:Core/Src/si5351.c **** or any fractional values between 8 + 1/1,048,575 and 900 + 0/1 + 376:Core/Src/si5351.c **** + 377:Core/Src/si5351.c **** The following formula is used for the fractional mode divider: + 378:Core/Src/si5351.c **** + 379:Core/Src/si5351.c **** a + b / c + 380:Core/Src/si5351.c **** + 381:Core/Src/si5351.c **** a = The integer value, which must be 4, 6 or 8 in integer mode (MSx_INT=1) + 382:Core/Src/si5351.c **** or 8..900 in fractional mode (MSx_INT=0). + 383:Core/Src/si5351.c **** b = The fractional numerator (0..1,048,575) + 384:Core/Src/si5351.c **** c = The fractional denominator (1..1,048,575) + 385:Core/Src/si5351.c **** + 386:Core/Src/si5351.c **** @note Try to use integers whenever possible to avoid clock jitter + 387:Core/Src/si5351.c **** + 388:Core/Src/si5351.c **** @note For output frequencies > 150MHz, you must set the divider + 389:Core/Src/si5351.c **** to 4 and adjust to PLL to generate the frequency (for example + 390:Core/Src/si5351.c **** a PLL of 640 to generate a 160MHz output clock). This is not + 391:Core/Src/si5351.c **** yet supported in the driver, which limits frequencies to + 392:Core/Src/si5351.c **** 500kHz .. 150MHz. + 393:Core/Src/si5351.c **** + 394:Core/Src/si5351.c **** @note For frequencies below 500kHz (down to 8kHz) Rx_DIV must be + 395:Core/Src/si5351.c **** used, but this isn't currently implemented in the driver. + 396:Core/Src/si5351.c **** */ + 397:Core/Src/si5351.c **** /**************************************************************************/ + 398:Core/Src/si5351.c **** err_t si5351_setupMultisynth(uint8_t output, + 399:Core/Src/si5351.c **** si5351PLL_t pllSource, + 400:Core/Src/si5351.c **** uint32_t div, + 401:Core/Src/si5351.c **** uint32_t num, + 402:Core/Src/si5351.c **** uint32_t denom) + 403:Core/Src/si5351.c **** { + 404:Core/Src/si5351.c **** uint32_t P1; /* Multisynth config register P1 */ + 405:Core/Src/si5351.c **** uint32_t P2; /* Multisynth config register P2 */ + 406:Core/Src/si5351.c **** uint32_t P3; /* Multisynth config register P3 */ + 407:Core/Src/si5351.c **** + 408:Core/Src/si5351.c **** /* Basic validation */ + 409:Core/Src/si5351.c **** ASSERT( m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED); + 410:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 411:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 412:Core/Src/si5351.c **** //ASSERT( div < 901, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 413:Core/Src/si5351.c **** //ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 414:Core/Src/si5351.c **** //ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 415:Core/Src/si5351.c **** //ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 416:Core/Src/si5351.c **** + 417:Core/Src/si5351.c **** + 418:Core/Src/si5351.c **** /* Make sure the requested PLL has been initialised */ + 419:Core/Src/si5351.c **** if (pllSource == SI5351_PLL_A) + 420:Core/Src/si5351.c **** { + 421:Core/Src/si5351.c **** ASSERT(m_si5351Config.plla_configured = 1, ERROR_INVALIDPARAMETER); + 422:Core/Src/si5351.c **** } + 423:Core/Src/si5351.c **** else + 424:Core/Src/si5351.c **** { + 425:Core/Src/si5351.c **** ASSERT(m_si5351Config.pllb_configured = 1, ERROR_INVALIDPARAMETER); + 426:Core/Src/si5351.c **** } + 427:Core/Src/si5351.c **** + 428:Core/Src/si5351.c **** /* Output Multisynth Divider Equations + 429:Core/Src/si5351.c **** * + 430:Core/Src/si5351.c **** * where: a = div, b = num and c = denom + ARM GAS /tmp/ccV7ORbp.s page 9 + + + 431:Core/Src/si5351.c **** * + 432:Core/Src/si5351.c **** * P1 register is an 18-bit value using following formula: + 433:Core/Src/si5351.c **** * + 434:Core/Src/si5351.c **** * P1[17:0] = 128 * a + floor(128*(b/c)) - 512 + 435:Core/Src/si5351.c **** * + 436:Core/Src/si5351.c **** * P2 register is a 20-bit value using the following formula: + 437:Core/Src/si5351.c **** * + 438:Core/Src/si5351.c **** * P2[19:0] = 128 * b - c * floor(128*(b/c)) + 439:Core/Src/si5351.c **** * + 440:Core/Src/si5351.c **** * P3 register is a 20-bit value using the following formula: + 441:Core/Src/si5351.c **** * + 442:Core/Src/si5351.c **** * P3[19:0] = c + 443:Core/Src/si5351.c **** */ + 444:Core/Src/si5351.c **** + 445:Core/Src/si5351.c **** /* Set the main PLL config registers */ + 446:Core/Src/si5351.c **** if (num == 0) + 447:Core/Src/si5351.c **** { + 448:Core/Src/si5351.c **** /* Integer mode */ + 449:Core/Src/si5351.c **** P1 = 128 * div - 512; + 450:Core/Src/si5351.c **** P2 = num; + 451:Core/Src/si5351.c **** P3 = denom; + 452:Core/Src/si5351.c **** } + 453:Core/Src/si5351.c **** else + 454:Core/Src/si5351.c **** { + 455:Core/Src/si5351.c **** /* Fractional mode */ + 456:Core/Src/si5351.c **** P1 = (uint32_t)(128 * div + floor(128 * ((float)num/(float)denom)) - 512); + 457:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 458:Core/Src/si5351.c **** P3 = denom; + 459:Core/Src/si5351.c **** } + 460:Core/Src/si5351.c **** + 461:Core/Src/si5351.c **** /* Get the appropriate starting point for the PLL registers */ + 462:Core/Src/si5351.c **** uint8_t baseaddr = 0; + 463:Core/Src/si5351.c **** switch (output) + 464:Core/Src/si5351.c **** { + 465:Core/Src/si5351.c **** case 0: + 466:Core/Src/si5351.c **** baseaddr = SI5351_REGISTER_42_MULTISYNTH0_PARAMETERS_1; + 467:Core/Src/si5351.c **** break; + 468:Core/Src/si5351.c **** case 1: + 469:Core/Src/si5351.c **** baseaddr = SI5351_REGISTER_50_MULTISYNTH1_PARAMETERS_1; + 470:Core/Src/si5351.c **** break; + 471:Core/Src/si5351.c **** case 2: + 472:Core/Src/si5351.c **** baseaddr = SI5351_REGISTER_58_MULTISYNTH2_PARAMETERS_1; + 473:Core/Src/si5351.c **** break; + 474:Core/Src/si5351.c **** } + 475:Core/Src/si5351.c **** + 476:Core/Src/si5351.c **** /* Set the MSx config registers */ + 477:Core/Src/si5351.c **** si5351_write8( baseaddr, (P3 & 0x0000FF00) >> 8); + 478:Core/Src/si5351.c **** si5351_write8( baseaddr+1, (P3 & 0x000000FF)); + 479:Core/Src/si5351.c **** si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16); /* ToDo: Add DIVBY4 (>150MHz) and R0 support + 480:Core/Src/si5351.c **** si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8); + 481:Core/Src/si5351.c **** si5351_write8( baseaddr+4, (P1 & 0x000000FF)); + 482:Core/Src/si5351.c **** si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ); + 483:Core/Src/si5351.c **** si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + 484:Core/Src/si5351.c **** si5351_write8( baseaddr+7, (P2 & 0x000000FF)); + 485:Core/Src/si5351.c **** + 486:Core/Src/si5351.c **** + 487:Core/Src/si5351.c **** if (pllSource == SI5351_PLL_A) + ARM GAS /tmp/ccV7ORbp.s page 10 + + + 488:Core/Src/si5351.c **** { + 489:Core/Src/si5351.c **** float fvco = m_si5351Config.plla_freq / (div + ( (float)num / (float)denom )); + 490:Core/Src/si5351.c **** switch (output) + 491:Core/Src/si5351.c **** { + 492:Core/Src/si5351.c **** case 0: + 493:Core/Src/si5351.c **** m_si5351Config.ms0_freq = (uint32_t)floor(fvco); + 494:Core/Src/si5351.c **** break; + 495:Core/Src/si5351.c **** case 1: + 496:Core/Src/si5351.c **** m_si5351Config.ms1_freq = (uint32_t)floor(fvco); + 497:Core/Src/si5351.c **** break; + 498:Core/Src/si5351.c **** case 2: + 499:Core/Src/si5351.c **** m_si5351Config.ms2_freq = (uint32_t)floor(fvco); + 500:Core/Src/si5351.c **** break; + 501:Core/Src/si5351.c **** } + 502:Core/Src/si5351.c **** } + 503:Core/Src/si5351.c **** else + 504:Core/Src/si5351.c **** { + 505:Core/Src/si5351.c **** float fvco = m_si5351Config.pllb_freq / (div + ( (float)num / (float)denom)); + 506:Core/Src/si5351.c **** switch (output) + 507:Core/Src/si5351.c **** { + 508:Core/Src/si5351.c **** case 0: + 509:Core/Src/si5351.c **** m_si5351Config.ms0_freq = (uint32_t)floor(fvco); + 510:Core/Src/si5351.c **** break; + 511:Core/Src/si5351.c **** case 1: + 512:Core/Src/si5351.c **** m_si5351Config.ms1_freq = (uint32_t)floor(fvco); + 513:Core/Src/si5351.c **** break; + 514:Core/Src/si5351.c **** case 2: + 515:Core/Src/si5351.c **** m_si5351Config.ms2_freq = (uint32_t)floor(fvco); + 516:Core/Src/si5351.c **** break; + 517:Core/Src/si5351.c **** } + 518:Core/Src/si5351.c **** } + 519:Core/Src/si5351.c **** + 520:Core/Src/si5351.c **** + 521:Core/Src/si5351.c **** + 522:Core/Src/si5351.c **** /* Configure the clk control and enable the output */ + 523:Core/Src/si5351.c **** uint8_t clkControlReg = 0x0F; /* 8mA drive strength, MS0 as CLK0 sour + 524:Core/Src/si5351.c **** // controfase + 525:Core/Src/si5351.c **** if(output == 1) clkControlReg = 0x1F; + 526:Core/Src/si5351.c **** + 527:Core/Src/si5351.c **** if (pllSource == SI5351_PLL_B) clkControlReg |= (1 << 5); /* Uses PLLB */ + 528:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 529:Core/Src/si5351.c **** switch (output) + 530:Core/Src/si5351.c **** { + 531:Core/Src/si5351.c **** case 0: + 532:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_16_CLK0_CONTROL, clkControlReg)); + 533:Core/Src/si5351.c **** break; + 534:Core/Src/si5351.c **** case 1: + 535:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, clkControlReg)); + 536:Core/Src/si5351.c **** break; + 537:Core/Src/si5351.c **** case 2: + 538:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, clkControlReg)); + 539:Core/Src/si5351.c **** break; + 540:Core/Src/si5351.c **** } + 541:Core/Src/si5351.c **** + 542:Core/Src/si5351.c **** return ERROR_NONE; + 543:Core/Src/si5351.c **** } + 544:Core/Src/si5351.c **** + ARM GAS /tmp/ccV7ORbp.s page 11 + + + 545:Core/Src/si5351.c **** /**************************************************************************/ + 546:Core/Src/si5351.c **** /*! + 547:Core/Src/si5351.c **** @brief Enables or disables all clock outputs + 548:Core/Src/si5351.c **** */ + 549:Core/Src/si5351.c **** /**************************************************************************/ + 550:Core/Src/si5351.c **** err_t si5351_enableOutputs(uint8_t enabled) + 551:Core/Src/si5351.c **** { + 552:Core/Src/si5351.c **** /* Make sure we've called init first */ + 553:Core/Src/si5351.c **** ASSERT(m_si5351Config.initialised, ERROR_DEVICENOTINITIALISED); + 554:Core/Src/si5351.c **** + 555:Core/Src/si5351.c **** /* Enabled desired outputs (see Register 3) */ + 556:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_3_OUTPUT_ENABLE_CONTROL, enabled ? 0x00: 0xFF)); + 557:Core/Src/si5351.c **** + 558:Core/Src/si5351.c **** return ERROR_NONE; + 559:Core/Src/si5351.c **** } + 560:Core/Src/si5351.c **** + 561:Core/Src/si5351.c **** /* ---------------------------------------------------------------------- */ + 562:Core/Src/si5351.c **** /* PRUVATE FUNCTIONS */ + 563:Core/Src/si5351.c **** /* ---------------------------------------------------------------------- */ + 564:Core/Src/si5351.c **** + 565:Core/Src/si5351.c **** /**************************************************************************/ + 566:Core/Src/si5351.c **** /*! + 567:Core/Src/si5351.c **** @brief Writes a register and an 8 bit value over I2C + 568:Core/Src/si5351.c **** */ + 569:Core/Src/si5351.c **** /**************************************************************************/ + 570:Core/Src/si5351.c **** err_t si5351_write8 (uint8_t reg, uint8_t value) + 571:Core/Src/si5351.c **** { + 28 .loc 1 571 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 571 1 is_stmt 0 view .LVU1 + 33 0000 10B5 push {r4, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 8 + 36 .cfi_offset 4, -8 + 37 .cfi_offset 14, -4 + 38 0002 86B0 sub sp, sp, #24 + 39 .LCFI1: + 40 .cfi_def_cfa_offset 32 + 41 0004 0400 movs r4, r0 + 42 0006 1723 movs r3, #23 + 43 0008 6B44 add r3, r3, sp + 44 000a 1970 strb r1, [r3] + 572:Core/Src/si5351.c **** HAL_StatusTypeDef status = HAL_OK; + 45 .loc 1 572 2 is_stmt 1 view .LVU2 + 46 .LVL1: + 573:Core/Src/si5351.c **** + 574:Core/Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c2, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } + 47 .loc 1 574 2 view .LVU3 + 48 .L2: + 49 .loc 1 574 91 discriminator 1 view .LVU4 + 50 .loc 1 574 8 discriminator 1 view .LVU5 + 51 .loc 1 574 9 is_stmt 0 discriminator 1 view .LVU6 + 52 000c 6423 movs r3, #100 + 53 000e 0322 movs r2, #3 + 54 0010 C021 movs r1, #192 + ARM GAS /tmp/ccV7ORbp.s page 12 + + + 55 0012 0A48 ldr r0, .L3 + 56 0014 FFF7FEFF bl HAL_I2C_IsDeviceReady + 57 .LVL2: + 58 .loc 1 574 8 discriminator 1 view .LVU7 + 59 0018 0028 cmp r0, #0 + 60 001a F7D1 bne .L2 + 575:Core/Src/si5351.c **** + 576:Core/Src/si5351.c **** status = HAL_I2C_Mem_Write(&hi2c2, // i2c handle + 61 .loc 1 576 5 is_stmt 1 view .LVU8 + 62 .loc 1 576 14 is_stmt 0 view .LVU9 + 63 001c A2B2 uxth r2, r4 + 64 001e 6423 movs r3, #100 + 65 0020 0293 str r3, [sp, #8] + 66 0022 633B subs r3, r3, #99 + 67 0024 0193 str r3, [sp, #4] + 68 0026 1633 adds r3, r3, #22 + 69 0028 6B44 add r3, r3, sp + 70 002a 0093 str r3, [sp] + 71 002c 0123 movs r3, #1 + 72 002e C021 movs r1, #192 + 73 0030 0248 ldr r0, .L3 + 74 0032 FFF7FEFF bl HAL_I2C_Mem_Write + 75 .LVL3: + 577:Core/Src/si5351.c **** (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned + 578:Core/Src/si5351.c **** (uint8_t)reg, // register address + 579:Core/Src/si5351.c **** I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses + 580:Core/Src/si5351.c **** (uint8_t*)(&value), // write returned data to this variable + 581:Core/Src/si5351.c **** 1, // how many bytes to expect returned + 582:Core/Src/si5351.c **** 100); // timeout + 583:Core/Src/si5351.c **** + 584:Core/Src/si5351.c **** return ERROR_NONE; + 76 .loc 1 584 3 is_stmt 1 view .LVU10 + 585:Core/Src/si5351.c **** } + 77 .loc 1 585 1 is_stmt 0 view .LVU11 + 78 0036 0020 movs r0, #0 + 79 0038 06B0 add sp, sp, #24 + 80 @ sp needed + 81 003a 10BD pop {r4, pc} + 82 .L4: + 83 .align 2 + 84 .L3: + 85 003c 00000000 .word hi2c2 + 86 .cfi_endproc + 87 .LFE304: + 89 .section .text.si5351_Init,"ax",%progbits + 90 .align 1 + 91 .global si5351_Init + 92 .syntax unified + 93 .code 16 + 94 .thumb_func + 95 .fpu softvfp + 97 si5351_Init: + 98 .LFB297: + 63:Core/Src/si5351.c **** + 99 .loc 1 63 1 is_stmt 1 view -0 + 100 .cfi_startproc + 101 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccV7ORbp.s page 13 + + + 102 @ frame_needed = 0, uses_anonymous_args = 0 + 103 0000 10B5 push {r4, lr} + 104 .LCFI2: + 105 .cfi_def_cfa_offset 8 + 106 .cfi_offset 4, -8 + 107 .cfi_offset 14, -4 + 68:Core/Src/si5351.c **** m_si5351Config.crystalFreq = SI5351_CRYSTAL_FREQ_24MHZ; + 108 .loc 1 68 4 view .LVU13 + 68:Core/Src/si5351.c **** m_si5351Config.crystalFreq = SI5351_CRYSTAL_FREQ_24MHZ; + 109 .loc 1 68 35 is_stmt 0 view .LVU14 + 110 0002 2D4B ldr r3, .L8 + 111 0004 0022 movs r2, #0 + 112 0006 1A70 strb r2, [r3] + 69:Core/Src/si5351.c **** m_si5351Config.crystalLoad = SI5351_CRYSTAL_LOAD_10PF; + 113 .loc 1 69 4 is_stmt 1 view .LVU15 + 69:Core/Src/si5351.c **** m_si5351Config.crystalLoad = SI5351_CRYSTAL_LOAD_10PF; + 114 .loc 1 69 35 is_stmt 0 view .LVU16 + 115 0008 2C49 ldr r1, .L8+4 + 116 000a 5960 str r1, [r3, #4] + 70:Core/Src/si5351.c **** m_si5351Config.crystalPPM = 30; + 117 .loc 1 70 4 is_stmt 1 view .LVU17 + 70:Core/Src/si5351.c **** m_si5351Config.crystalPPM = 30; + 118 .loc 1 70 35 is_stmt 0 view .LVU18 + 119 000c C021 movs r1, #192 + 120 000e 1972 strb r1, [r3, #8] + 71:Core/Src/si5351.c **** m_si5351Config.plla_configured = 0; + 121 .loc 1 71 4 is_stmt 1 view .LVU19 + 71:Core/Src/si5351.c **** m_si5351Config.plla_configured = 0; + 122 .loc 1 71 35 is_stmt 0 view .LVU20 + 123 0010 A239 subs r1, r1, #162 + 124 0012 D960 str r1, [r3, #12] + 72:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 125 .loc 1 72 4 is_stmt 1 view .LVU21 + 72:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 126 .loc 1 72 35 is_stmt 0 view .LVU22 + 127 0014 1A74 strb r2, [r3, #16] + 73:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 128 .loc 1 73 4 is_stmt 1 view .LVU23 + 73:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 129 .loc 1 73 35 is_stmt 0 view .LVU24 + 130 0016 5A61 str r2, [r3, #20] + 74:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 131 .loc 1 74 4 is_stmt 1 view .LVU25 + 74:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 132 .loc 1 74 35 is_stmt 0 view .LVU26 + 133 0018 1A76 strb r2, [r3, #24] + 75:Core/Src/si5351.c **** m_si5351Config.ms0_freq = 0; + 134 .loc 1 75 4 is_stmt 1 view .LVU27 + 75:Core/Src/si5351.c **** m_si5351Config.ms0_freq = 0; + 135 .loc 1 75 35 is_stmt 0 view .LVU28 + 136 001a DA61 str r2, [r3, #28] + 76:Core/Src/si5351.c **** m_si5351Config.ms1_freq = 0; + 137 .loc 1 76 4 is_stmt 1 view .LVU29 + 76:Core/Src/si5351.c **** m_si5351Config.ms1_freq = 0; + 138 .loc 1 76 30 is_stmt 0 view .LVU30 + 139 001c 1A62 str r2, [r3, #32] + 77:Core/Src/si5351.c **** m_si5351Config.ms2_freq = 0; + ARM GAS /tmp/ccV7ORbp.s page 14 + + + 140 .loc 1 77 4 is_stmt 1 view .LVU31 + 77:Core/Src/si5351.c **** m_si5351Config.ms2_freq = 0; + 141 .loc 1 77 30 is_stmt 0 view .LVU32 + 142 001e 5A62 str r2, [r3, #36] + 78:Core/Src/si5351.c **** m_si5351Config.ms0_r_div = 0; + 143 .loc 1 78 4 is_stmt 1 view .LVU33 + 78:Core/Src/si5351.c **** m_si5351Config.ms0_r_div = 0; + 144 .loc 1 78 30 is_stmt 0 view .LVU34 + 145 0020 9A62 str r2, [r3, #40] + 79:Core/Src/si5351.c **** m_si5351Config.ms1_r_div = 0; + 146 .loc 1 79 4 is_stmt 1 view .LVU35 + 79:Core/Src/si5351.c **** m_si5351Config.ms1_r_div = 0; + 147 .loc 1 79 31 is_stmt 0 view .LVU36 + 148 0022 DA62 str r2, [r3, #44] + 80:Core/Src/si5351.c **** m_si5351Config.ms2_r_div = 0; + 149 .loc 1 80 4 is_stmt 1 view .LVU37 + 80:Core/Src/si5351.c **** m_si5351Config.ms2_r_div = 0; + 150 .loc 1 80 31 is_stmt 0 view .LVU38 + 151 0024 1A63 str r2, [r3, #48] + 81:Core/Src/si5351.c **** + 152 .loc 1 81 4 is_stmt 1 view .LVU39 + 81:Core/Src/si5351.c **** + 153 .loc 1 81 31 is_stmt 0 view .LVU40 + 154 0026 5A63 str r2, [r3, #52] + 86:Core/Src/si5351.c **** + 155 .loc 1 86 3 is_stmt 1 view .LVU41 + 156 .LBB2: + 86:Core/Src/si5351.c **** + 157 .loc 1 86 3 view .LVU42 + 158 0028 E131 adds r1, r1, #225 + 159 002a 0320 movs r0, #3 + 160 002c FFF7FEFF bl si5351_write8 + 161 .LVL4: + 86:Core/Src/si5351.c **** + 162 .loc 1 86 3 view .LVU43 + 163 0030 0028 cmp r0, #0 + 164 0032 00D0 beq .L7 + 165 .LVL5: + 166 .L6: + 86:Core/Src/si5351.c **** + 167 .loc 1 86 3 is_stmt 0 view .LVU44 + 168 .LBE2: + 117:Core/Src/si5351.c **** + 169 .loc 1 117 1 view .LVU45 + 170 @ sp needed + 171 0034 10BD pop {r4, pc} + 172 .LVL6: + 173 .L7: + 86:Core/Src/si5351.c **** + 174 .loc 1 86 3 is_stmt 1 discriminator 2 view .LVU46 + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 175 .loc 1 89 3 discriminator 2 view .LVU47 + 176 .LBB3: + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 177 .loc 1 89 3 discriminator 2 view .LVU48 + 178 0036 8021 movs r1, #128 + 179 0038 1030 adds r0, r0, #16 + ARM GAS /tmp/ccV7ORbp.s page 15 + + + 180 .LVL7: + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 181 .loc 1 89 3 is_stmt 0 discriminator 2 view .LVU49 + 182 003a FFF7FEFF bl si5351_write8 + 183 .LVL8: + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 184 .loc 1 89 3 is_stmt 1 discriminator 2 view .LVU50 + 185 003e 0028 cmp r0, #0 + 186 0040 F8D1 bne .L6 + 187 .LBE3: + 89:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_17_CLK1_CONTROL, 0x80)); + 188 .loc 1 89 3 discriminator 2 view .LVU51 + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 189 .loc 1 90 3 discriminator 2 view .LVU52 + 190 .LBB4: + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 191 .loc 1 90 3 discriminator 2 view .LVU53 + 192 0042 8021 movs r1, #128 + 193 0044 1130 adds r0, r0, #17 + 194 .LVL9: + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 195 .loc 1 90 3 is_stmt 0 discriminator 2 view .LVU54 + 196 0046 FFF7FEFF bl si5351_write8 + 197 .LVL10: + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 198 .loc 1 90 3 is_stmt 1 discriminator 2 view .LVU55 + 199 004a 0028 cmp r0, #0 + 200 004c F2D1 bne .L6 + 201 .LBE4: + 90:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_18_CLK2_CONTROL, 0x80)); + 202 .loc 1 90 3 discriminator 2 view .LVU56 + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 203 .loc 1 91 3 discriminator 2 view .LVU57 + 204 .LBB5: + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 205 .loc 1 91 3 discriminator 2 view .LVU58 + 206 004e 8021 movs r1, #128 + 207 0050 1230 adds r0, r0, #18 + 208 .LVL11: + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 209 .loc 1 91 3 is_stmt 0 discriminator 2 view .LVU59 + 210 0052 FFF7FEFF bl si5351_write8 + 211 .LVL12: + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 212 .loc 1 91 3 is_stmt 1 discriminator 2 view .LVU60 + 213 0056 0028 cmp r0, #0 + 214 0058 ECD1 bne .L6 + 215 .LBE5: + 91:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_19_CLK3_CONTROL, 0x80)); + 216 .loc 1 91 3 discriminator 2 view .LVU61 + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 217 .loc 1 92 3 discriminator 2 view .LVU62 + 218 .LBB6: + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 219 .loc 1 92 3 discriminator 2 view .LVU63 + 220 005a 8021 movs r1, #128 + 221 005c 1330 adds r0, r0, #19 + ARM GAS /tmp/ccV7ORbp.s page 16 + + + 222 .LVL13: + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 223 .loc 1 92 3 is_stmt 0 discriminator 2 view .LVU64 + 224 005e FFF7FEFF bl si5351_write8 + 225 .LVL14: + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 226 .loc 1 92 3 is_stmt 1 discriminator 2 view .LVU65 + 227 0062 0028 cmp r0, #0 + 228 0064 E6D1 bne .L6 + 229 .LBE6: + 92:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_20_CLK4_CONTROL, 0x80)); + 230 .loc 1 92 3 discriminator 2 view .LVU66 + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 231 .loc 1 93 3 discriminator 2 view .LVU67 + 232 .LBB7: + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 233 .loc 1 93 3 discriminator 2 view .LVU68 + 234 0066 8021 movs r1, #128 + 235 0068 1430 adds r0, r0, #20 + 236 .LVL15: + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 237 .loc 1 93 3 is_stmt 0 discriminator 2 view .LVU69 + 238 006a FFF7FEFF bl si5351_write8 + 239 .LVL16: + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 240 .loc 1 93 3 is_stmt 1 discriminator 2 view .LVU70 + 241 006e 0028 cmp r0, #0 + 242 0070 E0D1 bne .L6 + 243 .LBE7: + 93:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_21_CLK5_CONTROL, 0x80)); + 244 .loc 1 93 3 discriminator 2 view .LVU71 + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 245 .loc 1 94 3 discriminator 2 view .LVU72 + 246 .LBB8: + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 247 .loc 1 94 3 discriminator 2 view .LVU73 + 248 0072 8021 movs r1, #128 + 249 0074 1530 adds r0, r0, #21 + 250 .LVL17: + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 251 .loc 1 94 3 is_stmt 0 discriminator 2 view .LVU74 + 252 0076 FFF7FEFF bl si5351_write8 + 253 .LVL18: + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 254 .loc 1 94 3 is_stmt 1 discriminator 2 view .LVU75 + 255 007a 0028 cmp r0, #0 + 256 007c DAD1 bne .L6 + 257 .LBE8: + 94:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_22_CLK6_CONTROL, 0x80)); + 258 .loc 1 94 3 discriminator 2 view .LVU76 + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 259 .loc 1 95 3 discriminator 2 view .LVU77 + 260 .LBB9: + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 261 .loc 1 95 3 discriminator 2 view .LVU78 + 262 007e 8021 movs r1, #128 + 263 0080 1630 adds r0, r0, #22 + ARM GAS /tmp/ccV7ORbp.s page 17 + + + 264 .LVL19: + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 265 .loc 1 95 3 is_stmt 0 discriminator 2 view .LVU79 + 266 0082 FFF7FEFF bl si5351_write8 + 267 .LVL20: + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 268 .loc 1 95 3 is_stmt 1 discriminator 2 view .LVU80 + 269 0086 0028 cmp r0, #0 + 270 0088 D4D1 bne .L6 + 271 .LBE9: + 95:Core/Src/si5351.c **** ASSERT_STATUS(si5351_write8(SI5351_REGISTER_23_CLK7_CONTROL, 0x80)); + 272 .loc 1 95 3 discriminator 2 view .LVU81 + 96:Core/Src/si5351.c **** + 273 .loc 1 96 3 discriminator 2 view .LVU82 + 274 .LBB10: + 96:Core/Src/si5351.c **** + 275 .loc 1 96 3 discriminator 2 view .LVU83 + 276 008a 8021 movs r1, #128 + 277 008c 1730 adds r0, r0, #23 + 278 .LVL21: + 96:Core/Src/si5351.c **** + 279 .loc 1 96 3 is_stmt 0 discriminator 2 view .LVU84 + 280 008e FFF7FEFF bl si5351_write8 + 281 .LVL22: + 96:Core/Src/si5351.c **** + 282 .loc 1 96 3 is_stmt 1 discriminator 2 view .LVU85 + 283 0092 0028 cmp r0, #0 + 284 0094 CED1 bne .L6 + 285 .LBE10: + 96:Core/Src/si5351.c **** + 286 .loc 1 96 3 discriminator 2 view .LVU86 + 99:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 287 .loc 1 99 3 discriminator 2 view .LVU87 + 288 .LBB11: + 99:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 289 .loc 1 99 3 discriminator 2 view .LVU88 + 290 0096 084B ldr r3, .L8 + 291 0098 197A ldrb r1, [r3, #8] + 292 009a B730 adds r0, r0, #183 + 293 .LVL23: + 99:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 294 .loc 1 99 3 is_stmt 0 discriminator 2 view .LVU89 + 295 009c FFF7FEFF bl si5351_write8 + 296 .LVL24: + 99:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 297 .loc 1 99 3 is_stmt 1 discriminator 2 view .LVU90 + 298 00a0 0028 cmp r0, #0 + 299 00a2 C7D1 bne .L6 + 300 .LBE11: + 99:Core/Src/si5351.c **** m_si5351Config.crystalLoad)); + 301 .loc 1 99 3 discriminator 2 view .LVU91 + 108:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 302 .loc 1 108 3 discriminator 2 view .LVU92 + 108:Core/Src/si5351.c **** m_si5351Config.plla_freq = 0; + 303 .loc 1 108 34 is_stmt 0 discriminator 2 view .LVU93 + 304 00a4 044B ldr r3, .L8 + 305 00a6 0022 movs r2, #0 + ARM GAS /tmp/ccV7ORbp.s page 18 + + + 306 00a8 1A74 strb r2, [r3, #16] + 109:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 307 .loc 1 109 3 is_stmt 1 discriminator 2 view .LVU94 + 109:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 0; + 308 .loc 1 109 28 is_stmt 0 discriminator 2 view .LVU95 + 309 00aa 5A61 str r2, [r3, #20] + 110:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 310 .loc 1 110 3 is_stmt 1 discriminator 2 view .LVU96 + 110:Core/Src/si5351.c **** m_si5351Config.pllb_freq = 0; + 311 .loc 1 110 34 is_stmt 0 discriminator 2 view .LVU97 + 312 00ac 1A76 strb r2, [r3, #24] + 111:Core/Src/si5351.c **** + 313 .loc 1 111 3 is_stmt 1 discriminator 2 view .LVU98 + 111:Core/Src/si5351.c **** + 314 .loc 1 111 28 is_stmt 0 discriminator 2 view .LVU99 + 315 00ae DA61 str r2, [r3, #28] + 114:Core/Src/si5351.c **** + 316 .loc 1 114 3 is_stmt 1 discriminator 2 view .LVU100 + 114:Core/Src/si5351.c **** + 317 .loc 1 114 30 is_stmt 0 discriminator 2 view .LVU101 + 318 00b0 0132 adds r2, r2, #1 + 319 00b2 1A70 strb r2, [r3] + 116:Core/Src/si5351.c **** } + 320 .loc 1 116 3 is_stmt 1 discriminator 2 view .LVU102 + 116:Core/Src/si5351.c **** } + 321 .loc 1 116 10 is_stmt 0 discriminator 2 view .LVU103 + 322 00b4 BEE7 b .L6 + 323 .L9: + 324 00b6 C046 .align 2 + 325 .L8: + 326 00b8 00000000 .word .LANCHOR0 + 327 00bc 00366E01 .word 24000000 + 328 .cfi_endproc + 329 .LFE297: + 331 .global __aeabi_ui2f + 332 .global __aeabi_fdiv + 333 .global __aeabi_fmul + 334 .global __aeabi_f2d + 335 .global __aeabi_i2d + 336 .global __aeabi_dadd + 337 .global __aeabi_dsub + 338 .global __aeabi_d2uiz + 339 .global __aeabi_ui2d + 340 .global __aeabi_dmul + 341 .global __aeabi_i2f + 342 .global __aeabi_fadd + 343 .section .text.si5351_setupPLL,"ax",%progbits + 344 .align 1 + 345 .global si5351_setupPLL + 346 .syntax unified + 347 .code 16 + 348 .thumb_func + 349 .fpu softvfp + 351 si5351_setupPLL: + 352 .LVL25: + 353 .LFB299: + 169:Core/Src/si5351.c **** uint32_t P1; /* PLL config register P1 */ + ARM GAS /tmp/ccV7ORbp.s page 19 + + + 354 .loc 1 169 1 is_stmt 1 view -0 + 355 .cfi_startproc + 356 @ args = 0, pretend = 0, frame = 8 + 357 @ frame_needed = 0, uses_anonymous_args = 0 + 169:Core/Src/si5351.c **** uint32_t P1; /* PLL config register P1 */ + 358 .loc 1 169 1 is_stmt 0 view .LVU105 + 359 0000 F0B5 push {r4, r5, r6, r7, lr} + 360 .LCFI3: + 361 .cfi_def_cfa_offset 20 + 362 .cfi_offset 4, -20 + 363 .cfi_offset 5, -16 + 364 .cfi_offset 6, -12 + 365 .cfi_offset 7, -8 + 366 .cfi_offset 14, -4 + 367 0002 DE46 mov lr, fp + 368 0004 5746 mov r7, r10 + 369 0006 4E46 mov r6, r9 + 370 0008 4546 mov r5, r8 + 371 000a E0B5 push {r5, r6, r7, lr} + 372 .LCFI4: + 373 .cfi_def_cfa_offset 36 + 374 .cfi_offset 8, -36 + 375 .cfi_offset 9, -32 + 376 .cfi_offset 10, -28 + 377 .cfi_offset 11, -24 + 378 000c 83B0 sub sp, sp, #12 + 379 .LCFI5: + 380 .cfi_def_cfa_offset 48 + 381 000e 0090 str r0, [sp] + 382 0010 0D00 movs r5, r1 + 383 0012 9146 mov r9, r2 + 384 0014 1C00 movs r4, r3 + 170:Core/Src/si5351.c **** uint32_t P2; /* PLL config register P2 */ + 385 .loc 1 170 3 is_stmt 1 view .LVU106 + 171:Core/Src/si5351.c **** uint32_t P3; /* PLL config register P3 */ + 386 .loc 1 171 3 view .LVU107 + 172:Core/Src/si5351.c **** + 387 .loc 1 172 3 view .LVU108 + 175:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 388 .loc 1 175 3 view .LVU109 + 175:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 389 .loc 1 175 3 view .LVU110 + 390 0016 874B ldr r3, .L22 + 391 .LVL26: + 175:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 392 .loc 1 175 3 is_stmt 0 view .LVU111 + 393 0018 1B78 ldrb r3, [r3] + 394 001a 002B cmp r3, #0 + 395 001c 00D1 bne .LCB335 + 396 001e F8E0 b .L16 @long jump + 397 .LCB335: + 175:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 398 .loc 1 175 3 is_stmt 1 discriminator 2 view .LVU112 + 176:Core/Src/si5351.c **** ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 399 .loc 1 176 3 discriminator 2 view .LVU113 + 176:Core/Src/si5351.c **** ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 400 .loc 1 176 3 discriminator 2 view .LVU114 + ARM GAS /tmp/ccV7ORbp.s page 20 + + + 401 0020 0B00 movs r3, r1 + 402 0022 0F3B subs r3, r3, #15 + 403 0024 DBB2 uxtb r3, r3 + 404 0026 4B2B cmp r3, #75 + 405 0028 00D9 bls .LCB343 + 406 002a FBE0 b .L17 @long jump + 407 .LCB343: + 176:Core/Src/si5351.c **** ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 408 .loc 1 176 3 discriminator 2 view .LVU115 + 177:Core/Src/si5351.c **** ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 409 .loc 1 177 3 discriminator 2 view .LVU116 + 177:Core/Src/si5351.c **** ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 410 .loc 1 177 3 discriminator 2 view .LVU117 + 411 002c 002C cmp r4, #0 + 412 002e 00D1 bne .LCB348 + 413 0030 FAE0 b .L18 @long jump + 414 .LCB348: + 177:Core/Src/si5351.c **** ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 415 .loc 1 177 3 discriminator 2 view .LVU118 + 178:Core/Src/si5351.c **** ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 416 .loc 1 178 3 discriminator 2 view .LVU119 + 178:Core/Src/si5351.c **** ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 417 .loc 1 178 3 discriminator 2 view .LVU120 + 418 0032 8023 movs r3, #128 + 419 0034 5B03 lsls r3, r3, #13 + 420 0036 9A42 cmp r2, r3 + 421 0038 00D3 bcc .LCB355 + 422 003a F7E0 b .L19 @long jump + 423 .LCB355: + 178:Core/Src/si5351.c **** ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 424 .loc 1 178 3 discriminator 2 view .LVU121 + 179:Core/Src/si5351.c **** + 425 .loc 1 179 3 discriminator 2 view .LVU122 + 179:Core/Src/si5351.c **** + 426 .loc 1 179 3 discriminator 2 view .LVU123 + 427 003c 9C42 cmp r4, r3 + 428 003e 00D3 bcc .LCB360 + 429 0040 F6E0 b .L20 @long jump + 430 .LCB360: + 179:Core/Src/si5351.c **** + 431 .loc 1 179 3 discriminator 2 view .LVU124 + 199:Core/Src/si5351.c **** { + 432 .loc 1 199 3 discriminator 2 view .LVU125 + 199:Core/Src/si5351.c **** { + 433 .loc 1 199 6 is_stmt 0 discriminator 2 view .LVU126 + 434 0042 002A cmp r2, #0 + 435 0044 00D0 beq .LCB364 + 436 0046 81E0 b .L12 @long jump + 437 .LCB364: + 202:Core/Src/si5351.c **** P2 = num; + 438 .loc 1 202 5 is_stmt 1 view .LVU127 + 202:Core/Src/si5351.c **** P2 = num; + 439 .loc 1 202 21 is_stmt 0 view .LVU128 + 440 0048 0439 subs r1, r1, #4 + 441 .LVL27: + 202:Core/Src/si5351.c **** P2 = num; + 442 .loc 1 202 21 view .LVU129 + ARM GAS /tmp/ccV7ORbp.s page 21 + + + 443 004a CB01 lsls r3, r1, #7 + 444 004c 9B46 mov fp, r3 + 445 .LVL28: + 203:Core/Src/si5351.c **** P3 = denom; + 446 .loc 1 203 5 is_stmt 1 view .LVU130 + 204:Core/Src/si5351.c **** } + 447 .loc 1 204 5 view .LVU131 + 203:Core/Src/si5351.c **** P3 = denom; + 448 .loc 1 203 8 is_stmt 0 view .LVU132 + 449 004e 0192 str r2, [sp, #4] + 450 .LVL29: + 451 .L13: + 215:Core/Src/si5351.c **** + 452 .loc 1 215 3 is_stmt 1 view .LVU133 + 215:Core/Src/si5351.c **** + 453 .loc 1 215 11 is_stmt 0 view .LVU134 + 454 0050 009B ldr r3, [sp] + 455 0052 002B cmp r3, #0 + 456 0054 00D0 beq .LCB388 + 457 0056 B2E0 b .L21 @long jump + 458 .LCB388: + 215:Core/Src/si5351.c **** + 459 .loc 1 215 11 view .LVU135 + 460 0058 1A27 movs r7, #26 + 461 .L14: + 462 .LVL30: + 218:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + 463 .loc 1 218 3 is_stmt 1 discriminator 4 view .LVU136 + 464 .LBB12: + 218:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + 465 .loc 1 218 3 discriminator 4 view .LVU137 + 466 005a 210A lsrs r1, r4, #8 + 467 005c C9B2 uxtb r1, r1 + 468 005e 3800 movs r0, r7 + 469 0060 FFF7FEFF bl si5351_write8 + 470 .LVL31: + 471 0064 061E subs r6, r0, #0 + 472 .LVL32: + 218:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + 473 .loc 1 218 3 discriminator 4 view .LVU138 + 474 0066 00D0 beq .LCB407 + 475 0068 D4E0 b .L11 @long jump + 476 .LCB407: + 477 .LBE12: + 218:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+1, (P3 & 0x000000FF))); + 478 .loc 1 218 3 discriminator 2 view .LVU139 + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 479 .loc 1 219 3 discriminator 2 view .LVU140 + 480 .LBB13: + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 481 .loc 1 219 3 discriminator 2 view .LVU141 + 482 006a E1B2 uxtb r1, r4 + 483 006c 781C adds r0, r7, #1 + 484 .LVL33: + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 485 .loc 1 219 3 is_stmt 0 discriminator 2 view .LVU142 + 486 006e FFF7FEFF bl si5351_write8 + ARM GAS /tmp/ccV7ORbp.s page 22 + + + 487 .LVL34: + 488 0072 061E subs r6, r0, #0 + 489 .LVL35: + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 490 .loc 1 219 3 is_stmt 1 discriminator 2 view .LVU143 + 491 0074 00D0 beq .LCB424 + 492 0076 CDE0 b .L11 @long jump + 493 .LCB424: + 494 .LBE13: + 219:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16)); + 495 .loc 1 219 3 discriminator 2 view .LVU144 + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 496 .loc 1 220 3 discriminator 2 view .LVU145 + 497 .LBB14: + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 498 .loc 1 220 3 discriminator 2 view .LVU146 + 499 0078 5B46 mov r3, fp + 500 007a 1B0C lsrs r3, r3, #16 + 501 007c 0321 movs r1, #3 + 502 007e 1940 ands r1, r3 + 503 0080 B81C adds r0, r7, #2 + 504 .LVL36: + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 505 .loc 1 220 3 is_stmt 0 discriminator 2 view .LVU147 + 506 0082 FFF7FEFF bl si5351_write8 + 507 .LVL37: + 508 0086 061E subs r6, r0, #0 + 509 .LVL38: + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 510 .loc 1 220 3 is_stmt 1 discriminator 2 view .LVU148 + 511 0088 00D0 beq .LCB445 + 512 008a C3E0 b .L11 @long jump + 513 .LCB445: + 514 .LBE14: + 220:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8)); + 515 .loc 1 220 3 discriminator 2 view .LVU149 + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 516 .loc 1 221 3 discriminator 2 view .LVU150 + 517 .LBB15: + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 518 .loc 1 221 3 discriminator 2 view .LVU151 + 519 008c 5B46 mov r3, fp + 520 008e 190A lsrs r1, r3, #8 + 521 0090 C9B2 uxtb r1, r1 + 522 0092 F81C adds r0, r7, #3 + 523 .LVL39: + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 524 .loc 1 221 3 is_stmt 0 discriminator 2 view .LVU152 + 525 0094 FFF7FEFF bl si5351_write8 + 526 .LVL40: + 527 0098 061E subs r6, r0, #0 + 528 .LVL41: + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 529 .loc 1 221 3 is_stmt 1 discriminator 2 view .LVU153 + 530 009a 00D0 beq .LCB464 + 531 009c BAE0 b .L11 @long jump + 532 .LCB464: + ARM GAS /tmp/ccV7ORbp.s page 23 + + + 533 .LBE15: + 221:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+4, (P1 & 0x000000FF))); + 534 .loc 1 221 3 discriminator 2 view .LVU154 + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 535 .loc 1 222 3 discriminator 2 view .LVU155 + 536 .LBB16: + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 537 .loc 1 222 3 discriminator 2 view .LVU156 + 538 009e 5B46 mov r3, fp + 539 00a0 D9B2 uxtb r1, r3 + 540 00a2 381D adds r0, r7, #4 + 541 .LVL42: + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 542 .loc 1 222 3 is_stmt 0 discriminator 2 view .LVU157 + 543 00a4 FFF7FEFF bl si5351_write8 + 544 .LVL43: + 545 00a8 061E subs r6, r0, #0 + 546 .LVL44: + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 547 .loc 1 222 3 is_stmt 1 discriminator 2 view .LVU158 + 548 00aa 00D0 beq .LCB482 + 549 00ac B2E0 b .L11 @long jump + 550 .LCB482: + 551 .LBE16: + 222:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ) + 552 .loc 1 222 3 discriminator 2 view .LVU159 + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 553 .loc 1 223 3 discriminator 2 view .LVU160 + 554 .LBB17: + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 555 .loc 1 223 3 discriminator 2 view .LVU161 + 556 00ae 210B lsrs r1, r4, #12 + 557 00b0 0F23 movs r3, #15 + 558 00b2 9943 bics r1, r3 + 559 00b4 C9B2 uxtb r1, r1 + 560 00b6 019B ldr r3, [sp, #4] + 561 00b8 1A0C lsrs r2, r3, #16 + 562 00ba 0F23 movs r3, #15 + 563 00bc 1340 ands r3, r2 + 564 00be 1943 orrs r1, r3 + 565 00c0 781D adds r0, r7, #5 + 566 .LVL45: + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 567 .loc 1 223 3 is_stmt 0 discriminator 2 view .LVU162 + 568 00c2 FFF7FEFF bl si5351_write8 + 569 .LVL46: + 570 00c6 061E subs r6, r0, #0 + 571 .LVL47: + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 572 .loc 1 223 3 is_stmt 1 discriminator 2 view .LVU163 + 573 00c8 00D0 beq .LCB510 + 574 00ca A3E0 b .L11 @long jump + 575 .LCB510: + 576 .LBE17: + 223:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8)); + 577 .loc 1 223 3 discriminator 2 view .LVU164 + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + ARM GAS /tmp/ccV7ORbp.s page 24 + + + 578 .loc 1 224 3 discriminator 2 view .LVU165 + 579 .LBB18: + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + 580 .loc 1 224 3 discriminator 2 view .LVU166 + 581 00cc 019B ldr r3, [sp, #4] + 582 00ce 190A lsrs r1, r3, #8 + 583 00d0 C9B2 uxtb r1, r1 + 584 00d2 B81D adds r0, r7, #6 + 585 .LVL48: + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + 586 .loc 1 224 3 is_stmt 0 discriminator 2 view .LVU167 + 587 00d4 FFF7FEFF bl si5351_write8 + 588 .LVL49: + 589 00d8 061E subs r6, r0, #0 + 590 .LVL50: + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + 591 .loc 1 224 3 is_stmt 1 discriminator 2 view .LVU168 + 592 00da 00D0 beq .LCB530 + 593 00dc 9AE0 b .L11 @long jump + 594 .LCB530: + 595 .LBE18: + 224:Core/Src/si5351.c **** ASSERT_STATUS( si5351_write8( baseaddr+7, (P2 & 0x000000FF))); + 596 .loc 1 224 3 discriminator 2 view .LVU169 + 225:Core/Src/si5351.c **** + 597 .loc 1 225 3 discriminator 2 view .LVU170 + 598 .LBB19: + 225:Core/Src/si5351.c **** + 599 .loc 1 225 3 discriminator 2 view .LVU171 + 600 00de 6B46 mov r3, sp + 601 00e0 1979 ldrb r1, [r3, #4] + 602 00e2 F81D adds r0, r7, #7 + 603 .LVL51: + 225:Core/Src/si5351.c **** + 604 .loc 1 225 3 is_stmt 0 discriminator 2 view .LVU172 + 605 00e4 FFF7FEFF bl si5351_write8 + 606 .LVL52: + 607 00e8 061E subs r6, r0, #0 + 608 .LVL53: + 225:Core/Src/si5351.c **** + 609 .loc 1 225 3 is_stmt 1 discriminator 2 view .LVU173 + 610 00ea 00D0 beq .LCB548 + 611 00ec 92E0 b .L11 @long jump + 612 .LCB548: + 613 .LBE19: + 225:Core/Src/si5351.c **** + 614 .loc 1 225 3 discriminator 2 view .LVU174 + 228:Core/Src/si5351.c **** + 615 .loc 1 228 3 discriminator 2 view .LVU175 + 616 .LBB20: + 228:Core/Src/si5351.c **** + 617 .loc 1 228 3 discriminator 2 view .LVU176 + 618 00ee A021 movs r1, #160 + 619 00f0 B120 movs r0, #177 + 620 .LVL54: + 228:Core/Src/si5351.c **** + 621 .loc 1 228 3 is_stmt 0 discriminator 2 view .LVU177 + 622 00f2 FFF7FEFF bl si5351_write8 + ARM GAS /tmp/ccV7ORbp.s page 25 + + + 623 .LVL55: + 624 00f6 061E subs r6, r0, #0 + 625 .LVL56: + 228:Core/Src/si5351.c **** + 626 .loc 1 228 3 is_stmt 1 discriminator 2 view .LVU178 + 627 00f8 00D0 beq .LCB564 + 628 00fa 8BE0 b .L11 @long jump + 629 .LCB564: + 630 .LBE20: + 228:Core/Src/si5351.c **** + 631 .loc 1 228 3 discriminator 2 view .LVU179 + 231:Core/Src/si5351.c **** { + 632 .loc 1 231 3 discriminator 2 view .LVU180 + 231:Core/Src/si5351.c **** { + 633 .loc 1 231 6 is_stmt 0 discriminator 2 view .LVU181 + 634 00fc 009B ldr r3, [sp] + 635 00fe 002B cmp r3, #0 + 636 0100 5FD1 bne .L15 + 637 .LBB21: + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 638 .loc 1 233 5 is_stmt 1 view .LVU182 + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 639 .loc 1 233 32 is_stmt 0 view .LVU183 + 640 0102 4C4F ldr r7, .L22 + 641 .LVL57: + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 642 .loc 1 233 45 view .LVU184 + 643 0104 7868 ldr r0, [r7, #4] + 644 .LVL58: + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 645 .loc 1 233 45 view .LVU185 + 646 0106 FFF7FEFF bl __aeabi_ui2f + 647 .LVL59: + 648 010a 8046 mov r8, r0 + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 649 .loc 1 233 57 view .LVU186 + 650 010c 4846 mov r0, r9 + 651 010e FFF7FEFF bl __aeabi_ui2f + 652 .LVL60: + 653 0112 8146 mov r9, r0 + 654 .LVL61: + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 655 .loc 1 233 70 view .LVU187 + 656 0114 2000 movs r0, r4 + 657 0116 FFF7FEFF bl __aeabi_ui2f + 658 .LVL62: + 659 011a 011C adds r1, r0, #0 + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 660 .loc 1 233 68 view .LVU188 + 661 011c 4846 mov r0, r9 + 662 011e FFF7FEFF bl __aeabi_fdiv + 663 .LVL63: + 664 0122 041C adds r4, r0, #0 + 665 .LVL64: + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 666 .loc 1 233 53 view .LVU189 + 667 0124 2800 movs r0, r5 + ARM GAS /tmp/ccV7ORbp.s page 26 + + + 668 0126 FFF7FEFF bl __aeabi_i2f + 669 .LVL65: + 670 012a 211C adds r1, r4, #0 + 671 012c FFF7FEFF bl __aeabi_fadd + 672 .LVL66: + 673 0130 011C adds r1, r0, #0 + 233:Core/Src/si5351.c **** m_si5351Config.plla_configured = 1; //true + 674 .loc 1 233 11 view .LVU190 + 675 0132 4046 mov r0, r8 + 676 0134 FFF7FEFF bl __aeabi_fmul + 677 .LVL67: + 234:Core/Src/si5351.c **** m_si5351Config.plla_freq = (uint32_t)floor(fvco); + 678 .loc 1 234 5 is_stmt 1 view .LVU191 + 234:Core/Src/si5351.c **** m_si5351Config.plla_freq = (uint32_t)floor(fvco); + 679 .loc 1 234 36 is_stmt 0 view .LVU192 + 680 0138 0123 movs r3, #1 + 681 013a 3B74 strb r3, [r7, #16] + 235:Core/Src/si5351.c **** } + 682 .loc 1 235 5 is_stmt 1 view .LVU193 + 235:Core/Src/si5351.c **** } + 683 .loc 1 235 42 is_stmt 0 view .LVU194 + 684 013c FFF7FEFF bl __aeabi_f2d + 685 .LVL68: + 235:Core/Src/si5351.c **** } + 686 .loc 1 235 42 view .LVU195 + 687 0140 FFF7FEFF bl floor + 688 .LVL69: + 235:Core/Src/si5351.c **** } + 689 .loc 1 235 32 view .LVU196 + 690 0144 FFF7FEFF bl __aeabi_d2uiz + 691 .LVL70: + 235:Core/Src/si5351.c **** } + 692 .loc 1 235 30 view .LVU197 + 693 0148 7861 str r0, [r7, #20] + 694 .LBE21: + 695 014a 63E0 b .L11 + 696 .LVL71: + 697 .L12: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 698 .loc 1 209 5 is_stmt 1 view .LVU198 + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 699 .loc 1 209 47 is_stmt 0 view .LVU199 + 700 014c 1000 movs r0, r2 + 701 .LVL72: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 702 .loc 1 209 47 view .LVU200 + 703 014e FFF7FEFF bl __aeabi_ui2f + 704 .LVL73: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 705 .loc 1 209 47 view .LVU201 + 706 0152 061C adds r6, r0, #0 + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 707 .loc 1 209 58 view .LVU202 + 708 0154 2000 movs r0, r4 + 709 0156 FFF7FEFF bl __aeabi_ui2f + 710 .LVL74: + 711 015a 011C adds r1, r0, #0 + ARM GAS /tmp/ccV7ORbp.s page 27 + + + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 712 .loc 1 209 57 view .LVU203 + 713 015c 301C adds r0, r6, #0 + 714 015e FFF7FEFF bl __aeabi_fdiv + 715 .LVL75: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 716 .loc 1 209 44 view .LVU204 + 717 0162 8621 movs r1, #134 + 718 0164 C905 lsls r1, r1, #23 + 719 0166 FFF7FEFF bl __aeabi_fmul + 720 .LVL76: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 721 .loc 1 209 34 view .LVU205 + 722 016a FFF7FEFF bl __aeabi_f2d + 723 .LVL77: + 724 016e FFF7FEFF bl floor + 725 .LVL78: + 726 0172 0600 movs r6, r0 + 727 0174 0F00 movs r7, r1 + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 728 .loc 1 209 32 view .LVU206 + 729 0176 E801 lsls r0, r5, #7 + 730 0178 FFF7FEFF bl __aeabi_i2d + 731 .LVL79: + 732 017c 3200 movs r2, r6 + 733 017e 3B00 movs r3, r7 + 734 0180 FFF7FEFF bl __aeabi_dadd + 735 .LVL80: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 736 .loc 1 209 73 view .LVU207 + 737 0184 0022 movs r2, #0 + 738 0186 8123 movs r3, #129 + 739 0188 DB05 lsls r3, r3, #23 + 740 018a FFF7FEFF bl __aeabi_dsub + 741 .LVL81: + 209:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 742 .loc 1 209 8 view .LVU208 + 743 018e FFF7FEFF bl __aeabi_d2uiz + 744 .LVL82: + 745 0192 8346 mov fp, r0 + 746 .LVL83: + 210:Core/Src/si5351.c **** P3 = denom; + 747 .loc 1 210 5 is_stmt 1 view .LVU209 + 210:Core/Src/si5351.c **** P3 = denom; + 748 .loc 1 210 39 is_stmt 0 view .LVU210 + 749 0194 2000 movs r0, r4 + 750 .LVL84: + 210:Core/Src/si5351.c **** P3 = denom; + 751 .loc 1 210 39 view .LVU211 + 752 0196 FFF7FEFF bl __aeabi_ui2d + 753 .LVL85: + 754 019a 3200 movs r2, r6 + 755 019c 3B00 movs r3, r7 + 756 019e FFF7FEFF bl __aeabi_dmul + 757 .LVL86: + 758 01a2 0600 movs r6, r0 + 759 01a4 0F00 movs r7, r1 + ARM GAS /tmp/ccV7ORbp.s page 28 + + + 210:Core/Src/si5351.c **** P3 = denom; + 760 .loc 1 210 31 view .LVU212 + 761 01a6 4B46 mov r3, r9 + 762 01a8 D801 lsls r0, r3, #7 + 763 01aa FFF7FEFF bl __aeabi_ui2d + 764 .LVL87: + 765 01ae 3200 movs r2, r6 + 766 01b0 3B00 movs r3, r7 + 767 01b2 FFF7FEFF bl __aeabi_dsub + 768 .LVL88: + 210:Core/Src/si5351.c **** P3 = denom; + 769 .loc 1 210 8 view .LVU213 + 770 01b6 FFF7FEFF bl __aeabi_d2uiz + 771 .LVL89: + 772 01ba 0190 str r0, [sp, #4] + 773 .LVL90: + 211:Core/Src/si5351.c **** } + 774 .loc 1 211 5 is_stmt 1 view .LVU214 + 211:Core/Src/si5351.c **** } + 775 .loc 1 211 5 is_stmt 0 view .LVU215 + 776 01bc 48E7 b .L13 + 777 .LVL91: + 778 .L21: + 215:Core/Src/si5351.c **** + 779 .loc 1 215 11 view .LVU216 + 780 01be 2227 movs r7, #34 + 781 01c0 4BE7 b .L14 + 782 .LVL92: + 783 .L15: + 784 .LBB22: + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 785 .loc 1 239 5 is_stmt 1 view .LVU217 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 786 .loc 1 239 32 is_stmt 0 view .LVU218 + 787 01c2 1C4B ldr r3, .L22 + 788 01c4 9A46 mov r10, r3 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 789 .loc 1 239 45 view .LVU219 + 790 01c6 5868 ldr r0, [r3, #4] + 791 .LVL93: + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 792 .loc 1 239 45 view .LVU220 + 793 01c8 FFF7FEFF bl __aeabi_ui2f + 794 .LVL94: + 795 01cc 8046 mov r8, r0 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 796 .loc 1 239 57 view .LVU221 + 797 01ce 4846 mov r0, r9 + 798 01d0 FFF7FEFF bl __aeabi_ui2f + 799 .LVL95: + 800 01d4 071C adds r7, r0, #0 + 801 .LVL96: + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 802 .loc 1 239 70 view .LVU222 + 803 01d6 2000 movs r0, r4 + 804 01d8 FFF7FEFF bl __aeabi_ui2f + 805 .LVL97: + ARM GAS /tmp/ccV7ORbp.s page 29 + + + 806 01dc 011C adds r1, r0, #0 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 807 .loc 1 239 68 view .LVU223 + 808 01de 381C adds r0, r7, #0 + 809 01e0 FFF7FEFF bl __aeabi_fdiv + 810 .LVL98: + 811 01e4 071C adds r7, r0, #0 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 812 .loc 1 239 53 view .LVU224 + 813 01e6 2800 movs r0, r5 + 814 01e8 FFF7FEFF bl __aeabi_i2f + 815 .LVL99: + 816 01ec 391C adds r1, r7, #0 + 817 01ee FFF7FEFF bl __aeabi_fadd + 818 .LVL100: + 819 01f2 011C adds r1, r0, #0 + 239:Core/Src/si5351.c **** m_si5351Config.pllb_configured = 1; //true + 820 .loc 1 239 11 view .LVU225 + 821 01f4 4046 mov r0, r8 + 822 01f6 FFF7FEFF bl __aeabi_fmul + 823 .LVL101: + 240:Core/Src/si5351.c **** m_si5351Config.pllb_freq = (uint32_t)floor(fvco); + 824 .loc 1 240 5 is_stmt 1 view .LVU226 + 240:Core/Src/si5351.c **** m_si5351Config.pllb_freq = (uint32_t)floor(fvco); + 825 .loc 1 240 36 is_stmt 0 view .LVU227 + 826 01fa 0123 movs r3, #1 + 827 01fc 5246 mov r2, r10 + 828 01fe 1376 strb r3, [r2, #24] + 241:Core/Src/si5351.c **** } + 829 .loc 1 241 5 is_stmt 1 view .LVU228 + 241:Core/Src/si5351.c **** } + 830 .loc 1 241 42 is_stmt 0 view .LVU229 + 831 0200 FFF7FEFF bl __aeabi_f2d + 832 .LVL102: + 241:Core/Src/si5351.c **** } + 833 .loc 1 241 42 view .LVU230 + 834 0204 FFF7FEFF bl floor + 835 .LVL103: + 241:Core/Src/si5351.c **** } + 836 .loc 1 241 32 view .LVU231 + 837 0208 FFF7FEFF bl __aeabi_d2uiz + 838 .LVL104: + 241:Core/Src/si5351.c **** } + 839 .loc 1 241 30 view .LVU232 + 840 020c 5346 mov r3, r10 + 841 020e D861 str r0, [r3, #28] + 842 0210 00E0 b .L11 + 843 .LVL105: + 844 .L16: + 241:Core/Src/si5351.c **** } + 845 .loc 1 241 30 view .LVU233 + 846 .LBE22: + 175:Core/Src/si5351.c **** ASSERT( (mult > 14) && (mult < 91), ERROR_INVALIDPARAMETER ); /* mult = 15..90 */ + 847 .loc 1 175 3 view .LVU234 + 848 0212 0526 movs r6, #5 + 849 .LVL106: + 850 .L11: + ARM GAS /tmp/ccV7ORbp.s page 30 + + + 245:Core/Src/si5351.c **** + 851 .loc 1 245 1 view .LVU235 + 852 0214 3000 movs r0, r6 + 853 0216 03B0 add sp, sp, #12 + 854 @ sp needed + 855 0218 F0BC pop {r4, r5, r6, r7} + 856 021a BB46 mov fp, r7 + 857 021c B246 mov r10, r6 + 858 021e A946 mov r9, r5 + 859 0220 A046 mov r8, r4 + 860 0222 F0BD pop {r4, r5, r6, r7, pc} + 861 .LVL107: + 862 .L17: + 176:Core/Src/si5351.c **** ASSERT( denom > 0, ERROR_INVALIDPARAMETER ); /* Avoid divide by zero */ + 863 .loc 1 176 3 view .LVU236 + 864 0224 0426 movs r6, #4 + 865 0226 F5E7 b .L11 + 866 .L18: + 177:Core/Src/si5351.c **** ASSERT( num <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 867 .loc 1 177 3 view .LVU237 + 868 0228 0426 movs r6, #4 + 869 022a F3E7 b .L11 + 870 .L19: + 178:Core/Src/si5351.c **** ASSERT( denom <= 0xFFFFF, ERROR_INVALIDPARAMETER ); /* 20-bit limit */ + 871 .loc 1 178 3 view .LVU238 + 872 022c 0426 movs r6, #4 + 873 022e F1E7 b .L11 + 874 .L20: + 179:Core/Src/si5351.c **** + 875 .loc 1 179 3 view .LVU239 + 876 0230 0426 movs r6, #4 + 877 0232 EFE7 b .L11 + 878 .L23: + 879 .align 2 + 880 .L22: + 881 0234 00000000 .word .LANCHOR0 + 882 .cfi_endproc + 883 .LFE299: + 885 .section .text.si5351_setupPLLInt,"ax",%progbits + 886 .align 1 + 887 .global si5351_setupPLLInt + 888 .syntax unified + 889 .code 16 + 890 .thumb_func + 891 .fpu softvfp + 893 si5351_setupPLLInt: + 894 .LVL108: + 895 .LFB298: + 131:Core/Src/si5351.c **** return si5351_setupPLL(pll, mult, 0, 1); + 896 .loc 1 131 1 is_stmt 1 view -0 + 897 .cfi_startproc + 898 @ args = 0, pretend = 0, frame = 0 + 899 @ frame_needed = 0, uses_anonymous_args = 0 + 131:Core/Src/si5351.c **** return si5351_setupPLL(pll, mult, 0, 1); + 900 .loc 1 131 1 is_stmt 0 view .LVU241 + 901 0000 10B5 push {r4, lr} + 902 .LCFI6: + ARM GAS /tmp/ccV7ORbp.s page 31 + + + 903 .cfi_def_cfa_offset 8 + 904 .cfi_offset 4, -8 + 905 .cfi_offset 14, -4 + 132:Core/Src/si5351.c **** } + 906 .loc 1 132 3 is_stmt 1 view .LVU242 + 132:Core/Src/si5351.c **** } + 907 .loc 1 132 10 is_stmt 0 view .LVU243 + 908 0002 0123 movs r3, #1 + 909 0004 0022 movs r2, #0 + 910 0006 FFF7FEFF bl si5351_setupPLL + 911 .LVL109: + 133:Core/Src/si5351.c **** + 912 .loc 1 133 1 view .LVU244 + 913 @ sp needed + 914 000a 10BD pop {r4, pc} + 915 .cfi_endproc + 916 .LFE298: + 918 .section .text.si5351_setupMultisynth,"ax",%progbits + 919 .align 1 + 920 .global si5351_setupMultisynth + 921 .syntax unified + 922 .code 16 + 923 .thumb_func + 924 .fpu softvfp + 926 si5351_setupMultisynth: + 927 .LVL110: + 928 .LFB302: + 403:Core/Src/si5351.c **** uint32_t P1; /* Multisynth config register P1 */ + 929 .loc 1 403 1 is_stmt 1 view -0 + 930 .cfi_startproc + 931 @ args = 4, pretend = 0, frame = 0 + 932 @ frame_needed = 0, uses_anonymous_args = 0 + 403:Core/Src/si5351.c **** uint32_t P1; /* Multisynth config register P1 */ + 933 .loc 1 403 1 is_stmt 0 view .LVU246 + 934 0000 F0B5 push {r4, r5, r6, r7, lr} + 935 .LCFI7: + 936 .cfi_def_cfa_offset 20 + 937 .cfi_offset 4, -20 + 938 .cfi_offset 5, -16 + 939 .cfi_offset 6, -12 + 940 .cfi_offset 7, -8 + 941 .cfi_offset 14, -4 + 942 0002 DE46 mov lr, fp + 943 0004 5746 mov r7, r10 + 944 0006 4E46 mov r6, r9 + 945 0008 C0B5 push {r6, r7, lr} + 946 .LCFI8: + 947 .cfi_def_cfa_offset 32 + 948 .cfi_offset 9, -32 + 949 .cfi_offset 10, -28 + 950 .cfi_offset 11, -24 + 951 000a 0400 movs r4, r0 + 952 000c 8A46 mov r10, r1 + 953 000e 9346 mov fp, r2 + 954 0010 1D00 movs r5, r3 + 404:Core/Src/si5351.c **** uint32_t P2; /* Multisynth config register P2 */ + 955 .loc 1 404 3 is_stmt 1 view .LVU247 + ARM GAS /tmp/ccV7ORbp.s page 32 + + + 405:Core/Src/si5351.c **** uint32_t P3; /* Multisynth config register P3 */ + 956 .loc 1 405 3 view .LVU248 + 406:Core/Src/si5351.c **** + 957 .loc 1 406 3 view .LVU249 + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 958 .loc 1 409 3 view .LVU250 + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 959 .loc 1 409 3 view .LVU251 + 960 0012 A24B ldr r3, .L54 + 961 .LVL111: + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 962 .loc 1 409 3 is_stmt 0 view .LVU252 + 963 0014 1B78 ldrb r3, [r3] + 964 0016 002B cmp r3, #0 + 965 0018 00D1 bne .LCB890 + 966 001a 3AE1 b .L43 @long jump + 967 .LCB890: + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 968 .loc 1 409 3 is_stmt 1 discriminator 2 view .LVU253 + 410:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 969 .loc 1 410 3 discriminator 2 view .LVU254 + 410:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 970 .loc 1 410 3 discriminator 2 view .LVU255 + 971 001c 0228 cmp r0, #2 + 972 001e 00D9 bls .LCB895 + 973 0020 39E1 b .L44 @long jump + 974 .LCB895: + 410:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 975 .loc 1 410 3 discriminator 2 view .LVU256 + 419:Core/Src/si5351.c **** { + 976 .loc 1 419 3 discriminator 2 view .LVU257 + 419:Core/Src/si5351.c **** { + 977 .loc 1 419 6 is_stmt 0 discriminator 2 view .LVU258 + 978 0022 0029 cmp r1, #0 + 979 0024 00D0 beq .LCB899 + 980 0026 87E0 b .L27 @long jump + 981 .LCB899: + 421:Core/Src/si5351.c **** } + 982 .loc 1 421 5 is_stmt 1 view .LVU259 + 421:Core/Src/si5351.c **** } + 983 .loc 1 421 5 view .LVU260 + 984 0028 9C4B ldr r3, .L54 + 985 002a 0122 movs r2, #1 + 986 .LVL112: + 421:Core/Src/si5351.c **** } + 987 .loc 1 421 5 is_stmt 0 view .LVU261 + 988 002c 1A74 strb r2, [r3, #16] + 421:Core/Src/si5351.c **** } + 989 .loc 1 421 5 is_stmt 1 view .LVU262 + 990 .L28: + 425:Core/Src/si5351.c **** } + 991 .loc 1 425 5 discriminator 2 view .LVU263 + 446:Core/Src/si5351.c **** { + 992 .loc 1 446 3 discriminator 2 view .LVU264 + 446:Core/Src/si5351.c **** { + 993 .loc 1 446 6 is_stmt 0 discriminator 2 view .LVU265 + 994 002e 002D cmp r5, #0 + ARM GAS /tmp/ccV7ORbp.s page 33 + + + 995 0030 00D0 beq .LCB912 + 996 0032 85E0 b .L29 @long jump + 997 .LCB912: + 449:Core/Src/si5351.c **** P2 = num; + 998 .loc 1 449 5 is_stmt 1 view .LVU266 + 449:Core/Src/si5351.c **** P2 = num; + 999 .loc 1 449 20 is_stmt 0 view .LVU267 + 1000 0034 9A49 ldr r1, .L54+4 + 1001 .LVL113: + 449:Core/Src/si5351.c **** P2 = num; + 1002 .loc 1 449 20 view .LVU268 + 1003 0036 5944 add r1, r1, fp + 449:Core/Src/si5351.c **** P2 = num; + 1004 .loc 1 449 8 view .LVU269 + 1005 0038 CB01 lsls r3, r1, #7 + 1006 003a 9946 mov r9, r3 + 1007 .LVL114: + 450:Core/Src/si5351.c **** P3 = denom; + 1008 .loc 1 450 5 is_stmt 1 view .LVU270 + 451:Core/Src/si5351.c **** } + 1009 .loc 1 451 5 view .LVU271 + 450:Core/Src/si5351.c **** P3 = denom; + 1010 .loc 1 450 8 is_stmt 0 view .LVU272 + 1011 003c 2F00 movs r7, r5 + 1012 .LVL115: + 1013 .L30: + 462:Core/Src/si5351.c **** switch (output) + 1014 .loc 1 462 3 is_stmt 1 view .LVU273 + 463:Core/Src/si5351.c **** { + 1015 .loc 1 463 3 view .LVU274 + 1016 003e 012C cmp r4, #1 + 1017 0040 00D1 bne .LCB941 + 1018 0042 B8E0 b .L45 @long jump + 1019 .LCB941: + 463:Core/Src/si5351.c **** { + 1020 .loc 1 463 3 is_stmt 0 view .LVU275 + 1021 0044 022C cmp r4, #2 + 1022 0046 00D1 bne .LCB945 + 1023 0048 B7E0 b .L46 @long jump + 1024 .LCB945: + 1025 004a 002C cmp r4, #0 + 1026 004c 00D1 bne .LCB947 + 1027 004e B0E0 b .L50 @long jump + 1028 .LCB947: + 1029 0050 0026 movs r6, #0 + 1030 .L31: + 1031 .LVL116: + 477:Core/Src/si5351.c **** si5351_write8( baseaddr+1, (P3 & 0x000000FF)); + 1032 .loc 1 477 3 is_stmt 1 view .LVU276 + 477:Core/Src/si5351.c **** si5351_write8( baseaddr+1, (P3 & 0x000000FF)); + 1033 .loc 1 477 48 is_stmt 0 view .LVU277 + 1034 0052 089B ldr r3, [sp, #32] + 1035 0054 190A lsrs r1, r3, #8 + 477:Core/Src/si5351.c **** si5351_write8( baseaddr+1, (P3 & 0x000000FF)); + 1036 .loc 1 477 3 view .LVU278 + 1037 0056 C9B2 uxtb r1, r1 + 1038 0058 3000 movs r0, r6 + ARM GAS /tmp/ccV7ORbp.s page 34 + + + 1039 005a FFF7FEFF bl si5351_write8 + 1040 .LVL117: + 478:Core/Src/si5351.c **** si5351_write8( baseaddr+2, (P1 & 0x00030000) >> 16); /* ToDo: Add DIVBY4 (>150MHz) and R0 support + 1041 .loc 1 478 3 is_stmt 1 view .LVU279 + 1042 005e 089B ldr r3, [sp, #32] + 1043 0060 D9B2 uxtb r1, r3 + 1044 0062 701C adds r0, r6, #1 + 1045 0064 FFF7FEFF bl si5351_write8 + 1046 .LVL118: + 479:Core/Src/si5351.c **** si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8); + 1047 .loc 1 479 3 view .LVU280 + 479:Core/Src/si5351.c **** si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8); + 1048 .loc 1 479 48 is_stmt 0 view .LVU281 + 1049 0068 4B46 mov r3, r9 + 1050 006a 1B0C lsrs r3, r3, #16 + 479:Core/Src/si5351.c **** si5351_write8( baseaddr+3, (P1 & 0x0000FF00) >> 8); + 1051 .loc 1 479 3 view .LVU282 + 1052 006c 0321 movs r1, #3 + 1053 006e 1940 ands r1, r3 + 1054 0070 B01C adds r0, r6, #2 + 1055 0072 FFF7FEFF bl si5351_write8 + 1056 .LVL119: + 480:Core/Src/si5351.c **** si5351_write8( baseaddr+4, (P1 & 0x000000FF)); + 1057 .loc 1 480 3 is_stmt 1 view .LVU283 + 480:Core/Src/si5351.c **** si5351_write8( baseaddr+4, (P1 & 0x000000FF)); + 1058 .loc 1 480 48 is_stmt 0 view .LVU284 + 1059 0076 4B46 mov r3, r9 + 1060 0078 190A lsrs r1, r3, #8 + 480:Core/Src/si5351.c **** si5351_write8( baseaddr+4, (P1 & 0x000000FF)); + 1061 .loc 1 480 3 view .LVU285 + 1062 007a C9B2 uxtb r1, r1 + 1063 007c F01C adds r0, r6, #3 + 1064 007e FFF7FEFF bl si5351_write8 + 1065 .LVL120: + 481:Core/Src/si5351.c **** si5351_write8( baseaddr+5, ((P3 & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16) ); + 1066 .loc 1 481 3 is_stmt 1 view .LVU286 + 1067 0082 4B46 mov r3, r9 + 1068 0084 D9B2 uxtb r1, r3 + 1069 0086 301D adds r0, r6, #4 + 1070 0088 FFF7FEFF bl si5351_write8 + 1071 .LVL121: + 482:Core/Src/si5351.c **** si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + 1072 .loc 1 482 3 view .LVU287 + 482:Core/Src/si5351.c **** si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + 1073 .loc 1 482 49 is_stmt 0 view .LVU288 + 1074 008c 089B ldr r3, [sp, #32] + 1075 008e 190B lsrs r1, r3, #12 + 1076 0090 0F23 movs r3, #15 + 1077 0092 9943 bics r1, r3 + 1078 0094 C9B2 uxtb r1, r1 + 482:Core/Src/si5351.c **** si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + 1079 .loc 1 482 77 view .LVU289 + 1080 0096 3A0C lsrs r2, r7, #16 + 1081 0098 1340 ands r3, r2 + 482:Core/Src/si5351.c **** si5351_write8( baseaddr+6, (P2 & 0x0000FF00) >> 8); + 1082 .loc 1 482 3 view .LVU290 + 1083 009a 1943 orrs r1, r3 + ARM GAS /tmp/ccV7ORbp.s page 35 + + + 1084 009c 701D adds r0, r6, #5 + 1085 009e FFF7FEFF bl si5351_write8 + 1086 .LVL122: + 483:Core/Src/si5351.c **** si5351_write8( baseaddr+7, (P2 & 0x000000FF)); + 1087 .loc 1 483 3 is_stmt 1 view .LVU291 + 483:Core/Src/si5351.c **** si5351_write8( baseaddr+7, (P2 & 0x000000FF)); + 1088 .loc 1 483 48 is_stmt 0 view .LVU292 + 1089 00a2 390A lsrs r1, r7, #8 + 483:Core/Src/si5351.c **** si5351_write8( baseaddr+7, (P2 & 0x000000FF)); + 1090 .loc 1 483 3 view .LVU293 + 1091 00a4 C9B2 uxtb r1, r1 + 1092 00a6 B01D adds r0, r6, #6 + 1093 00a8 FFF7FEFF bl si5351_write8 + 1094 .LVL123: + 484:Core/Src/si5351.c **** + 1095 .loc 1 484 3 is_stmt 1 view .LVU294 + 1096 00ac F9B2 uxtb r1, r7 + 1097 00ae F01D adds r0, r6, #7 + 1098 00b0 FFF7FEFF bl si5351_write8 + 1099 .LVL124: + 487:Core/Src/si5351.c **** { + 1100 .loc 1 487 3 view .LVU295 + 487:Core/Src/si5351.c **** { + 1101 .loc 1 487 6 is_stmt 0 view .LVU296 + 1102 00b4 5346 mov r3, r10 + 1103 00b6 002B cmp r3, #0 + 1104 00b8 00D0 beq .LCB1014 + 1105 00ba 9BE0 b .L32 @long jump + 1106 .LCB1014: + 1107 .LBB23: + 489:Core/Src/si5351.c **** switch (output) + 1108 .loc 1 489 11 is_stmt 1 view .LVU297 + 489:Core/Src/si5351.c **** switch (output) + 1109 .loc 1 489 38 is_stmt 0 view .LVU298 + 1110 00bc 774B ldr r3, .L54 + 1111 00be 5869 ldr r0, [r3, #20] + 489:Core/Src/si5351.c **** switch (output) + 1112 .loc 1 489 49 view .LVU299 + 1113 00c0 FFF7FEFF bl __aeabi_ui2f + 1114 .LVL125: + 1115 00c4 061C adds r6, r0, #0 + 1116 .LVL126: + 489:Core/Src/si5351.c **** switch (output) + 1117 .loc 1 489 60 view .LVU300 + 1118 00c6 2800 movs r0, r5 + 1119 00c8 FFF7FEFF bl __aeabi_ui2f + 1120 .LVL127: + 1121 00cc 071C adds r7, r0, #0 + 1122 .LVL128: + 489:Core/Src/si5351.c **** switch (output) + 1123 .loc 1 489 73 view .LVU301 + 1124 00ce 0898 ldr r0, [sp, #32] + 1125 00d0 FFF7FEFF bl __aeabi_ui2f + 1126 .LVL129: + 1127 00d4 011C adds r1, r0, #0 + 489:Core/Src/si5351.c **** switch (output) + 1128 .loc 1 489 71 view .LVU302 + ARM GAS /tmp/ccV7ORbp.s page 36 + + + 1129 00d6 381C adds r0, r7, #0 + 1130 00d8 FFF7FEFF bl __aeabi_fdiv + 1131 .LVL130: + 1132 00dc 071C adds r7, r0, #0 + 489:Core/Src/si5351.c **** switch (output) + 1133 .loc 1 489 56 view .LVU303 + 1134 00de 5846 mov r0, fp + 1135 00e0 FFF7FEFF bl __aeabi_ui2f + 1136 .LVL131: + 1137 00e4 391C adds r1, r7, #0 + 1138 00e6 FFF7FEFF bl __aeabi_fadd + 1139 .LVL132: + 1140 00ea 011C adds r1, r0, #0 + 489:Core/Src/si5351.c **** switch (output) + 1141 .loc 1 489 17 view .LVU304 + 1142 00ec 301C adds r0, r6, #0 + 1143 00ee FFF7FEFF bl __aeabi_fdiv + 1144 .LVL133: + 490:Core/Src/si5351.c **** { + 1145 .loc 1 490 11 is_stmt 1 view .LVU305 + 1146 00f2 012C cmp r4, #1 + 1147 00f4 6CD0 beq .L33 + 1148 00f6 022C cmp r4, #2 + 1149 00f8 00D1 bne .LCB1044 + 1150 00fa 72E0 b .L34 @long jump + 1151 .LCB1044: + 1152 00fc 002C cmp r4, #0 + 1153 00fe 5ED0 beq .L51 + 1154 .LVL134: + 1155 .L35: + 490:Core/Src/si5351.c **** { + 1156 .loc 1 490 11 is_stmt 0 view .LVU306 + 1157 .LBE23: + 523:Core/Src/si5351.c **** // controfase + 1158 .loc 1 523 3 is_stmt 1 view .LVU307 + 525:Core/Src/si5351.c **** + 1159 .loc 1 525 3 view .LVU308 + 525:Core/Src/si5351.c **** + 1160 .loc 1 525 5 is_stmt 0 view .LVU309 + 1161 0100 012C cmp r4, #1 + 1162 0102 00D1 bne .LCB1056 + 1163 0104 B3E0 b .L48 @long jump + 1164 .LCB1056: + 523:Core/Src/si5351.c **** // controfase + 1165 .loc 1 523 11 view .LVU310 + 1166 0106 0F21 movs r1, #15 + 1167 .L38: + 1168 .LVL135: + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1169 .loc 1 527 3 is_stmt 1 view .LVU311 + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1170 .loc 1 527 6 is_stmt 0 view .LVU312 + 1171 0108 5346 mov r3, r10 + 1172 010a 012B cmp r3, #1 + 1173 010c 00D1 bne .LCB1064 + 1174 010e B0E0 b .L52 @long jump + 1175 .LCB1064: + ARM GAS /tmp/ccV7ORbp.s page 37 + + + 1176 .L39: + 528:Core/Src/si5351.c **** switch (output) + 1177 .loc 1 528 3 is_stmt 1 view .LVU313 + 528:Core/Src/si5351.c **** switch (output) + 1178 .loc 1 528 6 is_stmt 0 view .LVU314 + 1179 0110 002D cmp r5, #0 + 1180 0112 02D1 bne .L40 + 528:Core/Src/si5351.c **** switch (output) + 1181 .loc 1 528 17 is_stmt 1 discriminator 1 view .LVU315 + 528:Core/Src/si5351.c **** switch (output) + 1182 .loc 1 528 31 is_stmt 0 discriminator 1 view .LVU316 + 1183 0114 4023 movs r3, #64 + 1184 0116 1943 orrs r1, r3 + 1185 .LVL136: + 528:Core/Src/si5351.c **** switch (output) + 1186 .loc 1 528 31 discriminator 1 view .LVU317 + 1187 0118 C9B2 uxtb r1, r1 + 1188 .LVL137: + 1189 .L40: + 529:Core/Src/si5351.c **** { + 1190 .loc 1 529 3 is_stmt 1 view .LVU318 + 1191 011a 012C cmp r4, #1 + 1192 011c 00D1 bne .LCB1084 + 1193 011e B0E0 b .L41 @long jump + 1194 .LCB1084: + 529:Core/Src/si5351.c **** { + 1195 .loc 1 529 3 is_stmt 0 view .LVU319 + 1196 0120 022C cmp r4, #2 + 1197 0122 00D1 bne .LCB1087 + 1198 0124 B1E0 b .L42 @long jump + 1199 .LCB1087: + 1200 0126 002C cmp r4, #0 + 1201 0128 00D1 bne .LCB1089 + 1202 012a A6E0 b .L53 @long jump + 1203 .LCB1089: + 1204 012c 0020 movs r0, #0 + 1205 .LVL138: + 1206 .L26: + 543:Core/Src/si5351.c **** + 1207 .loc 1 543 1 view .LVU320 + 1208 @ sp needed + 1209 .LVL139: + 1210 .LVL140: + 543:Core/Src/si5351.c **** + 1211 .loc 1 543 1 view .LVU321 + 1212 012e E0BC pop {r5, r6, r7} + 1213 0130 BB46 mov fp, r7 + 1214 0132 B246 mov r10, r6 + 1215 0134 A946 mov r9, r5 + 1216 0136 F0BD pop {r4, r5, r6, r7, pc} + 1217 .LVL141: + 1218 .L27: + 425:Core/Src/si5351.c **** } + 1219 .loc 1 425 5 is_stmt 1 view .LVU322 + 425:Core/Src/si5351.c **** } + 1220 .loc 1 425 5 view .LVU323 + 1221 0138 584B ldr r3, .L54 + ARM GAS /tmp/ccV7ORbp.s page 38 + + + 1222 013a 0122 movs r2, #1 + 1223 .LVL142: + 425:Core/Src/si5351.c **** } + 1224 .loc 1 425 5 is_stmt 0 view .LVU324 + 1225 013c 1A76 strb r2, [r3, #24] + 1226 013e 76E7 b .L28 + 1227 .L29: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1228 .loc 1 456 5 is_stmt 1 view .LVU325 + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1229 .loc 1 456 46 is_stmt 0 view .LVU326 + 1230 0140 2800 movs r0, r5 + 1231 .LVL143: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1232 .loc 1 456 46 view .LVU327 + 1233 0142 FFF7FEFF bl __aeabi_ui2f + 1234 .LVL144: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1235 .loc 1 456 46 view .LVU328 + 1236 0146 061C adds r6, r0, #0 + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1237 .loc 1 456 57 view .LVU329 + 1238 0148 0898 ldr r0, [sp, #32] + 1239 014a FFF7FEFF bl __aeabi_ui2f + 1240 .LVL145: + 1241 014e 011C adds r1, r0, #0 + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1242 .loc 1 456 56 view .LVU330 + 1243 0150 301C adds r0, r6, #0 + 1244 0152 FFF7FEFF bl __aeabi_fdiv + 1245 .LVL146: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1246 .loc 1 456 43 view .LVU331 + 1247 0156 8621 movs r1, #134 + 1248 0158 C905 lsls r1, r1, #23 + 1249 015a FFF7FEFF bl __aeabi_fmul + 1250 .LVL147: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1251 .loc 1 456 33 view .LVU332 + 1252 015e FFF7FEFF bl __aeabi_f2d + 1253 .LVL148: + 1254 0162 FFF7FEFF bl floor + 1255 .LVL149: + 1256 0166 0600 movs r6, r0 + 1257 0168 0F00 movs r7, r1 + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1258 .loc 1 456 31 view .LVU333 + 1259 016a 5B46 mov r3, fp + 1260 016c D801 lsls r0, r3, #7 + 1261 016e FFF7FEFF bl __aeabi_ui2d + 1262 .LVL150: + 1263 0172 3200 movs r2, r6 + 1264 0174 3B00 movs r3, r7 + 1265 0176 FFF7FEFF bl __aeabi_dadd + 1266 .LVL151: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1267 .loc 1 456 72 view .LVU334 + ARM GAS /tmp/ccV7ORbp.s page 39 + + + 1268 017a 0022 movs r2, #0 + 1269 017c 8123 movs r3, #129 + 1270 017e DB05 lsls r3, r3, #23 + 1271 0180 FFF7FEFF bl __aeabi_dsub + 1272 .LVL152: + 456:Core/Src/si5351.c **** P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom))); + 1273 .loc 1 456 8 view .LVU335 + 1274 0184 FFF7FEFF bl __aeabi_d2uiz + 1275 .LVL153: + 1276 0188 8146 mov r9, r0 + 1277 .LVL154: + 457:Core/Src/si5351.c **** P3 = denom; + 1278 .loc 1 457 5 is_stmt 1 view .LVU336 + 457:Core/Src/si5351.c **** P3 = denom; + 1279 .loc 1 457 39 is_stmt 0 view .LVU337 + 1280 018a 0898 ldr r0, [sp, #32] + 1281 .LVL155: + 457:Core/Src/si5351.c **** P3 = denom; + 1282 .loc 1 457 39 view .LVU338 + 1283 018c FFF7FEFF bl __aeabi_ui2d + 1284 .LVL156: + 1285 0190 3200 movs r2, r6 + 1286 0192 3B00 movs r3, r7 + 1287 0194 FFF7FEFF bl __aeabi_dmul + 1288 .LVL157: + 1289 0198 0600 movs r6, r0 + 1290 019a 0F00 movs r7, r1 + 457:Core/Src/si5351.c **** P3 = denom; + 1291 .loc 1 457 31 view .LVU339 + 1292 019c E801 lsls r0, r5, #7 + 1293 019e FFF7FEFF bl __aeabi_ui2d + 1294 .LVL158: + 1295 01a2 3200 movs r2, r6 + 1296 01a4 3B00 movs r3, r7 + 1297 01a6 FFF7FEFF bl __aeabi_dsub + 1298 .LVL159: + 457:Core/Src/si5351.c **** P3 = denom; + 1299 .loc 1 457 8 view .LVU340 + 1300 01aa FFF7FEFF bl __aeabi_d2uiz + 1301 .LVL160: + 1302 01ae 0700 movs r7, r0 + 1303 .LVL161: + 458:Core/Src/si5351.c **** } + 1304 .loc 1 458 5 is_stmt 1 view .LVU341 + 458:Core/Src/si5351.c **** } + 1305 .loc 1 458 5 is_stmt 0 view .LVU342 + 1306 01b0 45E7 b .L30 + 1307 .LVL162: + 1308 .L50: + 466:Core/Src/si5351.c **** break; + 1309 .loc 1 466 16 view .LVU343 + 1310 01b2 2A26 movs r6, #42 + 1311 01b4 4DE7 b .L31 + 1312 .L45: + 469:Core/Src/si5351.c **** break; + 1313 .loc 1 469 16 view .LVU344 + 1314 01b6 3226 movs r6, #50 + ARM GAS /tmp/ccV7ORbp.s page 40 + + + 1315 01b8 4BE7 b .L31 + 1316 .L46: + 472:Core/Src/si5351.c **** break; + 1317 .loc 1 472 16 view .LVU345 + 1318 01ba 3A26 movs r6, #58 + 1319 01bc 49E7 b .L31 + 1320 .LVL163: + 1321 .L51: + 1322 .LBB24: + 493:Core/Src/si5351.c **** break; + 1323 .loc 1 493 12 is_stmt 1 view .LVU346 + 493:Core/Src/si5351.c **** break; + 1324 .loc 1 493 48 is_stmt 0 view .LVU347 + 1325 01be FFF7FEFF bl __aeabi_f2d + 1326 .LVL164: + 493:Core/Src/si5351.c **** break; + 1327 .loc 1 493 48 view .LVU348 + 1328 01c2 FFF7FEFF bl floor + 1329 .LVL165: + 493:Core/Src/si5351.c **** break; + 1330 .loc 1 493 38 view .LVU349 + 1331 01c6 FFF7FEFF bl __aeabi_d2uiz + 1332 .LVL166: + 493:Core/Src/si5351.c **** break; + 1333 .loc 1 493 36 view .LVU350 + 1334 01ca 344B ldr r3, .L54 + 1335 01cc 1862 str r0, [r3, #32] + 494:Core/Src/si5351.c **** case 1: + 1336 .loc 1 494 12 is_stmt 1 view .LVU351 + 1337 01ce 97E7 b .L35 + 1338 .LVL167: + 1339 .L33: + 496:Core/Src/si5351.c **** break; + 1340 .loc 1 496 12 view .LVU352 + 496:Core/Src/si5351.c **** break; + 1341 .loc 1 496 48 is_stmt 0 view .LVU353 + 1342 01d0 FFF7FEFF bl __aeabi_f2d + 1343 .LVL168: + 496:Core/Src/si5351.c **** break; + 1344 .loc 1 496 48 view .LVU354 + 1345 01d4 FFF7FEFF bl floor + 1346 .LVL169: + 496:Core/Src/si5351.c **** break; + 1347 .loc 1 496 38 view .LVU355 + 1348 01d8 FFF7FEFF bl __aeabi_d2uiz + 1349 .LVL170: + 496:Core/Src/si5351.c **** break; + 1350 .loc 1 496 36 view .LVU356 + 1351 01dc 2F4B ldr r3, .L54 + 1352 01de 5862 str r0, [r3, #36] + 497:Core/Src/si5351.c **** case 2: + 1353 .loc 1 497 12 is_stmt 1 view .LVU357 + 1354 01e0 8EE7 b .L35 + 1355 .LVL171: + 1356 .L34: + 499:Core/Src/si5351.c **** break; + 1357 .loc 1 499 12 view .LVU358 + ARM GAS /tmp/ccV7ORbp.s page 41 + + + 499:Core/Src/si5351.c **** break; + 1358 .loc 1 499 48 is_stmt 0 view .LVU359 + 1359 01e2 FFF7FEFF bl __aeabi_f2d + 1360 .LVL172: + 499:Core/Src/si5351.c **** break; + 1361 .loc 1 499 48 view .LVU360 + 1362 01e6 FFF7FEFF bl floor + 1363 .LVL173: + 499:Core/Src/si5351.c **** break; + 1364 .loc 1 499 38 view .LVU361 + 1365 01ea FFF7FEFF bl __aeabi_d2uiz + 1366 .LVL174: + 499:Core/Src/si5351.c **** break; + 1367 .loc 1 499 36 view .LVU362 + 1368 01ee 2B4B ldr r3, .L54 + 1369 01f0 9862 str r0, [r3, #40] + 500:Core/Src/si5351.c **** } + 1370 .loc 1 500 12 is_stmt 1 view .LVU363 + 1371 01f2 85E7 b .L35 + 1372 .LVL175: + 1373 .L32: + 500:Core/Src/si5351.c **** } + 1374 .loc 1 500 12 is_stmt 0 view .LVU364 + 1375 .LBE24: + 1376 .LBB25: + 505:Core/Src/si5351.c **** switch (output) + 1377 .loc 1 505 11 is_stmt 1 view .LVU365 + 505:Core/Src/si5351.c **** switch (output) + 1378 .loc 1 505 38 is_stmt 0 view .LVU366 + 1379 01f4 294B ldr r3, .L54 + 1380 01f6 D869 ldr r0, [r3, #28] + 505:Core/Src/si5351.c **** switch (output) + 1381 .loc 1 505 49 view .LVU367 + 1382 01f8 FFF7FEFF bl __aeabi_ui2f + 1383 .LVL176: + 1384 01fc 061C adds r6, r0, #0 + 1385 .LVL177: + 505:Core/Src/si5351.c **** switch (output) + 1386 .loc 1 505 60 view .LVU368 + 1387 01fe 2800 movs r0, r5 + 1388 0200 FFF7FEFF bl __aeabi_ui2f + 1389 .LVL178: + 1390 0204 071C adds r7, r0, #0 + 1391 .LVL179: + 505:Core/Src/si5351.c **** switch (output) + 1392 .loc 1 505 73 view .LVU369 + 1393 0206 0898 ldr r0, [sp, #32] + 1394 0208 FFF7FEFF bl __aeabi_ui2f + 1395 .LVL180: + 1396 020c 011C adds r1, r0, #0 + 505:Core/Src/si5351.c **** switch (output) + 1397 .loc 1 505 71 view .LVU370 + 1398 020e 381C adds r0, r7, #0 + 1399 0210 FFF7FEFF bl __aeabi_fdiv + 1400 .LVL181: + 1401 0214 071C adds r7, r0, #0 + 505:Core/Src/si5351.c **** switch (output) + ARM GAS /tmp/ccV7ORbp.s page 42 + + + 1402 .loc 1 505 56 view .LVU371 + 1403 0216 5846 mov r0, fp + 1404 0218 FFF7FEFF bl __aeabi_ui2f + 1405 .LVL182: + 1406 021c 391C adds r1, r7, #0 + 1407 021e FFF7FEFF bl __aeabi_fadd + 1408 .LVL183: + 1409 0222 011C adds r1, r0, #0 + 505:Core/Src/si5351.c **** switch (output) + 1410 .loc 1 505 17 view .LVU372 + 1411 0224 301C adds r0, r6, #0 + 1412 0226 FFF7FEFF bl __aeabi_fdiv + 1413 .LVL184: + 506:Core/Src/si5351.c **** { + 1414 .loc 1 506 11 is_stmt 1 view .LVU373 + 1415 022a 012C cmp r4, #1 + 1416 022c 0DD0 beq .L36 + 1417 022e 022C cmp r4, #2 + 1418 0230 14D0 beq .L37 + 1419 0232 002C cmp r4, #0 + 1420 0234 00D0 beq .LCB1289 + 1421 0236 63E7 b .L35 @long jump + 1422 .LCB1289: + 509:Core/Src/si5351.c **** break; + 1423 .loc 1 509 12 view .LVU374 + 509:Core/Src/si5351.c **** break; + 1424 .loc 1 509 48 is_stmt 0 view .LVU375 + 1425 0238 FFF7FEFF bl __aeabi_f2d + 1426 .LVL185: + 509:Core/Src/si5351.c **** break; + 1427 .loc 1 509 48 view .LVU376 + 1428 023c FFF7FEFF bl floor + 1429 .LVL186: + 509:Core/Src/si5351.c **** break; + 1430 .loc 1 509 38 view .LVU377 + 1431 0240 FFF7FEFF bl __aeabi_d2uiz + 1432 .LVL187: + 509:Core/Src/si5351.c **** break; + 1433 .loc 1 509 36 view .LVU378 + 1434 0244 154B ldr r3, .L54 + 1435 0246 1862 str r0, [r3, #32] + 510:Core/Src/si5351.c **** case 1: + 1436 .loc 1 510 12 is_stmt 1 view .LVU379 + 1437 0248 5AE7 b .L35 + 1438 .LVL188: + 1439 .L36: + 512:Core/Src/si5351.c **** break; + 1440 .loc 1 512 12 view .LVU380 + 512:Core/Src/si5351.c **** break; + 1441 .loc 1 512 48 is_stmt 0 view .LVU381 + 1442 024a FFF7FEFF bl __aeabi_f2d + 1443 .LVL189: + 512:Core/Src/si5351.c **** break; + 1444 .loc 1 512 48 view .LVU382 + 1445 024e FFF7FEFF bl floor + 1446 .LVL190: + 512:Core/Src/si5351.c **** break; + ARM GAS /tmp/ccV7ORbp.s page 43 + + + 1447 .loc 1 512 38 view .LVU383 + 1448 0252 FFF7FEFF bl __aeabi_d2uiz + 1449 .LVL191: + 512:Core/Src/si5351.c **** break; + 1450 .loc 1 512 36 view .LVU384 + 1451 0256 114B ldr r3, .L54 + 1452 0258 5862 str r0, [r3, #36] + 513:Core/Src/si5351.c **** case 2: + 1453 .loc 1 513 12 is_stmt 1 view .LVU385 + 1454 025a 51E7 b .L35 + 1455 .LVL192: + 1456 .L37: + 515:Core/Src/si5351.c **** break; + 1457 .loc 1 515 12 view .LVU386 + 515:Core/Src/si5351.c **** break; + 1458 .loc 1 515 48 is_stmt 0 view .LVU387 + 1459 025c FFF7FEFF bl __aeabi_f2d + 1460 .LVL193: + 515:Core/Src/si5351.c **** break; + 1461 .loc 1 515 48 view .LVU388 + 1462 0260 FFF7FEFF bl floor + 1463 .LVL194: + 515:Core/Src/si5351.c **** break; + 1464 .loc 1 515 38 view .LVU389 + 1465 0264 FFF7FEFF bl __aeabi_d2uiz + 1466 .LVL195: + 515:Core/Src/si5351.c **** break; + 1467 .loc 1 515 36 view .LVU390 + 1468 0268 0C4B ldr r3, .L54 + 1469 026a 9862 str r0, [r3, #40] + 516:Core/Src/si5351.c **** } + 1470 .loc 1 516 12 is_stmt 1 view .LVU391 + 1471 026c 48E7 b .L35 + 1472 .LVL196: + 1473 .L48: + 516:Core/Src/si5351.c **** } + 1474 .loc 1 516 12 is_stmt 0 view .LVU392 + 1475 .LBE25: + 525:Core/Src/si5351.c **** + 1476 .loc 1 525 33 view .LVU393 + 1477 026e 1F21 movs r1, #31 + 1478 0270 4AE7 b .L38 + 1479 .LVL197: + 1480 .L52: + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1481 .loc 1 527 34 is_stmt 1 discriminator 1 view .LVU394 + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1482 .loc 1 527 48 is_stmt 0 discriminator 1 view .LVU395 + 1483 0272 2023 movs r3, #32 + 1484 0274 1943 orrs r1, r3 + 1485 .LVL198: + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1486 .loc 1 527 48 discriminator 1 view .LVU396 + 1487 0276 C9B2 uxtb r1, r1 + 1488 .LVL199: + 527:Core/Src/si5351.c **** if (num == 0) clkControlReg |= (1 << 6); /* Integer mode */ + 1489 .loc 1 527 48 discriminator 1 view .LVU397 + ARM GAS /tmp/ccV7ORbp.s page 44 + + + 1490 0278 4AE7 b .L39 + 1491 .L53: + 532:Core/Src/si5351.c **** break; + 1492 .loc 1 532 7 is_stmt 1 view .LVU398 + 1493 .LBB26: + 532:Core/Src/si5351.c **** break; + 1494 .loc 1 532 7 view .LVU399 + 1495 027a 1020 movs r0, #16 + 1496 027c FFF7FEFF bl si5351_write8 + 1497 .LVL200: + 532:Core/Src/si5351.c **** break; + 1498 .loc 1 532 7 view .LVU400 + 1499 0280 55E7 b .L26 + 1500 .LVL201: + 1501 .L41: + 532:Core/Src/si5351.c **** break; + 1502 .loc 1 532 7 is_stmt 0 view .LVU401 + 1503 .LBE26: + 535:Core/Src/si5351.c **** break; + 1504 .loc 1 535 7 is_stmt 1 view .LVU402 + 1505 .LBB27: + 535:Core/Src/si5351.c **** break; + 1506 .loc 1 535 7 view .LVU403 + 1507 0282 1120 movs r0, #17 + 1508 0284 FFF7FEFF bl si5351_write8 + 1509 .LVL202: + 535:Core/Src/si5351.c **** break; + 1510 .loc 1 535 7 view .LVU404 + 1511 0288 51E7 b .L26 + 1512 .LVL203: + 1513 .L42: + 535:Core/Src/si5351.c **** break; + 1514 .loc 1 535 7 is_stmt 0 view .LVU405 + 1515 .LBE27: + 538:Core/Src/si5351.c **** break; + 1516 .loc 1 538 7 is_stmt 1 view .LVU406 + 1517 .LBB28: + 538:Core/Src/si5351.c **** break; + 1518 .loc 1 538 7 view .LVU407 + 1519 028a 1220 movs r0, #18 + 1520 028c FFF7FEFF bl si5351_write8 + 1521 .LVL204: + 538:Core/Src/si5351.c **** break; + 1522 .loc 1 538 7 view .LVU408 + 1523 0290 4DE7 b .L26 + 1524 .LVL205: + 1525 .L43: + 538:Core/Src/si5351.c **** break; + 1526 .loc 1 538 7 is_stmt 0 view .LVU409 + 1527 .LBE28: + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 1528 .loc 1 409 3 view .LVU410 + 1529 0292 0520 movs r0, #5 + 1530 .LVL206: + 409:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 1531 .loc 1 409 3 view .LVU411 + 1532 0294 4BE7 b .L26 + ARM GAS /tmp/ccV7ORbp.s page 45 + + + 1533 .LVL207: + 1534 .L44: + 410:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 1535 .loc 1 410 3 view .LVU412 + 1536 0296 0420 movs r0, #4 + 1537 .LVL208: + 410:Core/Src/si5351.c **** //ASSERT( div > 3, ERROR_INVALIDPARAMETER); /* Divider integer value */ + 1538 .loc 1 410 3 view .LVU413 + 1539 0298 49E7 b .L26 + 1540 .L55: + 1541 029a C046 .align 2 + 1542 .L54: + 1543 029c 00000000 .word .LANCHOR0 + 1544 02a0 FCFFFF01 .word 33554428 + 1545 .cfi_endproc + 1546 .LFE302: + 1548 .section .text.si5351_setupMultisynthInt,"ax",%progbits + 1549 .align 1 + 1550 .global si5351_setupMultisynthInt + 1551 .syntax unified + 1552 .code 16 + 1553 .thumb_func + 1554 .fpu softvfp + 1556 si5351_setupMultisynthInt: + 1557 .LVL209: + 1558 .LFB300: + 265:Core/Src/si5351.c **** return si5351_setupMultisynth(output, pllSource, div, 0, 1); + 1559 .loc 1 265 1 is_stmt 1 view -0 + 1560 .cfi_startproc + 1561 @ args = 0, pretend = 0, frame = 0 + 1562 @ frame_needed = 0, uses_anonymous_args = 0 + 265:Core/Src/si5351.c **** return si5351_setupMultisynth(output, pllSource, div, 0, 1); + 1563 .loc 1 265 1 is_stmt 0 view .LVU415 + 1564 0000 00B5 push {lr} + 1565 .LCFI9: + 1566 .cfi_def_cfa_offset 4 + 1567 .cfi_offset 14, -4 + 1568 0002 83B0 sub sp, sp, #12 + 1569 .LCFI10: + 1570 .cfi_def_cfa_offset 16 + 266:Core/Src/si5351.c **** } + 1571 .loc 1 266 3 is_stmt 1 view .LVU416 + 266:Core/Src/si5351.c **** } + 1572 .loc 1 266 10 is_stmt 0 view .LVU417 + 1573 0004 0123 movs r3, #1 + 1574 0006 0093 str r3, [sp] + 1575 0008 0023 movs r3, #0 + 1576 000a FFF7FEFF bl si5351_setupMultisynth + 1577 .LVL210: + 267:Core/Src/si5351.c **** + 1578 .loc 1 267 1 view .LVU418 + 1579 000e 03B0 add sp, sp, #12 + 1580 @ sp needed + 1581 0010 00BD pop {pc} + 1582 .cfi_endproc + 1583 .LFE300: + 1585 .section .text.si5351_enableOutputs,"ax",%progbits + ARM GAS /tmp/ccV7ORbp.s page 46 + + + 1586 .align 1 + 1587 .global si5351_enableOutputs + 1588 .syntax unified + 1589 .code 16 + 1590 .thumb_func + 1591 .fpu softvfp + 1593 si5351_enableOutputs: + 1594 .LVL211: + 1595 .LFB303: + 551:Core/Src/si5351.c **** /* Make sure we've called init first */ + 1596 .loc 1 551 1 is_stmt 1 view -0 + 1597 .cfi_startproc + 1598 @ args = 0, pretend = 0, frame = 0 + 1599 @ frame_needed = 0, uses_anonymous_args = 0 + 551:Core/Src/si5351.c **** /* Make sure we've called init first */ + 1600 .loc 1 551 1 is_stmt 0 view .LVU420 + 1601 0000 10B5 push {r4, lr} + 1602 .LCFI11: + 1603 .cfi_def_cfa_offset 8 + 1604 .cfi_offset 4, -8 + 1605 .cfi_offset 14, -4 + 553:Core/Src/si5351.c **** + 1606 .loc 1 553 3 is_stmt 1 view .LVU421 + 553:Core/Src/si5351.c **** + 1607 .loc 1 553 3 view .LVU422 + 1608 0002 074B ldr r3, .L62 + 1609 0004 1B78 ldrb r3, [r3] + 1610 0006 002B cmp r3, #0 + 1611 0008 08D0 beq .L60 + 553:Core/Src/si5351.c **** + 1612 .loc 1 553 3 discriminator 2 view .LVU423 + 556:Core/Src/si5351.c **** + 1613 .loc 1 556 3 discriminator 2 view .LVU424 + 1614 .LBB29: + 556:Core/Src/si5351.c **** + 1615 .loc 1 556 3 discriminator 2 view .LVU425 + 1616 000a 0028 cmp r0, #0 + 1617 000c 04D0 beq .L61 + 556:Core/Src/si5351.c **** + 1618 .loc 1 556 3 is_stmt 0 view .LVU426 + 1619 000e 0021 movs r1, #0 + 1620 .L59: + 556:Core/Src/si5351.c **** + 1621 .loc 1 556 3 discriminator 4 view .LVU427 + 1622 0010 0320 movs r0, #3 + 1623 .LVL212: + 556:Core/Src/si5351.c **** + 1624 .loc 1 556 3 discriminator 4 view .LVU428 + 1625 0012 FFF7FEFF bl si5351_write8 + 1626 .LVL213: + 556:Core/Src/si5351.c **** + 1627 .loc 1 556 3 is_stmt 1 discriminator 4 view .LVU429 + 1628 .L58: + 556:Core/Src/si5351.c **** + 1629 .loc 1 556 3 is_stmt 0 discriminator 4 view .LVU430 + 1630 .LBE29: + 559:Core/Src/si5351.c **** + ARM GAS /tmp/ccV7ORbp.s page 47 + + + 1631 .loc 1 559 1 view .LVU431 + 1632 @ sp needed + 1633 0016 10BD pop {r4, pc} + 1634 .LVL214: + 1635 .L61: + 1636 .LBB30: + 556:Core/Src/si5351.c **** + 1637 .loc 1 556 3 view .LVU432 + 1638 0018 FF21 movs r1, #255 + 1639 001a F9E7 b .L59 + 1640 .L60: + 1641 .LBE30: + 553:Core/Src/si5351.c **** + 1642 .loc 1 553 3 view .LVU433 + 1643 001c 0520 movs r0, #5 + 1644 .LVL215: + 553:Core/Src/si5351.c **** + 1645 .loc 1 553 3 view .LVU434 + 1646 001e FAE7 b .L58 + 1647 .L63: + 1648 .align 2 + 1649 .L62: + 1650 0020 00000000 .word .LANCHOR0 + 1651 .cfi_endproc + 1652 .LFE303: + 1654 .section .text.si5351_read8,"ax",%progbits + 1655 .align 1 + 1656 .global si5351_read8 + 1657 .syntax unified + 1658 .code 16 + 1659 .thumb_func + 1660 .fpu softvfp + 1662 si5351_read8: + 1663 .LVL216: + 1664 .LFB305: + 586:Core/Src/si5351.c **** + 587:Core/Src/si5351.c **** /**************************************************************************/ + 588:Core/Src/si5351.c **** /*! + 589:Core/Src/si5351.c **** @brief Reads an 8 bit value over I2C + 590:Core/Src/si5351.c **** */ + 591:Core/Src/si5351.c **** /**************************************************************************/ + 592:Core/Src/si5351.c **** err_t si5351_read8(uint8_t reg, uint8_t *value) + 593:Core/Src/si5351.c **** { + 1665 .loc 1 593 1 is_stmt 1 view -0 + 1666 .cfi_startproc + 1667 @ args = 0, pretend = 0, frame = 8 + 1668 @ frame_needed = 0, uses_anonymous_args = 0 + 1669 .loc 1 593 1 is_stmt 0 view .LVU436 + 1670 0000 10B5 push {r4, lr} + 1671 .LCFI12: + 1672 .cfi_def_cfa_offset 8 + 1673 .cfi_offset 4, -8 + 1674 .cfi_offset 14, -4 + 1675 0002 86B0 sub sp, sp, #24 + 1676 .LCFI13: + 1677 .cfi_def_cfa_offset 32 + 1678 0004 0400 movs r4, r0 + ARM GAS /tmp/ccV7ORbp.s page 48 + + + 1679 0006 0591 str r1, [sp, #20] + 594:Core/Src/si5351.c **** HAL_StatusTypeDef status = HAL_OK; + 1680 .loc 1 594 2 is_stmt 1 view .LVU437 + 1681 .LVL217: + 595:Core/Src/si5351.c **** + 596:Core/Src/si5351.c **** while (HAL_I2C_IsDeviceReady(&hi2c2, (uint16_t)(SI5351_ADDRESS<<1), 3, 100) != HAL_OK) { } + 1682 .loc 1 596 2 view .LVU438 + 1683 .L65: + 1684 .loc 1 596 91 discriminator 1 view .LVU439 + 1685 .loc 1 596 8 discriminator 1 view .LVU440 + 1686 .loc 1 596 9 is_stmt 0 discriminator 1 view .LVU441 + 1687 0008 6423 movs r3, #100 + 1688 000a 0322 movs r2, #3 + 1689 000c C021 movs r1, #192 + 1690 000e 0A48 ldr r0, .L66 + 1691 0010 FFF7FEFF bl HAL_I2C_IsDeviceReady + 1692 .LVL218: + 1693 .loc 1 596 8 discriminator 1 view .LVU442 + 1694 0014 0028 cmp r0, #0 + 1695 0016 F7D1 bne .L65 + 597:Core/Src/si5351.c **** + 598:Core/Src/si5351.c **** status = HAL_I2C_Mem_Read(&hi2c2, // i2c handle + 1696 .loc 1 598 5 is_stmt 1 view .LVU443 + 1697 .loc 1 598 14 is_stmt 0 view .LVU444 + 1698 0018 A2B2 uxth r2, r4 + 1699 001a 6423 movs r3, #100 + 1700 001c 0293 str r3, [sp, #8] + 1701 001e 633B subs r3, r3, #99 + 1702 0020 0193 str r3, [sp, #4] + 1703 0022 05AB add r3, sp, #20 + 1704 0024 0093 str r3, [sp] + 1705 0026 0123 movs r3, #1 + 1706 0028 C021 movs r1, #192 + 1707 002a 0348 ldr r0, .L66 + 1708 002c FFF7FEFF bl HAL_I2C_Mem_Read + 1709 .LVL219: + 599:Core/Src/si5351.c **** (uint8_t)(SI5351_ADDRESS<<1), // i2c address, left aligned + 600:Core/Src/si5351.c **** (uint8_t)reg, // register address + 601:Core/Src/si5351.c **** I2C_MEMADD_SIZE_8BIT, // si5351 uses 8bit register addresses + 602:Core/Src/si5351.c **** (uint8_t*)(&value), // write returned data to this variable + 603:Core/Src/si5351.c **** 1, // how many bytes to expect returned + 604:Core/Src/si5351.c **** 100); // timeout + 605:Core/Src/si5351.c **** + 606:Core/Src/si5351.c **** return ERROR_NONE; + 1710 .loc 1 606 3 is_stmt 1 view .LVU445 + 607:Core/Src/si5351.c **** } + 1711 .loc 1 607 1 is_stmt 0 view .LVU446 + 1712 0030 0020 movs r0, #0 + 1713 0032 06B0 add sp, sp, #24 + 1714 @ sp needed + 1715 0034 10BD pop {r4, pc} + 1716 .L67: + 1717 0036 C046 .align 2 + 1718 .L66: + 1719 0038 00000000 .word hi2c2 + 1720 .cfi_endproc + 1721 .LFE305: + ARM GAS /tmp/ccV7ORbp.s page 49 + + + 1723 .section .text.si5351_setupRdiv,"ax",%progbits + 1724 .align 1 + 1725 .global si5351_setupRdiv + 1726 .syntax unified + 1727 .code 16 + 1728 .thumb_func + 1729 .fpu softvfp + 1731 si5351_setupRdiv: + 1732 .LVL220: + 1733 .LFB301: + 270:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 1734 .loc 1 270 59 is_stmt 1 view -0 + 1735 .cfi_startproc + 1736 @ args = 0, pretend = 0, frame = 8 + 1737 @ frame_needed = 0, uses_anonymous_args = 0 + 270:Core/Src/si5351.c **** ASSERT( output < 3, ERROR_INVALIDPARAMETER); /* Channel range */ + 1738 .loc 1 270 59 is_stmt 0 view .LVU448 + 1739 0000 F0B5 push {r4, r5, r6, r7, lr} + 1740 .LCFI14: + 1741 .cfi_def_cfa_offset 20 + 1742 .cfi_offset 4, -20 + 1743 .cfi_offset 5, -16 + 1744 .cfi_offset 6, -12 + 1745 .cfi_offset 7, -8 + 1746 .cfi_offset 14, -4 + 1747 0002 C646 mov lr, r8 + 1748 0004 00B5 push {lr} + 1749 .LCFI15: + 1750 .cfi_def_cfa_offset 24 + 1751 .cfi_offset 8, -24 + 1752 0006 82B0 sub sp, sp, #8 + 1753 .LCFI16: + 1754 .cfi_def_cfa_offset 32 + 1755 0008 0400 movs r4, r0 + 1756 000a 0D00 movs r5, r1 + 1757 000c 0023 movs r3, #0 + 1758 000e 9846 mov r8, r3 + 271:Core/Src/si5351.c **** + 1759 .loc 1 271 3 is_stmt 1 view .LVU449 + 271:Core/Src/si5351.c **** + 1760 .loc 1 271 3 view .LVU450 + 1761 0010 0228 cmp r0, #2 + 1762 0012 51D8 bhi .L84 + 271:Core/Src/si5351.c **** + 1763 .loc 1 271 3 view .LVU451 + 273:Core/Src/si5351.c **** + 1764 .loc 1 273 3 view .LVU452 + 275:Core/Src/si5351.c **** if (output == 1) Rreg = SI5351_REGISTER_52_MULTISYNTH1_PARAMETERS_3; + 1765 .loc 1 275 3 view .LVU453 + 1766 .LVL221: + 276:Core/Src/si5351.c **** if (output == 2) Rreg = SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3; + 1767 .loc 1 276 3 view .LVU454 + 276:Core/Src/si5351.c **** if (output == 2) Rreg = SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3; + 1768 .loc 1 276 6 is_stmt 0 view .LVU455 + 1769 0014 0128 cmp r0, #1 + 1770 0016 1AD0 beq .L85 + 1771 0018 2C27 movs r7, #44 + ARM GAS /tmp/ccV7ORbp.s page 50 + + + 1772 .L70: + 1773 .LVL222: + 277:Core/Src/si5351.c **** + 1774 .loc 1 277 3 is_stmt 1 view .LVU456 + 277:Core/Src/si5351.c **** + 1775 .loc 1 277 6 is_stmt 0 view .LVU457 + 1776 001a 022C cmp r4, #2 + 1777 001c 19D0 beq .L89 + 1778 .LVL223: + 1779 .L71: + 279:Core/Src/si5351.c **** + 1780 .loc 1 279 3 is_stmt 1 view .LVU458 + 1781 001e 6B46 mov r3, sp + 1782 0020 DE1D adds r6, r3, #7 + 1783 0022 3100 movs r1, r6 + 1784 .LVL224: + 279:Core/Src/si5351.c **** + 1785 .loc 1 279 3 is_stmt 0 view .LVU459 + 1786 0024 3800 movs r0, r7 + 1787 .LVL225: + 279:Core/Src/si5351.c **** + 1788 .loc 1 279 3 view .LVU460 + 1789 0026 FFF7FEFF bl si5351_read8 + 1790 .LVL226: + 281:Core/Src/si5351.c **** uint8_t divider = div; + 1791 .loc 1 281 3 is_stmt 1 view .LVU461 + 281:Core/Src/si5351.c **** uint8_t divider = div; + 1792 .loc 1 281 10 is_stmt 0 view .LVU462 + 1793 002a 3378 ldrb r3, [r6] + 1794 002c 0F21 movs r1, #15 + 1795 002e 1940 ands r1, r3 + 1796 0030 3170 strb r1, [r6] + 282:Core/Src/si5351.c **** divider &= 0x07; + 1797 .loc 1 282 3 is_stmt 1 view .LVU463 + 1798 .LVL227: + 283:Core/Src/si5351.c **** divider <<= 4; + 1799 .loc 1 283 3 view .LVU464 + 284:Core/Src/si5351.c **** regval |= divider; + 1800 .loc 1 284 3 view .LVU465 + 284:Core/Src/si5351.c **** regval |= divider; + 1801 .loc 1 284 11 is_stmt 0 view .LVU466 + 1802 0032 2A01 lsls r2, r5, #4 + 1803 0034 7023 movs r3, #112 + 1804 0036 1340 ands r3, r2 + 1805 .LVL228: + 285:Core/Src/si5351.c **** si5351_write8(Rreg, regval); + 1806 .loc 1 285 3 is_stmt 1 view .LVU467 + 285:Core/Src/si5351.c **** si5351_write8(Rreg, regval); + 1807 .loc 1 285 10 is_stmt 0 view .LVU468 + 1808 0038 1943 orrs r1, r3 + 1809 003a 3170 strb r1, [r6] + 286:Core/Src/si5351.c **** + 1810 .loc 1 286 3 is_stmt 1 view .LVU469 + 1811 003c 3800 movs r0, r7 + 1812 003e FFF7FEFF bl si5351_write8 + 1813 .LVL229: + 288:Core/Src/si5351.c **** { + ARM GAS /tmp/ccV7ORbp.s page 51 + + + 1814 .loc 1 288 3 view .LVU470 + 1815 0042 072D cmp r5, #7 + 1816 0044 1ED8 bhi .L81 + 1817 0046 AD00 lsls r5, r5, #2 + 1818 .LVL230: + 288:Core/Src/si5351.c **** { + 1819 .loc 1 288 3 is_stmt 0 view .LVU471 + 1820 0048 1C4B ldr r3, .L91 + 1821 004a 5B59 ldr r3, [r3, r5] + 1822 004c 9F46 mov pc, r3 + 1823 .section .rodata.si5351_setupRdiv,"a",%progbits + 1824 .align 2 + 1825 .L74: + 1826 0000 80000000 .word .L87 + 1827 0004 56000000 .word .L80 + 1828 0008 5C000000 .word .L79 + 1829 000c 62000000 .word .L78 + 1830 0010 68000000 .word .L77 + 1831 0014 6E000000 .word .L76 + 1832 0018 74000000 .word .L75 + 1833 001c 7A000000 .word .L73 + 1834 .section .text.si5351_setupRdiv + 1835 .LVL231: + 1836 .L85: + 276:Core/Src/si5351.c **** if (output == 2) Rreg = SI5351_REGISTER_60_MULTISYNTH2_PARAMETERS_3; + 1837 .loc 1 276 25 view .LVU472 + 1838 004e 3427 movs r7, #52 + 1839 0050 E3E7 b .L70 + 1840 .LVL232: + 1841 .L89: + 277:Core/Src/si5351.c **** + 1842 .loc 1 277 25 view .LVU473 + 1843 0052 3C27 movs r7, #60 + 1844 .LVL233: + 277:Core/Src/si5351.c **** + 1845 .loc 1 277 25 view .LVU474 + 1846 0054 E3E7 b .L71 + 1847 .LVL234: + 1848 .L80: + 295:Core/Src/si5351.c **** break; + 1849 .loc 1 295 3 is_stmt 1 view .LVU475 + 296:Core/Src/si5351.c **** + 1850 .loc 1 296 3 view .LVU476 + 295:Core/Src/si5351.c **** break; + 1851 .loc 1 295 8 is_stmt 0 view .LVU477 + 1852 0056 0223 movs r3, #2 + 1853 0058 9846 mov r8, r3 + 296:Core/Src/si5351.c **** + 1854 .loc 1 296 3 view .LVU478 + 1855 005a 13E0 b .L81 + 1856 .LVL235: + 1857 .L79: + 299:Core/Src/si5351.c **** break; + 1858 .loc 1 299 3 is_stmt 1 view .LVU479 + 300:Core/Src/si5351.c **** + 1859 .loc 1 300 3 view .LVU480 + 299:Core/Src/si5351.c **** break; + ARM GAS /tmp/ccV7ORbp.s page 52 + + + 1860 .loc 1 299 8 is_stmt 0 view .LVU481 + 1861 005c 0423 movs r3, #4 + 1862 005e 9846 mov r8, r3 + 300:Core/Src/si5351.c **** + 1863 .loc 1 300 3 view .LVU482 + 1864 0060 10E0 b .L81 + 1865 .LVL236: + 1866 .L78: + 303:Core/Src/si5351.c **** break; + 1867 .loc 1 303 3 is_stmt 1 view .LVU483 + 304:Core/Src/si5351.c **** + 1868 .loc 1 304 3 view .LVU484 + 303:Core/Src/si5351.c **** break; + 1869 .loc 1 303 8 is_stmt 0 view .LVU485 + 1870 0062 0823 movs r3, #8 + 1871 0064 9846 mov r8, r3 + 304:Core/Src/si5351.c **** + 1872 .loc 1 304 3 view .LVU486 + 1873 0066 0DE0 b .L81 + 1874 .LVL237: + 1875 .L77: + 307:Core/Src/si5351.c **** break; + 1876 .loc 1 307 3 is_stmt 1 view .LVU487 + 308:Core/Src/si5351.c **** + 1877 .loc 1 308 3 view .LVU488 + 307:Core/Src/si5351.c **** break; + 1878 .loc 1 307 8 is_stmt 0 view .LVU489 + 1879 0068 1023 movs r3, #16 + 1880 006a 9846 mov r8, r3 + 308:Core/Src/si5351.c **** + 1881 .loc 1 308 3 view .LVU490 + 1882 006c 0AE0 b .L81 + 1883 .LVL238: + 1884 .L76: + 311:Core/Src/si5351.c **** break; + 1885 .loc 1 311 3 is_stmt 1 view .LVU491 + 312:Core/Src/si5351.c **** + 1886 .loc 1 312 3 view .LVU492 + 311:Core/Src/si5351.c **** break; + 1887 .loc 1 311 8 is_stmt 0 view .LVU493 + 1888 006e 2023 movs r3, #32 + 1889 0070 9846 mov r8, r3 + 312:Core/Src/si5351.c **** + 1890 .loc 1 312 3 view .LVU494 + 1891 0072 07E0 b .L81 + 1892 .LVL239: + 1893 .L75: + 315:Core/Src/si5351.c **** break; + 1894 .loc 1 315 3 is_stmt 1 view .LVU495 + 316:Core/Src/si5351.c **** + 1895 .loc 1 316 3 view .LVU496 + 315:Core/Src/si5351.c **** break; + 1896 .loc 1 315 8 is_stmt 0 view .LVU497 + 1897 0074 4023 movs r3, #64 + 1898 0076 9846 mov r8, r3 + 316:Core/Src/si5351.c **** + 1899 .loc 1 316 3 view .LVU498 + ARM GAS /tmp/ccV7ORbp.s page 53 + + + 1900 0078 04E0 b .L81 + 1901 .LVL240: + 1902 .L73: + 319:Core/Src/si5351.c **** break; + 1903 .loc 1 319 3 is_stmt 1 view .LVU499 + 320:Core/Src/si5351.c **** } + 1904 .loc 1 320 3 view .LVU500 + 319:Core/Src/si5351.c **** break; + 1905 .loc 1 319 8 is_stmt 0 view .LVU501 + 1906 007a 8023 movs r3, #128 + 1907 007c 9846 mov r8, r3 + 320:Core/Src/si5351.c **** } + 1908 .loc 1 320 3 view .LVU502 + 1909 007e 01E0 b .L81 + 1910 .LVL241: + 1911 .L87: + 291:Core/Src/si5351.c **** break; + 1912 .loc 1 291 8 view .LVU503 + 1913 0080 0123 movs r3, #1 + 1914 0082 9846 mov r8, r3 + 1915 .L81: + 1916 .LVL242: + 323:Core/Src/si5351.c **** { + 1917 .loc 1 323 3 is_stmt 1 view .LVU504 + 1918 0084 012C cmp r4, #1 + 1919 0086 0DD0 beq .L82 + 1920 0088 022C cmp r4, #2 + 1921 008a 10D0 beq .L83 + 1922 008c 002C cmp r4, #0 + 1923 008e 04D0 beq .L90 + 1924 0090 0020 movs r0, #0 + 1925 .LVL243: + 1926 .L69: + 339:Core/Src/si5351.c **** + 1927 .loc 1 339 1 is_stmt 0 view .LVU505 + 1928 0092 02B0 add sp, sp, #8 + 1929 @ sp needed + 1930 0094 80BC pop {r7} + 1931 0096 B846 mov r8, r7 + 1932 0098 F0BD pop {r4, r5, r6, r7, pc} + 1933 .LVL244: + 1934 .L90: + 326:Core/Src/si5351.c **** break; + 1935 .loc 1 326 3 is_stmt 1 view .LVU506 + 326:Core/Src/si5351.c **** break; + 1936 .loc 1 326 28 is_stmt 0 view .LVU507 + 1937 009a 094B ldr r3, .L91+4 + 1938 009c 4246 mov r2, r8 + 1939 009e DA62 str r2, [r3, #44] + 327:Core/Src/si5351.c **** + 1940 .loc 1 327 3 is_stmt 1 view .LVU508 + 338:Core/Src/si5351.c **** } + 1941 .loc 1 338 10 is_stmt 0 view .LVU509 + 1942 00a0 0020 movs r0, #0 + 327:Core/Src/si5351.c **** + 1943 .loc 1 327 3 view .LVU510 + 1944 00a2 F6E7 b .L69 + ARM GAS /tmp/ccV7ORbp.s page 54 + + + 1945 .L82: + 330:Core/Src/si5351.c **** break; + 1946 .loc 1 330 3 is_stmt 1 view .LVU511 + 330:Core/Src/si5351.c **** break; + 1947 .loc 1 330 28 is_stmt 0 view .LVU512 + 1948 00a4 064B ldr r3, .L91+4 + 1949 00a6 4246 mov r2, r8 + 1950 00a8 1A63 str r2, [r3, #48] + 331:Core/Src/si5351.c **** + 1951 .loc 1 331 3 is_stmt 1 view .LVU513 + 338:Core/Src/si5351.c **** } + 1952 .loc 1 338 10 is_stmt 0 view .LVU514 + 1953 00aa 0020 movs r0, #0 + 331:Core/Src/si5351.c **** + 1954 .loc 1 331 3 view .LVU515 + 1955 00ac F1E7 b .L69 + 1956 .L83: + 334:Core/Src/si5351.c **** break; + 1957 .loc 1 334 3 is_stmt 1 view .LVU516 + 334:Core/Src/si5351.c **** break; + 1958 .loc 1 334 28 is_stmt 0 view .LVU517 + 1959 00ae 044B ldr r3, .L91+4 + 1960 00b0 4246 mov r2, r8 + 1961 00b2 5A63 str r2, [r3, #52] + 335:Core/Src/si5351.c **** } + 1962 .loc 1 335 3 is_stmt 1 view .LVU518 + 338:Core/Src/si5351.c **** } + 1963 .loc 1 338 10 is_stmt 0 view .LVU519 + 1964 00b4 0020 movs r0, #0 + 335:Core/Src/si5351.c **** } + 1965 .loc 1 335 3 view .LVU520 + 1966 00b6 ECE7 b .L69 + 1967 .LVL245: + 1968 .L84: + 271:Core/Src/si5351.c **** + 1969 .loc 1 271 3 view .LVU521 + 1970 00b8 0420 movs r0, #4 + 1971 .LVL246: + 271:Core/Src/si5351.c **** + 1972 .loc 1 271 3 view .LVU522 + 1973 00ba EAE7 b .L69 + 1974 .L92: + 1975 .align 2 + 1976 .L91: + 1977 00bc 00000000 .word .L74 + 1978 00c0 00000000 .word .LANCHOR0 + 1979 .cfi_endproc + 1980 .LFE301: + 1982 .global __aeabi_ddiv + 1983 .global __aeabi_d2iz + 1984 .global __aeabi_uidiv + 1985 .global __aeabi_uidivmod + 1986 .section .text.CalcRegisters,"ax",%progbits + 1987 .align 1 + 1988 .global CalcRegisters + 1989 .syntax unified + 1990 .code 16 + ARM GAS /tmp/ccV7ORbp.s page 55 + + + 1991 .thumb_func + 1992 .fpu softvfp + 1994 CalcRegisters: + 1995 .LVL247: + 1996 .LFB306: + 608:Core/Src/si5351.c **** + 609:Core/Src/si5351.c **** + 610:Core/Src/si5351.c **** void CalcRegisters(uint32_t fout){ + 1997 .loc 1 610 34 is_stmt 1 view -0 + 1998 .cfi_startproc + 1999 @ args = 0, pretend = 0, frame = 8 + 2000 @ frame_needed = 0, uses_anonymous_args = 0 + 2001 .loc 1 610 34 is_stmt 0 view .LVU524 + 2002 0000 F0B5 push {r4, r5, r6, r7, lr} + 2003 .LCFI17: + 2004 .cfi_def_cfa_offset 20 + 2005 .cfi_offset 4, -20 + 2006 .cfi_offset 5, -16 + 2007 .cfi_offset 6, -12 + 2008 .cfi_offset 7, -8 + 2009 .cfi_offset 14, -4 + 2010 0002 DE46 mov lr, fp + 2011 0004 5746 mov r7, r10 + 2012 0006 4E46 mov r6, r9 + 2013 0008 4546 mov r5, r8 + 2014 000a E0B5 push {r5, r6, r7, lr} + 2015 .LCFI18: + 2016 .cfi_def_cfa_offset 36 + 2017 .cfi_offset 8, -36 + 2018 .cfi_offset 9, -32 + 2019 .cfi_offset 10, -28 + 2020 .cfi_offset 11, -24 + 2021 000c 85B0 sub sp, sp, #20 + 2022 .LCFI19: + 2023 .cfi_def_cfa_offset 56 + 611:Core/Src/si5351.c **** fout *= 2; + 2024 .loc 1 611 2 is_stmt 1 view .LVU525 + 2025 .loc 1 611 7 is_stmt 0 view .LVU526 + 2026 000e 4400 lsls r4, r0, #1 + 2027 .LVL248: + 612:Core/Src/si5351.c **** uint8_t *regs; + 2028 .loc 1 612 2 is_stmt 1 view .LVU527 + 613:Core/Src/si5351.c **** uint32_t fref = SI5351_CRYSTAL_FREQ_24MHZ; // The reference frequency + 2029 .loc 1 613 5 view .LVU528 + 614:Core/Src/si5351.c **** + 615:Core/Src/si5351.c **** // Calc Output Multisynth Divider and R with e = 0 and f = 1 => msx_p2 = 0 and msx_p3 = 1 + 616:Core/Src/si5351.c **** uint32_t d = 4; + 2030 .loc 1 616 5 view .LVU529 + 617:Core/Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY + 2031 .loc 1 617 5 view .LVU530 + 618:Core/Src/si5351.c **** int msx_divby4 = 0; + 2032 .loc 1 618 5 view .LVU531 + 619:Core/Src/si5351.c **** int rx_div = 0; + 2033 .loc 1 619 5 view .LVU532 + 620:Core/Src/si5351.c **** int r = 1; + 2034 .loc 1 620 5 view .LVU533 + 621:Core/Src/si5351.c **** + ARM GAS /tmp/ccV7ORbp.s page 56 + + + 622:Core/Src/si5351.c **** if (fout > 150e6) + 2035 .loc 1 622 5 view .LVU534 + 2036 .loc 1 622 8 is_stmt 0 view .LVU535 + 2037 0010 8A4B ldr r3, .L110 + 2038 0012 9C42 cmp r4, r3 + 2039 0014 54D8 bhi .L102 + 623:Core/Src/si5351.c **** msx_divby4 = 0x0C; // MSx_DIVBY4[1:0] = 0b11, see datasheet 4.1.3 + 624:Core/Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas + 2040 .loc 1 624 10 is_stmt 1 view .LVU536 + 2041 .loc 1 624 13 is_stmt 0 view .LVU537 + 2042 0016 8A4B ldr r3, .L110+4 + 2043 0018 9C42 cmp r4, r3 + 2044 001a 3FD9 bls .L103 + 625:Core/Src/si5351.c **** { + 626:Core/Src/si5351.c **** int rd = 0; + 627:Core/Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL)) + 628:Core/Src/si5351.c **** { + 629:Core/Src/si5351.c **** r <<= 1; + 630:Core/Src/si5351.c **** rd++; + 631:Core/Src/si5351.c **** } + 632:Core/Src/si5351.c **** rx_div = rd << 4; + 633:Core/Src/si5351.c **** + 634:Core/Src/si5351.c **** d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum + 635:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 636:Core/Src/si5351.c **** d++; + 637:Core/Src/si5351.c **** + 638:Core/Src/si5351.c **** if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even + 639:Core/Src/si5351.c **** d += 2; + 640:Core/Src/si5351.c **** } + 641:Core/Src/si5351.c **** else // 292968 Hz <= fout <= 150 MHz + 642:Core/Src/si5351.c **** { + 643:Core/Src/si5351.c **** d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum + 2045 .loc 1 643 9 is_stmt 1 view .LVU538 + 2046 .loc 1 643 19 is_stmt 0 view .LVU539 + 2047 001c 2000 movs r0, r4 + 2048 001e FFF7FEFF bl __aeabi_ui2d + 2049 .LVL249: + 2050 0022 0200 movs r2, r0 + 2051 0024 0B00 movs r3, r1 + 2052 0026 0020 movs r0, #0 + 2053 0028 8649 ldr r1, .L110+8 + 2054 002a FFF7FEFF bl __aeabi_ddiv + 2055 .LVL250: + 2056 .loc 1 643 11 view .LVU540 + 2057 002e FFF7FEFF bl __aeabi_d2uiz + 2058 .LVL251: + 2059 0032 8046 mov r8, r0 + 2060 .LVL252: + 644:Core/Src/si5351.c **** if (d < 6) + 2061 .loc 1 644 9 is_stmt 1 view .LVU541 + 2062 .loc 1 644 12 is_stmt 0 view .LVU542 + 2063 0034 0300 movs r3, r0 + 2064 0036 0528 cmp r0, #5 + 2065 0038 33D9 bls .L105 + 645:Core/Src/si5351.c **** d = 6; + 646:Core/Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d + 2066 .loc 1 646 14 is_stmt 1 view .LVU543 + ARM GAS /tmp/ccV7ORbp.s page 57 + + + 2067 .loc 1 646 17 is_stmt 0 view .LVU544 + 2068 003a DB07 lsls r3, r3, #31 + 2069 003c 33D5 bpl .L100 + 647:Core/Src/si5351.c **** d++; + 2070 .loc 1 647 12 is_stmt 1 view .LVU545 + 2071 .loc 1 647 13 is_stmt 0 view .LVU546 + 2072 003e 0123 movs r3, #1 + 2073 0040 9C46 mov ip, r3 + 2074 0042 E044 add r8, r8, ip + 2075 .LVL253: + 2076 .loc 1 647 13 view .LVU547 + 2077 0044 2FE0 b .L100 + 2078 .LVL254: + 2079 .L98: + 2080 .LBB31: + 629:Core/Src/si5351.c **** rd++; + 2081 .loc 1 629 13 is_stmt 1 view .LVU548 + 629:Core/Src/si5351.c **** rd++; + 2082 .loc 1 629 15 is_stmt 0 view .LVU549 + 2083 0046 7600 lsls r6, r6, #1 + 2084 .LVL255: + 630:Core/Src/si5351.c **** } + 2085 .loc 1 630 13 is_stmt 1 view .LVU550 + 630:Core/Src/si5351.c **** } + 2086 .loc 1 630 15 is_stmt 0 view .LVU551 + 2087 0048 0135 adds r5, r5, #1 + 2088 .LVL256: + 2089 .L95: + 627:Core/Src/si5351.c **** { + 2090 .loc 1 627 15 is_stmt 1 view .LVU552 + 2091 004a 7F2E cmp r6, #127 + 2092 004c 04DC bgt .L97 + 627:Core/Src/si5351.c **** { + 2093 .loc 1 627 26 is_stmt 0 discriminator 1 view .LVU553 + 2094 004e 7C4A ldr r2, .L110+4 + 2095 0050 2300 movs r3, r4 + 2096 0052 7343 muls r3, r6 + 2097 0054 9342 cmp r3, r2 + 2098 0056 F6D9 bls .L98 + 2099 .L97: + 632:Core/Src/si5351.c **** + 2100 .loc 1 632 9 is_stmt 1 view .LVU554 + 632:Core/Src/si5351.c **** + 2101 .loc 1 632 16 is_stmt 0 view .LVU555 + 2102 0058 2B01 lsls r3, r5, #4 + 2103 005a 0293 str r3, [sp, #8] + 2104 .LVL257: + 634:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 2105 .loc 1 634 9 is_stmt 1 view .LVU556 + 634:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 2106 .loc 1 634 24 is_stmt 0 view .LVU557 + 2107 005c 3700 movs r7, r6 + 2108 005e 2000 movs r0, r4 + 2109 0060 7043 muls r0, r6 + 634:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 2110 .loc 1 634 19 view .LVU558 + 2111 0062 FFF7FEFF bl __aeabi_ui2d + ARM GAS /tmp/ccV7ORbp.s page 58 + + + 2112 .LVL258: + 634:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 2113 .loc 1 634 19 view .LVU559 + 2114 0066 0200 movs r2, r0 + 2115 0068 0B00 movs r3, r1 + 2116 006a 0020 movs r0, #0 + 2117 006c 7549 ldr r1, .L110+8 + 2118 006e FFF7FEFF bl __aeabi_ddiv + 2119 .LVL259: + 634:Core/Src/si5351.c **** if (d % 2) // Make d even to reduce spurious and phase noise/ + 2120 .loc 1 634 11 view .LVU560 + 2121 0072 FFF7FEFF bl __aeabi_d2uiz + 2122 .LVL260: + 2123 0076 8046 mov r8, r0 + 2124 .LVL261: + 635:Core/Src/si5351.c **** d++; + 2125 .loc 1 635 9 is_stmt 1 view .LVU561 + 635:Core/Src/si5351.c **** d++; + 2126 .loc 1 635 12 is_stmt 0 view .LVU562 + 2127 0078 0300 movs r3, r0 + 2128 007a DB07 lsls r3, r3, #31 + 2129 007c 02D5 bpl .L99 + 636:Core/Src/si5351.c **** + 2130 .loc 1 636 13 is_stmt 1 view .LVU563 + 636:Core/Src/si5351.c **** + 2131 .loc 1 636 14 is_stmt 0 view .LVU564 + 2132 007e 0123 movs r3, #1 + 2133 0080 9C46 mov ip, r3 + 2134 0082 E044 add r8, r8, ip + 2135 .LVL262: + 2136 .L99: + 638:Core/Src/si5351.c **** d += 2; + 2137 .loc 1 638 9 is_stmt 1 view .LVU565 + 638:Core/Src/si5351.c **** d += 2; + 2138 .loc 1 638 15 is_stmt 0 view .LVU566 + 2139 0084 4346 mov r3, r8 + 2140 0086 5F43 muls r7, r3 + 638:Core/Src/si5351.c **** d += 2; + 2141 .loc 1 638 19 view .LVU567 + 2142 0088 6743 muls r7, r4 + 638:Core/Src/si5351.c **** d += 2; + 2143 .loc 1 638 12 view .LVU568 + 2144 008a 6F4B ldr r3, .L110+12 + 2145 008c 9F42 cmp r7, r3 + 2146 008e 56D8 bhi .L104 + 639:Core/Src/si5351.c **** } + 2147 .loc 1 639 13 is_stmt 1 view .LVU569 + 639:Core/Src/si5351.c **** } + 2148 .loc 1 639 15 is_stmt 0 view .LVU570 + 2149 0090 0223 movs r3, #2 + 2150 0092 9C46 mov ip, r3 + 2151 0094 E044 add r8, r8, ip + 2152 .LVL263: + 639:Core/Src/si5351.c **** } + 2153 .loc 1 639 15 view .LVU571 + 2154 .LBE31: + 618:Core/Src/si5351.c **** int rx_div = 0; + ARM GAS /tmp/ccV7ORbp.s page 59 + + + 2155 .loc 1 618 9 view .LVU572 + 2156 0096 0023 movs r3, #0 + 2157 0098 0393 str r3, [sp, #12] + 2158 009a 18E0 b .L94 + 2159 .LVL264: + 2160 .L103: + 2161 .LBB32: + 626:Core/Src/si5351.c **** while ((r < 128) && (r * fout < 292969UL)) + 2162 .loc 1 626 13 view .LVU573 + 2163 009c 0025 movs r5, #0 + 2164 .LBE32: + 620:Core/Src/si5351.c **** + 2165 .loc 1 620 9 view .LVU574 + 2166 009e 0126 movs r6, #1 + 2167 00a0 D3E7 b .L95 + 2168 .LVL265: + 2169 .L105: + 645:Core/Src/si5351.c **** else if (d % 2) // Make d even to reduce phase noise/jitter, see d + 2170 .loc 1 645 15 view .LVU575 + 2171 00a2 0623 movs r3, #6 + 2172 00a4 9846 mov r8, r3 + 2173 .LVL266: + 2174 .L100: + 648:Core/Src/si5351.c **** + 649:Core/Src/si5351.c **** if (d * fout < 600e6) // VCO frequency to low check and maintain an even + 2175 .loc 1 649 9 is_stmt 1 view .LVU576 + 2176 .loc 1 649 12 is_stmt 0 view .LVU577 + 2177 00a6 684A ldr r2, .L110+12 + 2178 00a8 4346 mov r3, r8 + 2179 00aa 6343 muls r3, r4 + 2180 00ac 9342 cmp r3, r2 + 2181 00ae 49D8 bhi .L106 + 650:Core/Src/si5351.c **** d += 2; + 2182 .loc 1 650 13 is_stmt 1 view .LVU578 + 2183 .loc 1 650 15 is_stmt 0 view .LVU579 + 2184 00b0 0223 movs r3, #2 + 2185 00b2 9C46 mov ip, r3 + 2186 00b4 E044 add r8, r8, ip + 2187 .LVL267: + 620:Core/Src/si5351.c **** + 2188 .loc 1 620 9 view .LVU580 + 2189 00b6 0126 movs r6, #1 + 619:Core/Src/si5351.c **** int r = 1; + 2190 .loc 1 619 9 view .LVU581 + 2191 00b8 0023 movs r3, #0 + 2192 00ba 0293 str r3, [sp, #8] + 618:Core/Src/si5351.c **** int rx_div = 0; + 2193 .loc 1 618 9 view .LVU582 + 2194 00bc 0393 str r3, [sp, #12] + 2195 00be 06E0 b .L94 + 2196 .LVL268: + 2197 .L102: + 620:Core/Src/si5351.c **** + 2198 .loc 1 620 9 view .LVU583 + 2199 00c0 0126 movs r6, #1 + 619:Core/Src/si5351.c **** int r = 1; + 2200 .loc 1 619 9 view .LVU584 + ARM GAS /tmp/ccV7ORbp.s page 60 + + + 2201 00c2 0023 movs r3, #0 + 2202 00c4 0293 str r3, [sp, #8] + 623:Core/Src/si5351.c **** else if (fout < 292969UL) // If fout < 500 kHz then use R divider, see datas + 2203 .loc 1 623 20 view .LVU585 + 2204 00c6 0C33 adds r3, r3, #12 + 2205 00c8 0393 str r3, [sp, #12] + 616:Core/Src/si5351.c **** uint32_t msx_p1 = 0; // If fout > 150 MHz then MSx_P1 = 0 and MSx_DIVBY + 2206 .loc 1 616 14 view .LVU586 + 2207 00ca 083B subs r3, r3, #8 + 2208 00cc 9846 mov r8, r3 + 2209 .LVL269: + 2210 .L94: + 651:Core/Src/si5351.c **** } + 652:Core/Src/si5351.c **** msx_p1 = 128 * d - 512; + 2211 .loc 1 652 5 is_stmt 1 view .LVU587 + 2212 .loc 1 652 22 is_stmt 0 view .LVU588 + 2213 00ce 5F4B ldr r3, .L110+16 + 2214 00d0 4344 add r3, r3, r8 + 2215 .loc 1 652 12 view .LVU589 + 2216 00d2 DB01 lsls r3, r3, #7 + 2217 00d4 9946 mov r9, r3 + 2218 .LVL270: + 653:Core/Src/si5351.c **** + 654:Core/Src/si5351.c **** uint32_t fvco = (uint32_t) d * r * fout; + 2219 .loc 1 654 5 is_stmt 1 view .LVU590 + 2220 .loc 1 654 34 is_stmt 0 view .LVU591 + 2221 00d6 4346 mov r3, r8 + 2222 .LVL271: + 2223 .loc 1 654 34 view .LVU592 + 2224 00d8 5E43 muls r6, r3 + 2225 .LVL272: + 2226 .loc 1 654 14 view .LVU593 + 2227 00da 2000 movs r0, r4 + 2228 00dc 7043 muls r0, r6 + 2229 .LVL273: + 655:Core/Src/si5351.c **** + 656:Core/Src/si5351.c **** // Calc Feedback Multisynth Divider + 657:Core/Src/si5351.c **** double fmd = (double)fvco / fref; // The FMD value has been found + 2230 .loc 1 657 5 is_stmt 1 view .LVU594 + 2231 .loc 1 657 18 is_stmt 0 view .LVU595 + 2232 00de FFF7FEFF bl __aeabi_ui2d + 2233 .LVL274: + 2234 .loc 1 657 12 view .LVU596 + 2235 00e2 0022 movs r2, #0 + 2236 00e4 5A4B ldr r3, .L110+20 + 2237 00e6 FFF7FEFF bl __aeabi_ddiv + 2238 .LVL275: + 2239 00ea 0600 movs r6, r0 + 2240 .LVL276: + 2241 .loc 1 657 12 view .LVU597 + 2242 00ec 0F00 movs r7, r1 + 2243 .LVL277: + 658:Core/Src/si5351.c **** int a = fmd; // a is the integer part of the FMD value + 2244 .loc 1 658 5 is_stmt 1 view .LVU598 + 2245 .loc 1 658 9 is_stmt 0 view .LVU599 + 2246 00ee FFF7FEFF bl __aeabi_d2iz + 2247 .LVL278: + ARM GAS /tmp/ccV7ORbp.s page 61 + + + 2248 00f2 0400 movs r4, r0 + 2249 .LVL279: + 659:Core/Src/si5351.c **** + 660:Core/Src/si5351.c **** double b_c = (double)fmd - a; // Get b/c + 2250 .loc 1 660 5 is_stmt 1 view .LVU600 + 2251 .loc 1 660 30 is_stmt 0 view .LVU601 + 2252 00f4 FFF7FEFF bl __aeabi_i2d + 2253 .LVL280: + 2254 .loc 1 660 30 view .LVU602 + 2255 00f8 0200 movs r2, r0 + 2256 00fa 0B00 movs r3, r1 + 2257 .loc 1 660 12 view .LVU603 + 2258 00fc 3000 movs r0, r6 + 2259 00fe 3900 movs r1, r7 + 2260 0100 FFF7FEFF bl __aeabi_dsub + 2261 .LVL281: + 2262 0104 0600 movs r6, r0 + 2263 .LVL282: + 2264 .loc 1 660 12 view .LVU604 + 2265 0106 0F00 movs r7, r1 + 2266 .LVL283: + 661:Core/Src/si5351.c **** uint32_t c = 1048575UL; + 2267 .loc 1 661 5 is_stmt 1 view .LVU605 + 662:Core/Src/si5351.c **** uint32_t b = (double)b_c * c; + 2268 .loc 1 662 5 view .LVU606 + 2269 .loc 1 662 30 is_stmt 0 view .LVU607 + 2270 0108 0022 movs r2, #0 + 2271 010a 524B ldr r3, .L110+24 + 2272 010c FFF7FEFF bl __aeabi_dmul + 2273 .LVL284: + 2274 .loc 1 662 14 view .LVU608 + 2275 0110 FFF7FEFF bl __aeabi_d2uiz + 2276 .LVL285: + 2277 0114 051E subs r5, r0, #0 + 2278 .LVL286: + 663:Core/Src/si5351.c **** if (b > 0) + 2279 .loc 1 663 5 is_stmt 1 view .LVU609 + 2280 .loc 1 663 8 is_stmt 0 view .LVU610 + 2281 0116 1AD0 beq .L107 + 664:Core/Src/si5351.c **** { + 665:Core/Src/si5351.c **** c = (double)b / b_c + 0.5; // Improves frequency precision in some cases + 2282 .loc 1 665 9 is_stmt 1 view .LVU611 + 2283 .loc 1 665 13 is_stmt 0 view .LVU612 + 2284 0118 FFF7FEFF bl __aeabi_ui2d + 2285 .LVL287: + 2286 .loc 1 665 23 view .LVU613 + 2287 011c 3200 movs r2, r6 + 2288 011e 3B00 movs r3, r7 + 2289 0120 FFF7FEFF bl __aeabi_ddiv + 2290 .LVL288: + 2291 .loc 1 665 29 view .LVU614 + 2292 0124 0022 movs r2, #0 + 2293 0126 4C4B ldr r3, .L110+28 + 2294 0128 FFF7FEFF bl __aeabi_dadd + 2295 .LVL289: + 2296 .loc 1 665 11 view .LVU615 + 2297 012c FFF7FEFF bl __aeabi_d2uiz + ARM GAS /tmp/ccV7ORbp.s page 62 + + + 2298 .LVL290: + 2299 0130 0600 movs r6, r0 + 2300 .LVL291: + 666:Core/Src/si5351.c **** if (c > 1048575UL) + 2301 .loc 1 666 9 is_stmt 1 view .LVU616 + 2302 .loc 1 666 12 is_stmt 0 view .LVU617 + 2303 0132 8023 movs r3, #128 + 2304 0134 5B03 lsls r3, r3, #13 + 2305 0136 9842 cmp r0, r3 + 2306 0138 0AD3 bcc .L101 + 667:Core/Src/si5351.c **** c = 1048575UL; + 2307 .loc 1 667 15 view .LVU618 + 2308 013a 484E ldr r6, .L110+32 + 2309 013c 08E0 b .L101 + 2310 .LVL292: + 2311 .L104: + 618:Core/Src/si5351.c **** int rx_div = 0; + 2312 .loc 1 618 9 view .LVU619 + 2313 013e 0023 movs r3, #0 + 2314 0140 0393 str r3, [sp, #12] + 2315 0142 C4E7 b .L94 + 2316 .LVL293: + 2317 .L106: + 620:Core/Src/si5351.c **** + 2318 .loc 1 620 9 view .LVU620 + 2319 0144 0126 movs r6, #1 + 619:Core/Src/si5351.c **** int r = 1; + 2320 .loc 1 619 9 view .LVU621 + 2321 0146 0023 movs r3, #0 + 2322 0148 0293 str r3, [sp, #8] + 618:Core/Src/si5351.c **** int rx_div = 0; + 2323 .loc 1 618 9 view .LVU622 + 2324 014a 0393 str r3, [sp, #12] + 2325 014c BFE7 b .L94 + 2326 .LVL294: + 2327 .L107: + 661:Core/Src/si5351.c **** uint32_t b = (double)b_c * c; + 2328 .loc 1 661 14 view .LVU623 + 2329 014e 434E ldr r6, .L110+32 + 2330 .LVL295: + 2331 .L101: + 668:Core/Src/si5351.c **** } + 669:Core/Src/si5351.c **** + 670:Core/Src/si5351.c **** + 671:Core/Src/si5351.c **** si5351_setupPLL(SI5351_PLL_A, a, b, c); + 2332 .loc 1 671 9 is_stmt 1 view .LVU624 + 2333 0150 E3B2 uxtb r3, r4 + 2334 0152 9B46 mov fp, r3 + 2335 0154 3300 movs r3, r6 + 2336 0156 2A00 movs r2, r5 + 2337 0158 5946 mov r1, fp + 2338 015a 0020 movs r0, #0 + 2339 015c FFF7FEFF bl si5351_setupPLL + 2340 .LVL296: + 672:Core/Src/si5351.c **** HAL_Delay(10); + 2341 .loc 1 672 9 view .LVU625 + 2342 0160 0A20 movs r0, #10 + ARM GAS /tmp/ccV7ORbp.s page 63 + + + 2343 0162 FFF7FEFF bl HAL_Delay + 2344 .LVL297: + 673:Core/Src/si5351.c **** si5351_setupMultisynth(0, SI5351_PLL_A, d, 0, 1); + 2345 .loc 1 673 9 view .LVU626 + 2346 0166 0127 movs r7, #1 + 2347 0168 0097 str r7, [sp] + 2348 016a 0023 movs r3, #0 + 2349 016c 4246 mov r2, r8 + 2350 016e 0021 movs r1, #0 + 2351 0170 0020 movs r0, #0 + 2352 0172 FFF7FEFF bl si5351_setupMultisynth + 2353 .LVL298: + 674:Core/Src/si5351.c **** HAL_Delay(10); + 2354 .loc 1 674 9 view .LVU627 + 2355 0176 0A20 movs r0, #10 + 2356 0178 FFF7FEFF bl HAL_Delay + 2357 .LVL299: + 675:Core/Src/si5351.c **** si5351_setupRdiv(0, SI5351_R_DIV_2); + 2358 .loc 1 675 9 view .LVU628 + 2359 017c 0121 movs r1, #1 + 2360 017e 0020 movs r0, #0 + 2361 0180 FFF7FEFF bl si5351_setupRdiv + 2362 .LVL300: + 676:Core/Src/si5351.c **** HAL_Delay(10); + 2363 .loc 1 676 9 view .LVU629 + 2364 0184 0A20 movs r0, #10 + 2365 0186 FFF7FEFF bl HAL_Delay + 2366 .LVL301: + 677:Core/Src/si5351.c **** + 678:Core/Src/si5351.c **** si5351_setupMultisynth(1, SI5351_PLL_A, d, 0, 1); + 2367 .loc 1 678 9 view .LVU630 + 2368 018a 0097 str r7, [sp] + 2369 018c 0023 movs r3, #0 + 2370 018e 4246 mov r2, r8 + 2371 0190 0021 movs r1, #0 + 2372 0192 0120 movs r0, #1 + 2373 0194 FFF7FEFF bl si5351_setupMultisynth + 2374 .LVL302: + 679:Core/Src/si5351.c **** HAL_Delay(10); + 2375 .loc 1 679 9 view .LVU631 + 2376 0198 0A20 movs r0, #10 + 2377 019a FFF7FEFF bl HAL_Delay + 2378 .LVL303: + 680:Core/Src/si5351.c **** si5351_setupRdiv(1, SI5351_R_DIV_2); + 2379 .loc 1 680 9 view .LVU632 + 2380 019e 0121 movs r1, #1 + 2381 01a0 0120 movs r0, #1 + 2382 01a2 FFF7FEFF bl si5351_setupRdiv + 2383 .LVL304: + 681:Core/Src/si5351.c **** HAL_Delay(10); + 2384 .loc 1 681 9 view .LVU633 + 2385 01a6 0A20 movs r0, #10 + 2386 01a8 FFF7FEFF bl HAL_Delay + 2387 .LVL305: + 682:Core/Src/si5351.c **** + 683:Core/Src/si5351.c **** + 684:Core/Src/si5351.c **** // 2a volta serve per avere fase non casuale + ARM GAS /tmp/ccV7ORbp.s page 64 + + + 685:Core/Src/si5351.c **** si5351_setupPLL(SI5351_PLL_A, a, b, c); + 2388 .loc 1 685 2 view .LVU634 + 2389 01ac 3300 movs r3, r6 + 2390 01ae 2A00 movs r2, r5 + 2391 01b0 5946 mov r1, fp + 2392 01b2 0020 movs r0, #0 + 2393 01b4 FFF7FEFF bl si5351_setupPLL + 2394 .LVL306: + 686:Core/Src/si5351.c **** + 687:Core/Src/si5351.c **** + 688:Core/Src/si5351.c **** uint32_t msnx_p1 = 128 * a + 128 * b / c - 512; // See datasheet 3.2 + 2395 .loc 1 688 5 view .LVU635 + 2396 .loc 1 688 28 is_stmt 0 view .LVU636 + 2397 01b8 E401 lsls r4, r4, #7 + 2398 .LVL307: + 2399 .loc 1 688 38 view .LVU637 + 2400 01ba EB01 lsls r3, r5, #7 + 2401 01bc 9A46 mov r10, r3 + 2402 .loc 1 688 42 view .LVU638 + 2403 01be 3100 movs r1, r6 + 2404 01c0 1800 movs r0, r3 + 2405 01c2 FFF7FEFF bl __aeabi_uidiv + 2406 .LVL308: + 2407 .loc 1 688 32 view .LVU639 + 2408 01c6 2418 adds r4, r4, r0 + 2409 .loc 1 688 14 view .LVU640 + 2410 01c8 254B ldr r3, .L110+36 + 2411 01ca 9C46 mov ip, r3 + 2412 01cc 6444 add r4, r4, ip + 2413 .LVL309: + 689:Core/Src/si5351.c **** uint32_t msnx_p2 = 128 * b - c * (128 * b / c); + 2414 .loc 1 689 5 is_stmt 1 view .LVU641 + 2415 .loc 1 689 14 is_stmt 0 view .LVU642 + 2416 01ce 3100 movs r1, r6 + 2417 01d0 5046 mov r0, r10 + 2418 01d2 FFF7FEFF bl __aeabi_uidivmod + 2419 .LVL310: + 690:Core/Src/si5351.c **** uint32_t msnx_p3 = c; + 2420 .loc 1 690 5 is_stmt 1 view .LVU643 + 691:Core/Src/si5351.c **** + 692:Core/Src/si5351.c **** // Feedback Multisynth Divider registers + 693:Core/Src/si5351.c **** regs[0] = (msnx_p3 >> 8) & 0xFF; + 2421 .loc 1 693 5 view .LVU644 + 2422 .loc 1 693 24 is_stmt 0 view .LVU645 + 2423 01d6 320A lsrs r2, r6, #8 + 2424 .loc 1 693 13 view .LVU646 + 2425 01d8 0023 movs r3, #0 + 2426 01da 1A70 strb r2, [r3] + 694:Core/Src/si5351.c **** regs[1] = msnx_p3 & 0xFF; + 2427 .loc 1 694 5 is_stmt 1 view .LVU647 + 2428 .loc 1 694 13 is_stmt 0 view .LVU648 + 2429 01dc 5E70 strb r6, [r3, #1] + 695:Core/Src/si5351.c **** regs[2] = (msnx_p1 >> 16) & 0x03; + 2430 .loc 1 695 5 is_stmt 1 view .LVU649 + 2431 .loc 1 695 24 is_stmt 0 view .LVU650 + 2432 01de 200C lsrs r0, r4, #16 + 2433 .loc 1 695 31 view .LVU651 + ARM GAS /tmp/ccV7ORbp.s page 65 + + + 2434 01e0 0322 movs r2, #3 + 2435 01e2 1040 ands r0, r2 + 2436 .loc 1 695 13 view .LVU652 + 2437 01e4 9870 strb r0, [r3, #2] + 696:Core/Src/si5351.c **** regs[3] = (msnx_p1 >> 8) & 0xFF; + 2438 .loc 1 696 5 is_stmt 1 view .LVU653 + 2439 .loc 1 696 24 is_stmt 0 view .LVU654 + 2440 01e6 200A lsrs r0, r4, #8 + 2441 .loc 1 696 13 view .LVU655 + 2442 01e8 D870 strb r0, [r3, #3] + 697:Core/Src/si5351.c **** regs[4] = msnx_p1 & 0xFF; + 2443 .loc 1 697 5 is_stmt 1 view .LVU656 + 2444 .loc 1 697 13 is_stmt 0 view .LVU657 + 2445 01ea 1C71 strb r4, [r3, #4] + 698:Core/Src/si5351.c **** regs[5] = ((msnx_p3 >> 12) & 0xF0) + ((msnx_p2 >> 16) & 0x0F); + 2446 .loc 1 698 5 is_stmt 1 view .LVU658 + 2447 .loc 1 698 25 is_stmt 0 view .LVU659 + 2448 01ec 360B lsrs r6, r6, #12 + 2449 .LVL311: + 2450 .loc 1 698 32 view .LVU660 + 2451 01ee 0F20 movs r0, #15 + 2452 01f0 8643 bics r6, r0 + 2453 01f2 F6B2 uxtb r6, r6 + 2454 .loc 1 698 52 view .LVU661 + 2455 01f4 0C0C lsrs r4, r1, #16 + 2456 .LVL312: + 2457 .loc 1 698 59 view .LVU662 + 2458 01f6 2040 ands r0, r4 + 2459 .loc 1 698 40 view .LVU663 + 2460 01f8 0643 orrs r6, r0 + 2461 .loc 1 698 13 view .LVU664 + 2462 01fa 5E71 strb r6, [r3, #5] + 699:Core/Src/si5351.c **** regs[6] = (msnx_p2 >> 8) & 0xFF; + 2463 .loc 1 699 5 is_stmt 1 view .LVU665 + 2464 .loc 1 699 24 is_stmt 0 view .LVU666 + 2465 01fc 080A lsrs r0, r1, #8 + 2466 .loc 1 699 13 view .LVU667 + 2467 01fe 9871 strb r0, [r3, #6] + 700:Core/Src/si5351.c **** regs[7] = msnx_p2 & 0xFF; + 2468 .loc 1 700 5 is_stmt 1 view .LVU668 + 2469 .loc 1 700 13 is_stmt 0 view .LVU669 + 2470 0200 D971 strb r1, [r3, #7] + 701:Core/Src/si5351.c **** + 702:Core/Src/si5351.c **** // Output Multisynth Divider registers + 703:Core/Src/si5351.c **** regs[8] = 0; // (msx_p3 >> 8) & 0xFF + 2471 .loc 1 703 5 is_stmt 1 view .LVU670 + 2472 .loc 1 703 13 is_stmt 0 view .LVU671 + 2473 0202 0021 movs r1, #0 + 2474 .LVL313: + 2475 .loc 1 703 13 view .LVU672 + 2476 0204 1972 strb r1, [r3, #8] + 704:Core/Src/si5351.c **** regs[9] = 1; // msx_p3 & 0xFF + 2477 .loc 1 704 5 is_stmt 1 view .LVU673 + 2478 .loc 1 704 13 is_stmt 0 view .LVU674 + 2479 0206 5F72 strb r7, [r3, #9] + 705:Core/Src/si5351.c **** regs[10] = rx_div + msx_divby4 + ((msx_p1 >> 16) & 0x03); + 2480 .loc 1 705 5 is_stmt 1 view .LVU675 + ARM GAS /tmp/ccV7ORbp.s page 66 + + + 2481 .loc 1 705 23 is_stmt 0 view .LVU676 + 2482 0208 029D ldr r5, [sp, #8] + 2483 .LVL314: + 2484 .loc 1 705 23 view .LVU677 + 2485 020a 0398 ldr r0, [sp, #12] + 2486 020c 8446 mov ip, r0 + 2487 020e 6544 add r5, r5, ip + 2488 0210 EDB2 uxtb r5, r5 + 2489 .loc 1 705 47 view .LVU678 + 2490 0212 4846 mov r0, r9 + 2491 0214 000C lsrs r0, r0, #16 + 2492 .loc 1 705 54 view .LVU679 + 2493 0216 0240 ands r2, r0 + 2494 .loc 1 705 36 view .LVU680 + 2495 0218 AD18 adds r5, r5, r2 + 2496 021a EDB2 uxtb r5, r5 + 2497 .loc 1 705 14 view .LVU681 + 2498 021c 9D72 strb r5, [r3, #10] + 706:Core/Src/si5351.c **** regs[11] = (msx_p1 >> 8) & 0xFF; + 2499 .loc 1 706 5 is_stmt 1 view .LVU682 + 2500 .loc 1 706 24 is_stmt 0 view .LVU683 + 2501 021e 4A46 mov r2, r9 + 2502 0220 120A lsrs r2, r2, #8 + 2503 .loc 1 706 14 view .LVU684 + 2504 0222 DA72 strb r2, [r3, #11] + 707:Core/Src/si5351.c **** regs[12] = msx_p1 & 0xFF; + 2505 .loc 1 707 5 is_stmt 1 view .LVU685 + 2506 .loc 1 707 14 is_stmt 0 view .LVU686 + 2507 0224 4A46 mov r2, r9 + 2508 0226 1A73 strb r2, [r3, #12] + 708:Core/Src/si5351.c **** regs[13] = 0; // ((msx_p3 >> 12) & 0xF0) + (msx_p2 >> 16) & 0x0 + 2509 .loc 1 708 5 is_stmt 1 view .LVU687 + 2510 .loc 1 708 14 is_stmt 0 view .LVU688 + 2511 0228 5973 strb r1, [r3, #13] + 709:Core/Src/si5351.c **** regs[14] = 0; // (msx_p2 >> 8) & 0xFF + 2512 .loc 1 709 5 is_stmt 1 view .LVU689 + 2513 .loc 1 709 14 is_stmt 0 view .LVU690 + 2514 022a 9973 strb r1, [r3, #14] + 710:Core/Src/si5351.c **** regs[15] = 0; // msx_p2 & 0xFF + 2515 .loc 1 710 5 is_stmt 1 view .LVU691 + 2516 .loc 1 710 14 is_stmt 0 view .LVU692 + 2517 022c D973 strb r1, [r3, #15] + 711:Core/Src/si5351.c **** + 712:Core/Src/si5351.c **** return; + 2518 .loc 1 712 5 is_stmt 1 view .LVU693 + 713:Core/Src/si5351.c **** } + 2519 .loc 1 713 1 is_stmt 0 view .LVU694 + 2520 022e 05B0 add sp, sp, #20 + 2521 @ sp needed + 2522 .LVL315: + 2523 .LVL316: + 2524 .loc 1 713 1 view .LVU695 + 2525 0230 F0BC pop {r4, r5, r6, r7} + 2526 0232 BB46 mov fp, r7 + 2527 0234 B246 mov r10, r6 + 2528 0236 A946 mov r9, r5 + 2529 0238 A046 mov r8, r4 + ARM GAS /tmp/ccV7ORbp.s page 67 + + + 2530 023a F0BD pop {r4, r5, r6, r7, pc} + 2531 .L111: + 2532 .align 2 + 2533 .L110: + 2534 023c 80D1F008 .word 150000000 + 2535 0240 68780400 .word 292968 + 2536 0244 A3E1C141 .word 1103225251 + 2537 0248 FF45C323 .word 599999999 + 2538 024c FCFFFF01 .word 33554428 + 2539 0250 60E37641 .word 1098310496 + 2540 0254 FEFF2F41 .word 1093664766 + 2541 0258 0000E03F .word 1071644672 + 2542 025c FFFF0F00 .word 1048575 + 2543 0260 00FEFFFF .word -512 + 2544 .cfi_endproc + 2545 .LFE306: + 2547 .global m_si5351Config + 2548 .section .bss.m_si5351Config,"aw",%nobits + 2549 .align 2 + 2550 .set .LANCHOR0,. + 0 + 2553 m_si5351Config: + 2554 0000 00000000 .space 56 + 2554 00000000 + 2554 00000000 + 2554 00000000 + 2554 00000000 + 2555 .text + 2556 .Letext0: + 2557 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 2558 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 2559 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 2560 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 2561 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h" + 2562 .file 7 "Core/Inc/si5351_errors.h" + 2563 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 2564 .file 9 "Core/Inc/si5351.h" + 2565 .file 10 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + 2566 .file 11 "/usr/include/newlib/math.h" + ARM GAS /tmp/ccV7ORbp.s page 68 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 si5351.c + /tmp/ccV7ORbp.s:16 .text.si5351_write8:0000000000000000 $t + /tmp/ccV7ORbp.s:24 .text.si5351_write8:0000000000000000 si5351_write8 + /tmp/ccV7ORbp.s:85 .text.si5351_write8:000000000000003c $d + /tmp/ccV7ORbp.s:90 .text.si5351_Init:0000000000000000 $t + /tmp/ccV7ORbp.s:97 .text.si5351_Init:0000000000000000 si5351_Init + /tmp/ccV7ORbp.s:326 .text.si5351_Init:00000000000000b8 $d + /tmp/ccV7ORbp.s:344 .text.si5351_setupPLL:0000000000000000 $t + /tmp/ccV7ORbp.s:351 .text.si5351_setupPLL:0000000000000000 si5351_setupPLL + /tmp/ccV7ORbp.s:881 .text.si5351_setupPLL:0000000000000234 $d + /tmp/ccV7ORbp.s:886 .text.si5351_setupPLLInt:0000000000000000 $t + /tmp/ccV7ORbp.s:893 .text.si5351_setupPLLInt:0000000000000000 si5351_setupPLLInt + /tmp/ccV7ORbp.s:919 .text.si5351_setupMultisynth:0000000000000000 $t + /tmp/ccV7ORbp.s:926 .text.si5351_setupMultisynth:0000000000000000 si5351_setupMultisynth + /tmp/ccV7ORbp.s:1543 .text.si5351_setupMultisynth:000000000000029c $d + /tmp/ccV7ORbp.s:1549 .text.si5351_setupMultisynthInt:0000000000000000 $t + /tmp/ccV7ORbp.s:1556 .text.si5351_setupMultisynthInt:0000000000000000 si5351_setupMultisynthInt + /tmp/ccV7ORbp.s:1586 .text.si5351_enableOutputs:0000000000000000 $t + /tmp/ccV7ORbp.s:1593 .text.si5351_enableOutputs:0000000000000000 si5351_enableOutputs + /tmp/ccV7ORbp.s:1650 .text.si5351_enableOutputs:0000000000000020 $d + /tmp/ccV7ORbp.s:1655 .text.si5351_read8:0000000000000000 $t + /tmp/ccV7ORbp.s:1662 .text.si5351_read8:0000000000000000 si5351_read8 + /tmp/ccV7ORbp.s:1719 .text.si5351_read8:0000000000000038 $d + /tmp/ccV7ORbp.s:1724 .text.si5351_setupRdiv:0000000000000000 $t + /tmp/ccV7ORbp.s:1731 .text.si5351_setupRdiv:0000000000000000 si5351_setupRdiv + /tmp/ccV7ORbp.s:1824 .rodata.si5351_setupRdiv:0000000000000000 $d + /tmp/ccV7ORbp.s:1977 .text.si5351_setupRdiv:00000000000000bc $d + /tmp/ccV7ORbp.s:1987 .text.CalcRegisters:0000000000000000 $t + /tmp/ccV7ORbp.s:1994 .text.CalcRegisters:0000000000000000 CalcRegisters + /tmp/ccV7ORbp.s:2534 .text.CalcRegisters:000000000000023c $d + /tmp/ccV7ORbp.s:2553 .bss.m_si5351Config:0000000000000000 m_si5351Config + /tmp/ccV7ORbp.s:2549 .bss.m_si5351Config:0000000000000000 $d + +UNDEFINED SYMBOLS +HAL_I2C_IsDeviceReady +HAL_I2C_Mem_Write +hi2c2 +__aeabi_ui2f +__aeabi_fdiv +__aeabi_fmul +__aeabi_f2d +__aeabi_i2d +__aeabi_dadd +__aeabi_dsub +__aeabi_d2uiz +__aeabi_ui2d +__aeabi_dmul +__aeabi_i2f +__aeabi_fadd +floor +HAL_I2C_Mem_Read +__aeabi_ddiv +__aeabi_d2iz +__aeabi_uidiv +__aeabi_uidivmod +HAL_Delay + ARM GAS /tmp/ccV7ORbp.s page 69 + + diff --git a/squero/build/si5351.o b/squero/build/si5351.o new file mode 100644 index 0000000000000000000000000000000000000000..f15e2d57065d472cc5f15c404d3ef317e8bda20c GIT binary patch literal 42784 zcmdVDd3;pW{r`XNY{`(ogd}V+!i0nnw(NwkXB|ia*};HI%nH$vU>1zlDxyV;eiX$j zDhjpkOFzg*Ep;m{txK&!wHDCY*s7>?Yire3E5Fz4-1nWiGr>>4kMHmI&+o#?^PKm2 zpZD3%J@?+3xfhkM2pEQ;tiw!<|HCr9}*YM`lQ=K=Js8_!n-i5zk46B*y;KjqP`M)-94j9*}o00C|zTu?lDWhK4 zSEyJ^&t!G*wc)q-4JBKl-wdA`I4RbdGO1{PQ1%RDlaS`CpyW|Vj_fNu*-EuoH zdSmGe`;42DVtuIzMUzU0g0VjtHg0D6{Xxl1!)FI3o%dBReC_a_lm~S$utZl3v#iaB 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build/stm32g0xx_hal_tim.o +LOAD build/stm32g0xx_hal_tim_ex.o +LOAD build/system_stm32g0xx.o +LOAD build/startup_stm32g031xx.o +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000020002000 _estack = 0x20002000 + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xbc + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xbc build/startup_stm32g031xx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000bc . = ALIGN (0x4) + +.text 0x00000000080000bc 0x491c + 0x00000000080000bc . = ALIGN (0x4) + *(.text) + .text 0x00000000080000bc 0x98 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000008000154 0x44 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + 0x0000000008000154 __libc_init_array + .text 0x0000000008000198 0xa8 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + 0x0000000008000198 memset + .text 0x0000000008000240 0x138 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) + 0x0000000008000240 floor + .text 0x0000000008000378 0x114 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.data.uwTickFreq + 0x0000000020000000 0x1 build/stm32g0xx_hal.o + 0x0000000020000000 uwTickFreq + *fill* 0x0000000020000001 0x3 + .data.uwTickPrio + 0x0000000020000004 0x4 build/stm32g0xx_hal.o + 0x0000000020000004 uwTickPrio + .data.SystemCoreClock + 0x0000000020000008 0x4 build/system_stm32g0xx.o + 0x0000000020000008 SystemCoreClock + 0x000000002000000c . = ALIGN (0x4) + 0x000000002000000c _edata = . + +.tm_clone_table + 0x000000002000000c 0x0 load address 0x0000000008004b8c + .tm_clone_table + 0x000000002000000c 0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + .tm_clone_table + 0x000000002000000c 0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtend.o + +.igot.plt 0x000000002000000c 0x0 load address 0x0000000008004b8c + .igot.plt 0x000000002000000c 0x0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + 0x000000002000000c . = ALIGN (0x4) + +.bss 0x000000002000000c 0xa8 load address 0x0000000008004b8c + 0x000000002000000c _sbss = . + 0x000000002000000c __bss_start__ = _sbss + *(.bss) + .bss 0x000000002000000c 0x1c /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + *(.bss*) + .bss.frequenza + 0x0000000020000028 0x4 build/main.o + 0x0000000020000028 frequenza + .bss.hi2c2 0x000000002000002c 0x4c build/main.o + 0x000000002000002c hi2c2 + .bss.m_si5351Config + 0x0000000020000078 0x38 build/si5351.o + 0x0000000020000078 m_si5351Config + .bss.uwTick 0x00000000200000b0 0x4 build/stm32g0xx_hal.o + 0x00000000200000b0 uwTick + *(COMMON) + 0x00000000200000b4 . = ALIGN (0x4) + 0x00000000200000b4 _ebss = . + 0x00000000200000b4 __bss_end__ = _ebss + +._user_heap_stack + 0x00000000200000b4 0x604 load address 0x0000000008004b8c + 0x00000000200000b8 . = ALIGN (0x8) + *fill* 0x00000000200000b4 0x4 + [!provide] PROVIDE (end = .) + [!provide] PROVIDE (_end = .) + 0x00000000200002b8 . = (. + _Min_Heap_Size) + *fill* 0x00000000200000b8 0x200 + 0x00000000200006b8 . = (. + _Min_Stack_Size) + *fill* 0x00000000200002b8 0x400 + 0x00000000200006b8 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crti.o + .ARM.attributes + 0x000000000000001e 0x2c /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + .ARM.attributes + 0x000000000000004a 0x2c build/main.o + .ARM.attributes + 0x0000000000000076 0x2c build/si5351.o + .ARM.attributes + 0x00000000000000a2 0x2c build/stm32g0xx_it.o + .ARM.attributes + 0x00000000000000ce 0x2c build/stm32g0xx_hal_msp.o + .ARM.attributes + 0x00000000000000fa 0x2c build/stm32g0xx_hal_i2c.o + .ARM.attributes + 0x0000000000000126 0x2c build/stm32g0xx_hal_i2c_ex.o + .ARM.attributes + 0x0000000000000152 0x2c build/stm32g0xx_hal_rcc.o + .ARM.attributes + 0x000000000000017e 0x2c build/stm32g0xx_hal_gpio.o + .ARM.attributes + 0x00000000000001aa 0x2c build/stm32g0xx_hal_pwr_ex.o + .ARM.attributes + 0x00000000000001d6 0x2c build/stm32g0xx_hal_cortex.o + .ARM.attributes + 0x0000000000000202 0x2c build/stm32g0xx_hal.o + .ARM.attributes + 0x000000000000022e 0x2c build/system_stm32g0xx.o + .ARM.attributes + 0x000000000000025a 0x22 build/startup_stm32g031xx.o + .ARM.attributes + 0x000000000000027c 0x2c /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x00000000000002a8 0x2c /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x00000000000002d4 0x2c /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) + .ARM.attributes + 0x0000000000000300 0x1e /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .ARM.attributes + 0x000000000000031e 0x1e /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000000000000033c 0x1e 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/usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(extendsfdf2.o) + .ARM.attributes + 0x0000000000000646 0x1e /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .ARM.attributes + 0x0000000000000664 0x2c /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtend.o + .ARM.attributes + 0x0000000000000690 0x1e /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(build/squero.elf elf32-littlearm) +LOAD linker stubs +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +LOAD /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a + +.comment 0x0000000000000000 0x66 + .comment 0x0000000000000000 0x33 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o + 0x34 (size before relaxing) + .comment 0x0000000000000033 0x34 build/main.o + .comment 0x0000000000000033 0x34 build/si5351.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_it.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_msp.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_i2c.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_i2c_ex.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_rcc.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_gpio.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_pwr_ex.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal_cortex.o + .comment 0x0000000000000033 0x34 build/stm32g0xx_hal.o + .comment 0x0000000000000033 0x34 build/system_stm32g0xx.o + .comment 0x0000000000000033 0x33 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + 0x34 (size before relaxing) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(adddf3.o) + .comment 0x0000000000000066 0x34 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divdf3.o) + .comment 0x0000000000000066 0x34 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build/stm32g0xx_hal_flash.o +HAL_FLASH_IRQHandler build/stm32g0xx_hal_flash.o +HAL_FLASH_Lock build/stm32g0xx_hal_flash.o +HAL_FLASH_OB_Launch build/stm32g0xx_hal_flash.o +HAL_FLASH_OB_Lock build/stm32g0xx_hal_flash.o +HAL_FLASH_OB_Unlock build/stm32g0xx_hal_flash.o +HAL_FLASH_OperationErrorCallback build/stm32g0xx_hal_flash.o +HAL_FLASH_Program build/stm32g0xx_hal_flash.o +HAL_FLASH_Program_IT build/stm32g0xx_hal_flash.o +HAL_FLASH_Unlock build/stm32g0xx_hal_flash.o +HAL_GPIO_DeInit build/stm32g0xx_hal_gpio.o + build/stm32g0xx_hal_msp.o +HAL_GPIO_EXTI_Falling_Callback build/stm32g0xx_hal_gpio.o +HAL_GPIO_EXTI_IRQHandler build/stm32g0xx_hal_gpio.o +HAL_GPIO_EXTI_Rising_Callback build/stm32g0xx_hal_gpio.o +HAL_GPIO_Init build/stm32g0xx_hal_gpio.o + build/stm32g0xx_hal_rcc_ex.o + build/stm32g0xx_hal_rcc.o + build/stm32g0xx_hal_msp.o + build/main.o +HAL_GPIO_LockPin build/stm32g0xx_hal_gpio.o +HAL_GPIO_ReadPin build/stm32g0xx_hal_gpio.o + build/main.o +HAL_GPIO_TogglePin build/stm32g0xx_hal_gpio.o +HAL_GPIO_WritePin build/stm32g0xx_hal_gpio.o +HAL_GetDEVID build/stm32g0xx_hal.o +HAL_GetHalVersion build/stm32g0xx_hal.o +HAL_GetREVID build/stm32g0xx_hal.o +HAL_GetTick build/stm32g0xx_hal.o + build/stm32g0xx_hal_dma.o + build/stm32g0xx_hal_flash.o + build/stm32g0xx_hal_rcc_ex.o + build/stm32g0xx_hal_rcc.o + build/stm32g0xx_hal_i2c.o +HAL_GetTickFreq build/stm32g0xx_hal.o +HAL_GetTickPrio build/stm32g0xx_hal.o +HAL_GetUIDw0 build/stm32g0xx_hal.o +HAL_GetUIDw1 build/stm32g0xx_hal.o +HAL_GetUIDw2 build/stm32g0xx_hal.o +HAL_I2CEx_ConfigAnalogFilter build/stm32g0xx_hal_i2c_ex.o + build/main.o +HAL_I2CEx_ConfigDigitalFilter build/stm32g0xx_hal_i2c_ex.o + build/main.o +HAL_I2CEx_DisableFastModePlus build/stm32g0xx_hal_i2c_ex.o +HAL_I2CEx_DisableWakeUp build/stm32g0xx_hal_i2c_ex.o +HAL_I2CEx_EnableFastModePlus build/stm32g0xx_hal_i2c_ex.o +HAL_I2CEx_EnableWakeUp build/stm32g0xx_hal_i2c_ex.o +HAL_I2C_AbortCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_AddrCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_DeInit build/stm32g0xx_hal_i2c.o +HAL_I2C_DisableListen_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_ER_IRQHandler build/stm32g0xx_hal_i2c.o +HAL_I2C_EV_IRQHandler build/stm32g0xx_hal_i2c.o +HAL_I2C_EnableListen_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_ErrorCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_GetError build/stm32g0xx_hal_i2c.o +HAL_I2C_GetMode build/stm32g0xx_hal_i2c.o +HAL_I2C_GetState build/stm32g0xx_hal_i2c.o +HAL_I2C_Init build/stm32g0xx_hal_i2c.o + build/main.o +HAL_I2C_IsDeviceReady build/stm32g0xx_hal_i2c.o + build/si5351.o +HAL_I2C_ListenCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_MasterRxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_MasterTxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Abort_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Receive build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Receive_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Receive_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Transmit build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Transmit_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Master_Transmit_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_MemRxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_MemTxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_Mem_Read build/stm32g0xx_hal_i2c.o + build/si5351.o +HAL_I2C_Mem_Read_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Mem_Read_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Mem_Write build/stm32g0xx_hal_i2c.o + build/si5351.o +HAL_I2C_Mem_Write_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Mem_Write_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_MspDeInit build/stm32g0xx_hal_msp.o +HAL_I2C_MspInit build/stm32g0xx_hal_msp.o +HAL_I2C_SlaveRxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_SlaveTxCpltCallback build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Receive build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Receive_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Receive_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_IT build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Transmit build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Transmit_DMA build/stm32g0xx_hal_i2c.o +HAL_I2C_Slave_Transmit_IT build/stm32g0xx_hal_i2c.o +HAL_IncTick build/stm32g0xx_hal.o + build/stm32g0xx_it.o +HAL_Init build/stm32g0xx_hal.o + build/main.o +HAL_InitTick build/stm32g0xx_hal.o + build/stm32g0xx_hal_rcc.o +HAL_MPU_ConfigRegion build/stm32g0xx_hal_cortex.o +HAL_MPU_Disable build/stm32g0xx_hal_cortex.o +HAL_MPU_Enable build/stm32g0xx_hal_cortex.o +HAL_MspDeInit build/stm32g0xx_hal.o +HAL_MspInit build/stm32g0xx_hal_msp.o +HAL_NVIC_ClearPendingIRQ build/stm32g0xx_hal_cortex.o +HAL_NVIC_DisableIRQ build/stm32g0xx_hal_cortex.o +HAL_NVIC_EnableIRQ build/stm32g0xx_hal_cortex.o +HAL_NVIC_GetPendingIRQ build/stm32g0xx_hal_cortex.o +HAL_NVIC_GetPriority build/stm32g0xx_hal_cortex.o +HAL_NVIC_SetPendingIRQ build/stm32g0xx_hal_cortex.o +HAL_NVIC_SetPriority build/stm32g0xx_hal_cortex.o + build/stm32g0xx_hal.o +HAL_NVIC_SystemReset build/stm32g0xx_hal_cortex.o +HAL_PWREx_ConfigPVD build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_ControlVoltageScaling build/stm32g0xx_hal_pwr_ex.o + build/main.o +HAL_PWREx_DisableBatteryCharging build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableFlashPowerDown build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableGPIOPullDown build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableGPIOPullUp build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableInternalWakeUpLine build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableLowPowerRunMode build/stm32g0xx_hal_pwr_ex.o + build/stm32g0xx_hal_pwr.o +HAL_PWREx_DisablePORMonitorSampling build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisablePVD build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisablePullUpPullDownConfig build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_DisableSRAMRetention build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableBatteryCharging build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableFlashPowerDown build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableGPIOPullDown build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableGPIOPullUp build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableInternalWakeUpLine build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableLowPowerRunMode build/stm32g0xx_hal_pwr_ex.o + build/stm32g0xx_hal_pwr.o +HAL_PWREx_EnablePORMonitorSampling build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnablePVD build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnablePullUpPullDownConfig build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnableSRAMRetention build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_EnterSHUTDOWNMode build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_GetVoltageRange build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_PVD_Falling_Callback build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_PVD_IRQHandler build/stm32g0xx_hal_pwr_ex.o +HAL_PWREx_PVD_Rising_Callback build/stm32g0xx_hal_pwr_ex.o +HAL_PWR_DeInit build/stm32g0xx_hal_pwr.o +HAL_PWR_DisableBkUpAccess build/stm32g0xx_hal_pwr.o + build/stm32g0xx_hal_rcc_ex.o +HAL_PWR_DisableSEVOnPend build/stm32g0xx_hal_pwr.o +HAL_PWR_DisableSleepOnExit build/stm32g0xx_hal_pwr.o +HAL_PWR_DisableWakeUpPin build/stm32g0xx_hal_pwr.o +HAL_PWR_EnableBkUpAccess build/stm32g0xx_hal_pwr.o + build/stm32g0xx_hal_rcc_ex.o +HAL_PWR_EnableSEVOnPend build/stm32g0xx_hal_pwr.o +HAL_PWR_EnableSleepOnExit build/stm32g0xx_hal_pwr.o +HAL_PWR_EnableWakeUpPin build/stm32g0xx_hal_pwr.o +HAL_PWR_EnterSLEEPMode build/stm32g0xx_hal_pwr.o +HAL_PWR_EnterSTANDBYMode build/stm32g0xx_hal_pwr.o +HAL_PWR_EnterSTOPMode build/stm32g0xx_hal_pwr.o +HAL_RCCEx_DisableLSCO build/stm32g0xx_hal_rcc_ex.o +HAL_RCCEx_EnableLSCO build/stm32g0xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKConfig build/stm32g0xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKFreq build/stm32g0xx_hal_rcc_ex.o +HAL_RCCEx_PeriphCLKConfig build/stm32g0xx_hal_rcc_ex.o +HAL_RCC_CSSCallback build/stm32g0xx_hal_rcc.o +HAL_RCC_ClockConfig build/stm32g0xx_hal_rcc.o + build/main.o +HAL_RCC_DeInit build/stm32g0xx_hal_rcc.o +HAL_RCC_DisableLSECSS build/stm32g0xx_hal_rcc.o +HAL_RCC_EnableCSS build/stm32g0xx_hal_rcc.o +HAL_RCC_EnableLSECSS build/stm32g0xx_hal_rcc.o +HAL_RCC_GetClockConfig build/stm32g0xx_hal_rcc.o +HAL_RCC_GetHCLKFreq build/stm32g0xx_hal_rcc.o +HAL_RCC_GetOscConfig build/stm32g0xx_hal_rcc.o +HAL_RCC_GetPCLK1Freq build/stm32g0xx_hal_rcc.o + build/stm32g0xx_hal_rcc_ex.o +HAL_RCC_GetResetSource build/stm32g0xx_hal_rcc.o +HAL_RCC_GetSysClockFreq build/stm32g0xx_hal_rcc.o + build/stm32g0xx_hal_rcc_ex.o +HAL_RCC_LSECSSCallback build/stm32g0xx_hal_rcc.o +HAL_RCC_MCOConfig build/stm32g0xx_hal_rcc.o +HAL_RCC_NMI_IRQHandler build/stm32g0xx_hal_rcc.o +HAL_RCC_OscConfig build/stm32g0xx_hal_rcc.o + build/main.o +HAL_ResumeTick build/stm32g0xx_hal.o +HAL_SYSCFG_DisableClampingDiode build/stm32g0xx_hal.o +HAL_SYSCFG_DisableIOAnalogSwitchBooster build/stm32g0xx_hal.o +HAL_SYSCFG_DisableRemap build/stm32g0xx_hal.o +HAL_SYSCFG_DisableVREFBUF build/stm32g0xx_hal.o +HAL_SYSCFG_EnableClampingDiode build/stm32g0xx_hal.o +HAL_SYSCFG_EnableIOAnalogSwitchBooster build/stm32g0xx_hal.o +HAL_SYSCFG_EnableRemap build/stm32g0xx_hal.o +HAL_SYSCFG_EnableVREFBUF build/stm32g0xx_hal.o +HAL_SYSCFG_VREFBUF_HighImpedanceConfig build/stm32g0xx_hal.o +HAL_SYSCFG_VREFBUF_TrimmingConfig build/stm32g0xx_hal.o +HAL_SYSCFG_VREFBUF_VoltageScalingConfig build/stm32g0xx_hal.o +HAL_SYSTICK_CLKSourceConfig build/stm32g0xx_hal_cortex.o +HAL_SYSTICK_Callback build/stm32g0xx_hal_cortex.o +HAL_SYSTICK_Config build/stm32g0xx_hal_cortex.o + build/stm32g0xx_hal.o +HAL_SYSTICK_IRQHandler build/stm32g0xx_hal_cortex.o +HAL_SetTickFreq build/stm32g0xx_hal.o +HAL_SuspendTick build/stm32g0xx_hal.o +HardFault_Handler build/stm32g0xx_it.o +I2C1_IRQHandler build/startup_stm32g031xx.o +I2C2_IRQHandler build/startup_stm32g031xx.o +LPTIM1_IRQHandler build/startup_stm32g031xx.o +LPTIM2_IRQHandler build/startup_stm32g031xx.o +LPUART1_IRQHandler build/startup_stm32g031xx.o +NMI_Handler build/stm32g0xx_it.o +PVD_IRQHandler build/startup_stm32g031xx.o +PendSV_Handler build/stm32g0xx_it.o +RCC_IRQHandler build/startup_stm32g031xx.o +RTC_TAMP_IRQHandler build/startup_stm32g031xx.o +Reset_Handler build/startup_stm32g031xx.o +SPI1_IRQHandler build/startup_stm32g031xx.o +SPI2_IRQHandler build/startup_stm32g031xx.o +SVC_Handler build/stm32g0xx_it.o +SysTick_Handler build/stm32g0xx_it.o +SystemClock_Config build/main.o +SystemCoreClock build/system_stm32g0xx.o + build/stm32g0xx_hal.o + build/stm32g0xx_hal_pwr_ex.o + build/stm32g0xx_hal_rcc.o +SystemCoreClockUpdate build/system_stm32g0xx.o +SystemInit build/system_stm32g0xx.o + build/startup_stm32g031xx.o +TIM14_IRQHandler build/startup_stm32g031xx.o +TIM16_IRQHandler build/startup_stm32g031xx.o +TIM17_IRQHandler build/startup_stm32g031xx.o +TIM1_BRK_UP_TRG_COM_IRQHandler build/startup_stm32g031xx.o +TIM1_CC_IRQHandler build/startup_stm32g031xx.o +TIM2_IRQHandler build/startup_stm32g031xx.o +TIM3_IRQHandler build/startup_stm32g031xx.o +USART1_IRQHandler build/startup_stm32g031xx.o +USART2_IRQHandler build/startup_stm32g031xx.o +WWDG_IRQHandler build/startup_stm32g031xx.o +_ITM_deregisterTMCloneTable /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +_ITM_registerTMCloneTable /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +__TMC_END__ /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtend.o + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +__aeabi_cdcmpeq /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_cdcmple /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_cdrcmple /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_d2iz /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(fixdfsi.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) + build/si5351.o +__aeabi_d2uiz /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) + build/si5351.o +__aeabi_dadd /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(adddf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) + build/si5351.o +__aeabi_dcmpeq /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_dcmpge /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) +__aeabi_dcmpgt /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) +__aeabi_dcmple /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_dcmplt /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__aeabi_ddiv /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divdf3.o) + build/si5351.o +__aeabi_dmul /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(muldf3.o) + build/si5351.o +__aeabi_dsub /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(subdf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) + build/si5351.o +__aeabi_f2d /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(extendsfdf2.o) + build/si5351.o +__aeabi_fadd /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o) + build/si5351.o +__aeabi_fdiv /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o) + build/si5351.o +__aeabi_fmul /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o) + build/si5351.o +__aeabi_i2d /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatsidf.o) + build/si5351.o +__aeabi_i2f /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o) + build/si5351.o +__aeabi_idiv0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) +__aeabi_ldiv0 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) +__aeabi_ui2d /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatunsidf.o) + build/si5351.o +__aeabi_ui2f /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o) + build/si5351.o +__aeabi_uidiv /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + build/system_stm32g0xx.o + build/stm32g0xx_hal.o + build/stm32g0xx_hal_pwr_ex.o + build/stm32g0xx_hal_dma.o + build/stm32g0xx_hal_rcc_ex.o + build/stm32g0xx_hal_rcc.o + build/si5351.o +__aeabi_uidivmod /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divdf3.o) + build/si5351.o +__atexit_dummy /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) +__bss_end__ /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +__bss_start__ /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +__call_exitprocs /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) +__clzsi2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(extendsfdf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatunsidf.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatsidf.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(subdf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(muldf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divdf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(adddf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatunsisf.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(floatsisf.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(mulsf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(divsf3.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(addsf3.o) +__deregister_frame_info /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +__dso_handle /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +__eqdf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(eqdf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__fini_array_end /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-fini.o) +__fini_array_start /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-fini.o) +__fixunsdfsi /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_fixunsdfsi.o) +__gedf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(gedf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__gtdf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(gedf2.o) +__init_array_end /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) +__init_array_start /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) +__ledf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(ledf2.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_arm_cmpdf2.o) +__libc_fini_array /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +__libc_init_array /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + build/startup_stm32g031xx.o + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +__ltdf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(ledf2.o) +__nedf2 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(eqdf2.o) +__on_exit_args /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) +__preinit_array_end /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) +__preinit_array_start /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) +__register_exitproc /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-atexit.o) +__register_frame_info /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crtbegin.o +__sf_fake_stderr /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) +__sf_fake_stdin /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) +__sf_fake_stdout /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) +__stack /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +__udivsi3 /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) +_ebss build/startup_stm32g031xx.o +_edata build/startup_stm32g031xx.o +_estack build/startup_stm32g031xx.o +_exit /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a(_exit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) +_fini /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crti.o + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-fini.o) +_global_atexit /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__call_atexit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) +_global_impure_ptr /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) +_impure_ptr /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) +_init /usr/lib/gcc/arm-none-eabi/10.3.1/thumb/v6-m/nofp/crti.o + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) +_mainCRTStartup /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +_sbss build/startup_stm32g031xx.o +_sdata build/startup_stm32g031xx.o +_sidata build/startup_stm32g031xx.o +_stack_init /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +_start /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +assert_failed build/main.o +atexit /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-atexit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +exit /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +floor /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a(lib_a-s_floor.o) + build/si5351.o +frequenza build/main.o +g_pfnVectors build/startup_stm32g031xx.o +hardware_init_hook /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +hi2c2 build/main.o + build/si5351.o +m_si5351Config build/si5351.o +main build/main.o + build/startup_stm32g031xx.o + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +malloc /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-__atexit.o) +memset /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + build/stm32g0xx_hal_msp.o + build/main.o + /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +pFlash build/stm32g0xx_hal_flash.o + build/stm32g0xx_hal_flash_ex.o +si5351_Init build/si5351.o + build/main.o +si5351_enableOutputs build/si5351.o + build/main.o +si5351_read8 build/si5351.o +si5351_setupMultisynth build/si5351.o +si5351_setupMultisynthInt build/si5351.o +si5351_setupPLL build/si5351.o +si5351_setupPLLInt build/si5351.o +si5351_setupRdiv build/si5351.o +si5351_write8 build/si5351.o +software_init_hook /usr/lib/gcc/arm-none-eabi/10.3.1/../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +uwTick build/stm32g0xx_hal.o +uwTickFreq build/stm32g0xx_hal.o +uwTickPrio build/stm32g0xx_hal.o + build/stm32g0xx_hal_rcc.o diff --git a/squero/build/startup_stm32g031xx.d b/squero/build/startup_stm32g031xx.d new file mode 100644 index 0000000..97f5a8d --- /dev/null +++ b/squero/build/startup_stm32g031xx.d @@ -0,0 +1 @@ +build/startup_stm32g031xx.o: startup_stm32g031xx.s diff --git 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© Copyright (c) 2018 STMicroelectronics. + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * All rights reserved.

+ 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This software component is licensed by ST under BSD 3-Clause license, + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * the "License"; You may not use this file except in compliance with the + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * License. You may obtain a copy of the License at: + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * opensource.org/licenses/BSD-3-Clause + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ****************************************************************************** + ARM GAS /tmp/ccQNWmKP.s page 2 + + + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Includes ------------------------------------------------------------------*/ + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #include "stm32g0xx_hal.h" + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup STM32G0xx_HAL_Driver + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief HAL module driver + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #ifdef HAL_MODULE_ENABLED + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Private typedef -----------------------------------------------------------*/ + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Private define ------------------------------------------------------------*/ + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @defgroup HAL_Private_Constants HAL Private Constants + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief STM32G0xx HAL Driver version number + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define __STM32G0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\ + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** |(__STM32G0xx_HAL_VERSION_RC)) + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #if defined(VREFBUF) + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #define VREFBUF_TIMEOUT_VALUE 10U /*!< 10 ms */ + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #endif /* VREFBUF */ + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @} + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Private macro -------------------------------------------------------------*/ + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Exported variables ---------------------------------------------------------*/ + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @defgroup HAL_Exported_Variables HAL Exported Variables + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __IO uint32_t uwTick; + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @} + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Private function prototypes -----------------------------------------------*/ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Exported functions --------------------------------------------------------*/ + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + ARM GAS /tmp/ccQNWmKP.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL_Exported_Functions + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group1 + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief HAL Initialization and Configuration functions + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @verbatim + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ##### HAL Initialization and Configuration functions ##### + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** [..] This section provides functions allowing to: + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Initialize the Flash interface the NVIC allocation and initial time base + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** clock configuration. + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) De-initialize common part of the HAL. + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Configure the time base source to have 1ms time base with a dedicated + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** Tick interrupt priority. + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (++) SysTick timer is used by default as source of time base, but user + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** can eventually implement his proper time base source (a general purpose + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** timer for example or other time source), keeping in mind that Time base + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** handled in milliseconds basis. + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (++) Time base configuration function (HAL_InitTick ()) is called automatically + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** at the beginning of the program after reset by HAL_Init() or at any time + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** when clock is configured, by HAL_RCC_ClockConfig(). + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (++) Source of time base is configured to generate interrupts at regular + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** time intervals. Care must be taken if HAL_Delay() is called from a + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** peripheral ISR process, the Tick interrupt line must have higher priority + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (numerically lower) than the peripheral interrupt. Otherwise the caller + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ISR process will be blocked. + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (++) functions affecting time base configurations are declared as __weak + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** to make override possible in case of other implementations in user file. + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @endverbatim + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Configure the Flash prefetch and the Instruction cache, + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * the time base source, NVIC and any required global low level hardware + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * by calling the HAL_MspInit() callback function to be optionally defined in user file + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * stm32g0xx_hal_msp.c. + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note HAL_Init() function is called at the beginning of program after reset and before + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * the clock configuration. + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation the System Timer (Systick) is used as source of time base + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * The Systick configuration is based on HSI clock, as HSI is the clock + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * used after a system Reset. + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * Once done, time base tick starts incrementing: the tick variable counter is incremented + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * each 1ms in the SysTick_Handler() interrupt handler. + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval HAL status + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef HAL_Init(void) + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + ARM GAS /tmp/ccQNWmKP.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Configure Flash prefetch, Instruction cache */ + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Default configuration at reset is: */ + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* - Prefetch disabled */ + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* - Instruction cache enabled */ + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #if (INSTRUCTION_CACHE_ENABLE == 0U) + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #endif /* INSTRUCTION_CACHE_ENABLE */ + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #if (PREFETCH_ENABLE != 0U) + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** status = HAL_ERROR; + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** else + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Init the low level hardware */ + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_MspInit(); + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Return function status */ + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return status; + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief This function de-Initializes common part of the HAL and stops the source of time base. + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is optional. + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval HAL status + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void) + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Reset of all peripherals */ + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB1_FORCE_RESET(); + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB2_FORCE_RESET(); + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_AHB_FORCE_RESET(); + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_IOP_FORCE_RESET(); + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_IOP_RELEASE_RESET(); + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* De-Init the low level hardware */ + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_MspDeInit(); + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Return function status */ + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return HAL_OK; + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Initialize the MSP. + ARM GAS /tmp/ccQNWmKP.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_MspInit(void) + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 27 .loc 1 207 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** the HAL_MspInit could be implemented in the user file + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 32 .loc 1 211 1 view .LVU1 + 33 @ sp needed + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE299: + 38 .section .text.HAL_MspDeInit,"ax",%progbits + 39 .align 1 + 40 .weak HAL_MspDeInit + 41 .syntax unified + 42 .code 16 + 43 .thumb_func + 44 .fpu softvfp + 46 HAL_MspDeInit: + 47 .LFB300: + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief DeInitializes the MSP. + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_MspDeInit(void) + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 48 .loc 1 218 1 view -0 + 49 .cfi_startproc + 50 @ args = 0, pretend = 0, frame = 0 + 51 @ frame_needed = 0, uses_anonymous_args = 0 + 52 @ link register save eliminated. + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** the HAL_MspDeInit could be implemented in the user file + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 53 .loc 1 222 1 view .LVU3 + 54 @ sp needed + 55 0000 7047 bx lr + 56 .cfi_endproc + 57 .LFE300: + 59 .section .text.HAL_DeInit,"ax",%progbits + 60 .align 1 + 61 .global HAL_DeInit + 62 .syntax unified + 63 .code 16 + 64 .thumb_func + 65 .fpu softvfp + 67 HAL_DeInit: + 68 .LFB298: + ARM GAS /tmp/ccQNWmKP.s page 6 + + + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Reset of all peripherals */ + 69 .loc 1 181 1 view -0 + 70 .cfi_startproc + 71 @ args = 0, pretend = 0, frame = 0 + 72 @ frame_needed = 0, uses_anonymous_args = 0 + 73 0000 10B5 push {r4, lr} + 74 .LCFI0: + 75 .cfi_def_cfa_offset 8 + 76 .cfi_offset 4, -8 + 77 .cfi_offset 14, -4 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 78 .loc 1 183 3 view .LVU5 + 79 0002 084B ldr r3, .L4 + 80 0004 0121 movs r1, #1 + 81 0006 4942 rsbs r1, r1, #0 + 82 0008 D962 str r1, [r3, #44] + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 83 .loc 1 184 3 view .LVU6 + 84 000a 0022 movs r2, #0 + 85 000c DA62 str r2, [r3, #44] + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 86 .loc 1 186 3 view .LVU7 + 87 000e 1963 str r1, [r3, #48] + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 88 .loc 1 187 3 view .LVU8 + 89 0010 1A63 str r2, [r3, #48] + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 90 .loc 1 189 3 view .LVU9 + 91 0012 9962 str r1, [r3, #40] + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 92 .loc 1 190 3 view .LVU10 + 93 0014 9A62 str r2, [r3, #40] + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __HAL_RCC_IOP_RELEASE_RESET(); + 94 .loc 1 192 3 view .LVU11 + 95 0016 5962 str r1, [r3, #36] + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 96 .loc 1 193 3 view .LVU12 + 97 0018 5A62 str r2, [r3, #36] + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 98 .loc 1 196 3 view .LVU13 + 99 001a FFF7FEFF bl HAL_MspDeInit + 100 .LVL0: + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 101 .loc 1 199 3 view .LVU14 + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 102 .loc 1 200 1 is_stmt 0 view .LVU15 + 103 001e 0020 movs r0, #0 + 104 @ sp needed + 105 0020 10BD pop {r4, pc} + 106 .L5: + 107 0022 C046 .align 2 + 108 .L4: + 109 0024 00100240 .word 1073876992 + 110 .cfi_endproc + 111 .LFE298: + 113 .global __aeabi_uidiv + 114 .section .text.HAL_InitTick,"ax",%progbits + ARM GAS /tmp/ccQNWmKP.s page 7 + + + 115 .align 1 + 116 .weak HAL_InitTick + 117 .syntax unified + 118 .code 16 + 119 .thumb_func + 120 .fpu softvfp + 122 HAL_InitTick: + 123 .LVL1: + 124 .LFB301: + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief This function configures the source of the time base: + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * The time source is configured to have 1ms time base with a dedicated + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * Tick interrupt priority. + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is called automatically at the beginning of program after + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation, SysTick timer is the source of time base. + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * It is used to generate interrupts at regular time intervals. + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * The SysTick interrupt must have higher priority (numerically lower) + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * The function is declared as __weak to be overwritten in case of other + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementation in user file. + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param TickPriority Tick interrupt priority. + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval HAL status + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 125 .loc 1 241 1 is_stmt 1 view -0 + 126 .cfi_startproc + 127 @ args = 0, pretend = 0, frame = 0 + 128 @ frame_needed = 0, uses_anonymous_args = 0 + 129 .loc 1 241 1 is_stmt 0 view .LVU17 + 130 0000 10B5 push {r4, lr} + 131 .LCFI1: + 132 .cfi_def_cfa_offset 8 + 133 .cfi_offset 4, -8 + 134 .cfi_offset 14, -4 + 135 0002 0400 movs r4, r0 + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 136 .loc 1 242 3 is_stmt 1 view .LVU18 + 137 .LVL2: + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the valu + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if ((uint32_t)uwTickFreq != 0U) + 138 .loc 1 245 3 view .LVU19 + 139 .loc 1 245 28 is_stmt 0 view .LVU20 + 140 0004 114B ldr r3, .L13 + 141 0006 1978 ldrb r1, [r3] + 142 .loc 1 245 6 view .LVU21 + 143 0008 0029 cmp r1, #0 + 144 000a 01D1 bne .L11 + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /*Configure the SysTick to have interrupt in 1ms time basis*/ + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Configure the SysTick IRQ priority */ + ARM GAS /tmp/ccQNWmKP.s page 8 + + + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uwTickPrio = TickPriority; + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** else + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** status = HAL_ERROR; + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** else + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** status = HAL_ERROR; + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** else + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** status = HAL_ERROR; + 145 .loc 1 268 12 view .LVU22 + 146 000c 0120 movs r0, #1 + 147 .LVL3: + 148 .L7: + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Return function status */ + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return status; + 149 .loc 1 272 3 is_stmt 1 view .LVU23 + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 150 .loc 1 273 1 is_stmt 0 view .LVU24 + 151 @ sp needed + 152 .LVL4: + 153 .loc 1 273 1 view .LVU25 + 154 000e 10BD pop {r4, pc} + 155 .LVL5: + 156 .L11: + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 157 .loc 1 248 5 is_stmt 1 view .LVU26 + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 158 .loc 1 248 53 is_stmt 0 view .LVU27 + 159 0010 FA20 movs r0, #250 + 160 .LVL6: + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 161 .loc 1 248 53 view .LVU28 + 162 0012 8000 lsls r0, r0, #2 + 163 0014 FFF7FEFF bl __aeabi_uidiv + 164 .LVL7: + 165 0018 0100 movs r1, r0 + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 166 .loc 1 248 9 view .LVU29 + 167 001a 0D4B ldr r3, .L13+4 + 168 001c 1868 ldr r0, [r3] + 169 001e FFF7FEFF bl __aeabi_uidiv + 170 .LVL8: + 171 0022 FFF7FEFF bl HAL_SYSTICK_Config + 172 .LVL9: + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 173 .loc 1 248 8 view .LVU30 + ARM GAS /tmp/ccQNWmKP.s page 9 + + + 174 0026 0028 cmp r0, #0 + 175 0028 0DD1 bne .L9 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 176 .loc 1 251 7 is_stmt 1 view .LVU31 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 177 .loc 1 251 10 is_stmt 0 view .LVU32 + 178 002a 032C cmp r4, #3 + 179 002c 01D9 bls .L12 + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 180 .loc 1 258 16 view .LVU33 + 181 002e 0120 movs r0, #1 + 182 0030 EDE7 b .L7 + 183 .L12: + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uwTickPrio = TickPriority; + 184 .loc 1 253 9 is_stmt 1 view .LVU34 + 185 0032 0130 adds r0, r0, #1 + 186 0034 0022 movs r2, #0 + 187 0036 2100 movs r1, r4 + 188 0038 4042 rsbs r0, r0, #0 + 189 003a FFF7FEFF bl HAL_NVIC_SetPriority + 190 .LVL10: + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 191 .loc 1 254 9 view .LVU35 + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 192 .loc 1 254 20 is_stmt 0 view .LVU36 + 193 003e 054B ldr r3, .L13+8 + 194 0040 1C60 str r4, [r3] + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 195 .loc 1 242 22 view .LVU37 + 196 0042 0020 movs r0, #0 + 197 0044 E3E7 b .L7 + 198 .L9: + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 199 .loc 1 263 14 view .LVU38 + 200 0046 0120 movs r0, #1 + 201 0048 E1E7 b .L7 + 202 .L14: + 203 004a C046 .align 2 + 204 .L13: + 205 004c 00000000 .word .LANCHOR0 + 206 0050 00000000 .word SystemCoreClock + 207 0054 00000000 .word .LANCHOR1 + 208 .cfi_endproc + 209 .LFE301: + 211 .section .text.HAL_Init,"ax",%progbits + 212 .align 1 + 213 .global HAL_Init + 214 .syntax unified + 215 .code 16 + 216 .thumb_func + 217 .fpu softvfp + 219 HAL_Init: + 220 .LFB297: + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 221 .loc 1 144 1 is_stmt 1 view -0 + 222 .cfi_startproc + 223 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccQNWmKP.s page 10 + + + 224 @ frame_needed = 0, uses_anonymous_args = 0 + 225 0000 10B5 push {r4, lr} + 226 .LCFI2: + 227 .cfi_def_cfa_offset 8 + 228 .cfi_offset 4, -8 + 229 .cfi_offset 14, -4 + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 230 .loc 1 145 3 view .LVU40 + 231 .LVL11: + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 232 .loc 1 157 3 view .LVU41 + 233 0002 084A ldr r2, .L19 + 234 0004 1168 ldr r1, [r2] + 235 0006 8023 movs r3, #128 + 236 0008 5B00 lsls r3, r3, #1 + 237 000a 0B43 orrs r3, r1 + 238 000c 1360 str r3, [r2] + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 239 .loc 1 161 3 view .LVU42 + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 240 .loc 1 161 7 is_stmt 0 view .LVU43 + 241 000e 0320 movs r0, #3 + 242 0010 FFF7FEFF bl HAL_InitTick + 243 .LVL12: + 244 0014 041E subs r4, r0, #0 + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 245 .loc 1 161 6 view .LVU44 + 246 0016 02D0 beq .L18 + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 247 .loc 1 163 12 view .LVU45 + 248 0018 0124 movs r4, #1 + 249 .L16: + 250 .LVL13: + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 251 .loc 1 172 3 is_stmt 1 view .LVU46 + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 252 .loc 1 173 1 is_stmt 0 view .LVU47 + 253 001a 2000 movs r0, r4 + 254 @ sp needed + 255 .LVL14: + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 256 .loc 1 173 1 view .LVU48 + 257 001c 10BD pop {r4, pc} + 258 .LVL15: + 259 .L18: + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 260 .loc 1 168 3 is_stmt 1 view .LVU49 + 261 001e FFF7FEFF bl HAL_MspInit + 262 .LVL16: + 263 0022 FAE7 b .L16 + 264 .L20: + 265 .align 2 + 266 .L19: + 267 0024 00200240 .word 1073881088 + 268 .cfi_endproc + 269 .LFE297: + 271 .section .text.HAL_IncTick,"ax",%progbits + ARM GAS /tmp/ccQNWmKP.s page 11 + + + 272 .align 1 + 273 .weak HAL_IncTick + 274 .syntax unified + 275 .code 16 + 276 .thumb_func + 277 .fpu softvfp + 279 HAL_IncTick: + 280 .LFB302: + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @} + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group2 + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief HAL Control functions + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @verbatim + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ##### HAL Control functions ##### + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** [..] This section provides functions allowing to: + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Provide a tick value in millisecond + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Provide a blocking delay in millisecond + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Suspend the time base source interrupt + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Resume the time base source interrupt + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Get the HAL API driver version + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Get the device identifier + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Get the device revision identifier + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @endverbatim + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * used as application time base. + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * in SysTick ISR. + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementations in user file. + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_IncTick(void) + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 281 .loc 1 309 1 view -0 + 282 .cfi_startproc + 283 @ args = 0, pretend = 0, frame = 0 + 284 @ frame_needed = 0, uses_anonymous_args = 0 + 285 @ link register save eliminated. + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uwTick += (uint32_t)uwTickFreq; + 286 .loc 1 310 3 view .LVU51 + 287 .loc 1 310 13 is_stmt 0 view .LVU52 + 288 0000 034B ldr r3, .L22 + 289 0002 1B78 ldrb r3, [r3] + 290 .loc 1 310 10 view .LVU53 + 291 0004 034A ldr r2, .L22+4 + 292 0006 1168 ldr r1, [r2] + ARM GAS /tmp/ccQNWmKP.s page 12 + + + 293 0008 5B18 adds r3, r3, r1 + 294 000a 1360 str r3, [r2] + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 295 .loc 1 311 1 view .LVU54 + 296 @ sp needed + 297 000c 7047 bx lr + 298 .L23: + 299 000e C046 .align 2 + 300 .L22: + 301 0010 00000000 .word .LANCHOR0 + 302 0014 00000000 .word .LANCHOR2 + 303 .cfi_endproc + 304 .LFE302: + 306 .section .text.HAL_GetTick,"ax",%progbits + 307 .align 1 + 308 .weak HAL_GetTick + 309 .syntax unified + 310 .code 16 + 311 .thumb_func + 312 .fpu softvfp + 314 HAL_GetTick: + 315 .LFB303: + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Provides a tick value in millisecond. + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementations in user file. + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval tick value + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 316 .loc 1 320 1 is_stmt 1 view -0 + 317 .cfi_startproc + 318 @ args = 0, pretend = 0, frame = 0 + 319 @ frame_needed = 0, uses_anonymous_args = 0 + 320 @ link register save eliminated. + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return uwTick; + 321 .loc 1 321 3 view .LVU56 + 322 .loc 1 321 10 is_stmt 0 view .LVU57 + 323 0000 014B ldr r3, .L25 + 324 0002 1868 ldr r0, [r3] + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 325 .loc 1 322 1 view .LVU58 + 326 @ sp needed + 327 0004 7047 bx lr + 328 .L26: + 329 0006 C046 .align 2 + 330 .L25: + 331 0008 00000000 .word .LANCHOR2 + 332 .cfi_endproc + 333 .LFE303: + 335 .section .text.HAL_GetTickPrio,"ax",%progbits + 336 .align 1 + 337 .global HAL_GetTickPrio + 338 .syntax unified + 339 .code 16 + 340 .thumb_func + ARM GAS /tmp/ccQNWmKP.s page 13 + + + 341 .fpu softvfp + 343 HAL_GetTickPrio: + 344 .LFB304: + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief This function returns a tick priority. + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval tick priority + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetTickPrio(void) + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 345 .loc 1 329 1 is_stmt 1 view -0 + 346 .cfi_startproc + 347 @ args = 0, pretend = 0, frame = 0 + 348 @ frame_needed = 0, uses_anonymous_args = 0 + 349 @ link register save eliminated. + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return uwTickPrio; + 350 .loc 1 330 3 view .LVU60 + 351 .loc 1 330 10 is_stmt 0 view .LVU61 + 352 0000 014B ldr r3, .L28 + 353 0002 1868 ldr r0, [r3] + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 354 .loc 1 331 1 view .LVU62 + 355 @ sp needed + 356 0004 7047 bx lr + 357 .L29: + 358 0006 C046 .align 2 + 359 .L28: + 360 0008 00000000 .word .LANCHOR1 + 361 .cfi_endproc + 362 .LFE304: + 364 .section .text.HAL_SetTickFreq,"ax",%progbits + 365 .align 1 + 366 .global HAL_SetTickFreq + 367 .syntax unified + 368 .code 16 + 369 .thumb_func + 370 .fpu softvfp + 372 HAL_SetTickFreq: + 373 .LVL17: + 374 .LFB305: + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Set new tick Freq. + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval status + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 375 .loc 1 338 1 is_stmt 1 view -0 + 376 .cfi_startproc + 377 @ args = 0, pretend = 0, frame = 0 + 378 @ frame_needed = 0, uses_anonymous_args = 0 + 379 .loc 1 338 1 is_stmt 0 view .LVU64 + 380 0000 10B5 push {r4, lr} + 381 .LCFI3: + 382 .cfi_def_cfa_offset 8 + 383 .cfi_offset 4, -8 + 384 .cfi_offset 14, -4 + ARM GAS /tmp/ccQNWmKP.s page 14 + + + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 385 .loc 1 339 3 is_stmt 1 view .LVU65 + 386 .LVL18: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 387 .loc 1 340 3 view .LVU66 + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_TICKFREQ(Freq)); + 388 .loc 1 341 3 view .LVU67 + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (uwTickFreq != Freq) + 389 .loc 1 343 3 view .LVU68 + 390 .loc 1 343 18 is_stmt 0 view .LVU69 + 391 0002 084B ldr r3, .L34 + 392 0004 1C78 ldrb r4, [r3] + 393 .loc 1 343 6 view .LVU70 + 394 0006 8442 cmp r4, r0 + 395 0008 01D1 bne .L33 + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 396 .loc 1 339 21 view .LVU71 + 397 000a 0020 movs r0, #0 + 398 .LVL19: + 399 .L31: + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Back up uwTickFreq frequency */ + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** prevTickFreq = uwTickFreq; + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Update uwTickFreq global variable used by HAL_InitTick() */ + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uwTickFreq = Freq; + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Apply the new tick Freq */ + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** status = HAL_InitTick(uwTickPrio); + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (status != HAL_OK) + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Restore previous tick frequency */ + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uwTickFreq = prevTickFreq; + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return status; + 400 .loc 1 360 3 is_stmt 1 view .LVU72 + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 401 .loc 1 361 1 is_stmt 0 view .LVU73 + 402 @ sp needed + 403 000c 10BD pop {r4, pc} + 404 .LVL20: + 405 .L33: + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 406 .loc 1 346 5 is_stmt 1 view .LVU74 + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 407 .loc 1 349 5 view .LVU75 + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 408 .loc 1 349 16 is_stmt 0 view .LVU76 + 409 000e 1870 strb r0, [r3] + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (status != HAL_OK) + 410 .loc 1 352 5 is_stmt 1 view .LVU77 + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (status != HAL_OK) + 411 .loc 1 352 14 is_stmt 0 view .LVU78 + 412 0010 054B ldr r3, .L34+4 + ARM GAS /tmp/ccQNWmKP.s page 15 + + + 413 0012 1868 ldr r0, [r3] + 414 .LVL21: + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (status != HAL_OK) + 415 .loc 1 352 14 view .LVU79 + 416 0014 FFF7FEFF bl HAL_InitTick + 417 .LVL22: + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 418 .loc 1 353 5 is_stmt 1 view .LVU80 + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 419 .loc 1 353 8 is_stmt 0 view .LVU81 + 420 0018 0028 cmp r0, #0 + 421 001a F7D0 beq .L31 + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 422 .loc 1 356 7 is_stmt 1 view .LVU82 + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 423 .loc 1 356 18 is_stmt 0 view .LVU83 + 424 001c 014B ldr r3, .L34 + 425 001e 1C70 strb r4, [r3] + 426 0020 F4E7 b .L31 + 427 .L35: + 428 0022 C046 .align 2 + 429 .L34: + 430 0024 00000000 .word .LANCHOR0 + 431 0028 00000000 .word .LANCHOR1 + 432 .cfi_endproc + 433 .LFE305: + 435 .section .text.HAL_GetTickFreq,"ax",%progbits + 436 .align 1 + 437 .global HAL_GetTickFreq + 438 .syntax unified + 439 .code 16 + 440 .thumb_func + 441 .fpu softvfp + 443 HAL_GetTickFreq: + 444 .LFB306: + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief return tick frequency. + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval tick period in Hz + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void) + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 445 .loc 1 368 1 is_stmt 1 view -0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 0 + 448 @ frame_needed = 0, uses_anonymous_args = 0 + 449 @ link register save eliminated. + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return uwTickFreq; + 450 .loc 1 369 3 view .LVU85 + 451 .loc 1 369 10 is_stmt 0 view .LVU86 + 452 0000 014B ldr r3, .L37 + 453 0002 1878 ldrb r0, [r3] + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 454 .loc 1 370 1 view .LVU87 + 455 @ sp needed + 456 0004 7047 bx lr + 457 .L38: + ARM GAS /tmp/ccQNWmKP.s page 16 + + + 458 0006 C046 .align 2 + 459 .L37: + 460 0008 00000000 .word .LANCHOR0 + 461 .cfi_endproc + 462 .LFE306: + 464 .section .text.HAL_Delay,"ax",%progbits + 465 .align 1 + 466 .weak HAL_Delay + 467 .syntax unified + 468 .code 16 + 469 .thumb_func + 470 .fpu softvfp + 472 HAL_Delay: + 473 .LVL23: + 474 .LFB307: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief This function provides minimum delay (in milliseconds) based + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * on variable incremented. + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * is incremented. + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementations in user file. + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param Delay specifies the delay time length, in milliseconds. + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_Delay(uint32_t Delay) + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 475 .loc 1 384 1 is_stmt 1 view -0 + 476 .cfi_startproc + 477 @ args = 0, pretend = 0, frame = 0 + 478 @ frame_needed = 0, uses_anonymous_args = 0 + 479 .loc 1 384 1 is_stmt 0 view .LVU89 + 480 0000 70B5 push {r4, r5, r6, lr} + 481 .LCFI4: + 482 .cfi_def_cfa_offset 16 + 483 .cfi_offset 4, -16 + 484 .cfi_offset 5, -12 + 485 .cfi_offset 6, -8 + 486 .cfi_offset 14, -4 + 487 0002 0400 movs r4, r0 + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t tickstart = HAL_GetTick(); + 488 .loc 1 385 3 is_stmt 1 view .LVU90 + 489 .loc 1 385 24 is_stmt 0 view .LVU91 + 490 0004 FFF7FEFF bl HAL_GetTick + 491 .LVL24: + 492 .loc 1 385 24 view .LVU92 + 493 0008 0500 movs r5, r0 + 494 .LVL25: + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t wait = Delay; + 495 .loc 1 386 3 is_stmt 1 view .LVU93 + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Add a freq to guarantee minimum wait */ + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if (wait < HAL_MAX_DELAY) + 496 .loc 1 389 3 view .LVU94 + 497 .loc 1 389 6 is_stmt 0 view .LVU95 + ARM GAS /tmp/ccQNWmKP.s page 17 + + + 498 000a 631C adds r3, r4, #1 + 499 000c 02D0 beq .L41 + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** wait += (uint32_t)(uwTickFreq); + 500 .loc 1 391 5 is_stmt 1 view .LVU96 + 501 .loc 1 391 13 is_stmt 0 view .LVU97 + 502 000e 044B ldr r3, .L42 + 503 0010 1B78 ldrb r3, [r3] + 504 .loc 1 391 10 view .LVU98 + 505 0012 E418 adds r4, r4, r3 + 506 .LVL26: + 507 .L41: + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** while ((HAL_GetTick() - tickstart) < wait) + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 508 .loc 1 396 3 is_stmt 1 discriminator 1 view .LVU99 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 509 .loc 1 394 9 discriminator 1 view .LVU100 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 510 .loc 1 394 11 is_stmt 0 discriminator 1 view .LVU101 + 511 0014 FFF7FEFF bl HAL_GetTick + 512 .LVL27: + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 513 .loc 1 394 25 discriminator 1 view .LVU102 + 514 0018 401B subs r0, r0, r5 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 515 .loc 1 394 9 discriminator 1 view .LVU103 + 516 001a A042 cmp r0, r4 + 517 001c FAD3 bcc .L41 + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 518 .loc 1 397 1 view .LVU104 + 519 @ sp needed + 520 .LVL28: + 521 .LVL29: + 522 .loc 1 397 1 view .LVU105 + 523 001e 70BD pop {r4, r5, r6, pc} + 524 .L43: + 525 .align 2 + 526 .L42: + 527 0020 00000000 .word .LANCHOR0 + 528 .cfi_endproc + 529 .LFE307: + 531 .section .text.HAL_SuspendTick,"ax",%progbits + 532 .align 1 + 533 .weak HAL_SuspendTick + 534 .syntax unified + 535 .code 16 + 536 .thumb_func + 537 .fpu softvfp + 539 HAL_SuspendTick: + 540 .LFB308: + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Suspend Tick increment. + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + ARM GAS /tmp/ccQNWmKP.s page 18 + + + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * is called, the SysTick interrupt will be disabled and so Tick increment + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * is suspended. + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementations in user file. + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_SuspendTick(void) + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 541 .loc 1 410 1 is_stmt 1 view -0 + 542 .cfi_startproc + 543 @ args = 0, pretend = 0, frame = 0 + 544 @ frame_needed = 0, uses_anonymous_args = 0 + 545 @ link register save eliminated. + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Disable SysTick Interrupt */ + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); + 546 .loc 1 412 3 view .LVU107 + 547 0000 024A ldr r2, .L45 + 548 0002 1368 ldr r3, [r2] + 549 0004 0221 movs r1, #2 + 550 0006 8B43 bics r3, r1 + 551 0008 1360 str r3, [r2] + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 552 .loc 1 413 1 is_stmt 0 view .LVU108 + 553 @ sp needed + 554 000a 7047 bx lr + 555 .L46: + 556 .align 2 + 557 .L45: + 558 000c 10E000E0 .word -536813552 + 559 .cfi_endproc + 560 .LFE308: + 562 .section .text.HAL_ResumeTick,"ax",%progbits + 563 .align 1 + 564 .weak HAL_ResumeTick + 565 .syntax unified + 566 .code 16 + 567 .thumb_func + 568 .fpu softvfp + 570 HAL_ResumeTick: + 571 .LFB309: + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Resume Tick increment. + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * is called, the SysTick interrupt will be enabled and so Tick increment + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * is resumed. + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * implementations in user file. + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** __weak void HAL_ResumeTick(void) + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 572 .loc 1 426 1 is_stmt 1 view -0 + 573 .cfi_startproc + 574 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccQNWmKP.s page 19 + + + 575 @ frame_needed = 0, uses_anonymous_args = 0 + 576 @ link register save eliminated. + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Enable SysTick Interrupt */ + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 577 .loc 1 428 3 view .LVU110 + 578 0000 024A ldr r2, .L48 + 579 0002 1368 ldr r3, [r2] + 580 0004 0221 movs r1, #2 + 581 0006 0B43 orrs r3, r1 + 582 0008 1360 str r3, [r2] + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 583 .loc 1 429 1 is_stmt 0 view .LVU111 + 584 @ sp needed + 585 000a 7047 bx lr + 586 .L49: + 587 .align 2 + 588 .L48: + 589 000c 10E000E0 .word -536813552 + 590 .cfi_endproc + 591 .LFE309: + 593 .section .text.HAL_GetHalVersion,"ax",%progbits + 594 .align 1 + 595 .global HAL_GetHalVersion + 596 .syntax unified + 597 .code 16 + 598 .thumb_func + 599 .fpu softvfp + 601 HAL_GetHalVersion: + 602 .LFB310: + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns the HAL revision + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval version : 0xXYZR (8bits for each decimal, R for RC) + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 603 .loc 1 436 1 is_stmt 1 view -0 + 604 .cfi_startproc + 605 @ args = 0, pretend = 0, frame = 0 + 606 @ frame_needed = 0, uses_anonymous_args = 0 + 607 @ link register save eliminated. + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return __STM32G0xx_HAL_VERSION; + 608 .loc 1 437 3 view .LVU113 + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 609 .loc 1 438 1 is_stmt 0 view .LVU114 + 610 0000 0048 ldr r0, .L51 + 611 @ sp needed + 612 0002 7047 bx lr + 613 .L52: + 614 .align 2 + 615 .L51: + 616 0004 00020401 .word 17039872 + 617 .cfi_endproc + 618 .LFE310: + 620 .section .text.HAL_GetREVID,"ax",%progbits + 621 .align 1 + 622 .global HAL_GetREVID + ARM GAS /tmp/ccQNWmKP.s page 20 + + + 623 .syntax unified + 624 .code 16 + 625 .thumb_func + 626 .fpu softvfp + 628 HAL_GetREVID: + 629 .LFB311: + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns the device revision identifier. + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval Device revision identifier + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetREVID(void) + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 630 .loc 1 445 1 is_stmt 1 view -0 + 631 .cfi_startproc + 632 @ args = 0, pretend = 0, frame = 0 + 633 @ frame_needed = 0, uses_anonymous_args = 0 + 634 @ link register save eliminated. + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U); + 635 .loc 1 446 3 view .LVU116 + 636 .loc 1 446 15 is_stmt 0 view .LVU117 + 637 0000 014B ldr r3, .L54 + 638 0002 1868 ldr r0, [r3] + 639 .loc 1 446 45 view .LVU118 + 640 0004 000C lsrs r0, r0, #16 + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 641 .loc 1 447 1 view .LVU119 + 642 @ sp needed + 643 0006 7047 bx lr + 644 .L55: + 645 .align 2 + 646 .L54: + 647 0008 00580140 .word 1073829888 + 648 .cfi_endproc + 649 .LFE311: + 651 .section .text.HAL_GetDEVID,"ax",%progbits + 652 .align 1 + 653 .global HAL_GetDEVID + 654 .syntax unified + 655 .code 16 + 656 .thumb_func + 657 .fpu softvfp + 659 HAL_GetDEVID: + 660 .LFB312: + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns the device identifier. + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval Device identifier + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetDEVID(void) + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 661 .loc 1 454 1 is_stmt 1 view -0 + 662 .cfi_startproc + 663 @ args = 0, pretend = 0, frame = 0 + 664 @ frame_needed = 0, uses_anonymous_args = 0 + 665 @ link register save eliminated. + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID); + ARM GAS /tmp/ccQNWmKP.s page 21 + + + 666 .loc 1 455 3 view .LVU121 + 667 .loc 1 455 15 is_stmt 0 view .LVU122 + 668 0000 024B ldr r3, .L57 + 669 0002 1868 ldr r0, [r3] + 670 .loc 1 455 25 view .LVU123 + 671 0004 0005 lsls r0, r0, #20 + 672 0006 000D lsrs r0, r0, #20 + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 673 .loc 1 456 1 view .LVU124 + 674 @ sp needed + 675 0008 7047 bx lr + 676 .L58: + 677 000a C046 .align 2 + 678 .L57: + 679 000c 00580140 .word 1073829888 + 680 .cfi_endproc + 681 .LFE312: + 683 .section .text.HAL_GetUIDw0,"ax",%progbits + 684 .align 1 + 685 .global HAL_GetUIDw0 + 686 .syntax unified + 687 .code 16 + 688 .thumb_func + 689 .fpu softvfp + 691 HAL_GetUIDw0: + 692 .LFB313: + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns first word of the unique device identifier (UID based on 96 bits) + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval Device identifier + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetUIDw0(void) + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 693 .loc 1 463 1 is_stmt 1 view -0 + 694 .cfi_startproc + 695 @ args = 0, pretend = 0, frame = 0 + 696 @ frame_needed = 0, uses_anonymous_args = 0 + 697 @ link register save eliminated. + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return (READ_REG(*((uint32_t *)UID_BASE))); + 698 .loc 1 464 3 view .LVU126 + 699 .loc 1 464 11 is_stmt 0 view .LVU127 + 700 0000 014B ldr r3, .L60 + 701 0002 1868 ldr r0, [r3] + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 702 .loc 1 465 1 view .LVU128 + 703 @ sp needed + 704 0004 7047 bx lr + 705 .L61: + 706 0006 C046 .align 2 + 707 .L60: + 708 0008 9075FF1F .word 536835472 + 709 .cfi_endproc + 710 .LFE313: + 712 .section .text.HAL_GetUIDw1,"ax",%progbits + 713 .align 1 + 714 .global HAL_GetUIDw1 + 715 .syntax unified + ARM GAS /tmp/ccQNWmKP.s page 22 + + + 716 .code 16 + 717 .thumb_func + 718 .fpu softvfp + 720 HAL_GetUIDw1: + 721 .LFB314: + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns second word of the unique device identifier (UID based on 96 bits) + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval Device identifier + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetUIDw1(void) + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 722 .loc 1 472 1 is_stmt 1 view -0 + 723 .cfi_startproc + 724 @ args = 0, pretend = 0, frame = 0 + 725 @ frame_needed = 0, uses_anonymous_args = 0 + 726 @ link register save eliminated. + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + 727 .loc 1 473 3 view .LVU130 + 728 .loc 1 473 11 is_stmt 0 view .LVU131 + 729 0000 014B ldr r3, .L63 + 730 0002 1868 ldr r0, [r3] + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 731 .loc 1 474 1 view .LVU132 + 732 @ sp needed + 733 0004 7047 bx lr + 734 .L64: + 735 0006 C046 .align 2 + 736 .L63: + 737 0008 9475FF1F .word 536835476 + 738 .cfi_endproc + 739 .LFE314: + 741 .section .text.HAL_GetUIDw2,"ax",%progbits + 742 .align 1 + 743 .global HAL_GetUIDw2 + 744 .syntax unified + 745 .code 16 + 746 .thumb_func + 747 .fpu softvfp + 749 HAL_GetUIDw2: + 750 .LFB315: + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Returns third word of the unique device identifier (UID based on 96 bits) + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval Device identifier + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t HAL_GetUIDw2(void) + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 751 .loc 1 481 1 is_stmt 1 view -0 + 752 .cfi_startproc + 753 @ args = 0, pretend = 0, frame = 0 + 754 @ frame_needed = 0, uses_anonymous_args = 0 + 755 @ link register save eliminated. + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 756 .loc 1 482 3 view .LVU134 + 757 .loc 1 482 11 is_stmt 0 view .LVU135 + 758 0000 014B ldr r3, .L66 + ARM GAS /tmp/ccQNWmKP.s page 23 + + + 759 0002 1868 ldr r0, [r3] + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 760 .loc 1 483 1 view .LVU136 + 761 @ sp needed + 762 0004 7047 bx lr + 763 .L67: + 764 0006 C046 .align 2 + 765 .L66: + 766 0008 9875FF1F .word 536835480 + 767 .cfi_endproc + 768 .LFE315: + 770 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 771 .align 1 + 772 .global HAL_DBGMCU_EnableDBGStopMode + 773 .syntax unified + 774 .code 16 + 775 .thumb_func + 776 .fpu softvfp + 778 HAL_DBGMCU_EnableDBGStopMode: + 779 .LFB316: + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @} + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group3 + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief HAL Debug functions + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @verbatim + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ##### HAL Debug functions ##### + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** [..] This section provides functions allowing to: + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable Debug module during STOP mode + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable Debug module during STANDBY mode + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @endverbatim + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable the Debug Module during STOP mode + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void) + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 780 .loc 1 509 1 is_stmt 1 view -0 + 781 .cfi_startproc + 782 @ args = 0, pretend = 0, frame = 0 + 783 @ frame_needed = 0, uses_anonymous_args = 0 + 784 @ link register save eliminated. + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(DBG->CR, DBG_CR_DBG_STOP); + 785 .loc 1 510 3 view .LVU138 + 786 0000 024A ldr r2, .L69 + 787 0002 5368 ldr r3, [r2, #4] + 788 0004 0221 movs r1, #2 + 789 0006 0B43 orrs r3, r1 + ARM GAS /tmp/ccQNWmKP.s page 24 + + + 790 0008 5360 str r3, [r2, #4] + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 791 .loc 1 511 1 is_stmt 0 view .LVU139 + 792 @ sp needed + 793 000a 7047 bx lr + 794 .L70: + 795 .align 2 + 796 .L69: + 797 000c 00580140 .word 1073829888 + 798 .cfi_endproc + 799 .LFE316: + 801 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 802 .align 1 + 803 .global HAL_DBGMCU_DisableDBGStopMode + 804 .syntax unified + 805 .code 16 + 806 .thumb_func + 807 .fpu softvfp + 809 HAL_DBGMCU_DisableDBGStopMode: + 810 .LFB317: + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable the Debug Module during STOP mode + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void) + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 811 .loc 1 518 1 is_stmt 1 view -0 + 812 .cfi_startproc + 813 @ args = 0, pretend = 0, frame = 0 + 814 @ frame_needed = 0, uses_anonymous_args = 0 + 815 @ link register save eliminated. + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP); + 816 .loc 1 519 3 view .LVU141 + 817 0000 024A ldr r2, .L72 + 818 0002 5368 ldr r3, [r2, #4] + 819 0004 0221 movs r1, #2 + 820 0006 8B43 bics r3, r1 + 821 0008 5360 str r3, [r2, #4] + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 822 .loc 1 520 1 is_stmt 0 view .LVU142 + 823 @ sp needed + 824 000a 7047 bx lr + 825 .L73: + 826 .align 2 + 827 .L72: + 828 000c 00580140 .word 1073829888 + 829 .cfi_endproc + 830 .LFE317: + 832 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 833 .align 1 + 834 .global HAL_DBGMCU_EnableDBGStandbyMode + 835 .syntax unified + 836 .code 16 + 837 .thumb_func + 838 .fpu softvfp + 840 HAL_DBGMCU_EnableDBGStandbyMode: + ARM GAS /tmp/ccQNWmKP.s page 25 + + + 841 .LFB318: + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable the Debug Module during STANDBY mode + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void) + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 842 .loc 1 527 1 is_stmt 1 view -0 + 843 .cfi_startproc + 844 @ args = 0, pretend = 0, frame = 0 + 845 @ frame_needed = 0, uses_anonymous_args = 0 + 846 @ link register save eliminated. + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY); + 847 .loc 1 528 3 view .LVU144 + 848 0000 024A ldr r2, .L75 + 849 0002 5368 ldr r3, [r2, #4] + 850 0004 0421 movs r1, #4 + 851 0006 0B43 orrs r3, r1 + 852 0008 5360 str r3, [r2, #4] + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 853 .loc 1 529 1 is_stmt 0 view .LVU145 + 854 @ sp needed + 855 000a 7047 bx lr + 856 .L76: + 857 .align 2 + 858 .L75: + 859 000c 00580140 .word 1073829888 + 860 .cfi_endproc + 861 .LFE318: + 863 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 864 .align 1 + 865 .global HAL_DBGMCU_DisableDBGStandbyMode + 866 .syntax unified + 867 .code 16 + 868 .thumb_func + 869 .fpu softvfp + 871 HAL_DBGMCU_DisableDBGStandbyMode: + 872 .LFB319: + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable the Debug Module during STANDBY mode + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void) + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 873 .loc 1 536 1 is_stmt 1 view -0 + 874 .cfi_startproc + 875 @ args = 0, pretend = 0, frame = 0 + 876 @ frame_needed = 0, uses_anonymous_args = 0 + 877 @ link register save eliminated. + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY); + 878 .loc 1 537 3 view .LVU147 + 879 0000 024A ldr r2, .L78 + 880 0002 5368 ldr r3, [r2, #4] + 881 0004 0421 movs r1, #4 + 882 0006 8B43 bics r3, r1 + ARM GAS /tmp/ccQNWmKP.s page 26 + + + 883 0008 5360 str r3, [r2, #4] + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 884 .loc 1 538 1 is_stmt 0 view .LVU148 + 885 @ sp needed + 886 000a 7047 bx lr + 887 .L79: + 888 .align 2 + 889 .L78: + 890 000c 00580140 .word 1073829888 + 891 .cfi_endproc + 892 .LFE319: + 894 .section .text.HAL_SYSCFG_VREFBUF_VoltageScalingConfig,"ax",%progbits + 895 .align 1 + 896 .global HAL_SYSCFG_VREFBUF_VoltageScalingConfig + 897 .syntax unified + 898 .code 16 + 899 .thumb_func + 900 .fpu softvfp + 902 HAL_SYSCFG_VREFBUF_VoltageScalingConfig: + 903 .LVL30: + 904 .LFB320: + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @} + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** @addtogroup HAL_Exported_Functions_Group4 + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief SYSCFG configuration functions + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @verbatim + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** ##### HAL SYSCFG configuration functions ##### + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** =============================================================================== + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** [..] This section provides functions allowing to: + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable Pin remap + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Configure the Voltage reference buffer + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable the Voltage reference buffer + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable the I/O analog switch voltage booster + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Enable/Disable dead battery behavior(*) + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (+) Configure Clamping Diode on specific pins(*) + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** (*) Feature not available on all devices + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** @endverbatim + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @{ + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #if defined(VREFBUF) + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Configure the internal voltage reference buffer voltage scale. + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param VoltageScaling specifies the output voltage to achieve + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be one of the following values: + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_VREFBUF_VoltageScale + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 905 .loc 1 572 1 is_stmt 1 view -0 + 906 .cfi_startproc + ARM GAS /tmp/ccQNWmKP.s page 27 + + + 907 @ args = 0, pretend = 0, frame = 0 + 908 @ frame_needed = 0, uses_anonymous_args = 0 + 909 @ link register save eliminated. + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameters */ + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + 910 .loc 1 574 3 view .LVU150 + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); + 911 .loc 1 576 3 view .LVU151 + 912 0000 034A ldr r2, .L81 + 913 0002 1368 ldr r3, [r2] + 914 0004 0421 movs r1, #4 + 915 0006 8B43 bics r3, r1 + 916 0008 0343 orrs r3, r0 + 917 000a 1360 str r3, [r2] + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 918 .loc 1 577 1 is_stmt 0 view .LVU152 + 919 @ sp needed + 920 000c 7047 bx lr + 921 .L82: + 922 000e C046 .align 2 + 923 .L81: + 924 0010 30000140 .word 1073807408 + 925 .cfi_endproc + 926 .LFE320: + 928 .section .text.HAL_SYSCFG_VREFBUF_HighImpedanceConfig,"ax",%progbits + 929 .align 1 + 930 .global HAL_SYSCFG_VREFBUF_HighImpedanceConfig + 931 .syntax unified + 932 .code 16 + 933 .thumb_func + 934 .fpu softvfp + 936 HAL_SYSCFG_VREFBUF_HighImpedanceConfig: + 937 .LVL31: + 938 .LFB321: + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Configure the internal voltage reference buffer high impedance mode. + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param Mode specifies the high impedance mode + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be one of the following values: + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_VREFBUF_HighImpedance + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 939 .loc 1 587 1 is_stmt 1 view -0 + 940 .cfi_startproc + 941 @ args = 0, pretend = 0, frame = 0 + 942 @ frame_needed = 0, uses_anonymous_args = 0 + 943 @ link register save eliminated. + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameters */ + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + 944 .loc 1 589 3 view .LVU154 + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); + 945 .loc 1 591 3 view .LVU155 + 946 0000 034A ldr r2, .L84 + ARM GAS /tmp/ccQNWmKP.s page 28 + + + 947 0002 1368 ldr r3, [r2] + 948 0004 0221 movs r1, #2 + 949 0006 8B43 bics r3, r1 + 950 0008 0343 orrs r3, r0 + 951 000a 1360 str r3, [r2] + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 952 .loc 1 592 1 is_stmt 0 view .LVU156 + 953 @ sp needed + 954 000c 7047 bx lr + 955 .L85: + 956 000e C046 .align 2 + 957 .L84: + 958 0010 30000140 .word 1073807408 + 959 .cfi_endproc + 960 .LFE321: + 962 .section .text.HAL_SYSCFG_VREFBUF_TrimmingConfig,"ax",%progbits + 963 .align 1 + 964 .global HAL_SYSCFG_VREFBUF_TrimmingConfig + 965 .syntax unified + 966 .code 16 + 967 .thumb_func + 968 .fpu softvfp + 970 HAL_SYSCFG_VREFBUF_TrimmingConfig: + 971 .LVL32: + 972 .LFB322: + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @note VrefBuf voltage scale is calibrated in production for each device, + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * using voltage scale 1. This calibration value is loaded + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * as default trimming value at device power up. + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This trimming value can be fine tuned for voltage scales 0 and 1 + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * using this function. + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 973 .loc 1 604 1 is_stmt 1 view -0 + 974 .cfi_startproc + 975 @ args = 0, pretend = 0, frame = 0 + 976 @ frame_needed = 0, uses_anonymous_args = 0 + 977 @ link register save eliminated. + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameters */ + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + 978 .loc 1 606 3 view .LVU158 + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); + 979 .loc 1 608 3 view .LVU159 + 980 0000 034A ldr r2, .L87 + 981 0002 5368 ldr r3, [r2, #4] + 982 0004 3F21 movs r1, #63 + 983 0006 8B43 bics r3, r1 + 984 0008 0343 orrs r3, r0 + 985 000a 5360 str r3, [r2, #4] + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 986 .loc 1 609 1 is_stmt 0 view .LVU160 + 987 @ sp needed + ARM GAS /tmp/ccQNWmKP.s page 29 + + + 988 000c 7047 bx lr + 989 .L88: + 990 000e C046 .align 2 + 991 .L87: + 992 0010 30000140 .word 1073807408 + 993 .cfi_endproc + 994 .LFE322: + 996 .section .text.HAL_SYSCFG_EnableVREFBUF,"ax",%progbits + 997 .align 1 + 998 .global HAL_SYSCFG_EnableVREFBUF + 999 .syntax unified + 1000 .code 16 + 1001 .thumb_func + 1002 .fpu softvfp + 1004 HAL_SYSCFG_EnableVREFBUF: + 1005 .LFB323: + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval HAL_OK/HAL_TIMEOUT + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1006 .loc 1 616 1 is_stmt 1 view -0 + 1007 .cfi_startproc + 1008 @ args = 0, pretend = 0, frame = 0 + 1009 @ frame_needed = 0, uses_anonymous_args = 0 + 1010 0000 10B5 push {r4, lr} + 1011 .LCFI5: + 1012 .cfi_def_cfa_offset 8 + 1013 .cfi_offset 4, -8 + 1014 .cfi_offset 14, -4 + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** uint32_t tickstart; + 1015 .loc 1 617 3 view .LVU162 + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + 1016 .loc 1 619 3 view .LVU163 + 1017 0002 0A4A ldr r2, .L95 + 1018 0004 1368 ldr r3, [r2] + 1019 0006 0121 movs r1, #1 + 1020 0008 0B43 orrs r3, r1 + 1021 000a 1360 str r3, [r2] + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Get Start Tick*/ + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** tickstart = HAL_GetTick(); + 1022 .loc 1 622 3 view .LVU164 + 1023 .loc 1 622 15 is_stmt 0 view .LVU165 + 1024 000c FFF7FEFF bl HAL_GetTick + 1025 .LVL33: + 1026 0010 0400 movs r4, r0 + 1027 .LVL34: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Wait for VRR bit */ + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) + 1028 .loc 1 625 3 is_stmt 1 view .LVU166 + 1029 .L90: + 1030 .loc 1 625 9 view .LVU167 + ARM GAS /tmp/ccQNWmKP.s page 30 + + + 1031 .loc 1 625 10 is_stmt 0 view .LVU168 + 1032 0012 064B ldr r3, .L95 + 1033 0014 1B68 ldr r3, [r3] + 1034 .loc 1 625 9 view .LVU169 + 1035 0016 1B07 lsls r3, r3, #28 + 1036 0018 06D4 bmi .L94 + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + 1037 .loc 1 627 5 is_stmt 1 view .LVU170 + 1038 .loc 1 627 10 is_stmt 0 view .LVU171 + 1039 001a FFF7FEFF bl HAL_GetTick + 1040 .LVL35: + 1041 .loc 1 627 24 view .LVU172 + 1042 001e 001B subs r0, r0, r4 + 1043 .loc 1 627 8 view .LVU173 + 1044 0020 0A28 cmp r0, #10 + 1045 0022 F6D9 bls .L90 + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return HAL_TIMEOUT; + 1046 .loc 1 629 14 view .LVU174 + 1047 0024 0320 movs r0, #3 + 1048 0026 00E0 b .L91 + 1049 .L94: + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** return HAL_OK; + 1050 .loc 1 633 10 view .LVU175 + 1051 0028 0020 movs r0, #0 + 1052 .L91: + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1053 .loc 1 634 1 view .LVU176 + 1054 @ sp needed + 1055 .LVL36: + 1056 .loc 1 634 1 view .LVU177 + 1057 002a 10BD pop {r4, pc} + 1058 .L96: + 1059 .align 2 + 1060 .L95: + 1061 002c 30000140 .word 1073807408 + 1062 .cfi_endproc + 1063 .LFE323: + 1065 .section .text.HAL_SYSCFG_DisableVREFBUF,"ax",%progbits + 1066 .align 1 + 1067 .global HAL_SYSCFG_DisableVREFBUF + 1068 .syntax unified + 1069 .code 16 + 1070 .thumb_func + 1071 .fpu softvfp + 1073 HAL_SYSCFG_DisableVREFBUF: + 1074 .LFB324: + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + ARM GAS /tmp/ccQNWmKP.s page 31 + + + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_DisableVREFBUF(void) + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1075 .loc 1 642 1 is_stmt 1 view -0 + 1076 .cfi_startproc + 1077 @ args = 0, pretend = 0, frame = 0 + 1078 @ frame_needed = 0, uses_anonymous_args = 0 + 1079 @ link register save eliminated. + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + 1080 .loc 1 643 3 view .LVU179 + 1081 0000 024A ldr r2, .L98 + 1082 0002 1368 ldr r3, [r2] + 1083 0004 0121 movs r1, #1 + 1084 0006 8B43 bics r3, r1 + 1085 0008 1360 str r3, [r2] + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1086 .loc 1 644 1 is_stmt 0 view .LVU180 + 1087 @ sp needed + 1088 000a 7047 bx lr + 1089 .L99: + 1090 .align 2 + 1091 .L98: + 1092 000c 30000140 .word 1073807408 + 1093 .cfi_endproc + 1094 .LFE324: + 1096 .section .text.HAL_SYSCFG_EnableIOAnalogSwitchBooster,"ax",%progbits + 1097 .align 1 + 1098 .global HAL_SYSCFG_EnableIOAnalogSwitchBooster + 1099 .syntax unified + 1100 .code 16 + 1101 .thumb_func + 1102 .fpu softvfp + 1104 HAL_SYSCFG_EnableIOAnalogSwitchBooster: + 1105 .LFB325: + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #endif /* VREFBUF */ + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable the I/O analog switch voltage booster + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1106 .loc 1 652 1 is_stmt 1 view -0 + 1107 .cfi_startproc + 1108 @ args = 0, pretend = 0, frame = 0 + 1109 @ frame_needed = 0, uses_anonymous_args = 0 + 1110 @ link register save eliminated. + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); + 1111 .loc 1 653 3 view .LVU182 + 1112 0000 034A ldr r2, .L101 + 1113 0002 1168 ldr r1, [r2] + 1114 0004 8023 movs r3, #128 + 1115 0006 5B00 lsls r3, r3, #1 + 1116 0008 0B43 orrs r3, r1 + 1117 000a 1360 str r3, [r2] + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1118 .loc 1 654 1 is_stmt 0 view .LVU183 + 1119 @ sp needed + ARM GAS /tmp/ccQNWmKP.s page 32 + + + 1120 000c 7047 bx lr + 1121 .L102: + 1122 000e C046 .align 2 + 1123 .L101: + 1124 0010 00000140 .word 1073807360 + 1125 .cfi_endproc + 1126 .LFE325: + 1128 .section .text.HAL_SYSCFG_DisableIOAnalogSwitchBooster,"ax",%progbits + 1129 .align 1 + 1130 .global HAL_SYSCFG_DisableIOAnalogSwitchBooster + 1131 .syntax unified + 1132 .code 16 + 1133 .thumb_func + 1134 .fpu softvfp + 1136 HAL_SYSCFG_DisableIOAnalogSwitchBooster: + 1137 .LFB326: + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable the I/O analog switch voltage booster + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1138 .loc 1 661 1 is_stmt 1 view -0 + 1139 .cfi_startproc + 1140 @ args = 0, pretend = 0, frame = 0 + 1141 @ frame_needed = 0, uses_anonymous_args = 0 + 1142 @ link register save eliminated. + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); + 1143 .loc 1 662 3 view .LVU185 + 1144 0000 024A ldr r2, .L104 + 1145 0002 1368 ldr r3, [r2] + 1146 0004 0249 ldr r1, .L104+4 + 1147 0006 0B40 ands r3, r1 + 1148 0008 1360 str r3, [r2] + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1149 .loc 1 663 1 is_stmt 0 view .LVU186 + 1150 @ sp needed + 1151 000a 7047 bx lr + 1152 .L105: + 1153 .align 2 + 1154 .L104: + 1155 000c 00000140 .word 1073807360 + 1156 0010 FFFEFFFF .word -257 + 1157 .cfi_endproc + 1158 .LFE326: + 1160 .section .text.HAL_SYSCFG_EnableRemap,"ax",%progbits + 1161 .align 1 + 1162 .global HAL_SYSCFG_EnableRemap + 1163 .syntax unified + 1164 .code 16 + 1165 .thumb_func + 1166 .fpu softvfp + 1168 HAL_SYSCFG_EnableRemap: + 1169 .LVL37: + 1170 .LFB327: + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + ARM GAS /tmp/ccQNWmKP.s page 33 + + + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable the remap on PA11_PA12 + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param PinRemap specifies which pins have to be remapped + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be any combination of the following values: + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_REMAP_PA11 + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_REMAP_PA12 + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_EnableRemap(uint32_t PinRemap) + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1171 .loc 1 674 1 is_stmt 1 view -0 + 1172 .cfi_startproc + 1173 @ args = 0, pretend = 0, frame = 0 + 1174 @ frame_needed = 0, uses_anonymous_args = 0 + 1175 @ link register save eliminated. + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameter */ + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_HAL_REMAP_PIN(PinRemap)); + 1176 .loc 1 676 3 view .LVU188 + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(SYSCFG->CFGR1, PinRemap); + 1177 .loc 1 677 3 view .LVU189 + 1178 0000 024A ldr r2, .L107 + 1179 0002 1368 ldr r3, [r2] + 1180 0004 0343 orrs r3, r0 + 1181 0006 1360 str r3, [r2] + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1182 .loc 1 678 1 is_stmt 0 view .LVU190 + 1183 @ sp needed + 1184 0008 7047 bx lr + 1185 .L108: + 1186 000a C046 .align 2 + 1187 .L107: + 1188 000c 00000140 .word 1073807360 + 1189 .cfi_endproc + 1190 .LFE327: + 1192 .section .text.HAL_SYSCFG_DisableRemap,"ax",%progbits + 1193 .align 1 + 1194 .global HAL_SYSCFG_DisableRemap + 1195 .syntax unified + 1196 .code 16 + 1197 .thumb_func + 1198 .fpu softvfp + 1200 HAL_SYSCFG_DisableRemap: + 1201 .LVL38: + 1202 .LFB328: + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable the remap on PA11_PA12 + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param PinRemap specifies which pins will behave normally + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be any combination of the following values: + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_REMAP_PA11 + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_REMAP_PA12 + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_DisableRemap(uint32_t PinRemap) + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1203 .loc 1 689 1 is_stmt 1 view -0 + 1204 .cfi_startproc + ARM GAS /tmp/ccQNWmKP.s page 34 + + + 1205 @ args = 0, pretend = 0, frame = 0 + 1206 @ frame_needed = 0, uses_anonymous_args = 0 + 1207 @ link register save eliminated. + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameter */ + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_HAL_REMAP_PIN(PinRemap)); + 1208 .loc 1 691 3 view .LVU192 + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(SYSCFG->CFGR1, PinRemap); + 1209 .loc 1 692 3 view .LVU193 + 1210 0000 024A ldr r2, .L110 + 1211 0002 1368 ldr r3, [r2] + 1212 0004 8343 bics r3, r0 + 1213 0006 1360 str r3, [r2] + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1214 .loc 1 693 1 is_stmt 0 view .LVU194 + 1215 @ sp needed + 1216 0008 7047 bx lr + 1217 .L111: + 1218 000a C046 .align 2 + 1219 .L110: + 1220 000c 00000140 .word 1073807360 + 1221 .cfi_endproc + 1222 .LFE328: + 1224 .section .text.HAL_SYSCFG_EnableClampingDiode,"ax",%progbits + 1225 .align 1 + 1226 .global HAL_SYSCFG_EnableClampingDiode + 1227 .syntax unified + 1228 .code 16 + 1229 .thumb_func + 1230 .fpu softvfp + 1232 HAL_SYSCFG_EnableClampingDiode: + 1233 .LVL39: + 1234 .LFB329: + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** #if defined(SYSCFG_CDEN_SUPPORT) + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Enable Clamping Diode on specified IO + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param PinConfig specifies on which pins clamping Diode has to be enabled + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be any combination of the following values: + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_ClampingDiode + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig) + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1235 .loc 1 704 1 is_stmt 1 view -0 + 1236 .cfi_startproc + 1237 @ args = 0, pretend = 0, frame = 0 + 1238 @ frame_needed = 0, uses_anonymous_args = 0 + 1239 @ link register save eliminated. + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameter */ + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + 1240 .loc 1 706 3 view .LVU196 + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** SET_BIT(SYSCFG->CFGR2, PinConfig); + 1241 .loc 1 707 3 view .LVU197 + 1242 0000 024A ldr r2, .L113 + 1243 0002 9369 ldr r3, [r2, #24] + 1244 0004 0343 orrs r3, r0 + 1245 0006 9361 str r3, [r2, #24] + ARM GAS /tmp/ccQNWmKP.s page 35 + + + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1246 .loc 1 708 1 is_stmt 0 view .LVU198 + 1247 @ sp needed + 1248 0008 7047 bx lr + 1249 .L114: + 1250 000a C046 .align 2 + 1251 .L113: + 1252 000c 00000140 .word 1073807360 + 1253 .cfi_endproc + 1254 .LFE329: + 1256 .section .text.HAL_SYSCFG_DisableClampingDiode,"ax",%progbits + 1257 .align 1 + 1258 .global HAL_SYSCFG_DisableClampingDiode + 1259 .syntax unified + 1260 .code 16 + 1261 .thumb_func + 1262 .fpu softvfp + 1264 HAL_SYSCFG_DisableClampingDiode: + 1265 .LVL40: + 1266 .LFB330: + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /** + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @brief Disable Clamping Diode on specified IO + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @param PinConfig specifies on which pins clamping Diode has to be disabled + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * This parameter can be any combination of the following values: + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @arg @ref SYSCFG_ClampingDiode + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** * @retval None + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** */ + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig) + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** { + 1267 .loc 1 718 1 is_stmt 1 view -0 + 1268 .cfi_startproc + 1269 @ args = 0, pretend = 0, frame = 0 + 1270 @ frame_needed = 0, uses_anonymous_args = 0 + 1271 @ link register save eliminated. + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** /* Check the parameter */ + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + 1272 .loc 1 720 3 view .LVU200 + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** CLEAR_BIT(SYSCFG->CFGR2, PinConfig); + 1273 .loc 1 721 3 view .LVU201 + 1274 0000 024A ldr r2, .L116 + 1275 0002 9369 ldr r3, [r2, #24] + 1276 0004 8343 bics r3, r0 + 1277 0006 9361 str r3, [r2, #24] + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c **** } + 1278 .loc 1 722 1 is_stmt 0 view .LVU202 + 1279 @ sp needed + 1280 0008 7047 bx lr + 1281 .L117: + 1282 000a C046 .align 2 + 1283 .L116: + 1284 000c 00000140 .word 1073807360 + 1285 .cfi_endproc + 1286 .LFE330: + 1288 .global uwTickFreq + 1289 .global uwTickPrio + 1290 .global uwTick + ARM GAS /tmp/ccQNWmKP.s page 36 + + + 1291 .section .bss.uwTick,"aw",%nobits + 1292 .align 2 + 1293 .set .LANCHOR2,. + 0 + 1296 uwTick: + 1297 0000 00000000 .space 4 + 1298 .section .data.uwTickFreq,"aw" + 1299 .set .LANCHOR0,. + 0 + 1302 uwTickFreq: + 1303 0000 01 .byte 1 + 1304 .section .data.uwTickPrio,"aw" + 1305 .align 2 + 1306 .set .LANCHOR1,. + 0 + 1309 uwTickPrio: + 1310 0000 04000000 .word 4 + 1311 .text + 1312 .Letext0: + 1313 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1314 .file 3 "Drivers/CMSIS/Include/core_cm0plus.h" + 1315 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1316 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1317 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + 1318 .file 7 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h" + 1319 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h" + 1320 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccQNWmKP.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal.c + /tmp/ccQNWmKP.s:16 .text.HAL_MspInit:0000000000000000 $t + /tmp/ccQNWmKP.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/ccQNWmKP.s:39 .text.HAL_MspDeInit:0000000000000000 $t + /tmp/ccQNWmKP.s:46 .text.HAL_MspDeInit:0000000000000000 HAL_MspDeInit + /tmp/ccQNWmKP.s:60 .text.HAL_DeInit:0000000000000000 $t + /tmp/ccQNWmKP.s:67 .text.HAL_DeInit:0000000000000000 HAL_DeInit + /tmp/ccQNWmKP.s:109 .text.HAL_DeInit:0000000000000024 $d + /tmp/ccQNWmKP.s:115 .text.HAL_InitTick:0000000000000000 $t + /tmp/ccQNWmKP.s:122 .text.HAL_InitTick:0000000000000000 HAL_InitTick + /tmp/ccQNWmKP.s:205 .text.HAL_InitTick:000000000000004c $d + /tmp/ccQNWmKP.s:212 .text.HAL_Init:0000000000000000 $t + /tmp/ccQNWmKP.s:219 .text.HAL_Init:0000000000000000 HAL_Init + /tmp/ccQNWmKP.s:267 .text.HAL_Init:0000000000000024 $d + /tmp/ccQNWmKP.s:272 .text.HAL_IncTick:0000000000000000 $t + /tmp/ccQNWmKP.s:279 .text.HAL_IncTick:0000000000000000 HAL_IncTick + /tmp/ccQNWmKP.s:301 .text.HAL_IncTick:0000000000000010 $d + /tmp/ccQNWmKP.s:307 .text.HAL_GetTick:0000000000000000 $t + /tmp/ccQNWmKP.s:314 .text.HAL_GetTick:0000000000000000 HAL_GetTick + /tmp/ccQNWmKP.s:331 .text.HAL_GetTick:0000000000000008 $d + /tmp/ccQNWmKP.s:336 .text.HAL_GetTickPrio:0000000000000000 $t + /tmp/ccQNWmKP.s:343 .text.HAL_GetTickPrio:0000000000000000 HAL_GetTickPrio + /tmp/ccQNWmKP.s:360 .text.HAL_GetTickPrio:0000000000000008 $d + /tmp/ccQNWmKP.s:365 .text.HAL_SetTickFreq:0000000000000000 $t + /tmp/ccQNWmKP.s:372 .text.HAL_SetTickFreq:0000000000000000 HAL_SetTickFreq + /tmp/ccQNWmKP.s:430 .text.HAL_SetTickFreq:0000000000000024 $d + /tmp/ccQNWmKP.s:436 .text.HAL_GetTickFreq:0000000000000000 $t + /tmp/ccQNWmKP.s:443 .text.HAL_GetTickFreq:0000000000000000 HAL_GetTickFreq + /tmp/ccQNWmKP.s:460 .text.HAL_GetTickFreq:0000000000000008 $d + /tmp/ccQNWmKP.s:465 .text.HAL_Delay:0000000000000000 $t + /tmp/ccQNWmKP.s:472 .text.HAL_Delay:0000000000000000 HAL_Delay + /tmp/ccQNWmKP.s:527 .text.HAL_Delay:0000000000000020 $d + /tmp/ccQNWmKP.s:532 .text.HAL_SuspendTick:0000000000000000 $t + /tmp/ccQNWmKP.s:539 .text.HAL_SuspendTick:0000000000000000 HAL_SuspendTick + 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zH$gmmCxPeh-{a`tx8ZOz3gVG4)xR4Jd&}^=`#9?MF3(<knk>>o5}jad4z9-QG=LkjHWS9VBcV1t6)fL)Dr4FYDz+ v^i`vt0xygkmlo*v<3oF#SF98EQrFQ2oRj+$o;?hsOkTTE-=`6|Jl_8YUb}7y literal 0 HcmV?d00001 diff --git a/squero/build/stm32g0xx_hal_cortex.d b/squero/build/stm32g0xx_hal_cortex.d new file mode 100644 index 0000000..d808cb2 --- /dev/null +++ b/squero/build/stm32g0xx_hal_cortex.d @@ -0,0 +1,59 @@ +build/stm32g0xx_hal_cortex.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_cortex.lst b/squero/build/stm32g0xx_hal_cortex.lst new file mode 100644 index 0000000..c4c3d1e --- /dev/null +++ b/squero/build/stm32g0xx_hal_cortex.lst @@ -0,0 +1,3801 @@ +ARM GAS /tmp/cc5M7qsZ.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_cortex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 16 .align 1 + 17 .global HAL_NVIC_SetPriority + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_NVIC_SetPriority: + 25 .LVL0: + 26 .LFB297: + 27 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @file stm32g0xx_hal_cortex.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + Initialization and Configuration functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + Peripheral Control functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @verbatim + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ##### How to use this driver ##### + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** [..] + 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** =========================================================== + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** [..] + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** The Cortex M0+ exceptions are managed by CMSIS functions. + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (#) Enable and Configure the priority of the selected IRQ Channels. + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** The priority can be 0..3. + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** -@- Lower priority values gives higher priority. + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** -@- Priority Order: + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (#@) Lowest priority. + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (#@) Lowest hardware priority (IRQn position). + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + ARM GAS /tmp/cc5M7qsZ.s page 2 + + + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** -@- Negative value of IRQn_Type are not allowed. + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ======================================================== + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** [..] + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** Setup SysTick Timer for time base. + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** is a CMSIS function that: + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x03). + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** inside the stm32g0xx_hal_cortex.h file. + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @endverbatim + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ****************************************************************************** + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @attention + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** *

© Copyright (c) 2018 STMicroelectronics. + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * All rights reserved.

+ 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * License. You may obtain a copy of the License at: + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ****************************************************************************** + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #include "stm32g0xx_hal.h" + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @{ + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @{ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + ARM GAS /tmp/cc5M7qsZ.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private types -------------------------------------------------------------*/ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private constants ---------------------------------------------------------*/ + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private macros ------------------------------------------------------------*/ + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/ + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Exported functions --------------------------------------------------------*/ + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @{ + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group1 + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @verbatim + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ##### Initialization and Configuration functions ##### + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** [..] + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** Systick functionalities + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @endverbatim + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @{ + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number . + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file) + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel. + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be a value between 0 and 3. + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * no subpriority supported in Cortex M0+ based products. + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 28 .loc 1 133 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 133 1 is_stmt 0 view .LVU1 + 33 0000 70B5 push {r4, r5, r6, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 16 + 36 .cfi_offset 4, -16 + 37 .cfi_offset 5, -12 + 38 .cfi_offset 6, -8 + 39 .cfi_offset 14, -4 + ARM GAS /tmp/cc5M7qsZ.s page 4 + + + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 40 .loc 1 135 3 is_stmt 1 view .LVU2 + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_SetPriority(IRQn,PreemptPriority); + 41 .loc 1 136 3 view .LVU3 + 42 .LVL1: + 43 .LBB34: + 44 .LBI34: + 45 .file 2 "Drivers/CMSIS/Include/core_cm0plus.h" + 1:Drivers/CMSIS/Include/core_cm0plus.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm0plus.h **** * @file core_cm0plus.h + 3:Drivers/CMSIS/Include/core_cm0plus.h **** * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm0plus.h **** * @version V5.0.7 + 5:Drivers/CMSIS/Include/core_cm0plus.h **** * @date 13. March 2019 + 6:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm0plus.h **** /* + 8:Drivers/CMSIS/Include/core_cm0plus.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm0plus.h **** * + 10:Drivers/CMSIS/Include/core_cm0plus.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm0plus.h **** * + 12:Drivers/CMSIS/Include/core_cm0plus.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm0plus.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm0plus.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm0plus.h **** * + 16:Drivers/CMSIS/Include/core_cm0plus.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm0plus.h **** * + 18:Drivers/CMSIS/Include/core_cm0plus.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm0plus.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm0plus.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm0plus.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm0plus.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 24:Drivers/CMSIS/Include/core_cm0plus.h **** + 25:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm0plus.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 30:Drivers/CMSIS/Include/core_cm0plus.h **** + 31:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm0plus.h **** + 34:Drivers/CMSIS/Include/core_cm0plus.h **** #include + 35:Drivers/CMSIS/Include/core_cm0plus.h **** + 36:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 39:Drivers/CMSIS/Include/core_cm0plus.h **** + 40:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 41:Drivers/CMSIS/Include/core_cm0plus.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm0plus.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm0plus.h **** + 44:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm0plus.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm0plus.h **** + 47:Drivers/CMSIS/Include/core_cm0plus.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm0plus.h **** Unions are used for effective representation of core registers. + ARM GAS /tmp/cc5M7qsZ.s page 5 + + + 49:Drivers/CMSIS/Include/core_cm0plus.h **** + 50:Drivers/CMSIS/Include/core_cm0plus.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm0plus.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 53:Drivers/CMSIS/Include/core_cm0plus.h **** + 54:Drivers/CMSIS/Include/core_cm0plus.h **** + 55:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm0plus.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 59:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup Cortex-M0+ + 60:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 61:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 62:Drivers/CMSIS/Include/core_cm0plus.h **** + 63:Drivers/CMSIS/Include/core_cm0plus.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm0plus.h **** + 65:Drivers/CMSIS/Include/core_cm0plus.h **** /* CMSIS CM0+ definitions */ + 66:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [3 + 67:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [1 + 68:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm0plus.h **** __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CM + 70:Drivers/CMSIS/Include/core_cm0plus.h **** + 71:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORTEX_M (0U) /*!< Cortex-M Core + 72:Drivers/CMSIS/Include/core_cm0plus.h **** + 73:Drivers/CMSIS/Include/core_cm0plus.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm0plus.h **** This core does not support an FPU at all + 75:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 76:Drivers/CMSIS/Include/core_cm0plus.h **** #define __FPU_USED 0U + 77:Drivers/CMSIS/Include/core_cm0plus.h **** + 78:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined ( __CC_ARM ) + 79:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TARGET_FPU_VFP + 80:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 81:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 82:Drivers/CMSIS/Include/core_cm0plus.h **** + 83:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 84:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARM_FP + 85:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 86:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 87:Drivers/CMSIS/Include/core_cm0plus.h **** + 88:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __GNUC__ ) + 89:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 90:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 91:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 92:Drivers/CMSIS/Include/core_cm0plus.h **** + 93:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __ICCARM__ ) + 94:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __ARMVFP__ + 95:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 96:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 97:Drivers/CMSIS/Include/core_cm0plus.h **** + 98:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TI_ARM__ ) + 99:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __TI_VFP_SUPPORT__ + 100:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 101:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 102:Drivers/CMSIS/Include/core_cm0plus.h **** + 103:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __TASKING__ ) + 104:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __FPU_VFP__ + 105:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + ARM GAS /tmp/cc5M7qsZ.s page 6 + + + 106:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 107:Drivers/CMSIS/Include/core_cm0plus.h **** + 108:Drivers/CMSIS/Include/core_cm0plus.h **** #elif defined ( __CSMC__ ) + 109:Drivers/CMSIS/Include/core_cm0plus.h **** #if ( __CSMC__ & 0x400U) + 110:Drivers/CMSIS/Include/core_cm0plus.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + 111:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 112:Drivers/CMSIS/Include/core_cm0plus.h **** + 113:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 114:Drivers/CMSIS/Include/core_cm0plus.h **** + 115:Drivers/CMSIS/Include/core_cm0plus.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 116:Drivers/CMSIS/Include/core_cm0plus.h **** + 117:Drivers/CMSIS/Include/core_cm0plus.h **** + 118:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 119:Drivers/CMSIS/Include/core_cm0plus.h **** } + 120:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 121:Drivers/CMSIS/Include/core_cm0plus.h **** + 122:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* __CORE_CM0PLUS_H_GENERIC */ + 123:Drivers/CMSIS/Include/core_cm0plus.h **** + 124:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CMSIS_GENERIC + 125:Drivers/CMSIS/Include/core_cm0plus.h **** + 126:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CORE_CM0PLUS_H_DEPENDANT + 127:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CORE_CM0PLUS_H_DEPENDANT + 128:Drivers/CMSIS/Include/core_cm0plus.h **** + 129:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 130:Drivers/CMSIS/Include/core_cm0plus.h **** extern "C" { + 131:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 132:Drivers/CMSIS/Include/core_cm0plus.h **** + 133:Drivers/CMSIS/Include/core_cm0plus.h **** /* check device defines and use defaults */ + 134:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined __CHECK_DEVICE_DEFINES + 135:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __CM0PLUS_REV + 136:Drivers/CMSIS/Include/core_cm0plus.h **** #define __CM0PLUS_REV 0x0000U + 137:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__CM0PLUS_REV not defined in device header file; using default!" + 138:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 139:Drivers/CMSIS/Include/core_cm0plus.h **** + 140:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __MPU_PRESENT + 141:Drivers/CMSIS/Include/core_cm0plus.h **** #define __MPU_PRESENT 0U + 142:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 143:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 144:Drivers/CMSIS/Include/core_cm0plus.h **** + 145:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __VTOR_PRESENT + 146:Drivers/CMSIS/Include/core_cm0plus.h **** #define __VTOR_PRESENT 0U + 147:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__VTOR_PRESENT not defined in device header file; using default!" + 148:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 149:Drivers/CMSIS/Include/core_cm0plus.h **** + 150:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __NVIC_PRIO_BITS + 151:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_PRIO_BITS 2U + 152:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 153:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 154:Drivers/CMSIS/Include/core_cm0plus.h **** + 155:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef __Vendor_SysTickConfig + 156:Drivers/CMSIS/Include/core_cm0plus.h **** #define __Vendor_SysTickConfig 0U + 157:Drivers/CMSIS/Include/core_cm0plus.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 158:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 159:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 160:Drivers/CMSIS/Include/core_cm0plus.h **** + 161:Drivers/CMSIS/Include/core_cm0plus.h **** /* IO definitions (access restrictions to peripheral registers) */ + 162:Drivers/CMSIS/Include/core_cm0plus.h **** /** + ARM GAS /tmp/cc5M7qsZ.s page 7 + + + 163:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 164:Drivers/CMSIS/Include/core_cm0plus.h **** + 165:Drivers/CMSIS/Include/core_cm0plus.h **** IO Type Qualifiers are used + 166:Drivers/CMSIS/Include/core_cm0plus.h **** \li to specify the access to peripheral variables. + 167:Drivers/CMSIS/Include/core_cm0plus.h **** \li for automatic generation of peripheral register debug information. + 168:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 169:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef __cplusplus + 170:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 171:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 172:Drivers/CMSIS/Include/core_cm0plus.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 173:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 174:Drivers/CMSIS/Include/core_cm0plus.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 175:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 176:Drivers/CMSIS/Include/core_cm0plus.h **** + 177:Drivers/CMSIS/Include/core_cm0plus.h **** /* following defines should be used for structure members */ + 178:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 179:Drivers/CMSIS/Include/core_cm0plus.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 180:Drivers/CMSIS/Include/core_cm0plus.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 181:Drivers/CMSIS/Include/core_cm0plus.h **** + 182:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group Cortex-M0+ */ + 183:Drivers/CMSIS/Include/core_cm0plus.h **** + 184:Drivers/CMSIS/Include/core_cm0plus.h **** + 185:Drivers/CMSIS/Include/core_cm0plus.h **** + 186:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 187:Drivers/CMSIS/Include/core_cm0plus.h **** * Register Abstraction + 188:Drivers/CMSIS/Include/core_cm0plus.h **** Core Register contain: + 189:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register + 190:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Register + 191:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SCB Register + 192:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Register + 193:Drivers/CMSIS/Include/core_cm0plus.h **** - Core MPU Register + 194:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 195:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 196:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 197:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 198:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 199:Drivers/CMSIS/Include/core_cm0plus.h **** + 200:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 201:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 202:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CORE Status and Control Registers + 203:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Core Register type definitions. + 204:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 205:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 206:Drivers/CMSIS/Include/core_cm0plus.h **** + 207:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 208:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Application Program Status Register (APSR). + 209:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 210:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 211:Drivers/CMSIS/Include/core_cm0plus.h **** { + 212:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 213:Drivers/CMSIS/Include/core_cm0plus.h **** { + 214:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + 215:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 216:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 217:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 218:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 219:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + ARM GAS /tmp/cc5M7qsZ.s page 8 + + + 220:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 221:Drivers/CMSIS/Include/core_cm0plus.h **** } APSR_Type; + 222:Drivers/CMSIS/Include/core_cm0plus.h **** + 223:Drivers/CMSIS/Include/core_cm0plus.h **** /* APSR Register Definitions */ + 224:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Pos 31U /*!< APSR + 225:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 226:Drivers/CMSIS/Include/core_cm0plus.h **** + 227:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Pos 30U /*!< APSR + 228:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 229:Drivers/CMSIS/Include/core_cm0plus.h **** + 230:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Pos 29U /*!< APSR + 231:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 232:Drivers/CMSIS/Include/core_cm0plus.h **** + 233:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Pos 28U /*!< APSR + 234:Drivers/CMSIS/Include/core_cm0plus.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 235:Drivers/CMSIS/Include/core_cm0plus.h **** + 236:Drivers/CMSIS/Include/core_cm0plus.h **** + 237:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 238:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 239:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 240:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 241:Drivers/CMSIS/Include/core_cm0plus.h **** { + 242:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 243:Drivers/CMSIS/Include/core_cm0plus.h **** { + 244:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 245:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 246:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 247:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 248:Drivers/CMSIS/Include/core_cm0plus.h **** } IPSR_Type; + 249:Drivers/CMSIS/Include/core_cm0plus.h **** + 250:Drivers/CMSIS/Include/core_cm0plus.h **** /* IPSR Register Definitions */ + 251:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 252:Drivers/CMSIS/Include/core_cm0plus.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 253:Drivers/CMSIS/Include/core_cm0plus.h **** + 254:Drivers/CMSIS/Include/core_cm0plus.h **** + 255:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 256:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 257:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 258:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 259:Drivers/CMSIS/Include/core_cm0plus.h **** { + 260:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 261:Drivers/CMSIS/Include/core_cm0plus.h **** { + 262:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 263:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + 264:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + 265:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + 266:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 267:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 268:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 269:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 270:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 271:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 272:Drivers/CMSIS/Include/core_cm0plus.h **** } xPSR_Type; + 273:Drivers/CMSIS/Include/core_cm0plus.h **** + 274:Drivers/CMSIS/Include/core_cm0plus.h **** /* xPSR Register Definitions */ + 275:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Pos 31U /*!< xPSR + 276:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + ARM GAS /tmp/cc5M7qsZ.s page 9 + + + 277:Drivers/CMSIS/Include/core_cm0plus.h **** + 278:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 279:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 280:Drivers/CMSIS/Include/core_cm0plus.h **** + 281:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Pos 29U /*!< xPSR + 282:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 283:Drivers/CMSIS/Include/core_cm0plus.h **** + 284:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Pos 28U /*!< xPSR + 285:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 286:Drivers/CMSIS/Include/core_cm0plus.h **** + 287:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Pos 24U /*!< xPSR + 288:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 289:Drivers/CMSIS/Include/core_cm0plus.h **** + 290:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 291:Drivers/CMSIS/Include/core_cm0plus.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 292:Drivers/CMSIS/Include/core_cm0plus.h **** + 293:Drivers/CMSIS/Include/core_cm0plus.h **** + 294:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 295:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Union type to access the Control Registers (CONTROL). + 296:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 297:Drivers/CMSIS/Include/core_cm0plus.h **** typedef union + 298:Drivers/CMSIS/Include/core_cm0plus.h **** { + 299:Drivers/CMSIS/Include/core_cm0plus.h **** struct + 300:Drivers/CMSIS/Include/core_cm0plus.h **** { + 301:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 302:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 303:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + 304:Drivers/CMSIS/Include/core_cm0plus.h **** } b; /*!< Structure used for bit access */ + 305:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t w; /*!< Type used for word access */ + 306:Drivers/CMSIS/Include/core_cm0plus.h **** } CONTROL_Type; + 307:Drivers/CMSIS/Include/core_cm0plus.h **** + 308:Drivers/CMSIS/Include/core_cm0plus.h **** /* CONTROL Register Definitions */ + 309:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 310:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 311:Drivers/CMSIS/Include/core_cm0plus.h **** + 312:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 313:Drivers/CMSIS/Include/core_cm0plus.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 314:Drivers/CMSIS/Include/core_cm0plus.h **** + 315:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CORE */ + 316:Drivers/CMSIS/Include/core_cm0plus.h **** + 317:Drivers/CMSIS/Include/core_cm0plus.h **** + 318:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 319:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 320:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 321:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the NVIC Registers + 322:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 323:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 324:Drivers/CMSIS/Include/core_cm0plus.h **** + 325:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 326:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 327:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 328:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 329:Drivers/CMSIS/Include/core_cm0plus.h **** { + 330:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 331:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0[31U]; + 332:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 333:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED1[31U]; + ARM GAS /tmp/cc5M7qsZ.s page 10 + + + 334:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 335:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED2[31U]; + 336:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 337:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED3[31U]; + 338:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED4[64U]; + 339:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ + 340:Drivers/CMSIS/Include/core_cm0plus.h **** } NVIC_Type; + 341:Drivers/CMSIS/Include/core_cm0plus.h **** + 342:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_NVIC */ + 343:Drivers/CMSIS/Include/core_cm0plus.h **** + 344:Drivers/CMSIS/Include/core_cm0plus.h **** + 345:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 346:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 347:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 348:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Control Block Registers + 349:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 350:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 351:Drivers/CMSIS/Include/core_cm0plus.h **** + 352:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 353:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Control Block (SCB). + 354:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 355:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 356:Drivers/CMSIS/Include/core_cm0plus.h **** { + 357:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 358:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 359:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + 360:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 361:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 362:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED0; + 363:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 364:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 365:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 366:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 367:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t RESERVED1; + 368:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registe + 369:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 370:Drivers/CMSIS/Include/core_cm0plus.h **** } SCB_Type; + 371:Drivers/CMSIS/Include/core_cm0plus.h **** + 372:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB CPUID Register Definitions */ + 373:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 374:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 375:Drivers/CMSIS/Include/core_cm0plus.h **** + 376:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 377:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 378:Drivers/CMSIS/Include/core_cm0plus.h **** + 379:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 380:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 381:Drivers/CMSIS/Include/core_cm0plus.h **** + 382:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 383:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 384:Drivers/CMSIS/Include/core_cm0plus.h **** + 385:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 386:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 387:Drivers/CMSIS/Include/core_cm0plus.h **** + 388:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */ + 389:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 390:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + ARM GAS /tmp/cc5M7qsZ.s page 11 + + + 391:Drivers/CMSIS/Include/core_cm0plus.h **** + 392:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 393:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + 394:Drivers/CMSIS/Include/core_cm0plus.h **** + 395:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 396:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 397:Drivers/CMSIS/Include/core_cm0plus.h **** + 398:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 399:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 400:Drivers/CMSIS/Include/core_cm0plus.h **** + 401:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 402:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 403:Drivers/CMSIS/Include/core_cm0plus.h **** + 404:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 405:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 406:Drivers/CMSIS/Include/core_cm0plus.h **** + 407:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 408:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 409:Drivers/CMSIS/Include/core_cm0plus.h **** + 410:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 411:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 412:Drivers/CMSIS/Include/core_cm0plus.h **** + 413:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 414:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 415:Drivers/CMSIS/Include/core_cm0plus.h **** + 416:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + 417:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Interrupt Control State Register Definitions */ + 418:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB + 419:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 420:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 421:Drivers/CMSIS/Include/core_cm0plus.h **** + 422:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 423:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 424:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 425:Drivers/CMSIS/Include/core_cm0plus.h **** + 426:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 427:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 428:Drivers/CMSIS/Include/core_cm0plus.h **** + 429:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 430:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 431:Drivers/CMSIS/Include/core_cm0plus.h **** + 432:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 433:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 434:Drivers/CMSIS/Include/core_cm0plus.h **** + 435:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 436:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 437:Drivers/CMSIS/Include/core_cm0plus.h **** + 438:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Control Register Definitions */ + 439:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 440:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 441:Drivers/CMSIS/Include/core_cm0plus.h **** + 442:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 443:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + 444:Drivers/CMSIS/Include/core_cm0plus.h **** + 445:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 446:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 447:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/cc5M7qsZ.s page 12 + + + 448:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB Configuration Control Register Definitions */ + 449:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 450:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 451:Drivers/CMSIS/Include/core_cm0plus.h **** + 452:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 453:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 454:Drivers/CMSIS/Include/core_cm0plus.h **** + 455:Drivers/CMSIS/Include/core_cm0plus.h **** /* SCB System Handler Control and State Register Definitions */ + 456:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 457:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 458:Drivers/CMSIS/Include/core_cm0plus.h **** + 459:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SCB */ + 460:Drivers/CMSIS/Include/core_cm0plus.h **** + 461:Drivers/CMSIS/Include/core_cm0plus.h **** + 462:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 463:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 464:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 465:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the System Timer Registers. + 466:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 467:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 468:Drivers/CMSIS/Include/core_cm0plus.h **** + 469:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 470:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the System Timer (SysTick). + 471:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 472:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 473:Drivers/CMSIS/Include/core_cm0plus.h **** { + 474:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 475:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 476:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 477:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 478:Drivers/CMSIS/Include/core_cm0plus.h **** } SysTick_Type; + 479:Drivers/CMSIS/Include/core_cm0plus.h **** + 480:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Control / Status Register Definitions */ + 481:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 482:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 483:Drivers/CMSIS/Include/core_cm0plus.h **** + 484:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + 485:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 486:Drivers/CMSIS/Include/core_cm0plus.h **** + 487:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 488:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 489:Drivers/CMSIS/Include/core_cm0plus.h **** + 490:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 491:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 492:Drivers/CMSIS/Include/core_cm0plus.h **** + 493:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Reload Register Definitions */ + 494:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 495:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 496:Drivers/CMSIS/Include/core_cm0plus.h **** + 497:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Current Register Definitions */ + 498:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 499:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 500:Drivers/CMSIS/Include/core_cm0plus.h **** + 501:Drivers/CMSIS/Include/core_cm0plus.h **** /* SysTick Calibration Register Definitions */ + 502:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 503:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 504:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/cc5M7qsZ.s page 13 + + + 505:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 506:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 507:Drivers/CMSIS/Include/core_cm0plus.h **** + 508:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 509:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 510:Drivers/CMSIS/Include/core_cm0plus.h **** + 511:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_SysTick */ + 512:Drivers/CMSIS/Include/core_cm0plus.h **** + 513:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + 514:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 515:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 516:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) + 517:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Type definitions for the Memory Protection Unit (MPU) + 518:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 519:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 520:Drivers/CMSIS/Include/core_cm0plus.h **** + 521:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 522:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Structure type to access the Memory Protection Unit (MPU). + 523:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 524:Drivers/CMSIS/Include/core_cm0plus.h **** typedef struct + 525:Drivers/CMSIS/Include/core_cm0plus.h **** { + 526:Drivers/CMSIS/Include/core_cm0plus.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + 527:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + 528:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + 529:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register + 530:Drivers/CMSIS/Include/core_cm0plus.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re + 531:Drivers/CMSIS/Include/core_cm0plus.h **** } MPU_Type; + 532:Drivers/CMSIS/Include/core_cm0plus.h **** + 533:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_RALIASES 1U + 534:Drivers/CMSIS/Include/core_cm0plus.h **** + 535:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Type Register Definitions */ + 536:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU + 537:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU + 538:Drivers/CMSIS/Include/core_cm0plus.h **** + 539:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU + 540:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU + 541:Drivers/CMSIS/Include/core_cm0plus.h **** + 542:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU + 543:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU + 544:Drivers/CMSIS/Include/core_cm0plus.h **** + 545:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Control Register Definitions */ + 546:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU + 547:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU + 548:Drivers/CMSIS/Include/core_cm0plus.h **** + 549:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU + 550:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU + 551:Drivers/CMSIS/Include/core_cm0plus.h **** + 552:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU + 553:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU + 554:Drivers/CMSIS/Include/core_cm0plus.h **** + 555:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Number Register Definitions */ + 556:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU + 557:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU + 558:Drivers/CMSIS/Include/core_cm0plus.h **** + 559:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Base Address Register Definitions */ + 560:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Pos 8U /*!< MPU + 561:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU + ARM GAS /tmp/cc5M7qsZ.s page 14 + + + 562:Drivers/CMSIS/Include/core_cm0plus.h **** + 563:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU + 564:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU + 565:Drivers/CMSIS/Include/core_cm0plus.h **** + 566:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU + 567:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU + 568:Drivers/CMSIS/Include/core_cm0plus.h **** + 569:Drivers/CMSIS/Include/core_cm0plus.h **** /* MPU Region Attribute and Size Register Definitions */ + 570:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU + 571:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU + 572:Drivers/CMSIS/Include/core_cm0plus.h **** + 573:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU + 574:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU + 575:Drivers/CMSIS/Include/core_cm0plus.h **** + 576:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU + 577:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU + 578:Drivers/CMSIS/Include/core_cm0plus.h **** + 579:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU + 580:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU + 581:Drivers/CMSIS/Include/core_cm0plus.h **** + 582:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Pos 18U /*!< MPU + 583:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU + 584:Drivers/CMSIS/Include/core_cm0plus.h **** + 585:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Pos 17U /*!< MPU + 586:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU + 587:Drivers/CMSIS/Include/core_cm0plus.h **** + 588:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Pos 16U /*!< MPU + 589:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU + 590:Drivers/CMSIS/Include/core_cm0plus.h **** + 591:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU + 592:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU + 593:Drivers/CMSIS/Include/core_cm0plus.h **** + 594:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU + 595:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU + 596:Drivers/CMSIS/Include/core_cm0plus.h **** + 597:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU + 598:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU + 599:Drivers/CMSIS/Include/core_cm0plus.h **** + 600:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_MPU */ + 601:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 602:Drivers/CMSIS/Include/core_cm0plus.h **** + 603:Drivers/CMSIS/Include/core_cm0plus.h **** + 604:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 605:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 606:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + 607:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ov + 608:Drivers/CMSIS/Include/core_cm0plus.h **** Therefore they are not covered by the Cortex-M0+ header file. + 609:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 610:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 611:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_CoreDebug */ + 612:Drivers/CMSIS/Include/core_cm0plus.h **** + 613:Drivers/CMSIS/Include/core_cm0plus.h **** + 614:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 615:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 616:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_bitfield Core register bit field macros + 617:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + 618:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + ARM GAS /tmp/cc5M7qsZ.s page 15 + + + 619:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 620:Drivers/CMSIS/Include/core_cm0plus.h **** + 621:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 622:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a bit field value for use in a register bit range. + 623:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field. + 624:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + 625:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted value. + 626:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 627:Drivers/CMSIS/Include/core_cm0plus.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + 628:Drivers/CMSIS/Include/core_cm0plus.h **** + 629:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 630:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Mask and shift a register value to extract a bit filed value. + 631:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] field Name of the register bit field. + 632:Drivers/CMSIS/Include/core_cm0plus.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + 633:Drivers/CMSIS/Include/core_cm0plus.h **** \return Masked and shifted bit field value. + 634:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 635:Drivers/CMSIS/Include/core_cm0plus.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + 636:Drivers/CMSIS/Include/core_cm0plus.h **** + 637:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of group CMSIS_core_bitfield */ + 638:Drivers/CMSIS/Include/core_cm0plus.h **** + 639:Drivers/CMSIS/Include/core_cm0plus.h **** + 640:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 641:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_core_register + 642:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_core_base Core Definitions + 643:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Definitions for base addresses, unions, and structures. + 644:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 645:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 646:Drivers/CMSIS/Include/core_cm0plus.h **** + 647:Drivers/CMSIS/Include/core_cm0plus.h **** /* Memory mapping of Core Hardware */ + 648:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas + 649:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + 650:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + 651:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas + 652:Drivers/CMSIS/Include/core_cm0plus.h **** + 653:Drivers/CMSIS/Include/core_cm0plus.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct + 654:Drivers/CMSIS/Include/core_cm0plus.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st + 655:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc + 656:Drivers/CMSIS/Include/core_cm0plus.h **** + 657:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + 658:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * + 659:Drivers/CMSIS/Include/core_cm0plus.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * + 660:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 661:Drivers/CMSIS/Include/core_cm0plus.h **** + 662:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} */ + 663:Drivers/CMSIS/Include/core_cm0plus.h **** + 664:Drivers/CMSIS/Include/core_cm0plus.h **** + 665:Drivers/CMSIS/Include/core_cm0plus.h **** + 666:Drivers/CMSIS/Include/core_cm0plus.h **** /******************************************************************************* + 667:Drivers/CMSIS/Include/core_cm0plus.h **** * Hardware Abstraction Layer + 668:Drivers/CMSIS/Include/core_cm0plus.h **** Core Function Interface contains: + 669:Drivers/CMSIS/Include/core_cm0plus.h **** - Core NVIC Functions + 670:Drivers/CMSIS/Include/core_cm0plus.h **** - Core SysTick Functions + 671:Drivers/CMSIS/Include/core_cm0plus.h **** - Core Register Access Functions + 672:Drivers/CMSIS/Include/core_cm0plus.h **** ******************************************************************************/ + 673:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 674:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference + 675:Drivers/CMSIS/Include/core_cm0plus.h **** */ + ARM GAS /tmp/cc5M7qsZ.s page 16 + + + 676:Drivers/CMSIS/Include/core_cm0plus.h **** + 677:Drivers/CMSIS/Include/core_cm0plus.h **** + 678:Drivers/CMSIS/Include/core_cm0plus.h **** + 679:Drivers/CMSIS/Include/core_cm0plus.h **** /* ########################## NVIC functions #################################### */ + 680:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 681:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface + 682:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions + 683:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that manage interrupts and exceptions via the NVIC. + 684:Drivers/CMSIS/Include/core_cm0plus.h **** @{ + 685:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 686:Drivers/CMSIS/Include/core_cm0plus.h **** + 687:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef CMSIS_NVIC_VIRTUAL + 688:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + 689:Drivers/CMSIS/Include/core_cm0plus.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + 690:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 691:Drivers/CMSIS/Include/core_cm0plus.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE + 692:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 693:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + 694:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + 695:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ + 696:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + 697:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ + 698:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + 699:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + 700:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + 701:Drivers/CMSIS/Include/core_cm0plus.h **** /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + 702:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_SetPriority __NVIC_SetPriority + 703:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_GetPriority __NVIC_GetPriority + 704:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_SystemReset __NVIC_SystemReset + 705:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* CMSIS_NVIC_VIRTUAL */ + 706:Drivers/CMSIS/Include/core_cm0plus.h **** + 707:Drivers/CMSIS/Include/core_cm0plus.h **** #ifdef CMSIS_VECTAB_VIRTUAL + 708:Drivers/CMSIS/Include/core_cm0plus.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + 709:Drivers/CMSIS/Include/core_cm0plus.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + 710:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 711:Drivers/CMSIS/Include/core_cm0plus.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE + 712:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 713:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_SetVector __NVIC_SetVector + 714:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_GetVector __NVIC_GetVector + 715:Drivers/CMSIS/Include/core_cm0plus.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ + 716:Drivers/CMSIS/Include/core_cm0plus.h **** + 717:Drivers/CMSIS/Include/core_cm0plus.h **** #define NVIC_USER_IRQ_OFFSET 16 + 718:Drivers/CMSIS/Include/core_cm0plus.h **** + 719:Drivers/CMSIS/Include/core_cm0plus.h **** + 720:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ + 721:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret + 722:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu + 723:Drivers/CMSIS/Include/core_cm0plus.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu + 724:Drivers/CMSIS/Include/core_cm0plus.h **** + 725:Drivers/CMSIS/Include/core_cm0plus.h **** + 726:Drivers/CMSIS/Include/core_cm0plus.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M */ + 727:Drivers/CMSIS/Include/core_cm0plus.h **** /* The following MACROS handle generation of the register offset and byte masks */ + 728:Drivers/CMSIS/Include/core_cm0plus.h **** #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) + 729:Drivers/CMSIS/Include/core_cm0plus.h **** #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) + 730:Drivers/CMSIS/Include/core_cm0plus.h **** #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + 731:Drivers/CMSIS/Include/core_cm0plus.h **** + 732:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X) + ARM GAS /tmp/cc5M7qsZ.s page 17 + + + 733:Drivers/CMSIS/Include/core_cm0plus.h **** #define __NVIC_GetPriorityGrouping() (0U) + 734:Drivers/CMSIS/Include/core_cm0plus.h **** + 735:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 736:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Enable Interrupt + 737:Drivers/CMSIS/Include/core_cm0plus.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. + 738:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 739:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 740:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 741:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) + 742:Drivers/CMSIS/Include/core_cm0plus.h **** { + 743:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 744:Drivers/CMSIS/Include/core_cm0plus.h **** { + 745:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + 746:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 747:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + 748:Drivers/CMSIS/Include/core_cm0plus.h **** } + 749:Drivers/CMSIS/Include/core_cm0plus.h **** } + 750:Drivers/CMSIS/Include/core_cm0plus.h **** + 751:Drivers/CMSIS/Include/core_cm0plus.h **** + 752:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 753:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Interrupt Enable status + 754:Drivers/CMSIS/Include/core_cm0plus.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + 755:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 756:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Interrupt is not enabled. + 757:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Interrupt is enabled. + 758:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 759:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 760:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) + 761:Drivers/CMSIS/Include/core_cm0plus.h **** { + 762:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 763:Drivers/CMSIS/Include/core_cm0plus.h **** { + 764:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) + 765:Drivers/CMSIS/Include/core_cm0plus.h **** } + 766:Drivers/CMSIS/Include/core_cm0plus.h **** else + 767:Drivers/CMSIS/Include/core_cm0plus.h **** { + 768:Drivers/CMSIS/Include/core_cm0plus.h **** return(0U); + 769:Drivers/CMSIS/Include/core_cm0plus.h **** } + 770:Drivers/CMSIS/Include/core_cm0plus.h **** } + 771:Drivers/CMSIS/Include/core_cm0plus.h **** + 772:Drivers/CMSIS/Include/core_cm0plus.h **** + 773:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 774:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Disable Interrupt + 775:Drivers/CMSIS/Include/core_cm0plus.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. + 776:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 777:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 778:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 779:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) + 780:Drivers/CMSIS/Include/core_cm0plus.h **** { + 781:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 782:Drivers/CMSIS/Include/core_cm0plus.h **** { + 783:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 784:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); + 785:Drivers/CMSIS/Include/core_cm0plus.h **** __ISB(); + 786:Drivers/CMSIS/Include/core_cm0plus.h **** } + 787:Drivers/CMSIS/Include/core_cm0plus.h **** } + 788:Drivers/CMSIS/Include/core_cm0plus.h **** + 789:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/cc5M7qsZ.s page 18 + + + 790:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 791:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Pending Interrupt + 792:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe + 793:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 794:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Interrupt status is not pending. + 795:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Interrupt status is pending. + 796:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 797:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 798:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) + 799:Drivers/CMSIS/Include/core_cm0plus.h **** { + 800:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 801:Drivers/CMSIS/Include/core_cm0plus.h **** { + 802:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) + 803:Drivers/CMSIS/Include/core_cm0plus.h **** } + 804:Drivers/CMSIS/Include/core_cm0plus.h **** else + 805:Drivers/CMSIS/Include/core_cm0plus.h **** { + 806:Drivers/CMSIS/Include/core_cm0plus.h **** return(0U); + 807:Drivers/CMSIS/Include/core_cm0plus.h **** } + 808:Drivers/CMSIS/Include/core_cm0plus.h **** } + 809:Drivers/CMSIS/Include/core_cm0plus.h **** + 810:Drivers/CMSIS/Include/core_cm0plus.h **** + 811:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 812:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Pending Interrupt + 813:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + 814:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 815:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 816:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 817:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) + 818:Drivers/CMSIS/Include/core_cm0plus.h **** { + 819:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 820:Drivers/CMSIS/Include/core_cm0plus.h **** { + 821:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 822:Drivers/CMSIS/Include/core_cm0plus.h **** } + 823:Drivers/CMSIS/Include/core_cm0plus.h **** } + 824:Drivers/CMSIS/Include/core_cm0plus.h **** + 825:Drivers/CMSIS/Include/core_cm0plus.h **** + 826:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 827:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Clear Pending Interrupt + 828:Drivers/CMSIS/Include/core_cm0plus.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + 829:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Device specific interrupt number. + 830:Drivers/CMSIS/Include/core_cm0plus.h **** \note IRQn must not be negative. + 831:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 832:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 833:Drivers/CMSIS/Include/core_cm0plus.h **** { + 834:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 835:Drivers/CMSIS/Include/core_cm0plus.h **** { + 836:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 837:Drivers/CMSIS/Include/core_cm0plus.h **** } + 838:Drivers/CMSIS/Include/core_cm0plus.h **** } + 839:Drivers/CMSIS/Include/core_cm0plus.h **** + 840:Drivers/CMSIS/Include/core_cm0plus.h **** + 841:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 842:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Interrupt Priority + 843:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets the priority of a device specific interrupt or a processor exception. + 844:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify a device specific interrupt, + 845:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify a processor exception. + 846:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + ARM GAS /tmp/cc5M7qsZ.s page 19 + + + 847:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] priority Priority to set. + 848:Drivers/CMSIS/Include/core_cm0plus.h **** \note The priority cannot be set for every processor exception. + 849:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 850:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) + 46 .loc 2 850 22 view .LVU4 + 47 .LBB35: + 851:Drivers/CMSIS/Include/core_cm0plus.h **** { + 852:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 48 .loc 2 852 3 view .LVU5 + 49 .loc 2 852 6 is_stmt 0 view .LVU6 + 50 0002 0028 cmp r0, #0 + 51 0004 11DB blt .L2 + 853:Drivers/CMSIS/Include/core_cm0plus.h **** { + 854:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 52 .loc 2 854 5 is_stmt 1 view .LVU7 + 53 .loc 2 854 53 is_stmt 0 view .LVU8 + 54 0006 8308 lsrs r3, r0, #2 + 55 .loc 2 854 52 view .LVU9 + 56 0008 134E ldr r6, .L4 + 57 000a C033 adds r3, r3, #192 + 58 000c 9B00 lsls r3, r3, #2 + 59 000e 9D59 ldr r5, [r3, r6] + 60 .loc 2 854 83 view .LVU10 + 61 0010 0324 movs r4, #3 + 62 0012 2040 ands r0, r4 + 63 .LVL2: + 64 .loc 2 854 83 view .LVU11 + 65 0014 C000 lsls r0, r0, #3 + 66 .loc 2 854 80 view .LVU12 + 67 0016 FF22 movs r2, #255 + 68 .LVL3: + 69 .loc 2 854 80 view .LVU13 + 70 0018 1400 movs r4, r2 + 71 001a 8440 lsls r4, r4, r0 + 72 .loc 2 854 33 view .LVU14 + 73 001c A543 bics r5, r4 + 855:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 74 .loc 2 855 20 view .LVU15 + 75 001e 8901 lsls r1, r1, #6 + 76 .LVL4: + 77 .loc 2 855 48 view .LVU16 + 78 0020 0A40 ands r2, r1 + 79 .loc 2 855 68 view .LVU17 + 80 0022 8240 lsls r2, r2, r0 + 854:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 81 .loc 2 854 102 view .LVU18 + 82 0024 2A43 orrs r2, r5 + 854:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 83 .loc 2 854 30 view .LVU19 + 84 0026 9A51 str r2, [r3, r6] + 85 .LVL5: + 86 .L1: + 854:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 87 .loc 2 854 30 view .LVU20 + 88 .LBE35: + 89 .LBE34: + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + ARM GAS /tmp/cc5M7qsZ.s page 20 + + + 90 .loc 1 137 1 view .LVU21 + 91 @ sp needed + 92 0028 70BD pop {r4, r5, r6, pc} + 93 .LVL6: + 94 .L2: + 95 .LBB37: + 96 .LBB36: + 856:Drivers/CMSIS/Include/core_cm0plus.h **** } + 857:Drivers/CMSIS/Include/core_cm0plus.h **** else + 858:Drivers/CMSIS/Include/core_cm0plus.h **** { + 859:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) + 97 .loc 2 859 5 is_stmt 1 view .LVU22 + 98 .loc 2 859 53 is_stmt 0 view .LVU23 + 99 002a 0F23 movs r3, #15 + 100 002c 0340 ands r3, r0 + 101 002e 083B subs r3, r3, #8 + 102 0030 9B08 lsrs r3, r3, #2 + 103 .loc 2 859 52 view .LVU24 + 104 0032 0633 adds r3, r3, #6 + 105 0034 9B00 lsls r3, r3, #2 + 106 0036 094A ldr r2, .L4+4 + 107 .LVL7: + 108 .loc 2 859 52 view .LVU25 + 109 0038 9446 mov ip, r2 + 110 003a 6344 add r3, r3, ip + 111 003c 5C68 ldr r4, [r3, #4] + 112 .loc 2 859 83 view .LVU26 + 113 003e 0322 movs r2, #3 + 114 0040 1040 ands r0, r2 + 115 .LVL8: + 116 .loc 2 859 83 view .LVU27 + 117 0042 C000 lsls r0, r0, #3 + 118 .loc 2 859 80 view .LVU28 + 119 0044 FC32 adds r2, r2, #252 + 120 0046 1500 movs r5, r2 + 121 0048 8540 lsls r5, r5, r0 + 122 .loc 2 859 33 view .LVU29 + 123 004a AC43 bics r4, r5 + 860:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 124 .loc 2 860 20 view .LVU30 + 125 004c 8901 lsls r1, r1, #6 + 126 .LVL9: + 127 .loc 2 860 48 view .LVU31 + 128 004e 0A40 ands r2, r1 + 129 .loc 2 860 68 view .LVU32 + 130 0050 8240 lsls r2, r2, r0 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 131 .loc 2 859 102 view .LVU33 + 132 0052 2243 orrs r2, r4 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 133 .loc 2 859 30 view .LVU34 + 134 0054 5A60 str r2, [r3, #4] + 135 .LVL10: + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 136 .loc 2 859 30 view .LVU35 + 137 .LBE36: + 138 .LBE37: + ARM GAS /tmp/cc5M7qsZ.s page 21 + + + 139 .loc 1 137 1 view .LVU36 + 140 0056 E7E7 b .L1 + 141 .L5: + 142 .align 2 + 143 .L4: + 144 0058 00E100E0 .word -536813312 + 145 005c 00ED00E0 .word -536810240 + 146 .cfi_endproc + 147 .LFE297: + 149 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 150 .align 1 + 151 .global HAL_NVIC_EnableIRQ + 152 .syntax unified + 153 .code 16 + 154 .thumb_func + 155 .fpu softvfp + 157 HAL_NVIC_EnableIRQ: + 158 .LVL11: + 159 .LFB298: + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Enable a device specific interrupt in the NVIC interrupt controller. + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number. + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 160 .loc 1 147 1 is_stmt 1 view -0 + 161 .cfi_startproc + 162 @ args = 0, pretend = 0, frame = 0 + 163 @ frame_needed = 0, uses_anonymous_args = 0 + 164 @ link register save eliminated. + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 165 .loc 1 149 3 view .LVU38 + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Enable interrupt */ + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 166 .loc 1 152 3 view .LVU39 + 167 .LBB38: + 168 .LBI38: + 741:Drivers/CMSIS/Include/core_cm0plus.h **** { + 169 .loc 2 741 22 view .LVU40 + 170 .LBB39: + 743:Drivers/CMSIS/Include/core_cm0plus.h **** { + 171 .loc 2 743 3 view .LVU41 + 743:Drivers/CMSIS/Include/core_cm0plus.h **** { + 172 .loc 2 743 6 is_stmt 0 view .LVU42 + 173 0000 0028 cmp r0, #0 + 174 0002 05DB blt .L6 + 745:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 175 .loc 2 745 5 is_stmt 1 view .LVU43 + 746:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + 176 .loc 2 746 5 view .LVU44 + 746:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + ARM GAS /tmp/cc5M7qsZ.s page 22 + + + 177 .loc 2 746 58 is_stmt 0 view .LVU45 + 178 0004 1F23 movs r3, #31 + 179 0006 1840 ands r0, r3 + 180 .LVL12: + 746:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + 181 .loc 2 746 22 view .LVU46 + 182 0008 1E3B subs r3, r3, #30 + 183 000a 8340 lsls r3, r3, r0 + 746:Drivers/CMSIS/Include/core_cm0plus.h **** __COMPILER_BARRIER(); + 184 .loc 2 746 20 view .LVU47 + 185 000c 014A ldr r2, .L8 + 186 000e 1360 str r3, [r2] + 747:Drivers/CMSIS/Include/core_cm0plus.h **** } + 187 .loc 2 747 5 is_stmt 1 view .LVU48 + 188 .LVL13: + 189 .L6: + 747:Drivers/CMSIS/Include/core_cm0plus.h **** } + 190 .loc 2 747 5 is_stmt 0 view .LVU49 + 191 .LBE39: + 192 .LBE38: + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 193 .loc 1 153 1 view .LVU50 + 194 @ sp needed + 195 0010 7047 bx lr + 196 .L9: + 197 0012 C046 .align 2 + 198 .L8: + 199 0014 00E100E0 .word -536813312 + 200 .cfi_endproc + 201 .LFE298: + 203 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 204 .align 1 + 205 .global HAL_NVIC_DisableIRQ + 206 .syntax unified + 207 .code 16 + 208 .thumb_func + 209 .fpu softvfp + 211 HAL_NVIC_DisableIRQ: + 212 .LVL14: + 213 .LFB299: + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Disable a device specific interrupt in the NVIC interrupt controller. + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number. + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 214 .loc 1 163 1 is_stmt 1 view -0 + 215 .cfi_startproc + 216 @ args = 0, pretend = 0, frame = 0 + 217 @ frame_needed = 0, uses_anonymous_args = 0 + 218 @ link register save eliminated. + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + ARM GAS /tmp/cc5M7qsZ.s page 23 + + + 219 .loc 1 165 3 view .LVU52 + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Disable interrupt */ + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 220 .loc 1 168 3 view .LVU53 + 221 .LBB40: + 222 .LBI40: + 779:Drivers/CMSIS/Include/core_cm0plus.h **** { + 223 .loc 2 779 22 view .LVU54 + 224 .LBB41: + 781:Drivers/CMSIS/Include/core_cm0plus.h **** { + 225 .loc 2 781 3 view .LVU55 + 781:Drivers/CMSIS/Include/core_cm0plus.h **** { + 226 .loc 2 781 6 is_stmt 0 view .LVU56 + 227 0000 0028 cmp r0, #0 + 228 0002 0ADB blt .L10 + 783:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); + 229 .loc 2 783 5 is_stmt 1 view .LVU57 + 783:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); + 230 .loc 2 783 58 is_stmt 0 view .LVU58 + 231 0004 1F23 movs r3, #31 + 232 0006 1840 ands r0, r3 + 233 .LVL15: + 783:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); + 234 .loc 2 783 22 view .LVU59 + 235 0008 1E3B subs r3, r3, #30 + 236 000a 8340 lsls r3, r3, r0 + 783:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); + 237 .loc 2 783 20 view .LVU60 + 238 000c 0349 ldr r1, .L12 + 239 000e 8022 movs r2, #128 + 240 0010 8B50 str r3, [r1, r2] + 784:Drivers/CMSIS/Include/core_cm0plus.h **** __ISB(); + 241 .loc 2 784 5 is_stmt 1 view .LVU61 + 242 .LBB42: + 243 .LBI42: + 244 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + ARM GAS /tmp/cc5M7qsZ.s page 24 + + + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/cc5M7qsZ.s page 25 + + + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5M7qsZ.s page 26 + + + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc5M7qsZ.s page 27 + + + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + ARM GAS /tmp/cc5M7qsZ.s page 28 + + + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/cc5M7qsZ.s page 29 + + + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5M7qsZ.s page 30 + + + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + ARM GAS /tmp/cc5M7qsZ.s page 31 + + + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + ARM GAS /tmp/cc5M7qsZ.s page 32 + + + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/cc5M7qsZ.s page 33 + + + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + ARM GAS /tmp/cc5M7qsZ.s page 34 + + + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + ARM GAS /tmp/cc5M7qsZ.s page 35 + + + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + ARM GAS /tmp/cc5M7qsZ.s page 36 + + + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc5M7qsZ.s page 37 + + + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/cc5M7qsZ.s page 38 + + + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc5M7qsZ.s page 39 + + + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc5M7qsZ.s page 40 + + + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 245 .loc 3 944 27 view .LVU62 + 246 .LBB43: + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 247 .loc 3 946 3 view .LVU63 + 248 .syntax divided + 249 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 250 0012 BFF34F8F dsb 0xF + 251 @ 0 "" 2 + 252 .thumb + 253 .syntax unified + 254 .LBE43: + 255 .LBE42: + 785:Drivers/CMSIS/Include/core_cm0plus.h **** } + 256 .loc 2 785 5 view .LVU64 + 257 .LBB44: + 258 .LBI44: + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 259 .loc 3 933 27 view .LVU65 + 260 .LBB45: + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 261 .loc 3 935 3 view .LVU66 + 262 .syntax divided + 263 @ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 264 0016 BFF36F8F isb 0xF + 265 @ 0 "" 2 + 266 .LVL16: + 267 .thumb + 268 .syntax unified + 269 .L10: + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 270 .loc 3 935 3 is_stmt 0 view .LVU67 + 271 .LBE45: + 272 .LBE44: + 273 .LBE41: + 274 .LBE40: + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 275 .loc 1 169 1 view .LVU68 + 276 @ sp needed + 277 001a 7047 bx lr + 278 .L13: + 279 .align 2 + 280 .L12: + 281 001c 00E100E0 .word -536813312 + 282 .cfi_endproc + ARM GAS /tmp/cc5M7qsZ.s page 41 + + + 283 .LFE299: + 285 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 286 .align 1 + 287 .global HAL_NVIC_SystemReset + 288 .syntax unified + 289 .code 16 + 290 .thumb_func + 291 .fpu softvfp + 293 HAL_NVIC_SystemReset: + 294 .LFB300: + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Initiate a system reset request to reset the MCU. + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 295 .loc 1 176 1 is_stmt 1 view -0 + 296 .cfi_startproc + 297 @ Volatile: function does not return. + 298 @ args = 0, pretend = 0, frame = 0 + 299 @ frame_needed = 0, uses_anonymous_args = 0 + 300 @ link register save eliminated. + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* System Reset */ + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_SystemReset(); + 301 .loc 1 178 3 view .LVU70 + 302 .LBB52: + 303 .LBI52: + 861:Drivers/CMSIS/Include/core_cm0plus.h **** } + 862:Drivers/CMSIS/Include/core_cm0plus.h **** } + 863:Drivers/CMSIS/Include/core_cm0plus.h **** + 864:Drivers/CMSIS/Include/core_cm0plus.h **** + 865:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 866:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Interrupt Priority + 867:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads the priority of a device specific interrupt or a processor exception. + 868:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify a device specific interrupt, + 869:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify a processor exception. + 870:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + 871:Drivers/CMSIS/Include/core_cm0plus.h **** \return Interrupt Priority. + 872:Drivers/CMSIS/Include/core_cm0plus.h **** Value is aligned automatically to the implemented priority bits of the microc + 873:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 874:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) + 875:Drivers/CMSIS/Include/core_cm0plus.h **** { + 876:Drivers/CMSIS/Include/core_cm0plus.h **** + 877:Drivers/CMSIS/Include/core_cm0plus.h **** if ((int32_t)(IRQn) >= 0) + 878:Drivers/CMSIS/Include/core_cm0plus.h **** { + 879:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - + 880:Drivers/CMSIS/Include/core_cm0plus.h **** } + 881:Drivers/CMSIS/Include/core_cm0plus.h **** else + 882:Drivers/CMSIS/Include/core_cm0plus.h **** { + 883:Drivers/CMSIS/Include/core_cm0plus.h **** return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - + 884:Drivers/CMSIS/Include/core_cm0plus.h **** } + 885:Drivers/CMSIS/Include/core_cm0plus.h **** } + 886:Drivers/CMSIS/Include/core_cm0plus.h **** + 887:Drivers/CMSIS/Include/core_cm0plus.h **** + 888:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 889:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Encode Priority + ARM GAS /tmp/cc5M7qsZ.s page 42 + + + 890:Drivers/CMSIS/Include/core_cm0plus.h **** \details Encodes the priority for an interrupt with the given priority group, + 891:Drivers/CMSIS/Include/core_cm0plus.h **** preemptive priority value, and subpriority value. + 892:Drivers/CMSIS/Include/core_cm0plus.h **** In case of a conflict between priority grouping and available + 893:Drivers/CMSIS/Include/core_cm0plus.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + 894:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] PriorityGroup Used priority group. + 895:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). + 896:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] SubPriority Subpriority value (starting from 0). + 897:Drivers/CMSIS/Include/core_cm0plus.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP + 898:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 899:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin + 900:Drivers/CMSIS/Include/core_cm0plus.h **** { + 901:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 902:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t PreemptPriorityBits; + 903:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t SubPriorityBits; + 904:Drivers/CMSIS/Include/core_cm0plus.h **** + 905:Drivers/CMSIS/Include/core_cm0plus.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 906:Drivers/CMSIS/Include/core_cm0plus.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 907:Drivers/CMSIS/Include/core_cm0plus.h **** + 908:Drivers/CMSIS/Include/core_cm0plus.h **** return ( + 909:Drivers/CMSIS/Include/core_cm0plus.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 910:Drivers/CMSIS/Include/core_cm0plus.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 911:Drivers/CMSIS/Include/core_cm0plus.h **** ); + 912:Drivers/CMSIS/Include/core_cm0plus.h **** } + 913:Drivers/CMSIS/Include/core_cm0plus.h **** + 914:Drivers/CMSIS/Include/core_cm0plus.h **** + 915:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 916:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Decode Priority + 917:Drivers/CMSIS/Include/core_cm0plus.h **** \details Decodes an interrupt priority value with a given priority group to + 918:Drivers/CMSIS/Include/core_cm0plus.h **** preemptive priority value and subpriority value. + 919:Drivers/CMSIS/Include/core_cm0plus.h **** In case of a conflict between priority grouping and available + 920:Drivers/CMSIS/Include/core_cm0plus.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + 921:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC + 922:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] PriorityGroup Used priority group. + 923:Drivers/CMSIS/Include/core_cm0plus.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). + 924:Drivers/CMSIS/Include/core_cm0plus.h **** \param [out] pSubPriority Subpriority value (starting from 0). + 925:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 926:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons + 927:Drivers/CMSIS/Include/core_cm0plus.h **** { + 928:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 929:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t PreemptPriorityBits; + 930:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t SubPriorityBits; + 931:Drivers/CMSIS/Include/core_cm0plus.h **** + 932:Drivers/CMSIS/Include/core_cm0plus.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 933:Drivers/CMSIS/Include/core_cm0plus.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 934:Drivers/CMSIS/Include/core_cm0plus.h **** + 935:Drivers/CMSIS/Include/core_cm0plus.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 + 936:Drivers/CMSIS/Include/core_cm0plus.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 937:Drivers/CMSIS/Include/core_cm0plus.h **** } + 938:Drivers/CMSIS/Include/core_cm0plus.h **** + 939:Drivers/CMSIS/Include/core_cm0plus.h **** + 940:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 941:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Set Interrupt Vector + 942:Drivers/CMSIS/Include/core_cm0plus.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. + 943:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify a device specific interrupt, + 944:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify a processor exception. + 945:Drivers/CMSIS/Include/core_cm0plus.h **** VTOR must been relocated to SRAM before. + 946:Drivers/CMSIS/Include/core_cm0plus.h **** If VTOR is not present address 0 must be mapped to SRAM. + ARM GAS /tmp/cc5M7qsZ.s page 43 + + + 947:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number + 948:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] vector Address of interrupt handler function + 949:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 950:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) + 951:Drivers/CMSIS/Include/core_cm0plus.h **** { + 952:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + 953:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t vectors = SCB->VTOR; + 954:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 955:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t vectors = 0x0U; + 956:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 957:Drivers/CMSIS/Include/core_cm0plus.h **** (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + 958:Drivers/CMSIS/Include/core_cm0plus.h **** /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ + 959:Drivers/CMSIS/Include/core_cm0plus.h **** } + 960:Drivers/CMSIS/Include/core_cm0plus.h **** + 961:Drivers/CMSIS/Include/core_cm0plus.h **** + 962:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 963:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Get Interrupt Vector + 964:Drivers/CMSIS/Include/core_cm0plus.h **** \details Reads an interrupt vector from interrupt vector table. + 965:Drivers/CMSIS/Include/core_cm0plus.h **** The interrupt number can be positive to specify a device specific interrupt, + 966:Drivers/CMSIS/Include/core_cm0plus.h **** or negative to specify a processor exception. + 967:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] IRQn Interrupt number. + 968:Drivers/CMSIS/Include/core_cm0plus.h **** \return Address of interrupt handler function + 969:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 970:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) + 971:Drivers/CMSIS/Include/core_cm0plus.h **** { + 972:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + 973:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t vectors = SCB->VTOR; + 974:Drivers/CMSIS/Include/core_cm0plus.h **** #else + 975:Drivers/CMSIS/Include/core_cm0plus.h **** uint32_t vectors = 0x0U; + 976:Drivers/CMSIS/Include/core_cm0plus.h **** #endif + 977:Drivers/CMSIS/Include/core_cm0plus.h **** return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); + 978:Drivers/CMSIS/Include/core_cm0plus.h **** } + 979:Drivers/CMSIS/Include/core_cm0plus.h **** + 980:Drivers/CMSIS/Include/core_cm0plus.h **** + 981:Drivers/CMSIS/Include/core_cm0plus.h **** /** + 982:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Reset + 983:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initiates a system reset request to reset the MCU. + 984:Drivers/CMSIS/Include/core_cm0plus.h **** */ + 985:Drivers/CMSIS/Include/core_cm0plus.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) + 304 .loc 2 985 34 view .LVU71 + 305 .LBB53: + 986:Drivers/CMSIS/Include/core_cm0plus.h **** { + 987:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure all outstanding memor + 306 .loc 2 987 3 view .LVU72 + 307 .LBB54: + 308 .LBI54: + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 309 .loc 3 944 27 view .LVU73 + 310 .LBB55: + 311 .loc 3 946 3 view .LVU74 + 312 .syntax divided + 313 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 314 0000 BFF34F8F dsb 0xF + 315 @ 0 "" 2 + 316 .thumb + 317 .syntax unified + 318 .LBE55: + ARM GAS /tmp/cc5M7qsZ.s page 44 + + + 319 .LBE54: + 988:Drivers/CMSIS/Include/core_cm0plus.h **** buffered write are completed + 989:Drivers/CMSIS/Include/core_cm0plus.h **** SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 320 .loc 2 989 3 view .LVU75 + 321 .loc 2 989 15 is_stmt 0 view .LVU76 + 322 0004 034B ldr r3, .L16 + 323 0006 044A ldr r2, .L16+4 + 324 0008 DA60 str r2, [r3, #12] + 990:Drivers/CMSIS/Include/core_cm0plus.h **** SCB_AIRCR_SYSRESETREQ_Msk); + 991:Drivers/CMSIS/Include/core_cm0plus.h **** __DSB(); /* Ensure completion of memory + 325 .loc 2 991 3 is_stmt 1 view .LVU77 + 326 .LBB56: + 327 .LBI56: + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 328 .loc 3 944 27 view .LVU78 + 329 .LBB57: + 330 .loc 3 946 3 view .LVU79 + 331 .syntax divided + 332 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 333 000a BFF34F8F dsb 0xF + 334 @ 0 "" 2 + 335 .thumb + 336 .syntax unified + 337 .L15: + 338 .LBE57: + 339 .LBE56: + 992:Drivers/CMSIS/Include/core_cm0plus.h **** + 993:Drivers/CMSIS/Include/core_cm0plus.h **** for(;;) /* wait until reset */ + 340 .loc 2 993 3 view .LVU80 + 994:Drivers/CMSIS/Include/core_cm0plus.h **** { + 995:Drivers/CMSIS/Include/core_cm0plus.h **** __NOP(); + 341 .loc 2 995 5 view .LVU81 + 342 .syntax divided + 343 @ 995 "Drivers/CMSIS/Include/core_cm0plus.h" 1 + 344 000e C046 nop + 345 @ 0 "" 2 + 993:Drivers/CMSIS/Include/core_cm0plus.h **** { + 346 .loc 2 993 8 view .LVU82 + 347 .thumb + 348 .syntax unified + 349 0010 FDE7 b .L15 + 350 .L17: + 351 0012 C046 .align 2 + 352 .L16: + 353 0014 00ED00E0 .word -536810240 + 354 0018 0400FA05 .word 100270084 + 355 .LBE53: + 356 .LBE52: + 357 .cfi_endproc + 358 .LFE300: + 360 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 361 .align 1 + 362 .global HAL_SYSTICK_Config + 363 .syntax unified + 364 .code 16 + 365 .thumb_func + 366 .fpu softvfp + ARM GAS /tmp/cc5M7qsZ.s page 45 + + + 368 HAL_SYSTICK_Config: + 369 .LVL17: + 370 .LFB301: + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (Sys + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * - 1 Function failed. + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 371 .loc 1 189 1 view -0 + 372 .cfi_startproc + 373 @ args = 0, pretend = 0, frame = 0 + 374 @ frame_needed = 0, uses_anonymous_args = 0 + 375 @ link register save eliminated. + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 376 .loc 1 190 3 view .LVU84 + 377 .LBB62: + 378 .LBI62: + 996:Drivers/CMSIS/Include/core_cm0plus.h **** } + 997:Drivers/CMSIS/Include/core_cm0plus.h **** } + 998:Drivers/CMSIS/Include/core_cm0plus.h **** + 999:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_NVICFunctions */ +1000:Drivers/CMSIS/Include/core_cm0plus.h **** +1001:Drivers/CMSIS/Include/core_cm0plus.h **** /* ########################## MPU functions #################################### */ +1002:Drivers/CMSIS/Include/core_cm0plus.h **** +1003:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1004:Drivers/CMSIS/Include/core_cm0plus.h **** +1005:Drivers/CMSIS/Include/core_cm0plus.h **** #include "mpu_armv7.h" +1006:Drivers/CMSIS/Include/core_cm0plus.h **** +1007:Drivers/CMSIS/Include/core_cm0plus.h **** #endif +1008:Drivers/CMSIS/Include/core_cm0plus.h **** +1009:Drivers/CMSIS/Include/core_cm0plus.h **** /* ########################## FPU functions #################################### */ +1010:Drivers/CMSIS/Include/core_cm0plus.h **** /** +1011:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface +1012:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions +1013:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Function that provides FPU type. +1014:Drivers/CMSIS/Include/core_cm0plus.h **** @{ +1015:Drivers/CMSIS/Include/core_cm0plus.h **** */ +1016:Drivers/CMSIS/Include/core_cm0plus.h **** +1017:Drivers/CMSIS/Include/core_cm0plus.h **** /** +1018:Drivers/CMSIS/Include/core_cm0plus.h **** \brief get FPU type +1019:Drivers/CMSIS/Include/core_cm0plus.h **** \details returns the FPU type +1020:Drivers/CMSIS/Include/core_cm0plus.h **** \returns +1021:Drivers/CMSIS/Include/core_cm0plus.h **** - \b 0: No FPU +1022:Drivers/CMSIS/Include/core_cm0plus.h **** - \b 1: Single precision FPU +1023:Drivers/CMSIS/Include/core_cm0plus.h **** - \b 2: Double + Single precision FPU +1024:Drivers/CMSIS/Include/core_cm0plus.h **** */ +1025:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) +1026:Drivers/CMSIS/Include/core_cm0plus.h **** { +1027:Drivers/CMSIS/Include/core_cm0plus.h **** return 0U; /* No FPU */ +1028:Drivers/CMSIS/Include/core_cm0plus.h **** } +1029:Drivers/CMSIS/Include/core_cm0plus.h **** + ARM GAS /tmp/cc5M7qsZ.s page 46 + + +1030:Drivers/CMSIS/Include/core_cm0plus.h **** +1031:Drivers/CMSIS/Include/core_cm0plus.h **** /*@} end of CMSIS_Core_FpuFunctions */ +1032:Drivers/CMSIS/Include/core_cm0plus.h **** +1033:Drivers/CMSIS/Include/core_cm0plus.h **** +1034:Drivers/CMSIS/Include/core_cm0plus.h **** +1035:Drivers/CMSIS/Include/core_cm0plus.h **** /* ################################## SysTick function ######################################## +1036:Drivers/CMSIS/Include/core_cm0plus.h **** /** +1037:Drivers/CMSIS/Include/core_cm0plus.h **** \ingroup CMSIS_Core_FunctionInterface +1038:Drivers/CMSIS/Include/core_cm0plus.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +1039:Drivers/CMSIS/Include/core_cm0plus.h **** \brief Functions that configure the System. +1040:Drivers/CMSIS/Include/core_cm0plus.h **** @{ +1041:Drivers/CMSIS/Include/core_cm0plus.h **** */ +1042:Drivers/CMSIS/Include/core_cm0plus.h **** +1043:Drivers/CMSIS/Include/core_cm0plus.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +1044:Drivers/CMSIS/Include/core_cm0plus.h **** +1045:Drivers/CMSIS/Include/core_cm0plus.h **** /** +1046:Drivers/CMSIS/Include/core_cm0plus.h **** \brief System Tick Configuration +1047:Drivers/CMSIS/Include/core_cm0plus.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +1048:Drivers/CMSIS/Include/core_cm0plus.h **** Counter is in free running mode to generate periodic interrupts. +1049:Drivers/CMSIS/Include/core_cm0plus.h **** \param [in] ticks Number of ticks between two interrupts. +1050:Drivers/CMSIS/Include/core_cm0plus.h **** \return 0 Function succeeded. +1051:Drivers/CMSIS/Include/core_cm0plus.h **** \return 1 Function failed. +1052:Drivers/CMSIS/Include/core_cm0plus.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the +1053:Drivers/CMSIS/Include/core_cm0plus.h **** function SysTick_Config is not included. In this case, the file device. +1054:Drivers/CMSIS/Include/core_cm0plus.h **** must contain a vendor-specific implementation of this function. +1055:Drivers/CMSIS/Include/core_cm0plus.h **** */ +1056:Drivers/CMSIS/Include/core_cm0plus.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) + 379 .loc 2 1056 26 view .LVU85 + 380 .LBB63: +1057:Drivers/CMSIS/Include/core_cm0plus.h **** { +1058:Drivers/CMSIS/Include/core_cm0plus.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 381 .loc 2 1058 3 view .LVU86 + 382 .loc 2 1058 14 is_stmt 0 view .LVU87 + 383 0000 0138 subs r0, r0, #1 + 384 .LVL18: + 385 .loc 2 1058 6 view .LVU88 + 386 0002 8023 movs r3, #128 + 387 0004 5B04 lsls r3, r3, #17 + 388 0006 9842 cmp r0, r3 + 389 0008 0FD2 bcs .L20 +1059:Drivers/CMSIS/Include/core_cm0plus.h **** { +1060:Drivers/CMSIS/Include/core_cm0plus.h **** return (1UL); /* Reload value impossible */ +1061:Drivers/CMSIS/Include/core_cm0plus.h **** } +1062:Drivers/CMSIS/Include/core_cm0plus.h **** +1063:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 390 .loc 2 1063 3 is_stmt 1 view .LVU89 + 391 .loc 2 1063 18 is_stmt 0 view .LVU90 + 392 000a 094A ldr r2, .L21 + 393 000c 5060 str r0, [r2, #4] +1064:Drivers/CMSIS/Include/core_cm0plus.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 394 .loc 2 1064 3 is_stmt 1 view .LVU91 + 395 .LVL19: + 396 .LBB64: + 397 .LBI64: + 850:Drivers/CMSIS/Include/core_cm0plus.h **** { + 398 .loc 2 850 22 view .LVU92 + 399 .LBB65: + ARM GAS /tmp/cc5M7qsZ.s page 47 + + + 852:Drivers/CMSIS/Include/core_cm0plus.h **** { + 400 .loc 2 852 3 view .LVU93 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 401 .loc 2 859 5 view .LVU94 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 402 .loc 2 859 52 is_stmt 0 view .LVU95 + 403 000e 0948 ldr r0, .L21+4 + 404 .LVL20: + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 405 .loc 2 859 52 view .LVU96 + 406 0010 036A ldr r3, [r0, #32] + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 407 .loc 2 859 33 view .LVU97 + 408 0012 1B02 lsls r3, r3, #8 + 409 0014 1B0A lsrs r3, r3, #8 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 410 .loc 2 859 102 view .LVU98 + 411 0016 C021 movs r1, #192 + 412 0018 0906 lsls r1, r1, #24 + 413 001a 0B43 orrs r3, r1 + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 414 .loc 2 859 30 view .LVU99 + 415 001c 0362 str r3, [r0, #32] + 416 .LVL21: + 859:Drivers/CMSIS/Include/core_cm0plus.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 417 .loc 2 859 30 view .LVU100 + 418 .LBE65: + 419 .LBE64: +1065:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 420 .loc 2 1065 3 is_stmt 1 view .LVU101 + 421 .loc 2 1065 18 is_stmt 0 view .LVU102 + 422 001e 0023 movs r3, #0 + 423 0020 9360 str r3, [r2, #8] +1066:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 424 .loc 2 1066 3 is_stmt 1 view .LVU103 + 425 .loc 2 1066 18 is_stmt 0 view .LVU104 + 426 0022 0733 adds r3, r3, #7 + 427 0024 1360 str r3, [r2] +1067:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_TICKINT_Msk | +1068:Drivers/CMSIS/Include/core_cm0plus.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi +1069:Drivers/CMSIS/Include/core_cm0plus.h **** return (0UL); /* Function successful */ + 428 .loc 2 1069 3 is_stmt 1 view .LVU105 + 429 .loc 2 1069 10 is_stmt 0 view .LVU106 + 430 0026 0020 movs r0, #0 + 431 .LVL22: + 432 .L18: + 433 .loc 2 1069 10 view .LVU107 + 434 .LBE63: + 435 .LBE62: + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 436 .loc 1 191 1 view .LVU108 + 437 @ sp needed + 438 0028 7047 bx lr + 439 .LVL23: + 440 .L20: + 441 .LBB67: + 442 .LBB66: + ARM GAS /tmp/cc5M7qsZ.s page 48 + + +1060:Drivers/CMSIS/Include/core_cm0plus.h **** } + 443 .loc 2 1060 12 view .LVU109 + 444 002a 0120 movs r0, #1 + 445 .LVL24: +1060:Drivers/CMSIS/Include/core_cm0plus.h **** } + 446 .loc 2 1060 12 view .LVU110 + 447 .LBE66: + 448 .LBE67: + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 449 .loc 1 190 10 view .LVU111 + 450 002c FCE7 b .L18 + 451 .L22: + 452 002e C046 .align 2 + 453 .L21: + 454 0030 10E000E0 .word -536813552 + 455 0034 00ED00E0 .word -536810240 + 456 .cfi_endproc + 457 .LFE301: + 459 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 460 .align 1 + 461 .global HAL_NVIC_GetPriority + 462 .syntax unified + 463 .code 16 + 464 .thumb_func + 465 .fpu softvfp + 467 HAL_NVIC_GetPriority: + 468 .LVL25: + 469 .LFB302: + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @} + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** @addtogroup CORTEX_Exported_Functions_Group2 + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Cortex control functions + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @verbatim + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ============================================================================== + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** [..] + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** @endverbatim + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @{ + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Get the priority of an interrupt. + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number. + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + ARM GAS /tmp/cc5M7qsZ.s page 49 + + + 470 .loc 1 220 1 is_stmt 1 view -0 + 471 .cfi_startproc + 472 @ args = 0, pretend = 0, frame = 0 + 473 @ frame_needed = 0, uses_anonymous_args = 0 + 474 @ link register save eliminated. + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** return NVIC_GetPriority(IRQn); + 475 .loc 1 222 3 view .LVU113 + 476 .LBB70: + 477 .LBI70: + 874:Drivers/CMSIS/Include/core_cm0plus.h **** { + 478 .loc 2 874 26 view .LVU114 + 479 .LBB71: + 877:Drivers/CMSIS/Include/core_cm0plus.h **** { + 480 .loc 2 877 3 view .LVU115 + 877:Drivers/CMSIS/Include/core_cm0plus.h **** { + 481 .loc 2 877 6 is_stmt 0 view .LVU116 + 482 0000 0028 cmp r0, #0 + 483 0002 0CDB blt .L24 + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 484 .loc 2 879 5 is_stmt 1 view .LVU117 + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 485 .loc 2 879 35 is_stmt 0 view .LVU118 + 486 0004 8308 lsrs r3, r0, #2 + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 487 .loc 2 879 33 view .LVU119 + 488 0006 C033 adds r3, r3, #192 + 489 0008 9B00 lsls r3, r3, #2 + 490 000a 0E4A ldr r2, .L26 + 491 000c 9B58 ldr r3, [r3, r2] + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 492 .loc 2 879 53 view .LVU120 + 493 000e 0322 movs r2, #3 + 494 0010 1040 ands r0, r2 + 495 .LVL26: + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 496 .loc 2 879 53 view .LVU121 + 497 0012 C000 lsls r0, r0, #3 + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 498 .loc 2 879 50 view .LVU122 + 499 0014 C340 lsrs r3, r3, r0 + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 500 .loc 2 879 12 view .LVU123 + 501 0016 9B09 lsrs r3, r3, #6 + 502 0018 0320 movs r0, #3 + 503 001a 1840 ands r0, r3 + 504 .LVL27: + 505 .L23: + 879:Drivers/CMSIS/Include/core_cm0plus.h **** } + 506 .loc 2 879 12 view .LVU124 + 507 .LBE71: + 508 .LBE70: + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 509 .loc 1 223 1 view .LVU125 + 510 @ sp needed + 511 001c 7047 bx lr + 512 .LVL28: + ARM GAS /tmp/cc5M7qsZ.s page 50 + + + 513 .L24: + 514 .LBB73: + 515 .LBB72: + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 516 .loc 2 883 5 is_stmt 1 view .LVU126 + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 517 .loc 2 883 34 is_stmt 0 view .LVU127 + 518 001e 0F23 movs r3, #15 + 519 0020 0340 ands r3, r0 + 520 0022 083B subs r3, r3, #8 + 521 0024 9B08 lsrs r3, r3, #2 + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 522 .loc 2 883 33 view .LVU128 + 523 0026 0633 adds r3, r3, #6 + 524 0028 9B00 lsls r3, r3, #2 + 525 002a 074A ldr r2, .L26+4 + 526 002c 9446 mov ip, r2 + 527 002e 6344 add r3, r3, ip + 528 0030 5B68 ldr r3, [r3, #4] + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 529 .loc 2 883 53 view .LVU129 + 530 0032 0322 movs r2, #3 + 531 0034 1040 ands r0, r2 + 532 .LVL29: + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 533 .loc 2 883 53 view .LVU130 + 534 0036 C000 lsls r0, r0, #3 + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 535 .loc 2 883 50 view .LVU131 + 536 0038 C340 lsrs r3, r3, r0 + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 537 .loc 2 883 12 view .LVU132 + 538 003a 9B09 lsrs r3, r3, #6 + 539 003c 0320 movs r0, #3 + 540 003e 1840 ands r0, r3 + 541 .LVL30: + 883:Drivers/CMSIS/Include/core_cm0plus.h **** } + 542 .loc 2 883 12 view .LVU133 + 543 .LBE72: + 544 .LBE73: + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 545 .loc 1 222 10 view .LVU134 + 546 0040 ECE7 b .L23 + 547 .L27: + 548 0042 C046 .align 2 + 549 .L26: + 550 0044 00E100E0 .word -536813312 + 551 0048 00ED00E0 .word -536810240 + 552 .cfi_endproc + 553 .LFE302: + 555 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 556 .align 1 + 557 .global HAL_NVIC_SetPendingIRQ + 558 .syntax unified + 559 .code 16 + 560 .thumb_func + 561 .fpu softvfp + ARM GAS /tmp/cc5M7qsZ.s page 51 + + + 563 HAL_NVIC_SetPendingIRQ: + 564 .LVL31: + 565 .LFB303: + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Set Pending bit of an external interrupt. + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 566 .loc 1 233 1 is_stmt 1 view -0 + 567 .cfi_startproc + 568 @ args = 0, pretend = 0, frame = 0 + 569 @ frame_needed = 0, uses_anonymous_args = 0 + 570 @ link register save eliminated. + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 571 .loc 1 235 3 view .LVU136 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Set interrupt pending */ + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 572 .loc 1 238 3 view .LVU137 + 573 .LBB74: + 574 .LBI74: + 817:Drivers/CMSIS/Include/core_cm0plus.h **** { + 575 .loc 2 817 22 view .LVU138 + 576 .LBB75: + 819:Drivers/CMSIS/Include/core_cm0plus.h **** { + 577 .loc 2 819 3 view .LVU139 + 819:Drivers/CMSIS/Include/core_cm0plus.h **** { + 578 .loc 2 819 6 is_stmt 0 view .LVU140 + 579 0000 0028 cmp r0, #0 + 580 0002 07DB blt .L28 + 821:Drivers/CMSIS/Include/core_cm0plus.h **** } + 581 .loc 2 821 5 is_stmt 1 view .LVU141 + 821:Drivers/CMSIS/Include/core_cm0plus.h **** } + 582 .loc 2 821 58 is_stmt 0 view .LVU142 + 583 0004 1F23 movs r3, #31 + 584 0006 1840 ands r0, r3 + 585 .LVL32: + 821:Drivers/CMSIS/Include/core_cm0plus.h **** } + 586 .loc 2 821 22 view .LVU143 + 587 0008 1E3B subs r3, r3, #30 + 588 000a 8340 lsls r3, r3, r0 + 821:Drivers/CMSIS/Include/core_cm0plus.h **** } + 589 .loc 2 821 20 view .LVU144 + 590 000c 0249 ldr r1, .L30 + 591 000e 8022 movs r2, #128 + 592 0010 5200 lsls r2, r2, #1 + 593 0012 8B50 str r3, [r1, r2] + 594 .LVL33: + 595 .L28: + 821:Drivers/CMSIS/Include/core_cm0plus.h **** } + 596 .loc 2 821 20 view .LVU145 + ARM GAS /tmp/cc5M7qsZ.s page 52 + + + 597 .LBE75: + 598 .LBE74: + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 599 .loc 1 239 1 view .LVU146 + 600 @ sp needed + 601 0014 7047 bx lr + 602 .L31: + 603 0016 C046 .align 2 + 604 .L30: + 605 0018 00E100E0 .word -536813312 + 606 .cfi_endproc + 607 .LFE303: + 609 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 610 .align 1 + 611 .global HAL_NVIC_GetPendingIRQ + 612 .syntax unified + 613 .code 16 + 614 .thumb_func + 615 .fpu softvfp + 617 HAL_NVIC_GetPendingIRQ: + 618 .LVL34: + 619 .LFB304: + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Get Pending Interrupt (read the pending register in the NVIC + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * and return the pending bit for the specified interrupt). + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number. + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 620 .loc 1 251 1 is_stmt 1 view -0 + 621 .cfi_startproc + 622 @ args = 0, pretend = 0, frame = 0 + 623 @ frame_needed = 0, uses_anonymous_args = 0 + 624 @ link register save eliminated. + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 625 .loc 1 253 3 view .LVU148 + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Return 1 if pending else 0 */ + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 626 .loc 1 256 3 view .LVU149 + 627 .LBB76: + 628 .LBI76: + 798:Drivers/CMSIS/Include/core_cm0plus.h **** { + 629 .loc 2 798 26 view .LVU150 + 630 .LBB77: + 800:Drivers/CMSIS/Include/core_cm0plus.h **** { + 631 .loc 2 800 3 view .LVU151 + 800:Drivers/CMSIS/Include/core_cm0plus.h **** { + 632 .loc 2 800 6 is_stmt 0 view .LVU152 + 633 0000 0028 cmp r0, #0 + 634 0002 09DB blt .L34 + ARM GAS /tmp/cc5M7qsZ.s page 53 + + + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 635 .loc 2 802 5 is_stmt 1 view .LVU153 + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 636 .loc 2 802 35 is_stmt 0 view .LVU154 + 637 0004 054A ldr r2, .L35 + 638 0006 8023 movs r3, #128 + 639 0008 5B00 lsls r3, r3, #1 + 640 000a D358 ldr r3, [r2, r3] + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 641 .loc 2 802 68 view .LVU155 + 642 000c 1F22 movs r2, #31 + 643 000e 1040 ands r0, r2 + 644 .LVL35: + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 645 .loc 2 802 80 view .LVU156 + 646 0010 C340 lsrs r3, r3, r0 + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 647 .loc 2 802 12 view .LVU157 + 648 0012 0120 movs r0, #1 + 649 0014 1840 ands r0, r3 + 650 .LVL36: + 651 .L32: + 802:Drivers/CMSIS/Include/core_cm0plus.h **** } + 652 .loc 2 802 12 view .LVU158 + 653 .LBE77: + 654 .LBE76: + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 655 .loc 1 257 1 view .LVU159 + 656 @ sp needed + 657 0016 7047 bx lr + 658 .LVL37: + 659 .L34: + 660 .LBB79: + 661 .LBB78: + 806:Drivers/CMSIS/Include/core_cm0plus.h **** } + 662 .loc 2 806 11 view .LVU160 + 663 0018 0020 movs r0, #0 + 664 .LVL38: + 806:Drivers/CMSIS/Include/core_cm0plus.h **** } + 665 .loc 2 806 11 view .LVU161 + 666 .LBE78: + 667 .LBE79: + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 668 .loc 1 256 10 view .LVU162 + 669 001a FCE7 b .L32 + 670 .L36: + 671 .align 2 + 672 .L35: + 673 001c 00E100E0 .word -536813312 + 674 .cfi_endproc + 675 .LFE304: + 677 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 678 .align 1 + 679 .global HAL_NVIC_ClearPendingIRQ + 680 .syntax unified + 681 .code 16 + 682 .thumb_func + ARM GAS /tmp/cc5M7qsZ.s page 54 + + + 683 .fpu softvfp + 685 HAL_NVIC_ClearPendingIRQ: + 686 .LVL39: + 687 .LFB305: + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Clear the pending bit of an external interrupt. + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param IRQn External interrupt number. + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 688 .loc 1 267 1 is_stmt 1 view -0 + 689 .cfi_startproc + 690 @ args = 0, pretend = 0, frame = 0 + 691 @ frame_needed = 0, uses_anonymous_args = 0 + 692 @ link register save eliminated. + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 693 .loc 1 269 3 view .LVU164 + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Clear pending interrupt */ + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 694 .loc 1 272 3 view .LVU165 + 695 .LBB80: + 696 .LBI80: + 832:Drivers/CMSIS/Include/core_cm0plus.h **** { + 697 .loc 2 832 22 view .LVU166 + 698 .LBB81: + 834:Drivers/CMSIS/Include/core_cm0plus.h **** { + 699 .loc 2 834 3 view .LVU167 + 834:Drivers/CMSIS/Include/core_cm0plus.h **** { + 700 .loc 2 834 6 is_stmt 0 view .LVU168 + 701 0000 0028 cmp r0, #0 + 702 0002 07DB blt .L37 + 836:Drivers/CMSIS/Include/core_cm0plus.h **** } + 703 .loc 2 836 5 is_stmt 1 view .LVU169 + 836:Drivers/CMSIS/Include/core_cm0plus.h **** } + 704 .loc 2 836 58 is_stmt 0 view .LVU170 + 705 0004 1F23 movs r3, #31 + 706 0006 1840 ands r0, r3 + 707 .LVL40: + 836:Drivers/CMSIS/Include/core_cm0plus.h **** } + 708 .loc 2 836 22 view .LVU171 + 709 0008 1E3B subs r3, r3, #30 + 710 000a 8340 lsls r3, r3, r0 + 836:Drivers/CMSIS/Include/core_cm0plus.h **** } + 711 .loc 2 836 20 view .LVU172 + 712 000c 0249 ldr r1, .L39 + 713 000e C022 movs r2, #192 + 714 0010 5200 lsls r2, r2, #1 + 715 0012 8B50 str r3, [r1, r2] + 716 .LVL41: + 717 .L37: + 836:Drivers/CMSIS/Include/core_cm0plus.h **** } + ARM GAS /tmp/cc5M7qsZ.s page 55 + + + 718 .loc 2 836 20 view .LVU173 + 719 .LBE81: + 720 .LBE80: + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 721 .loc 1 273 1 view .LVU174 + 722 @ sp needed + 723 0014 7047 bx lr + 724 .L40: + 725 0016 C046 .align 2 + 726 .L39: + 727 0018 00E100E0 .word -536813312 + 728 .cfi_endproc + 729 .LFE305: + 731 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 732 .align 1 + 733 .global HAL_SYSTICK_CLKSourceConfig + 734 .syntax unified + 735 .code 16 + 736 .thumb_func + 737 .fpu softvfp + 739 HAL_SYSTICK_CLKSourceConfig: + 740 .LVL42: + 741 .LFB306: + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Configure the SysTick clock source. + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be one of the following values: + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 742 .loc 1 284 1 is_stmt 1 view -0 + 743 .cfi_startproc + 744 @ args = 0, pretend = 0, frame = 0 + 745 @ frame_needed = 0, uses_anonymous_args = 0 + 746 @ link register save eliminated. + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 747 .loc 1 286 3 view .LVU176 + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 748 .loc 1 287 3 view .LVU177 + 749 .loc 1 287 6 is_stmt 0 view .LVU178 + 750 0000 0428 cmp r0, #4 + 751 0002 05D0 beq .L44 + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** else + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 752 .loc 1 293 5 is_stmt 1 view .LVU179 + 753 .loc 1 293 19 is_stmt 0 view .LVU180 + 754 0004 054A ldr r2, .L45 + 755 0006 1368 ldr r3, [r2] + ARM GAS /tmp/cc5M7qsZ.s page 56 + + + 756 0008 0421 movs r1, #4 + 757 000a 8B43 bics r3, r1 + 758 000c 1360 str r3, [r2] + 759 .L41: + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 760 .loc 1 295 1 view .LVU181 + 761 @ sp needed + 762 000e 7047 bx lr + 763 .L44: + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 764 .loc 1 289 5 is_stmt 1 view .LVU182 + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 765 .loc 1 289 19 is_stmt 0 view .LVU183 + 766 0010 024A ldr r2, .L45 + 767 0012 1368 ldr r3, [r2] + 768 0014 0421 movs r1, #4 + 769 0016 0B43 orrs r3, r1 + 770 0018 1360 str r3, [r2] + 771 001a F8E7 b .L41 + 772 .L46: + 773 .align 2 + 774 .L45: + 775 001c 10E000E0 .word -536813552 + 776 .cfi_endproc + 777 .LFE306: + 779 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 780 .align 1 + 781 .weak HAL_SYSTICK_Callback + 782 .syntax unified + 783 .code 16 + 784 .thumb_func + 785 .fpu softvfp + 787 HAL_SYSTICK_Callback: + 788 .LFB308: + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Handle SYSTICK interrupt request. + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief SYSTICK callback. + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 789 .loc 1 311 1 is_stmt 1 view -0 + 790 .cfi_startproc + 791 @ args = 0, pretend = 0, frame = 0 + 792 @ frame_needed = 0, uses_anonymous_args = 0 + 793 @ link register save eliminated. + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* NOTE : This function should not be modified, when the callback is needed, + ARM GAS /tmp/cc5M7qsZ.s page 57 + + + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 794 .loc 1 315 1 view .LVU185 + 795 @ sp needed + 796 0000 7047 bx lr + 797 .cfi_endproc + 798 .LFE308: + 800 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 801 .align 1 + 802 .global HAL_SYSTICK_IRQHandler + 803 .syntax unified + 804 .code 16 + 805 .thumb_func + 806 .fpu softvfp + 808 HAL_SYSTICK_IRQHandler: + 809 .LFB307: + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 810 .loc 1 302 1 view -0 + 811 .cfi_startproc + 812 @ args = 0, pretend = 0, frame = 0 + 813 @ frame_needed = 0, uses_anonymous_args = 0 + 814 0000 10B5 push {r4, lr} + 815 .LCFI1: + 816 .cfi_def_cfa_offset 8 + 817 .cfi_offset 4, -8 + 818 .cfi_offset 14, -4 + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 819 .loc 1 303 3 view .LVU187 + 820 0002 FFF7FEFF bl HAL_SYSTICK_Callback + 821 .LVL43: + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 822 .loc 1 304 1 is_stmt 0 view .LVU188 + 823 @ sp needed + 824 0006 10BD pop {r4, pc} + 825 .cfi_endproc + 826 .LFE307: + 828 .section .text.HAL_MPU_Enable,"ax",%progbits + 829 .align 1 + 830 .global HAL_MPU_Enable + 831 .syntax unified + 832 .code 16 + 833 .thumb_func + 834 .fpu softvfp + 836 HAL_MPU_Enable: + 837 .LVL44: + 838 .LFB309: + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U) + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Enable the MPU. + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * This parameter can be one of the following values: + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT + ARM GAS /tmp/cc5M7qsZ.s page 58 + + + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 839 .loc 1 330 1 is_stmt 1 view -0 + 840 .cfi_startproc + 841 @ args = 0, pretend = 0, frame = 0 + 842 @ frame_needed = 0, uses_anonymous_args = 0 + 843 @ link register save eliminated. + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Enable the MPU */ + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + 844 .loc 1 332 3 view .LVU190 + 845 .loc 1 332 28 is_stmt 0 view .LVU191 + 846 0000 0123 movs r3, #1 + 847 0002 1843 orrs r0, r3 + 848 .LVL45: + 849 .loc 1 332 13 view .LVU192 + 850 0004 034B ldr r3, .L50 + 851 0006 5860 str r0, [r3, #4] + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Ensure MPU setting take effects */ + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __DSB(); + 852 .loc 1 335 3 is_stmt 1 view .LVU193 + 853 .LBB82: + 854 .LBI82: + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 855 .loc 3 944 27 view .LVU194 + 856 .LBB83: + 857 .loc 3 946 3 view .LVU195 + 858 .syntax divided + 859 @ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 860 0008 BFF34F8F dsb 0xF + 861 @ 0 "" 2 + 862 .thumb + 863 .syntax unified + 864 .LBE83: + 865 .LBE82: + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __ISB(); + 866 .loc 1 336 3 view .LVU196 + 867 .LBB84: + 868 .LBI84: + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 869 .loc 3 933 27 view .LVU197 + 870 .LBB85: + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 871 .loc 3 935 3 view .LVU198 + 872 .syntax divided + 873 @ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 874 000c BFF36F8F isb 0xF + 875 @ 0 "" 2 + 876 .thumb + 877 .syntax unified + 878 .LBE85: + 879 .LBE84: + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 880 .loc 1 337 1 is_stmt 0 view .LVU199 + ARM GAS /tmp/cc5M7qsZ.s page 59 + + + 881 @ sp needed + 882 0010 7047 bx lr + 883 .L51: + 884 0012 C046 .align 2 + 885 .L50: + 886 0014 90ED00E0 .word -536810096 + 887 .cfi_endproc + 888 .LFE309: + 890 .section .text.HAL_MPU_Disable,"ax",%progbits + 891 .align 1 + 892 .global HAL_MPU_Disable + 893 .syntax unified + 894 .code 16 + 895 .thumb_func + 896 .fpu softvfp + 898 HAL_MPU_Disable: + 899 .LFB310: + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Disable the MPU. + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_Disable(void) + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 900 .loc 1 345 1 is_stmt 1 view -0 + 901 .cfi_startproc + 902 @ args = 0, pretend = 0, frame = 0 + 903 @ frame_needed = 0, uses_anonymous_args = 0 + 904 @ link register save eliminated. + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Make sure outstanding transfers are done */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** __DMB(); + 905 .loc 1 347 3 view .LVU201 + 906 .LBB86: + 907 .LBI86: + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 908 .loc 3 955 27 view .LVU202 + 909 .LBB87: + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 910 .loc 3 957 3 view .LVU203 + 911 .syntax divided + 912 @ 957 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 913 0000 BFF35F8F dmb 0xF + 914 @ 0 "" 2 + 915 .thumb + 916 .syntax unified + 917 .LBE87: + 918 .LBE86: + ARM GAS /tmp/cc5M7qsZ.s page 60 + + + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Disable the MPU and clear the control register*/ + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->CTRL = 0; + 919 .loc 1 350 3 view .LVU204 + 920 .loc 1 350 14 is_stmt 0 view .LVU205 + 921 0004 014B ldr r3, .L53 + 922 0006 0022 movs r2, #0 + 923 0008 5A60 str r2, [r3, #4] + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 924 .loc 1 351 1 view .LVU206 + 925 @ sp needed + 926 000a 7047 bx lr + 927 .L54: + 928 .align 2 + 929 .L53: + 930 000c 90ED00E0 .word -536810096 + 931 .cfi_endproc + 932 .LFE310: + 934 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 935 .align 1 + 936 .global HAL_MPU_ConfigRegion + 937 .syntax unified + 938 .code 16 + 939 .thumb_func + 940 .fpu softvfp + 942 HAL_MPU_ConfigRegion: + 943 .LVL46: + 944 .LFB311: + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /** + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @brief Initialize and configure the Region and the memory to be protected. + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * the initialization and configuration information. + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** * @retval None + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** */ + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 945 .loc 1 361 1 is_stmt 1 view -0 + 946 .cfi_startproc + 947 @ args = 0, pretend = 0, frame = 0 + 948 @ frame_needed = 0, uses_anonymous_args = 0 + 949 @ link register save eliminated. + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 950 .loc 1 363 3 view .LVU208 + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 951 .loc 1 364 3 view .LVU209 + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Set the Region number */ + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 952 .loc 1 367 3 view .LVU210 + 953 .loc 1 367 22 is_stmt 0 view .LVU211 + 954 0000 4278 ldrb r2, [r0, #1] + 955 .loc 1 367 12 view .LVU212 + 956 0002 144B ldr r3, .L58 + 957 0004 9A60 str r2, [r3, #8] + ARM GAS /tmp/cc5M7qsZ.s page 61 + + + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** if ((MPU_Init->Enable) != 0U) + 958 .loc 1 369 3 is_stmt 1 view .LVU213 + 959 .loc 1 369 16 is_stmt 0 view .LVU214 + 960 0006 0378 ldrb r3, [r0] + 961 .loc 1 369 6 view .LVU215 + 962 0008 002B cmp r3, #0 + 963 000a 1DD0 beq .L56 + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** /* Check the parameters */ + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 964 .loc 1 372 5 is_stmt 1 view .LVU216 + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 965 .loc 1 373 5 view .LVU217 + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + 966 .loc 1 374 5 view .LVU218 + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 967 .loc 1 375 5 view .LVU219 + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + 968 .loc 1 376 5 view .LVU220 + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 969 .loc 1 377 5 view .LVU221 + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 970 .loc 1 378 5 view .LVU222 + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 971 .loc 1 379 5 view .LVU223 + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; + 972 .loc 1 381 5 view .LVU224 + 973 .loc 1 381 15 is_stmt 0 view .LVU225 + 974 000c 1149 ldr r1, .L58 + 975 000e 4368 ldr r3, [r0, #4] + 976 0010 CB60 str r3, [r1, #12] + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 977 .loc 1 382 5 is_stmt 1 view .LVU226 + 978 .loc 1 382 36 is_stmt 0 view .LVU227 + 979 0012 037B ldrb r3, [r0, #12] + 980 .loc 1 382 62 view .LVU228 + 981 0014 1B07 lsls r3, r3, #28 + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 982 .loc 1 383 36 view .LVU229 + 983 0016 C27A ldrb r2, [r0, #11] + 984 .loc 1 383 62 view .LVU230 + 985 0018 1206 lsls r2, r2, #24 + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 986 .loc 1 382 84 view .LVU231 + 987 001a 1343 orrs r3, r2 + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 988 .loc 1 384 36 view .LVU232 + 989 001c 827A ldrb r2, [r0, #10] + 990 .loc 1 384 62 view .LVU233 + 991 001e D204 lsls r2, r2, #19 + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 992 .loc 1 383 84 view .LVU234 + 993 0020 1343 orrs r3, r2 + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 994 .loc 1 385 36 view .LVU235 + ARM GAS /tmp/cc5M7qsZ.s page 62 + + + 995 0022 427B ldrb r2, [r0, #13] + 996 .loc 1 385 62 view .LVU236 + 997 0024 9204 lsls r2, r2, #18 + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 998 .loc 1 384 84 view .LVU237 + 999 0026 1343 orrs r3, r2 + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 1000 .loc 1 386 36 view .LVU238 + 1001 0028 827B ldrb r2, [r0, #14] + 1002 .loc 1 386 62 view .LVU239 + 1003 002a 5204 lsls r2, r2, #17 + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 1004 .loc 1 385 84 view .LVU240 + 1005 002c 1343 orrs r3, r2 + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 1006 .loc 1 387 36 view .LVU241 + 1007 002e C27B ldrb r2, [r0, #15] + 1008 .loc 1 387 62 view .LVU242 + 1009 0030 1204 lsls r2, r2, #16 + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 1010 .loc 1 386 84 view .LVU243 + 1011 0032 1343 orrs r3, r2 + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 1012 .loc 1 388 36 view .LVU244 + 1013 0034 427A ldrb r2, [r0, #9] + 1014 .loc 1 388 62 view .LVU245 + 1015 0036 1202 lsls r2, r2, #8 + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 1016 .loc 1 387 84 view .LVU246 + 1017 0038 1343 orrs r3, r2 + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 1018 .loc 1 389 36 view .LVU247 + 1019 003a 027A ldrb r2, [r0, #8] + 1020 .loc 1 389 62 view .LVU248 + 1021 003c 5200 lsls r2, r2, #1 + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 1022 .loc 1 388 84 view .LVU249 + 1023 003e 1343 orrs r3, r2 + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 1024 .loc 1 390 36 view .LVU250 + 1025 0040 0278 ldrb r2, [r0] + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 1026 .loc 1 389 84 view .LVU251 + 1027 0042 1343 orrs r3, r2 + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 1028 .loc 1 382 15 view .LVU252 + 1029 0044 0B61 str r3, [r1, #16] + 1030 .L55: + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** else + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** { + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RBAR = 0x00U; + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RASR = 0x00U; + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 1031 .loc 1 397 1 view .LVU253 + 1032 @ sp needed + ARM GAS /tmp/cc5M7qsZ.s page 63 + + + 1033 0046 7047 bx lr + 1034 .L56: + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RASR = 0x00U; + 1035 .loc 1 394 5 is_stmt 1 view .LVU254 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** MPU->RASR = 0x00U; + 1036 .loc 1 394 15 is_stmt 0 view .LVU255 + 1037 0048 024B ldr r3, .L58 + 1038 004a 0022 movs r2, #0 + 1039 004c DA60 str r2, [r3, #12] + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 1040 .loc 1 395 5 is_stmt 1 view .LVU256 + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c **** } + 1041 .loc 1 395 15 is_stmt 0 view .LVU257 + 1042 004e 1A61 str r2, [r3, #16] + 1043 .loc 1 397 1 view .LVU258 + 1044 0050 F9E7 b .L55 + 1045 .L59: + 1046 0052 C046 .align 2 + 1047 .L58: + 1048 0054 90ED00E0 .word -536810096 + 1049 .cfi_endproc + 1050 .LFE311: + 1052 .text + 1053 .Letext0: + 1054 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1055 .file 5 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1056 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h" + 1057 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/cc5M7qsZ.s page 64 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_cortex.c + /tmp/cc5M7qsZ.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t + /tmp/cc5M7qsZ.s:24 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority + /tmp/cc5M7qsZ.s:144 .text.HAL_NVIC_SetPriority:0000000000000058 $d + /tmp/cc5M7qsZ.s:150 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t + /tmp/cc5M7qsZ.s:157 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ + /tmp/cc5M7qsZ.s:199 .text.HAL_NVIC_EnableIRQ:0000000000000014 $d + /tmp/cc5M7qsZ.s:204 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t + /tmp/cc5M7qsZ.s:211 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ + /tmp/cc5M7qsZ.s:281 .text.HAL_NVIC_DisableIRQ:000000000000001c $d + /tmp/cc5M7qsZ.s:286 .text.HAL_NVIC_SystemReset:0000000000000000 $t + /tmp/cc5M7qsZ.s:293 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset + /tmp/cc5M7qsZ.s:353 .text.HAL_NVIC_SystemReset:0000000000000014 $d + /tmp/cc5M7qsZ.s:361 .text.HAL_SYSTICK_Config:0000000000000000 $t + /tmp/cc5M7qsZ.s:368 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config + /tmp/cc5M7qsZ.s:454 .text.HAL_SYSTICK_Config:0000000000000030 $d + /tmp/cc5M7qsZ.s:460 .text.HAL_NVIC_GetPriority:0000000000000000 $t + /tmp/cc5M7qsZ.s:467 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority + /tmp/cc5M7qsZ.s:550 .text.HAL_NVIC_GetPriority:0000000000000044 $d + /tmp/cc5M7qsZ.s:556 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t + /tmp/cc5M7qsZ.s:563 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ + /tmp/cc5M7qsZ.s:605 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d + /tmp/cc5M7qsZ.s:610 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t + /tmp/cc5M7qsZ.s:617 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ + /tmp/cc5M7qsZ.s:673 .text.HAL_NVIC_GetPendingIRQ:000000000000001c $d + /tmp/cc5M7qsZ.s:678 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t + /tmp/cc5M7qsZ.s:685 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ + /tmp/cc5M7qsZ.s:727 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d + /tmp/cc5M7qsZ.s:732 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t + /tmp/cc5M7qsZ.s:739 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig + /tmp/cc5M7qsZ.s:775 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d + /tmp/cc5M7qsZ.s:780 .text.HAL_SYSTICK_Callback:0000000000000000 $t + /tmp/cc5M7qsZ.s:787 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback + /tmp/cc5M7qsZ.s:801 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t + /tmp/cc5M7qsZ.s:808 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler + /tmp/cc5M7qsZ.s:829 .text.HAL_MPU_Enable:0000000000000000 $t + /tmp/cc5M7qsZ.s:836 .text.HAL_MPU_Enable:0000000000000000 HAL_MPU_Enable + /tmp/cc5M7qsZ.s:886 .text.HAL_MPU_Enable:0000000000000014 $d + /tmp/cc5M7qsZ.s:891 .text.HAL_MPU_Disable:0000000000000000 $t + /tmp/cc5M7qsZ.s:898 .text.HAL_MPU_Disable:0000000000000000 HAL_MPU_Disable + /tmp/cc5M7qsZ.s:930 .text.HAL_MPU_Disable:000000000000000c $d + /tmp/cc5M7qsZ.s:935 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© Copyright (c) 2018 STMicroelectronics. + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * All rights reserved.
+ 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * This software component is licensed by ST under BSD 3-Clause license, + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the "License"; You may not use this file except in compliance with the + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * License. You may obtain a copy of the License at: + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * opensource.org/licenses/BSD-3-Clause + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** ****************************************************************************** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/ + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #include "stm32g0xx_hal.h" + ARM GAS /tmp/ccdBjPSF.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @addtogroup STM32G0xx_HAL_Driver + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA DMA + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief DMA HAL module driver + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Private typedef -----------------------------------------------------------*/ + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Private define ------------------------------------------------------------*/ + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Private macro -------------------------------------------------------------*/ + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/ + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA_Private_Functions DMA Private Functions + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @} + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/ + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions DMA Exported Functions + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Initialization and de-initialization functions + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @verbatim + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** ##### Initialization and de-initialization functions ##### + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** [..] + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** This section provides functions allowing to initialize the DMA Channel source + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** and destination addresses, incrementation and data sizes, transfer direction, + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** [..] + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** The HAL_DMA_Init() function follows the DMA configuration procedures as described in + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** reference manual. + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @endverbatim + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Initialize the DMA according to the specified + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * parameters in the DMA_InitTypeDef and initialize the associated handle. + ARM GAS /tmp/ccdBjPSF.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma == NULL) + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the parameters */ + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Compute the channel index */ + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA1 */ + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA2 */ + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chan + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change DMA peripheral state */ + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Set the DMA Channel configuration */ + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | \ + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority)); + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize parameters for DMAMUX channel : + ARM GAS /tmp/ccdBjPSF.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* if memory to memory force the request to 0*/ + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Init.Request = DMA_REQUEST_MEM2MEM; + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Set peripheral request to DMAMUX channel */ + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize parameters for DMAMUX request generator : + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Reset the DMAMUX request generator register*/ + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR = 0U; + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen = 0U; + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the error code */ + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the DMA state*/ + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Release Lock */ + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_OK; + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief DeInitialize the DMA peripheral. + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + ARM GAS /tmp/ccdBjPSF.s page 6 + + + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (NULL == hdma) + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the parameters */ + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the selected DMA Channelx */ + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Compute the channel index */ + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA1 */ + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA2 */ + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chan + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Reset DMA Channel control register */ + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CCR = 0U; + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize parameters for DMAMUX channel : + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Reset the DMAMUX channel that corresponds to the DMA channel */ + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel->CCR = 0U; + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Reset Request generator parameters if any */ + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize parameters for DMAMUX request generator : + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + ARM GAS /tmp/ccdBjPSF.s page 7 + + + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Reset the DMAMUX request generator register*/ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR = 0U; + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen = 0U; + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clean callbacks */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the error code */ + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the DMA state */ + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Release Lock */ + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_OK; + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @} + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Input and Output operation functions + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @verbatim + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** ##### IO operation functions ##### + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** [..] This section provides functions allowing to: + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** Start DMA transfer with interrupt + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Abort DMA transfer + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Poll for transfer complete + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Handle DMA interrupt request + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Register and Unregister DMA callbacks + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @endverbatim + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Start the DMA Transfer. + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + ARM GAS /tmp/ccdBjPSF.s page 8 + + + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the parameters */ + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process locked */ + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_LOCK(hdma); + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State == HAL_DMA_STATE_READY) + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change DMA peripheral state */ + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the error code */ + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the peripheral */ + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure the source, destination address and the data length & clear flags*/ + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable the Peripheral */ + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the error code */ + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return error status */ + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return status; + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + ARM GAS /tmp/ccdBjPSF.s page 9 + + + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the parameters */ + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process locked */ + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_LOCK(hdma); + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State == HAL_DMA_STATE_READY) + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change DMA peripheral state */ + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the peripheral */ + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure the source, destination address and the data length & clear flags*/ + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable the transfer complete interrupt */ + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable the transfer Error interrupt */ + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (NULL != hdma->XferHalfCpltCallback) + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable the Half transfer complete interrupt as well */ + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check if DMAMUX Synchronization is enabled*/ + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable DMAMUX sync overrun IT*/ + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->DMAmuxRequestGen != 0U) + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* enable the request gen overrun IT*/ + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Enable the Peripheral */ + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_ENABLE(hdma); + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the error code */ + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 10 + + + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return error status */ + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return status; + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Abort the DMA Transfer. + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (NULL == hdma) + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA peripheral state */ + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State != HAL_DMA_STATE_BUSY) + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable DMA IT */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* disable the DMAMUX sync overrun IT*/ + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the channel */ + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->DMAmuxRequestGen != 0U) + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + ARM GAS /tmp/ccdBjPSF.s page 11 + + + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* disable the request gen overrun IT*/ + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_OK; + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Aborts the DMA Transfer in Interrupt mode. + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State != HAL_DMA_STATE_BUSY) + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* no transfer ongoing */ + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable DMA IT */ + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the channel */ + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE(hdma); + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* disable the DMAMUX sync overrun IT*/ + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->DMAmuxRequestGen != 0U) + ARM GAS /tmp/ccdBjPSF.s page 12 + + + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* disable the request gen overrun IT*/ + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Call User Abort callback */ + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->XferAbortCallback != NULL) + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return status; + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Polling for transfer complete. + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param CompleteLevel Specifies the DMA level complete. + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param Timeout Timeout duration. + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t temp; + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t tickstart; + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State != HAL_DMA_STATE_BUSY) + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* no transfer ongoing */ + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Polling mode not supported in circular mode */ + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Get the level transfer complete flag */ + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Transfer Complete flag */ + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); + ARM GAS /tmp/ccdBjPSF.s page 13 + + + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Half Transfer Complete flag */ + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Get tick */ + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** tickstart = HAL_GetTick(); + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** while ((hdma->DmaBaseAddress->ISR & temp) == 0U) + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** while (0U == __HAL_DMA_GET_FLAG(hdma, temp)) + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU)))) + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check for the Timeout */ + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (Timeout != HAL_MAX_DELAY) + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + ARM GAS /tmp/ccdBjPSF.s page 14 + + + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /*Check for DMAMUX Request generator (if used) overrun status */ + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->DMAmuxRequestGen != 0U) + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the request gen overrun interrupt */ + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check for DMAMUX Synchronization overrun */ + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the transfer complete flag */ + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)); + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process unlocked */ + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* The selected Channelx EN bit is cleared (DMA is disabled and + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** all transfers are complete) */ + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + ARM GAS /tmp/ccdBjPSF.s page 15 + + + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_OK; + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Handle DMA interrupt request. + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval None + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t flag_it = DMA1->ISR; + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the half transfer interrupt */ + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA peripheral state is not updated in Half Transfer */ + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* but in Transfer Complete case */ + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->XferHalfCpltCallback != NULL) + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Half transfer callback */ + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it + ARM GAS /tmp/ccdBjPSF.s page 16 + + + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable the transfer complete and error interrupt */ + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the transfer complete flag */ + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->XferCpltCallback != NULL) + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Transfer complete callback */ + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Transfer Error Interrupt management **************************************/ + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_ + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Disable ALL DMA IT */ + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Update error code */ + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Change the DMA state */ + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process Unlocked */ + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->XferErrorCallback != NULL) + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Transfer error callback */ + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback(hdma); + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Nothing To Do */ + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return; + ARM GAS /tmp/ccdBjPSF.s page 17 + + + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Register callbacks + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param CallbackID User Callback identifier + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param pCallback Pointer to private callbacsk function which has pointer to + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process locked */ + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_LOCK(hdma); + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State == HAL_DMA_STATE_READY) + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** switch (CallbackID) + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferCpltCallback = pCallback; + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = pCallback; + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = pCallback; + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = pCallback; + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** default: + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Release Lock */ + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return status; + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief UnRegister callbacks + ARM GAS /tmp/ccdBjPSF.s page 18 + + + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param CallbackID User Callback identifier + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Process locked */ + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_LOCK(hdma); + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->State == HAL_DMA_STATE_READY) + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** switch (CallbackID) + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** case HAL_DMA_XFER_ALL_CB_ID: + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** default: + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** status = HAL_ERROR; + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Release Lock */ + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return status; + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** + ARM GAS /tmp/ccdBjPSF.s page 19 + + +1002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @} +1003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions +1008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Peripheral State and Errors functions +1009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * +1010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @verbatim +1011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== +1012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** ##### Peripheral State and Errors functions ##### +1013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** =============================================================================== +1014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** [..] +1015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** This subsection provides functions allowing to +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Check the DMA state +1017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** (+) Get error code +1018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** @endverbatim +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ +1021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Return the DMA handle state. +1025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains +1026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. +1027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL state +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return DMA handle state */ +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return hdma->State; +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Return the DMA error code. +1037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains +1038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. +1039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval DMA Error Code +1040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return the DMA error code */ +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return hdma->ErrorCode; +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @} +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @} +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions +1056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @{ +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 20 + + +1059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Sets the DMA Transfer parameter. +1061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains +1062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. +1063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address +1064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address +1065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination +1066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval HAL status +1067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 +1069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 27 .loc 1 1069 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 .loc 1 1069 1 is_stmt 0 view .LVU1 + 32 0000 F0B5 push {r4, r5, r6, r7, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 20 + 35 .cfi_offset 4, -20 + 36 .cfi_offset 5, -16 + 37 .cfi_offset 6, -12 + 38 .cfi_offset 7, -8 + 39 .cfi_offset 14, -4 +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX synchro overrun flag */ +1071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 40 .loc 1 1071 3 is_stmt 1 view .LVU2 + 41 .loc 1 1071 7 is_stmt 0 view .LVU3 + 42 0002 846C ldr r4, [r0, #72] + 43 .loc 1 1071 34 view .LVU4 + 44 0004 C56C ldr r5, [r0, #76] + 45 0006 6560 str r5, [r4, #4] +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if (hdma->DMAmuxRequestGen != 0U) + 46 .loc 1 1073 3 is_stmt 1 view .LVU5 + 47 .loc 1 1073 6 is_stmt 0 view .LVU6 + 48 0008 046D ldr r4, [r0, #80] + 49 000a 002C cmp r4, #0 + 50 000c 02D0 beq .L2 +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear the DMAMUX request generator overrun flag */ +1076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 51 .loc 1 1076 5 is_stmt 1 view .LVU7 + 52 .loc 1 1076 9 is_stmt 0 view .LVU8 + 53 000e 446D ldr r4, [r0, #84] + 54 .loc 1 1076 41 view .LVU9 + 55 0010 856D ldr r5, [r0, #88] + 56 0012 6560 str r5, [r4, #4] + 57 .L2: +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Clear all flags */ +1080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +1082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); + 58 .loc 1 1083 3 is_stmt 1 view .LVU10 + ARM GAS /tmp/ccdBjPSF.s page 21 + + + 59 0014 0B4F ldr r7, .L6 + 60 0016 7C68 ldr r4, [r7, #4] + 61 0018 1C26 movs r6, #28 + 62 001a 056C ldr r5, [r0, #64] + 63 001c 2E40 ands r6, r5 + 64 001e 0125 movs r5, #1 + 65 0020 B540 lsls r5, r5, r6 + 66 0022 2C43 orrs r4, r5 + 67 0024 7C60 str r4, [r7, #4] +1084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ +1085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure DMA Channel data length */ +1087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CNDTR = DataLength; + 68 .loc 1 1087 3 view .LVU11 + 69 .loc 1 1087 7 is_stmt 0 view .LVU12 + 70 0026 0468 ldr r4, [r0] + 71 .loc 1 1087 25 view .LVU13 + 72 0028 6360 str r3, [r4, #4] +1088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Memory to Peripheral */ +1090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 73 .loc 1 1090 3 is_stmt 1 view .LVU14 + 74 .loc 1 1090 6 is_stmt 0 view .LVU15 + 75 002a 8368 ldr r3, [r0, #8] + 76 .LVL1: + 77 .loc 1 1090 6 view .LVU16 + 78 002c 102B cmp r3, #16 + 79 002e 04D0 beq .L5 +1091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure DMA Channel destination address */ +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CPAR = DstAddress; +1094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure DMA Channel source address */ +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CMAR = SrcAddress; +1097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Peripheral to Memory */ +1099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else +1100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure DMA Channel source address */ +1102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CPAR = SrcAddress; + 80 .loc 1 1102 5 is_stmt 1 view .LVU17 + 81 .loc 1 1102 9 is_stmt 0 view .LVU18 + 82 0030 0368 ldr r3, [r0] + 83 .loc 1 1102 26 view .LVU19 + 84 0032 9960 str r1, [r3, #8] + 85 .LVL2: +1103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Configure DMA Channel destination address */ +1105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Instance->CMAR = DstAddress; + 86 .loc 1 1105 5 is_stmt 1 view .LVU20 + 87 .loc 1 1105 9 is_stmt 0 view .LVU21 + 88 0034 0368 ldr r3, [r0] + 89 .loc 1 1105 26 view .LVU22 + 90 0036 DA60 str r2, [r3, #12] + 91 .L1: +1106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + ARM GAS /tmp/ccdBjPSF.s page 22 + + + 92 .loc 1 1107 1 view .LVU23 + 93 @ sp needed + 94 0038 F0BD pop {r4, r5, r6, r7, pc} + 95 .LVL3: + 96 .L5: +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 97 .loc 1 1093 5 is_stmt 1 view .LVU24 +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 98 .loc 1 1093 9 is_stmt 0 view .LVU25 + 99 003a 0368 ldr r3, [r0] +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 100 .loc 1 1093 26 view .LVU26 + 101 003c 9A60 str r2, [r3, #8] + 102 .LVL4: +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 103 .loc 1 1096 5 is_stmt 1 view .LVU27 +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 104 .loc 1 1096 9 is_stmt 0 view .LVU28 + 105 003e 0368 ldr r3, [r0] +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 106 .loc 1 1096 26 view .LVU29 + 107 0040 D960 str r1, [r3, #12] + 108 0042 F9E7 b .L1 + 109 .L7: + 110 .align 2 + 111 .L6: + 112 0044 00000240 .word 1073872896 + 113 .cfi_endproc + 114 .LFE309: + 116 .global __aeabi_uidiv + 117 .section .text.DMA_CalcDMAMUXChannelBaseAndMask,"ax",%progbits + 118 .align 1 + 119 .syntax unified + 120 .code 16 + 121 .thumb_func + 122 .fpu softvfp + 124 DMA_CalcDMAMUXChannelBaseAndMask: + 125 .LVL5: + 126 .LFB310: +1108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel num +1111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains +1112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. +1113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval None +1114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +1116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 127 .loc 1 1116 1 is_stmt 1 view -0 + 128 .cfi_startproc + 129 @ args = 0, pretend = 0, frame = 0 + 130 @ frame_needed = 0, uses_anonymous_args = 0 + 131 .loc 1 1116 1 is_stmt 0 view .LVU31 + 132 0000 10B5 push {r4, lr} + 133 .LCFI1: + 134 .cfi_def_cfa_offset 8 + 135 .cfi_offset 4, -8 + ARM GAS /tmp/ccdBjPSF.s page 23 + + + 136 .cfi_offset 14, -4 + 137 0002 0400 movs r4, r0 +1117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t channel_number; + 138 .loc 1 1117 3 is_stmt 1 view .LVU32 +1118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* check if instance is not outside the DMA channel range */ +1121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA1 */ +1124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Associate a DMA Channel to a DMAMUX channel */ +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); +1126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; +1129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** else +1131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA2 */ +1133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Associate a DMA Channel to a DMAMUX channel */ +1134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } +1139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #else +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Associate a DMA Channel to a DMAMUX channel */ +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->C + 139 .loc 1 1141 3 view .LVU33 + 140 .loc 1 1141 112 is_stmt 0 view .LVU34 + 141 0004 036C ldr r3, [r0, #64] + 142 0006 9B08 lsrs r3, r3, #2 + 143 .loc 1 1141 51 view .LVU35 + 144 0008 094A ldr r2, .L9 + 145 000a 9446 mov ip, r2 + 146 000c 6344 add r3, r3, ip + 147 000e 9B00 lsls r3, r3, #2 + 148 .loc 1 1141 23 view .LVU36 + 149 0010 4364 str r3, [r0, #68] +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + 150 .loc 1 1144 3 is_stmt 1 view .LVU37 + 151 .loc 1 1144 47 is_stmt 0 view .LVU38 + 152 0012 FF20 movs r0, #255 + 153 .LVL6: + 154 .loc 1 1144 47 view .LVU39 + 155 0014 2368 ldr r3, [r4] + 156 0016 1840 ands r0, r3 + 157 .loc 1 1144 56 view .LVU40 + 158 0018 0838 subs r0, r0, #8 + 159 .loc 1 1144 18 view .LVU41 + 160 001a 1421 movs r1, #20 + 161 001c FFF7FEFF bl __aeabi_uidiv + 162 .LVL7: +1145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 24 + + +1147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + 163 .loc 1 1148 3 is_stmt 1 view .LVU42 + 164 .loc 1 1148 29 is_stmt 0 view .LVU43 + 165 0020 044B ldr r3, .L9+4 + 166 0022 A364 str r3, [r4, #72] +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channe +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); + 167 .loc 1 1151 3 is_stmt 1 view .LVU44 + 168 .loc 1 1151 58 is_stmt 0 view .LVU45 + 169 0024 1F23 movs r3, #31 + 170 0026 1840 ands r0, r3 + 171 .LVL8: + 172 .loc 1 1151 39 view .LVU46 + 173 0028 1E3B subs r3, r3, #30 + 174 002a 8340 lsls r3, r3, r0 + 175 .loc 1 1151 33 view .LVU47 + 176 002c E364 str r3, [r4, #76] +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 177 .loc 1 1152 1 view .LVU48 + 178 @ sp needed + 179 .LVL9: + 180 .loc 1 1152 1 view .LVU49 + 181 002e 10BD pop {r4, pc} + 182 .L10: + 183 .align 2 + 184 .L9: + 185 0030 00820010 .word 268468736 + 186 0034 80080240 .word 1073875072 + 187 .cfi_endproc + 188 .LFE310: + 190 .section .text.DMA_CalcDMAMUXRequestGenBaseAndMask,"ax",%progbits + 191 .align 1 + 192 .syntax unified + 193 .code 16 + 194 .thumb_func + 195 .fpu softvfp + 197 DMA_CalcDMAMUXRequestGenBaseAndMask: + 198 .LVL10: + 199 .LFB311: +1153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /** +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @brief Updates the DMA handle with the DMAMUX request generator params +1156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * the configuration information for the specified DMA Channel. +1158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** * @retval None +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** */ +1160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 200 .loc 1 1162 1 is_stmt 1 view -0 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 0 + 203 @ frame_needed = 0, uses_anonymous_args = 0 + 204 @ link register save eliminated. +1163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + ARM GAS /tmp/ccdBjPSF.s page 25 + + + 205 .loc 1 1163 3 view .LVU51 + 206 .loc 1 1163 12 is_stmt 0 view .LVU52 + 207 0000 3F23 movs r3, #63 + 208 0002 4268 ldr r2, [r0, #4] + 209 0004 1340 ands r3, r2 + 210 .LVL11: +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* DMA Channels are connected to DMAMUX1 request generator blocks*/ +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGener + 211 .loc 1 1166 3 is_stmt 1 view .LVU53 + 212 .loc 1 1166 58 is_stmt 0 view .LVU54 + 213 0006 064A ldr r2, .L12 + 214 0008 9A18 adds r2, r3, r2 + 215 000a 9200 lsls r2, r2, #2 + 216 .loc 1 1166 26 view .LVU55 + 217 000c 0265 str r2, [r0, #80] +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + 218 .loc 1 1168 3 is_stmt 1 view .LVU56 + 219 .loc 1 1168 32 is_stmt 0 view .LVU57 + 220 000e 054A ldr r2, .L12+4 + 221 0010 4265 str r2, [r0, #84] +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ +1171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); + 222 .loc 1 1171 3 is_stmt 1 view .LVU58 + 223 .loc 1 1171 55 is_stmt 0 view .LVU59 + 224 0012 013B subs r3, r3, #1 + 225 .LVL12: + 226 .loc 1 1171 61 view .LVU60 + 227 0014 0322 movs r2, #3 + 228 0016 1A40 ands r2, r3 + 229 .loc 1 1171 42 view .LVU61 + 230 0018 0123 movs r3, #1 + 231 .LVL13: + 232 .loc 1 1171 42 view .LVU62 + 233 001a 9340 lsls r3, r3, r2 + 234 .loc 1 1171 36 view .LVU63 + 235 001c 8365 str r3, [r0, #88] +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 236 .loc 1 1172 1 view .LVU64 + 237 @ sp needed + 238 001e 7047 bx lr + 239 .L13: + 240 .align 2 + 241 .L12: + 242 0020 3F820010 .word 268468799 + 243 0024 40090240 .word 1073875264 + 244 .cfi_endproc + 245 .LFE311: + 247 .section .text.HAL_DMA_Init,"ax",%progbits + 248 .align 1 + 249 .global HAL_DMA_Init + 250 .syntax unified + 251 .code 16 + 252 .thumb_func + 253 .fpu softvfp + ARM GAS /tmp/ccdBjPSF.s page 26 + + + 255 HAL_DMA_Init: + 256 .LVL14: + 257 .LFB297: + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + 258 .loc 1 152 1 is_stmt 1 view -0 + 259 .cfi_startproc + 260 @ args = 0, pretend = 0, frame = 0 + 261 @ frame_needed = 0, uses_anonymous_args = 0 + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + 262 .loc 1 152 1 is_stmt 0 view .LVU66 + 263 0000 70B5 push {r4, r5, r6, lr} + 264 .LCFI2: + 265 .cfi_def_cfa_offset 16 + 266 .cfi_offset 4, -16 + 267 .cfi_offset 5, -12 + 268 .cfi_offset 6, -8 + 269 .cfi_offset 14, -4 + 270 0002 041E subs r4, r0, #0 + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 271 .loc 1 154 3 is_stmt 1 view .LVU67 + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 272 .loc 1 154 6 is_stmt 0 view .LVU68 + 273 0004 4DD0 beq .L19 + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 274 .loc 1 160 3 is_stmt 1 view .LVU69 + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 275 .loc 1 161 3 view .LVU70 + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 276 .loc 1 162 3 view .LVU71 + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 277 .loc 1 163 3 view .LVU72 + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 278 .loc 1 164 3 view .LVU73 + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 279 .loc 1 165 3 view .LVU74 + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 280 .loc 1 166 3 view .LVU75 + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 281 .loc 1 167 3 view .LVU76 + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 282 .loc 1 169 3 view .LVU77 + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 283 .loc 1 186 3 view .LVU78 + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 284 .loc 1 186 40 is_stmt 0 view .LVU79 + 285 0006 0568 ldr r5, [r0] + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 286 .loc 1 186 51 view .LVU80 + 287 0008 274B ldr r3, .L22 + 288 000a E818 adds r0, r5, r3 + 289 .LVL15: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 290 .loc 1 186 78 view .LVU81 + 291 000c 1421 movs r1, #20 + 292 000e FFF7FEFF bl __aeabi_uidiv + 293 .LVL16: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + ARM GAS /tmp/ccdBjPSF.s page 27 + + + 294 .loc 1 186 133 view .LVU82 + 295 0012 8000 lsls r0, r0, #2 + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 296 .loc 1 186 22 view .LVU83 + 297 0014 2064 str r0, [r4, #64] + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 298 .loc 1 190 3 is_stmt 1 view .LVU84 + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 299 .loc 1 190 15 is_stmt 0 view .LVU85 + 300 0016 2523 movs r3, #37 + 301 0018 0222 movs r2, #2 + 302 001a E254 strb r2, [r4, r3] + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 303 .loc 1 193 3 is_stmt 1 view .LVU86 + 304 001c 2B68 ldr r3, [r5] + 305 001e 234A ldr r2, .L22+4 + 306 0020 1340 ands r3, r2 + 307 0022 2B60 str r3, [r5] + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | \ + 308 .loc 1 198 3 view .LVU87 + 309 0024 2168 ldr r1, [r4] + 310 0026 0A68 ldr r2, [r1] + 311 0028 A368 ldr r3, [r4, #8] + 312 002a E068 ldr r0, [r4, #12] + 313 002c 0343 orrs r3, r0 + 314 002e 2069 ldr r0, [r4, #16] + 315 0030 0343 orrs r3, r0 + 316 0032 6069 ldr r0, [r4, #20] + 317 0034 0343 orrs r3, r0 + 318 0036 A069 ldr r0, [r4, #24] + 319 0038 0343 orrs r3, r0 + 320 003a E069 ldr r0, [r4, #28] + 321 003c 0343 orrs r3, r0 + 322 003e 206A ldr r0, [r4, #32] + 323 0040 0343 orrs r3, r0 + 324 0042 1343 orrs r3, r2 + 325 0044 0B60 str r3, [r1] + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 326 .loc 1 206 3 view .LVU88 + 327 0046 2000 movs r0, r4 + 328 0048 FFF7FEFF bl DMA_CalcDMAMUXChannelBaseAndMask + 329 .LVL17: + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 330 .loc 1 208 3 view .LVU89 + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 331 .loc 1 208 6 is_stmt 0 view .LVU90 + 332 004c 8023 movs r3, #128 + 333 004e DB01 lsls r3, r3, #7 + 334 0050 A268 ldr r2, [r4, #8] + 335 0052 9A42 cmp r2, r3 + 336 0054 18D0 beq .L20 + 337 .L16: + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 338 .loc 1 215 3 is_stmt 1 view .LVU91 + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 339 .loc 1 215 7 is_stmt 0 view .LVU92 + 340 0056 626C ldr r2, [r4, #68] + ARM GAS /tmp/ccdBjPSF.s page 28 + + + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 341 .loc 1 215 50 view .LVU93 + 342 0058 3F23 movs r3, #63 + 343 005a 6168 ldr r1, [r4, #4] + 344 005c 0B40 ands r3, r1 + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 345 .loc 1 215 28 view .LVU94 + 346 005e 1360 str r3, [r2] + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 347 .loc 1 218 3 is_stmt 1 view .LVU95 + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 348 .loc 1 218 7 is_stmt 0 view .LVU96 + 349 0060 A36C ldr r3, [r4, #72] + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 350 .loc 1 218 34 view .LVU97 + 351 0062 E26C ldr r2, [r4, #76] + 352 0064 5A60 str r2, [r3, #4] + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 353 .loc 1 220 3 is_stmt 1 view .LVU98 + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 354 .loc 1 220 36 is_stmt 0 view .LVU99 + 355 0066 6368 ldr r3, [r4, #4] + 356 0068 013B subs r3, r3, #1 + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 357 .loc 1 220 6 view .LVU100 + 358 006a 032B cmp r3, #3 + 359 006c 0FD9 bls .L21 + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 360 .loc 1 235 5 is_stmt 1 view .LVU101 + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 361 .loc 1 235 28 is_stmt 0 view .LVU102 + 362 006e 0023 movs r3, #0 + 363 0070 2365 str r3, [r4, #80] + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 364 .loc 1 236 5 is_stmt 1 view .LVU103 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 365 .loc 1 236 34 is_stmt 0 view .LVU104 + 366 0072 6365 str r3, [r4, #84] + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 367 .loc 1 237 5 is_stmt 1 view .LVU105 + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 368 .loc 1 237 38 is_stmt 0 view .LVU106 + 369 0074 A365 str r3, [r4, #88] + 370 .L18: + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 371 .loc 1 241 3 is_stmt 1 view .LVU107 + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 372 .loc 1 241 19 is_stmt 0 view .LVU108 + 373 0076 0023 movs r3, #0 + 374 0078 E363 str r3, [r4, #60] + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 375 .loc 1 244 3 is_stmt 1 view .LVU109 + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 376 .loc 1 244 15 is_stmt 0 view .LVU110 + 377 007a 2522 movs r2, #37 + 378 007c 0121 movs r1, #1 + 379 007e A154 strb r1, [r4, r2] + ARM GAS /tmp/ccdBjPSF.s page 29 + + + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 380 .loc 1 247 3 is_stmt 1 view .LVU111 + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 381 .loc 1 247 3 view .LVU112 + 382 0080 013A subs r2, r2, #1 + 383 0082 A354 strb r3, [r4, r2] + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 384 .loc 1 247 3 view .LVU113 + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 385 .loc 1 249 3 view .LVU114 + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 386 .loc 1 249 10 is_stmt 0 view .LVU115 + 387 0084 0020 movs r0, #0 + 388 .L15: + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 389 .loc 1 250 1 view .LVU116 + 390 @ sp needed + 391 .LVL18: + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 392 .loc 1 250 1 view .LVU117 + 393 0086 70BD pop {r4, r5, r6, pc} + 394 .LVL19: + 395 .L20: + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 396 .loc 1 211 5 is_stmt 1 view .LVU118 + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 397 .loc 1 211 24 is_stmt 0 view .LVU119 + 398 0088 0023 movs r3, #0 + 399 008a 6360 str r3, [r4, #4] + 400 008c E3E7 b .L16 + 401 .L21: + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 402 .loc 1 225 5 is_stmt 1 view .LVU120 + 403 008e 2000 movs r0, r4 + 404 0090 FFF7FEFF bl DMA_CalcDMAMUXRequestGenBaseAndMask + 405 .LVL20: + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 406 .loc 1 228 5 view .LVU121 + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 407 .loc 1 228 9 is_stmt 0 view .LVU122 + 408 0094 236D ldr r3, [r4, #80] + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 409 .loc 1 228 34 view .LVU123 + 410 0096 0022 movs r2, #0 + 411 0098 1A60 str r2, [r3] + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 412 .loc 1 231 5 is_stmt 1 view .LVU124 + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 413 .loc 1 231 9 is_stmt 0 view .LVU125 + 414 009a 636D ldr r3, [r4, #84] + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 415 .loc 1 231 41 view .LVU126 + 416 009c A26D ldr r2, [r4, #88] + 417 009e 5A60 str r2, [r3, #4] + 418 00a0 E9E7 b .L18 + 419 .LVL21: + 420 .L19: + ARM GAS /tmp/ccdBjPSF.s page 30 + + + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 421 .loc 1 156 12 view .LVU127 + 422 00a2 0120 movs r0, #1 + 423 .LVL22: + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 424 .loc 1 156 12 view .LVU128 + 425 00a4 EFE7 b .L15 + 426 .L23: + 427 00a6 C046 .align 2 + 428 .L22: + 429 00a8 F8FFFDBF .word -1073872904 + 430 00ac 0F80FFFF .word -32753 + 431 .cfi_endproc + 432 .LFE297: + 434 .section .text.HAL_DMA_DeInit,"ax",%progbits + 435 .align 1 + 436 .global HAL_DMA_DeInit + 437 .syntax unified + 438 .code 16 + 439 .thumb_func + 440 .fpu softvfp + 442 HAL_DMA_DeInit: + 443 .LVL23: + 444 .LFB298: + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + 445 .loc 1 259 1 is_stmt 1 view -0 + 446 .cfi_startproc + 447 @ args = 0, pretend = 0, frame = 0 + 448 @ frame_needed = 0, uses_anonymous_args = 0 + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA handle allocation */ + 449 .loc 1 259 1 is_stmt 0 view .LVU130 + 450 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 451 .LCFI3: + 452 .cfi_def_cfa_offset 24 + 453 .cfi_offset 3, -24 + 454 .cfi_offset 4, -20 + 455 .cfi_offset 5, -16 + 456 .cfi_offset 6, -12 + 457 .cfi_offset 7, -8 + 458 .cfi_offset 14, -4 + 459 0002 041E subs r4, r0, #0 + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 460 .loc 1 261 3 is_stmt 1 view .LVU131 + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 461 .loc 1 261 6 is_stmt 0 view .LVU132 + 462 0004 3BD0 beq .L27 + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 463 .loc 1 267 3 is_stmt 1 view .LVU133 + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 464 .loc 1 270 3 view .LVU134 + 465 0006 0268 ldr r2, [r0] + 466 0008 1368 ldr r3, [r2] + 467 000a 0125 movs r5, #1 + 468 000c AB43 bics r3, r5 + 469 000e 1360 str r3, [r2] + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 470 .loc 1 287 3 view .LVU135 + ARM GAS /tmp/ccdBjPSF.s page 31 + + + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 471 .loc 1 287 40 is_stmt 0 view .LVU136 + 472 0010 0768 ldr r7, [r0] + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 473 .loc 1 287 51 view .LVU137 + 474 0012 1C4B ldr r3, .L29 + 475 0014 F818 adds r0, r7, r3 + 476 .LVL24: + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 477 .loc 1 287 78 view .LVU138 + 478 0016 1421 movs r1, #20 + 479 0018 FFF7FEFF bl __aeabi_uidiv + 480 .LVL25: + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 481 .loc 1 287 133 view .LVU139 + 482 001c 8000 lsls r0, r0, #2 + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 483 .loc 1 287 22 view .LVU140 + 484 001e 2064 str r0, [r4, #64] + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 485 .loc 1 291 3 is_stmt 1 view .LVU141 + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 486 .loc 1 291 23 is_stmt 0 view .LVU142 + 487 0020 0026 movs r6, #0 + 488 0022 3E60 str r6, [r7] + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 489 .loc 1 297 3 is_stmt 1 view .LVU143 + 490 0024 1849 ldr r1, .L29+4 + 491 0026 4B68 ldr r3, [r1, #4] + 492 0028 1C22 movs r2, #28 + 493 002a 206C ldr r0, [r4, #64] + 494 002c 0240 ands r2, r0 + 495 002e 9540 lsls r5, r5, r2 + 496 0030 1D43 orrs r5, r3 + 497 0032 4D60 str r5, [r1, #4] + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 498 .loc 1 303 3 view .LVU144 + 499 0034 2000 movs r0, r4 + 500 0036 FFF7FEFF bl DMA_CalcDMAMUXChannelBaseAndMask + 501 .LVL26: + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 502 .loc 1 306 3 view .LVU145 + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 503 .loc 1 306 7 is_stmt 0 view .LVU146 + 504 003a 636C ldr r3, [r4, #68] + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 505 .loc 1 306 28 view .LVU147 + 506 003c 1E60 str r6, [r3] + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 507 .loc 1 309 3 is_stmt 1 view .LVU148 + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 508 .loc 1 309 7 is_stmt 0 view .LVU149 + 509 003e A36C ldr r3, [r4, #72] + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 510 .loc 1 309 34 view .LVU150 + 511 0040 E26C ldr r2, [r4, #76] + 512 0042 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccdBjPSF.s page 32 + + + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 513 .loc 1 312 3 is_stmt 1 view .LVU151 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 514 .loc 1 312 36 is_stmt 0 view .LVU152 + 515 0044 6368 ldr r3, [r4, #4] + 516 0046 013B subs r3, r3, #1 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 517 .loc 1 312 6 view .LVU153 + 518 0048 032B cmp r3, #3 + 519 004a 0ED9 bls .L28 + 520 .L26: + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 521 .loc 1 326 3 is_stmt 1 view .LVU154 + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatus = 0U; + 522 .loc 1 326 26 is_stmt 0 view .LVU155 + 523 004c 0023 movs r3, #0 + 524 004e 2365 str r3, [r4, #80] + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 525 .loc 1 327 3 is_stmt 1 view .LVU156 + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->DMAmuxRequestGenStatusMask = 0U; + 526 .loc 1 327 32 is_stmt 0 view .LVU157 + 527 0050 6365 str r3, [r4, #84] + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 528 .loc 1 328 3 is_stmt 1 view .LVU158 + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 529 .loc 1 328 36 is_stmt 0 view .LVU159 + 530 0052 A365 str r3, [r4, #88] + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 531 .loc 1 331 3 is_stmt 1 view .LVU160 + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 532 .loc 1 331 26 is_stmt 0 view .LVU161 + 533 0054 E362 str r3, [r4, #44] + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 534 .loc 1 332 3 is_stmt 1 view .LVU162 + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 535 .loc 1 332 30 is_stmt 0 view .LVU163 + 536 0056 2363 str r3, [r4, #48] + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 537 .loc 1 333 3 is_stmt 1 view .LVU164 + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 538 .loc 1 333 27 is_stmt 0 view .LVU165 + 539 0058 6363 str r3, [r4, #52] + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 540 .loc 1 334 3 is_stmt 1 view .LVU166 + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 541 .loc 1 334 27 is_stmt 0 view .LVU167 + 542 005a A363 str r3, [r4, #56] + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 543 .loc 1 337 3 is_stmt 1 view .LVU168 + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 544 .loc 1 337 19 is_stmt 0 view .LVU169 + 545 005c E363 str r3, [r4, #60] + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 546 .loc 1 340 3 is_stmt 1 view .LVU170 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 547 .loc 1 340 15 is_stmt 0 view .LVU171 + 548 005e 2522 movs r2, #37 + ARM GAS /tmp/ccdBjPSF.s page 33 + + + 549 0060 A354 strb r3, [r4, r2] + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 550 .loc 1 343 3 is_stmt 1 view .LVU172 + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 551 .loc 1 343 3 view .LVU173 + 552 0062 013A subs r2, r2, #1 + 553 0064 A354 strb r3, [r4, r2] + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 554 .loc 1 343 3 view .LVU174 + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 555 .loc 1 345 3 view .LVU175 + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 556 .loc 1 345 10 is_stmt 0 view .LVU176 + 557 0066 0020 movs r0, #0 + 558 .L25: + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 559 .loc 1 346 1 view .LVU177 + 560 @ sp needed + 561 .LVL27: + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 562 .loc 1 346 1 view .LVU178 + 563 0068 F8BD pop {r3, r4, r5, r6, r7, pc} + 564 .LVL28: + 565 .L28: + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 566 .loc 1 317 5 is_stmt 1 view .LVU179 + 567 006a 2000 movs r0, r4 + 568 006c FFF7FEFF bl DMA_CalcDMAMUXRequestGenBaseAndMask + 569 .LVL29: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 570 .loc 1 320 5 view .LVU180 + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 571 .loc 1 320 9 is_stmt 0 view .LVU181 + 572 0070 236D ldr r3, [r4, #80] + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 573 .loc 1 320 34 view .LVU182 + 574 0072 0022 movs r2, #0 + 575 0074 1A60 str r2, [r3] + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 576 .loc 1 323 5 is_stmt 1 view .LVU183 + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 577 .loc 1 323 9 is_stmt 0 view .LVU184 + 578 0076 636D ldr r3, [r4, #84] + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 579 .loc 1 323 41 view .LVU185 + 580 0078 A26D ldr r2, [r4, #88] + 581 007a 5A60 str r2, [r3, #4] + 582 007c E6E7 b .L26 + 583 .LVL30: + 584 .L27: + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 585 .loc 1 263 12 view .LVU186 + 586 007e 0120 movs r0, #1 + 587 .LVL31: + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 588 .loc 1 263 12 view .LVU187 + 589 0080 F2E7 b .L25 + ARM GAS /tmp/ccdBjPSF.s page 34 + + + 590 .L30: + 591 0082 C046 .align 2 + 592 .L29: + 593 0084 F8FFFDBF .word -1073872904 + 594 0088 00000240 .word 1073872896 + 595 .cfi_endproc + 596 .LFE298: + 598 .section .text.HAL_DMA_Start,"ax",%progbits + 599 .align 1 + 600 .global HAL_DMA_Start + 601 .syntax unified + 602 .code 16 + 603 .thumb_func + 604 .fpu softvfp + 606 HAL_DMA_Start: + 607 .LVL32: + 608 .LFB299: + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 609 .loc 1 382 1 is_stmt 1 view -0 + 610 .cfi_startproc + 611 @ args = 0, pretend = 0, frame = 0 + 612 @ frame_needed = 0, uses_anonymous_args = 0 + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 613 .loc 1 382 1 is_stmt 0 view .LVU189 + 614 0000 70B5 push {r4, r5, r6, lr} + 615 .LCFI4: + 616 .cfi_def_cfa_offset 16 + 617 .cfi_offset 4, -16 + 618 .cfi_offset 5, -12 + 619 .cfi_offset 6, -8 + 620 .cfi_offset 14, -4 + 621 0002 0400 movs r4, r0 + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 622 .loc 1 383 3 is_stmt 1 view .LVU190 + 623 .LVL33: + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 624 .loc 1 386 3 view .LVU191 + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 625 .loc 1 389 3 view .LVU192 + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 626 .loc 1 389 3 view .LVU193 + 627 0004 2420 movs r0, #36 + 628 .LVL34: + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 629 .loc 1 389 3 is_stmt 0 view .LVU194 + 630 0006 205C ldrb r0, [r4, r0] + 631 0008 0128 cmp r0, #1 + 632 000a 20D0 beq .L34 + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 633 .loc 1 389 3 is_stmt 1 discriminator 2 view .LVU195 + 634 000c 2420 movs r0, #36 + 635 000e 0125 movs r5, #1 + 636 0010 2554 strb r5, [r4, r0] + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 637 .loc 1 389 3 discriminator 2 view .LVU196 + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 638 .loc 1 391 3 discriminator 2 view .LVU197 + ARM GAS /tmp/ccdBjPSF.s page 35 + + + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 639 .loc 1 391 11 is_stmt 0 discriminator 2 view .LVU198 + 640 0012 0130 adds r0, r0, #1 + 641 0014 205C ldrb r0, [r4, r0] + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 642 .loc 1 391 6 discriminator 2 view .LVU199 + 643 0016 0128 cmp r0, #1 + 644 0018 06D0 beq .L35 + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 645 .loc 1 411 5 is_stmt 1 view .LVU200 + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 646 .loc 1 411 21 is_stmt 0 view .LVU201 + 647 001a 8023 movs r3, #128 + 648 .LVL35: + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 649 .loc 1 411 21 view .LVU202 + 650 001c E363 str r3, [r4, #60] + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 651 .loc 1 414 5 is_stmt 1 view .LVU203 + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 652 .loc 1 414 5 view .LVU204 + 653 001e 5C3B subs r3, r3, #92 + 654 0020 0022 movs r2, #0 + 655 .LVL36: + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 656 .loc 1 414 5 is_stmt 0 view .LVU205 + 657 0022 E254 strb r2, [r4, r3] + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 658 .loc 1 414 5 is_stmt 1 view .LVU206 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 659 .loc 1 417 5 view .LVU207 + 660 .LVL37: + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 661 .loc 1 417 12 is_stmt 0 view .LVU208 + 662 0024 0120 movs r0, #1 + 663 .LVL38: + 664 .L32: + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 665 .loc 1 421 1 view .LVU209 + 666 @ sp needed + 667 .LVL39: + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 668 .loc 1 421 1 view .LVU210 + 669 0026 70BD pop {r4, r5, r6, pc} + 670 .LVL40: + 671 .L35: + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 672 .loc 1 394 5 is_stmt 1 view .LVU211 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 673 .loc 1 394 17 is_stmt 0 view .LVU212 + 674 0028 2430 adds r0, r0, #36 + 675 002a 0135 adds r5, r5, #1 + 676 002c 2554 strb r5, [r4, r0] + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 677 .loc 1 397 5 is_stmt 1 view .LVU213 + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 678 .loc 1 397 21 is_stmt 0 view .LVU214 + ARM GAS /tmp/ccdBjPSF.s page 36 + + + 679 002e 0020 movs r0, #0 + 680 0030 E063 str r0, [r4, #60] + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 681 .loc 1 400 5 is_stmt 1 view .LVU215 + 682 0032 2668 ldr r6, [r4] + 683 0034 3068 ldr r0, [r6] + 684 0036 013D subs r5, r5, #1 + 685 0038 A843 bics r0, r5 + 686 003a 3060 str r0, [r6] + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 687 .loc 1 403 5 view .LVU216 + 688 003c 2000 movs r0, r4 + 689 003e FFF7FEFF bl DMA_SetConfig + 690 .LVL41: + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 691 .loc 1 406 5 view .LVU217 + 692 0042 2268 ldr r2, [r4] + 693 0044 1368 ldr r3, [r2] + 694 0046 2B43 orrs r3, r5 + 695 0048 1360 str r3, [r2] + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 696 .loc 1 383 21 is_stmt 0 view .LVU218 + 697 004a 0020 movs r0, #0 + 698 004c EBE7 b .L32 + 699 .LVL42: + 700 .L34: + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 701 .loc 1 389 3 view .LVU219 + 702 004e 0220 movs r0, #2 + 703 0050 E9E7 b .L32 + 704 .cfi_endproc + 705 .LFE299: + 707 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 708 .align 1 + 709 .global HAL_DMA_Start_IT + 710 .syntax unified + 711 .code 16 + 712 .thumb_func + 713 .fpu softvfp + 715 HAL_DMA_Start_IT: + 716 .LVL43: + 717 .LFB300: + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 718 .loc 1 433 1 is_stmt 1 view -0 + 719 .cfi_startproc + 720 @ args = 0, pretend = 0, frame = 0 + 721 @ frame_needed = 0, uses_anonymous_args = 0 + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 722 .loc 1 433 1 is_stmt 0 view .LVU221 + 723 0000 70B5 push {r4, r5, r6, lr} + 724 .LCFI5: + 725 .cfi_def_cfa_offset 16 + 726 .cfi_offset 4, -16 + 727 .cfi_offset 5, -12 + 728 .cfi_offset 6, -8 + 729 .cfi_offset 14, -4 + 730 0002 0400 movs r4, r0 + ARM GAS /tmp/ccdBjPSF.s page 37 + + + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 731 .loc 1 434 3 is_stmt 1 view .LVU222 + 732 .LVL44: + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 733 .loc 1 437 3 view .LVU223 + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 734 .loc 1 440 3 view .LVU224 + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 735 .loc 1 440 3 view .LVU225 + 736 0004 2420 movs r0, #36 + 737 .LVL45: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 738 .loc 1 440 3 is_stmt 0 view .LVU226 + 739 0006 205C ldrb r0, [r4, r0] + 740 0008 0128 cmp r0, #1 + 741 000a 45D0 beq .L43 + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 742 .loc 1 440 3 is_stmt 1 discriminator 2 view .LVU227 + 743 000c 2420 movs r0, #36 + 744 000e 0125 movs r5, #1 + 745 0010 2554 strb r5, [r4, r0] + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 746 .loc 1 440 3 discriminator 2 view .LVU228 + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 747 .loc 1 442 3 discriminator 2 view .LVU229 + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 748 .loc 1 442 11 is_stmt 0 discriminator 2 view .LVU230 + 749 0012 0130 adds r0, r0, #1 + 750 0014 205C ldrb r0, [r4, r0] + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 751 .loc 1 442 6 discriminator 2 view .LVU231 + 752 0016 0128 cmp r0, #1 + 753 0018 06D0 beq .L44 + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 754 .loc 1 487 5 is_stmt 1 view .LVU232 + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 755 .loc 1 487 21 is_stmt 0 view .LVU233 + 756 001a 8023 movs r3, #128 + 757 .LVL46: + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 758 .loc 1 487 21 view .LVU234 + 759 001c E363 str r3, [r4, #60] + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 760 .loc 1 490 5 is_stmt 1 view .LVU235 + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 761 .loc 1 490 5 view .LVU236 + 762 001e 5C3B subs r3, r3, #92 + 763 0020 0022 movs r2, #0 + 764 .LVL47: + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 765 .loc 1 490 5 is_stmt 0 view .LVU237 + 766 0022 E254 strb r2, [r4, r3] + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 767 .loc 1 490 5 is_stmt 1 view .LVU238 + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 768 .loc 1 493 5 view .LVU239 + 769 .LVL48: + ARM GAS /tmp/ccdBjPSF.s page 38 + + + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 770 .loc 1 493 12 is_stmt 0 view .LVU240 + 771 0024 0120 movs r0, #1 + 772 .LVL49: + 773 .L37: + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 774 .loc 1 497 1 view .LVU241 + 775 @ sp needed + 776 .LVL50: + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 777 .loc 1 497 1 view .LVU242 + 778 0026 70BD pop {r4, r5, r6, pc} + 779 .LVL51: + 780 .L44: + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 781 .loc 1 445 5 is_stmt 1 view .LVU243 + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 782 .loc 1 445 17 is_stmt 0 view .LVU244 + 783 0028 2430 adds r0, r0, #36 + 784 002a 0135 adds r5, r5, #1 + 785 002c 2554 strb r5, [r4, r0] + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 786 .loc 1 446 5 is_stmt 1 view .LVU245 + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 787 .loc 1 446 21 is_stmt 0 view .LVU246 + 788 002e 0020 movs r0, #0 + 789 0030 E063 str r0, [r4, #60] + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 790 .loc 1 449 5 is_stmt 1 view .LVU247 + 791 0032 2568 ldr r5, [r4] + 792 0034 2868 ldr r0, [r5] + 793 0036 0126 movs r6, #1 + 794 0038 B043 bics r0, r6 + 795 003a 2860 str r0, [r5] + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 796 .loc 1 452 5 view .LVU248 + 797 003c 2000 movs r0, r4 + 798 003e FFF7FEFF bl DMA_SetConfig + 799 .LVL52: + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 800 .loc 1 456 5 view .LVU249 + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 801 .loc 1 456 8 is_stmt 0 view .LVU250 + 802 0042 236B ldr r3, [r4, #48] + 803 0044 002B cmp r3, #0 + 804 0046 1CD0 beq .L39 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 805 .loc 1 459 7 is_stmt 1 view .LVU251 + 806 0048 2268 ldr r2, [r4] + 807 004a 1368 ldr r3, [r2] + 808 004c 0E21 movs r1, #14 + 809 004e 0B43 orrs r3, r1 + 810 0050 1360 str r3, [r2] + 811 .L40: + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 812 .loc 1 468 5 view .LVU252 + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + ARM GAS /tmp/ccdBjPSF.s page 39 + + + 813 .loc 1 468 14 is_stmt 0 view .LVU253 + 814 0052 636C ldr r3, [r4, #68] + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 815 .loc 1 468 29 view .LVU254 + 816 0054 1A68 ldr r2, [r3] + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 817 .loc 1 468 8 view .LVU255 + 818 0056 D203 lsls r2, r2, #15 + 819 0058 04D5 bpl .L41 + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 820 .loc 1 471 7 is_stmt 1 view .LVU256 + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 821 .loc 1 471 32 is_stmt 0 view .LVU257 + 822 005a 1968 ldr r1, [r3] + 823 005c 8022 movs r2, #128 + 824 005e 5200 lsls r2, r2, #1 + 825 0060 0A43 orrs r2, r1 + 826 0062 1A60 str r2, [r3] + 827 .L41: + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 828 .loc 1 474 5 is_stmt 1 view .LVU258 + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 829 .loc 1 474 13 is_stmt 0 view .LVU259 + 830 0064 236D ldr r3, [r4, #80] + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 831 .loc 1 474 8 view .LVU260 + 832 0066 002B cmp r3, #0 + 833 0068 04D0 beq .L42 + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 834 .loc 1 478 7 is_stmt 1 view .LVU261 + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 835 .loc 1 478 36 is_stmt 0 view .LVU262 + 836 006a 1968 ldr r1, [r3] + 837 006c 8022 movs r2, #128 + 838 006e 5200 lsls r2, r2, #1 + 839 0070 0A43 orrs r2, r1 + 840 0072 1A60 str r2, [r3] + 841 .L42: + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 842 .loc 1 482 5 is_stmt 1 view .LVU263 + 843 0074 2268 ldr r2, [r4] + 844 0076 1368 ldr r3, [r2] + 845 0078 0121 movs r1, #1 + 846 007a 0B43 orrs r3, r1 + 847 007c 1360 str r3, [r2] + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 848 .loc 1 434 21 is_stmt 0 view .LVU264 + 849 007e 0020 movs r0, #0 + 850 0080 D1E7 b .L37 + 851 .L39: + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 852 .loc 1 463 7 is_stmt 1 view .LVU265 + 853 0082 2268 ldr r2, [r4] + 854 0084 1368 ldr r3, [r2] + 855 0086 0421 movs r1, #4 + 856 0088 8B43 bics r3, r1 + 857 008a 1360 str r3, [r2] + ARM GAS /tmp/ccdBjPSF.s page 40 + + + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 858 .loc 1 464 7 view .LVU266 + 859 008c 2268 ldr r2, [r4] + 860 008e 1368 ldr r3, [r2] + 861 0090 0631 adds r1, r1, #6 + 862 0092 0B43 orrs r3, r1 + 863 0094 1360 str r3, [r2] + 864 0096 DCE7 b .L40 + 865 .LVL53: + 866 .L43: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 867 .loc 1 440 3 is_stmt 0 view .LVU267 + 868 0098 0220 movs r0, #2 + 869 009a C4E7 b .L37 + 870 .cfi_endproc + 871 .LFE300: + 873 .section .text.HAL_DMA_Abort,"ax",%progbits + 874 .align 1 + 875 .global HAL_DMA_Abort + 876 .syntax unified + 877 .code 16 + 878 .thumb_func + 879 .fpu softvfp + 881 HAL_DMA_Abort: + 882 .LVL54: + 883 .LFB301: + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 884 .loc 1 506 1 is_stmt 1 view -0 + 885 .cfi_startproc + 886 @ args = 0, pretend = 0, frame = 0 + 887 @ frame_needed = 0, uses_anonymous_args = 0 + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Check the DMA peripheral handle */ + 888 .loc 1 506 1 is_stmt 0 view .LVU269 + 889 0000 30B5 push {r4, r5, lr} + 890 .LCFI6: + 891 .cfi_def_cfa_offset 12 + 892 .cfi_offset 4, -12 + 893 .cfi_offset 5, -8 + 894 .cfi_offset 14, -4 + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 895 .loc 1 508 3 is_stmt 1 view .LVU270 + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 896 .loc 1 508 6 is_stmt 0 view .LVU271 + 897 0002 0028 cmp r0, #0 + 898 0004 36D0 beq .L49 + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 899 .loc 1 514 3 is_stmt 1 view .LVU272 + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 900 .loc 1 514 11 is_stmt 0 view .LVU273 + 901 0006 2523 movs r3, #37 + 902 0008 C35C ldrb r3, [r0, r3] + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 903 .loc 1 514 6 view .LVU274 + 904 000a 022B cmp r3, #2 + 905 000c 06D0 beq .L47 + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 906 .loc 1 516 5 is_stmt 1 view .LVU275 + ARM GAS /tmp/ccdBjPSF.s page 41 + + + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 907 .loc 1 516 21 is_stmt 0 view .LVU276 + 908 000e 0423 movs r3, #4 + 909 0010 C363 str r3, [r0, #60] + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 910 .loc 1 519 5 is_stmt 1 view .LVU277 + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 911 .loc 1 519 5 view .LVU278 + 912 0012 2033 adds r3, r3, #32 + 913 0014 0022 movs r2, #0 + 914 0016 C254 strb r2, [r0, r3] + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 915 .loc 1 519 5 view .LVU279 + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 916 .loc 1 521 5 view .LVU280 + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 917 .loc 1 521 12 is_stmt 0 view .LVU281 + 918 0018 0120 movs r0, #1 + 919 .LVL55: + 920 .L46: + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 921 .loc 1 562 1 view .LVU282 + 922 @ sp needed + 923 001a 30BD pop {r4, r5, pc} + 924 .LVL56: + 925 .L47: + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 926 .loc 1 526 5 is_stmt 1 view .LVU283 + 927 001c 0268 ldr r2, [r0] + 928 001e 1368 ldr r3, [r2] + 929 0020 0E21 movs r1, #14 + 930 0022 8B43 bics r3, r1 + 931 0024 1360 str r3, [r2] + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 932 .loc 1 529 5 view .LVU284 + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 933 .loc 1 529 9 is_stmt 0 view .LVU285 + 934 0026 426C ldr r2, [r0, #68] + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 935 .loc 1 529 30 view .LVU286 + 936 0028 1368 ldr r3, [r2] + 937 002a 1349 ldr r1, .L50 + 938 002c 0B40 ands r3, r1 + 939 002e 1360 str r3, [r2] + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 940 .loc 1 532 5 is_stmt 1 view .LVU287 + 941 0030 0168 ldr r1, [r0] + 942 0032 0A68 ldr r2, [r1] + 943 0034 0123 movs r3, #1 + 944 0036 9A43 bics r2, r3 + 945 0038 0A60 str r2, [r1] + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 946 .loc 1 538 5 view .LVU288 + 947 003a 104C ldr r4, .L50+4 + 948 003c 6268 ldr r2, [r4, #4] + 949 003e 1C21 movs r1, #28 + 950 0040 056C ldr r5, [r0, #64] + ARM GAS /tmp/ccdBjPSF.s page 42 + + + 951 0042 2940 ands r1, r5 + 952 0044 8B40 lsls r3, r3, r1 + 953 0046 1343 orrs r3, r2 + 954 0048 6360 str r3, [r4, #4] + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 955 .loc 1 542 5 view .LVU289 + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 956 .loc 1 542 9 is_stmt 0 view .LVU290 + 957 004a 836C ldr r3, [r0, #72] + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 958 .loc 1 542 36 view .LVU291 + 959 004c C26C ldr r2, [r0, #76] + 960 004e 5A60 str r2, [r3, #4] + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 961 .loc 1 544 5 is_stmt 1 view .LVU292 + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 962 .loc 1 544 13 is_stmt 0 view .LVU293 + 963 0050 036D ldr r3, [r0, #80] + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 964 .loc 1 544 8 view .LVU294 + 965 0052 002B cmp r3, #0 + 966 0054 06D0 beq .L48 + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 967 .loc 1 548 7 is_stmt 1 view .LVU295 + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 968 .loc 1 548 36 is_stmt 0 view .LVU296 + 969 0056 1A68 ldr r2, [r3] + 970 0058 0749 ldr r1, .L50 + 971 005a 0A40 ands r2, r1 + 972 005c 1A60 str r2, [r3] + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 973 .loc 1 551 7 is_stmt 1 view .LVU297 + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 974 .loc 1 551 11 is_stmt 0 view .LVU298 + 975 005e 436D ldr r3, [r0, #84] + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 976 .loc 1 551 43 view .LVU299 + 977 0060 826D ldr r2, [r0, #88] + 978 0062 5A60 str r2, [r3, #4] + 979 .L48: + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 980 .loc 1 555 5 is_stmt 1 view .LVU300 + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 981 .loc 1 555 17 is_stmt 0 view .LVU301 + 982 0064 2523 movs r3, #37 + 983 0066 0122 movs r2, #1 + 984 0068 C254 strb r2, [r0, r3] + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 985 .loc 1 558 5 is_stmt 1 view .LVU302 + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 986 .loc 1 558 5 view .LVU303 + 987 006a 013B subs r3, r3, #1 + 988 006c 0022 movs r2, #0 + 989 006e C254 strb r2, [r0, r3] + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 990 .loc 1 558 5 view .LVU304 + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + ARM GAS /tmp/ccdBjPSF.s page 43 + + + 991 .loc 1 561 3 view .LVU305 + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 992 .loc 1 561 10 is_stmt 0 view .LVU306 + 993 0070 0020 movs r0, #0 + 994 .LVL57: + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 995 .loc 1 561 10 view .LVU307 + 996 0072 D2E7 b .L46 + 997 .LVL58: + 998 .L49: + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 999 .loc 1 510 12 view .LVU308 + 1000 0074 0120 movs r0, #1 + 1001 .LVL59: + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1002 .loc 1 510 12 view .LVU309 + 1003 0076 D0E7 b .L46 + 1004 .L51: + 1005 .align 2 + 1006 .L50: + 1007 0078 FFFEFFFF .word -257 + 1008 007c 00000240 .word 1073872896 + 1009 .cfi_endproc + 1010 .LFE301: + 1012 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 1013 .align 1 + 1014 .global HAL_DMA_Abort_IT + 1015 .syntax unified + 1016 .code 16 + 1017 .thumb_func + 1018 .fpu softvfp + 1020 HAL_DMA_Abort_IT: + 1021 .LVL60: + 1022 .LFB302: + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1023 .loc 1 571 1 is_stmt 1 view -0 + 1024 .cfi_startproc + 1025 @ args = 0, pretend = 0, frame = 0 + 1026 @ frame_needed = 0, uses_anonymous_args = 0 + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1027 .loc 1 571 1 is_stmt 0 view .LVU311 + 1028 0000 70B5 push {r4, r5, r6, lr} + 1029 .LCFI7: + 1030 .cfi_def_cfa_offset 16 + 1031 .cfi_offset 4, -16 + 1032 .cfi_offset 5, -12 + 1033 .cfi_offset 6, -8 + 1034 .cfi_offset 14, -4 + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1035 .loc 1 572 3 is_stmt 1 view .LVU312 + 1036 .LVL61: + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1037 .loc 1 574 3 view .LVU313 + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1038 .loc 1 574 11 is_stmt 0 view .LVU314 + 1039 0002 2523 movs r3, #37 + 1040 0004 C35C ldrb r3, [r0, r3] + ARM GAS /tmp/ccdBjPSF.s page 44 + + + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1041 .loc 1 574 6 view .LVU315 + 1042 0006 022B cmp r3, #2 + 1043 0008 03D0 beq .L53 + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1044 .loc 1 577 5 is_stmt 1 view .LVU316 + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1045 .loc 1 577 21 is_stmt 0 view .LVU317 + 1046 000a 0423 movs r3, #4 + 1047 000c C363 str r3, [r0, #60] + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1048 .loc 1 579 5 is_stmt 1 view .LVU318 + 1049 .LVL62: + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1050 .loc 1 579 12 is_stmt 0 view .LVU319 + 1051 000e 0120 movs r0, #1 + 1052 .LVL63: + 1053 .L54: + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1054 .loc 1 624 3 is_stmt 1 view .LVU320 + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1055 .loc 1 625 1 is_stmt 0 view .LVU321 + 1056 @ sp needed + 1057 0010 70BD pop {r4, r5, r6, pc} + 1058 .LVL64: + 1059 .L53: + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1060 .loc 1 584 5 is_stmt 1 view .LVU322 + 1061 0012 0268 ldr r2, [r0] + 1062 0014 1368 ldr r3, [r2] + 1063 0016 0E21 movs r1, #14 + 1064 0018 8B43 bics r3, r1 + 1065 001a 1360 str r3, [r2] + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1066 .loc 1 587 5 view .LVU323 + 1067 001c 0168 ldr r1, [r0] + 1068 001e 0A68 ldr r2, [r1] + 1069 0020 0123 movs r3, #1 + 1070 0022 9A43 bics r2, r3 + 1071 0024 0A60 str r2, [r1] + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1072 .loc 1 590 5 view .LVU324 + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1073 .loc 1 590 9 is_stmt 0 view .LVU325 + 1074 0026 416C ldr r1, [r0, #68] + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1075 .loc 1 590 30 view .LVU326 + 1076 0028 0A68 ldr r2, [r1] + 1077 002a 134C ldr r4, .L57 + 1078 002c 2240 ands r2, r4 + 1079 002e 0A60 str r2, [r1] + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1080 .loc 1 596 5 is_stmt 1 view .LVU327 + 1081 0030 124C ldr r4, .L57+4 + 1082 0032 6268 ldr r2, [r4, #4] + 1083 0034 1C21 movs r1, #28 + 1084 0036 056C ldr r5, [r0, #64] + ARM GAS /tmp/ccdBjPSF.s page 45 + + + 1085 0038 2940 ands r1, r5 + 1086 003a 8B40 lsls r3, r3, r1 + 1087 003c 1343 orrs r3, r2 + 1088 003e 6360 str r3, [r4, #4] + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1089 .loc 1 600 5 view .LVU328 + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1090 .loc 1 600 9 is_stmt 0 view .LVU329 + 1091 0040 836C ldr r3, [r0, #72] + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1092 .loc 1 600 36 view .LVU330 + 1093 0042 C26C ldr r2, [r0, #76] + 1094 0044 5A60 str r2, [r3, #4] + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1095 .loc 1 602 5 is_stmt 1 view .LVU331 + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1096 .loc 1 602 13 is_stmt 0 view .LVU332 + 1097 0046 036D ldr r3, [r0, #80] + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1098 .loc 1 602 8 view .LVU333 + 1099 0048 002B cmp r3, #0 + 1100 004a 06D0 beq .L55 + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1101 .loc 1 606 7 is_stmt 1 view .LVU334 + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1102 .loc 1 606 36 is_stmt 0 view .LVU335 + 1103 004c 1A68 ldr r2, [r3] + 1104 004e 0A49 ldr r1, .L57 + 1105 0050 0A40 ands r2, r1 + 1106 0052 1A60 str r2, [r3] + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1107 .loc 1 609 7 is_stmt 1 view .LVU336 + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1108 .loc 1 609 11 is_stmt 0 view .LVU337 + 1109 0054 436D ldr r3, [r0, #84] + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1110 .loc 1 609 43 view .LVU338 + 1111 0056 826D ldr r2, [r0, #88] + 1112 0058 5A60 str r2, [r3, #4] + 1113 .L55: + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1114 .loc 1 613 5 is_stmt 1 view .LVU339 + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1115 .loc 1 613 17 is_stmt 0 view .LVU340 + 1116 005a 2523 movs r3, #37 + 1117 005c 0122 movs r2, #1 + 1118 005e C254 strb r2, [r0, r3] + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1119 .loc 1 616 5 is_stmt 1 view .LVU341 + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1120 .loc 1 616 5 view .LVU342 + 1121 0060 013B subs r3, r3, #1 + 1122 0062 0022 movs r2, #0 + 1123 0064 C254 strb r2, [r0, r3] + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1124 .loc 1 616 5 view .LVU343 + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + ARM GAS /tmp/ccdBjPSF.s page 46 + + + 1125 .loc 1 619 5 view .LVU344 + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1126 .loc 1 619 13 is_stmt 0 view .LVU345 + 1127 0066 836B ldr r3, [r0, #56] + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1128 .loc 1 619 8 view .LVU346 + 1129 0068 002B cmp r3, #0 + 1130 006a 02D0 beq .L56 + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1131 .loc 1 621 7 is_stmt 1 view .LVU347 + 1132 006c 9847 blx r3 + 1133 .LVL65: + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1134 .loc 1 572 21 is_stmt 0 view .LVU348 + 1135 006e 0020 movs r0, #0 + 1136 0070 CEE7 b .L54 + 1137 .LVL66: + 1138 .L56: + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1139 .loc 1 572 21 view .LVU349 + 1140 0072 0020 movs r0, #0 + 1141 .LVL67: + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1142 .loc 1 572 21 view .LVU350 + 1143 0074 CCE7 b .L54 + 1144 .L58: + 1145 0076 C046 .align 2 + 1146 .L57: + 1147 0078 FFFEFFFF .word -257 + 1148 007c 00000240 .word 1073872896 + 1149 .cfi_endproc + 1150 .LFE302: + 1152 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 1153 .align 1 + 1154 .global HAL_DMA_PollForTransfer + 1155 .syntax unified + 1156 .code 16 + 1157 .thumb_func + 1158 .fpu softvfp + 1160 HAL_DMA_PollForTransfer: + 1161 .LVL68: + 1162 .LFB303: + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t temp; + 1163 .loc 1 636 1 is_stmt 1 view -0 + 1164 .cfi_startproc + 1165 @ args = 0, pretend = 0, frame = 8 + 1166 @ frame_needed = 0, uses_anonymous_args = 0 + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t temp; + 1167 .loc 1 636 1 is_stmt 0 view .LVU352 + 1168 0000 F0B5 push {r4, r5, r6, r7, lr} + 1169 .LCFI8: + 1170 .cfi_def_cfa_offset 20 + 1171 .cfi_offset 4, -20 + 1172 .cfi_offset 5, -16 + 1173 .cfi_offset 6, -12 + 1174 .cfi_offset 7, -8 + 1175 .cfi_offset 14, -4 + ARM GAS /tmp/ccdBjPSF.s page 47 + + + 1176 0002 83B0 sub sp, sp, #12 + 1177 .LCFI9: + 1178 .cfi_def_cfa_offset 32 + 1179 0004 0600 movs r6, r0 + 1180 0006 0C00 movs r4, r1 + 1181 0008 1700 movs r7, r2 + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** uint32_t tickstart; + 1182 .loc 1 637 3 is_stmt 1 view .LVU353 + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1183 .loc 1 638 3 view .LVU354 + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1184 .loc 1 640 3 view .LVU355 + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1185 .loc 1 640 11 is_stmt 0 view .LVU356 + 1186 000a 2523 movs r3, #37 + 1187 000c C35C ldrb r3, [r0, r3] + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1188 .loc 1 640 6 view .LVU357 + 1189 000e 022B cmp r3, #2 + 1190 0010 07D0 beq .L60 + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1191 .loc 1 643 5 is_stmt 1 view .LVU358 + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1192 .loc 1 643 21 is_stmt 0 view .LVU359 + 1193 0012 0423 movs r3, #4 + 1194 0014 C363 str r3, [r0, #60] + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1195 .loc 1 644 5 is_stmt 1 view .LVU360 + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1196 .loc 1 644 5 view .LVU361 + 1197 0016 2033 adds r3, r3, #32 + 1198 0018 0022 movs r2, #0 + 1199 .LVL69: + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1200 .loc 1 644 5 is_stmt 0 view .LVU362 + 1201 001a C254 strb r2, [r0, r3] + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1202 .loc 1 644 5 is_stmt 1 view .LVU363 + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1203 .loc 1 645 5 view .LVU364 + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1204 .loc 1 645 12 is_stmt 0 view .LVU365 + 1205 001c 0120 movs r0, #1 + 1206 .LVL70: + 1207 .L61: + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1208 .loc 1 786 1 view .LVU366 + 1209 001e 03B0 add sp, sp, #12 + 1210 @ sp needed + 1211 .LVL71: + 1212 .LVL72: + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1213 .loc 1 786 1 view .LVU367 + 1214 0020 F0BD pop {r4, r5, r6, r7, pc} + 1215 .LVL73: + 1216 .L60: + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + ARM GAS /tmp/ccdBjPSF.s page 48 + + + 1217 .loc 1 649 3 is_stmt 1 view .LVU368 + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1218 .loc 1 649 12 is_stmt 0 view .LVU369 + 1219 0022 0368 ldr r3, [r0] + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1220 .loc 1 649 22 view .LVU370 + 1221 0024 1B68 ldr r3, [r3] + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1222 .loc 1 649 6 view .LVU371 + 1223 0026 9B06 lsls r3, r3, #26 + 1224 0028 2AD4 bmi .L73 + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1225 .loc 1 656 3 is_stmt 1 view .LVU372 + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1226 .loc 1 656 6 is_stmt 0 view .LVU373 + 1227 002a 0029 cmp r1, #0 + 1228 002c 2DD1 bne .L63 + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1229 .loc 1 659 5 is_stmt 1 view .LVU374 + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1230 .loc 1 659 48 is_stmt 0 view .LVU375 + 1231 002e 1C23 movs r3, #28 + 1232 0030 026C ldr r2, [r0, #64] + 1233 .LVL74: + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1234 .loc 1 659 48 view .LVU376 + 1235 0032 1340 ands r3, r2 + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1236 .loc 1 659 10 view .LVU377 + 1237 0034 0225 movs r5, #2 + 1238 0036 9D40 lsls r5, r5, r3 + 1239 .LVL75: + 1240 .L64: + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1241 .loc 1 668 3 is_stmt 1 view .LVU378 + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1242 .loc 1 668 15 is_stmt 0 view .LVU379 + 1243 0038 FFF7FEFF bl HAL_GetTick + 1244 .LVL76: + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1245 .loc 1 668 15 view .LVU380 + 1246 003c 0190 str r0, [sp, #4] + 1247 .LVL77: + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1248 .loc 1 692 3 is_stmt 1 view .LVU381 + 1249 .L67: + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1250 .loc 1 692 9 view .LVU382 + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1251 .loc 1 692 16 is_stmt 0 view .LVU383 + 1252 003e 3D4B ldr r3, .L76 + 1253 0040 1B68 ldr r3, [r3] + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1254 .loc 1 692 9 view .LVU384 + 1255 0042 1D42 tst r5, r3 + 1256 0044 37D1 bne .L74 + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + ARM GAS /tmp/ccdBjPSF.s page 49 + + + 1257 .loc 1 694 5 is_stmt 1 view .LVU385 + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1258 .loc 1 694 15 is_stmt 0 view .LVU386 + 1259 0046 3B4B ldr r3, .L76 + 1260 0048 1A68 ldr r2, [r3] + 1261 004a 1C23 movs r3, #28 + 1262 004c 316C ldr r1, [r6, #64] + 1263 004e 0B40 ands r3, r1 + 1264 0050 0821 movs r1, #8 + 1265 0052 9940 lsls r1, r1, r3 + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1266 .loc 1 694 8 view .LVU387 + 1267 0054 1142 tst r1, r2 + 1268 0056 1ED1 bne .L75 + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1269 .loc 1 714 5 is_stmt 1 view .LVU388 + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1270 .loc 1 714 8 is_stmt 0 view .LVU389 + 1271 0058 7B1C adds r3, r7, #1 + 1272 005a F0D0 beq .L67 + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1273 .loc 1 716 7 is_stmt 1 view .LVU390 + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1274 .loc 1 716 13 is_stmt 0 view .LVU391 + 1275 005c FFF7FEFF bl HAL_GetTick + 1276 .LVL78: + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1277 .loc 1 716 27 view .LVU392 + 1278 0060 019B ldr r3, [sp, #4] + 1279 0062 C01A subs r0, r0, r3 + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1280 .loc 1 716 10 view .LVU393 + 1281 0064 B842 cmp r0, r7 + 1282 0066 01D8 bhi .L68 + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1283 .loc 1 716 51 discriminator 1 view .LVU394 + 1284 0068 002F cmp r7, #0 + 1285 006a E8D1 bne .L67 + 1286 .L68: + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1287 .loc 1 719 9 is_stmt 1 view .LVU395 + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1288 .loc 1 719 25 is_stmt 0 view .LVU396 + 1289 006c 2023 movs r3, #32 + 1290 006e F363 str r3, [r6, #60] + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1291 .loc 1 722 9 is_stmt 1 view .LVU397 + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1292 .loc 1 722 21 is_stmt 0 view .LVU398 + 1293 0070 0533 adds r3, r3, #5 + 1294 0072 0122 movs r2, #1 + 1295 0074 F254 strb r2, [r6, r3] + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1296 .loc 1 725 9 is_stmt 1 view .LVU399 + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1297 .loc 1 725 9 view .LVU400 + 1298 0076 013B subs r3, r3, #1 + ARM GAS /tmp/ccdBjPSF.s page 50 + + + 1299 0078 0022 movs r2, #0 + 1300 007a F254 strb r2, [r6, r3] + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1301 .loc 1 725 9 view .LVU401 + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1302 .loc 1 727 9 view .LVU402 + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1303 .loc 1 727 16 is_stmt 0 view .LVU403 + 1304 007c 0120 movs r0, #1 + 1305 007e CEE7 b .L61 + 1306 .LVL79: + 1307 .L73: + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1308 .loc 1 651 5 is_stmt 1 view .LVU404 + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return HAL_ERROR; + 1309 .loc 1 651 21 is_stmt 0 view .LVU405 + 1310 0080 8023 movs r3, #128 + 1311 0082 5B00 lsls r3, r3, #1 + 1312 0084 C363 str r3, [r0, #60] + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1313 .loc 1 652 5 is_stmt 1 view .LVU406 + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1314 .loc 1 652 12 is_stmt 0 view .LVU407 + 1315 0086 0120 movs r0, #1 + 1316 .LVL80: + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1317 .loc 1 652 12 view .LVU408 + 1318 0088 C9E7 b .L61 + 1319 .LVL81: + 1320 .L63: + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1321 .loc 1 664 5 is_stmt 1 view .LVU409 + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1322 .loc 1 664 48 is_stmt 0 view .LVU410 + 1323 008a 1C23 movs r3, #28 + 1324 008c 026C ldr r2, [r0, #64] + 1325 .LVL82: + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1326 .loc 1 664 48 view .LVU411 + 1327 008e 1340 ands r3, r2 + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1328 .loc 1 664 10 view .LVU412 + 1329 0090 0425 movs r5, #4 + 1330 0092 9D40 lsls r5, r5, r3 + 1331 .LVL83: + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1332 .loc 1 664 10 view .LVU413 + 1333 0094 D0E7 b .L64 + 1334 .LVL84: + 1335 .L75: + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1336 .loc 1 699 7 is_stmt 1 view .LVU414 + 1337 0096 2748 ldr r0, .L76 + 1338 0098 4168 ldr r1, [r0, #4] + 1339 009a 0122 movs r2, #1 + 1340 009c 1400 movs r4, r2 + 1341 009e 9C40 lsls r4, r4, r3 + ARM GAS /tmp/ccdBjPSF.s page 51 + + + 1342 00a0 2300 movs r3, r4 + 1343 00a2 0B43 orrs r3, r1 + 1344 00a4 4360 str r3, [r0, #4] + 1345 .LVL85: + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1346 .loc 1 702 7 view .LVU415 + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1347 .loc 1 702 23 is_stmt 0 view .LVU416 + 1348 00a6 F263 str r2, [r6, #60] + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1349 .loc 1 705 7 is_stmt 1 view .LVU417 + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1350 .loc 1 705 19 is_stmt 0 view .LVU418 + 1351 00a8 2523 movs r3, #37 + 1352 00aa F254 strb r2, [r6, r3] + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1353 .loc 1 708 7 is_stmt 1 view .LVU419 + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1354 .loc 1 708 7 view .LVU420 + 1355 00ac 013B subs r3, r3, #1 + 1356 00ae 0022 movs r2, #0 + 1357 00b0 F254 strb r2, [r6, r3] + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1358 .loc 1 708 7 view .LVU421 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1359 .loc 1 710 7 view .LVU422 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1360 .loc 1 710 14 is_stmt 0 view .LVU423 + 1361 00b2 0120 movs r0, #1 + 1362 00b4 B3E7 b .L61 + 1363 .LVL86: + 1364 .L74: + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1365 .loc 1 733 3 is_stmt 1 view .LVU424 + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1366 .loc 1 733 11 is_stmt 0 view .LVU425 + 1367 00b6 336D ldr r3, [r6, #80] + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1368 .loc 1 733 6 view .LVU426 + 1369 00b8 002B cmp r3, #0 + 1370 00ba 11D0 beq .L70 + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1371 .loc 1 736 5 is_stmt 1 view .LVU427 + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1372 .loc 1 736 14 is_stmt 0 view .LVU428 + 1373 00bc 726D ldr r2, [r6, #84] + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1374 .loc 1 736 38 view .LVU429 + 1375 00be 1268 ldr r2, [r2] + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1376 .loc 1 736 8 view .LVU430 + 1377 00c0 B16D ldr r1, [r6, #88] + 1378 00c2 1142 tst r1, r2 + 1379 00c4 0CD0 beq .L70 + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1380 .loc 1 739 7 is_stmt 1 view .LVU431 + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 52 + + + 1381 .loc 1 739 36 is_stmt 0 view .LVU432 + 1382 00c6 1968 ldr r1, [r3] + 1383 00c8 8022 movs r2, #128 + 1384 00ca 5200 lsls r2, r2, #1 + 1385 00cc 0A43 orrs r2, r1 + 1386 00ce 1A60 str r2, [r3] + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1387 .loc 1 742 7 is_stmt 1 view .LVU433 + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1388 .loc 1 742 11 is_stmt 0 view .LVU434 + 1389 00d0 736D ldr r3, [r6, #84] + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1390 .loc 1 742 43 view .LVU435 + 1391 00d2 B26D ldr r2, [r6, #88] + 1392 00d4 5A60 str r2, [r3, #4] + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1393 .loc 1 745 7 is_stmt 1 view .LVU436 + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1394 .loc 1 745 23 is_stmt 0 view .LVU437 + 1395 00d6 F26B ldr r2, [r6, #60] + 1396 00d8 8023 movs r3, #128 + 1397 00da DB00 lsls r3, r3, #3 + 1398 00dc 1343 orrs r3, r2 + 1399 00de F363 str r3, [r6, #60] + 1400 .L70: + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1401 .loc 1 750 3 is_stmt 1 view .LVU438 + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1402 .loc 1 750 12 is_stmt 0 view .LVU439 + 1403 00e0 B36C ldr r3, [r6, #72] + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1404 .loc 1 750 33 view .LVU440 + 1405 00e2 1968 ldr r1, [r3] + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1406 .loc 1 750 45 view .LVU441 + 1407 00e4 F26C ldr r2, [r6, #76] + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1408 .loc 1 750 6 view .LVU442 + 1409 00e6 0A42 tst r2, r1 + 1410 00e8 05D0 beq .L71 + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1411 .loc 1 753 5 is_stmt 1 view .LVU443 + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1412 .loc 1 753 36 is_stmt 0 view .LVU444 + 1413 00ea 5A60 str r2, [r3, #4] + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1414 .loc 1 756 5 is_stmt 1 view .LVU445 + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1415 .loc 1 756 21 is_stmt 0 view .LVU446 + 1416 00ec F26B ldr r2, [r6, #60] + 1417 00ee 8023 movs r3, #128 + 1418 00f0 9B00 lsls r3, r3, #2 + 1419 00f2 1343 orrs r3, r2 + 1420 00f4 F363 str r3, [r6, #60] + 1421 .L71: + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1422 .loc 1 759 3 is_stmt 1 view .LVU447 + ARM GAS /tmp/ccdBjPSF.s page 53 + + + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1423 .loc 1 759 6 is_stmt 0 view .LVU448 + 1424 00f6 002C cmp r4, #0 + 1425 00f8 10D1 bne .L72 + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1426 .loc 1 765 5 is_stmt 1 view .LVU449 + 1427 00fa 0E48 ldr r0, .L76 + 1428 00fc 4368 ldr r3, [r0, #4] + 1429 00fe 1C21 movs r1, #28 + 1430 0100 326C ldr r2, [r6, #64] + 1431 0102 1140 ands r1, r2 + 1432 0104 0222 movs r2, #2 + 1433 0106 8A40 lsls r2, r2, r1 + 1434 0108 1343 orrs r3, r2 + 1435 010a 4360 str r3, [r0, #4] + 1436 .LVL87: + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1437 .loc 1 769 5 view .LVU450 + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1438 .loc 1 769 5 view .LVU451 + 1439 010c 2423 movs r3, #36 + 1440 010e 0022 movs r2, #0 + 1441 0110 F254 strb r2, [r6, r3] + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1442 .loc 1 769 5 view .LVU452 + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1443 .loc 1 773 5 view .LVU453 + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1444 .loc 1 773 17 is_stmt 0 view .LVU454 + 1445 0112 0133 adds r3, r3, #1 + 1446 0114 0132 adds r2, r2, #1 + 1447 0116 F254 strb r2, [r6, r3] + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1448 .loc 1 785 10 view .LVU455 + 1449 0118 2000 movs r0, r4 + 1450 011a 80E7 b .L61 + 1451 .LVL88: + 1452 .L72: + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1453 .loc 1 781 5 is_stmt 1 view .LVU456 + 1454 011c 0548 ldr r0, .L76 + 1455 011e 4368 ldr r3, [r0, #4] + 1456 0120 326C ldr r2, [r6, #64] + 1457 0122 1C21 movs r1, #28 + 1458 0124 1140 ands r1, r2 + 1459 0126 0422 movs r2, #4 + 1460 0128 8A40 lsls r2, r2, r1 + 1461 012a 1343 orrs r3, r2 + 1462 012c 4360 str r3, [r0, #4] + 1463 .LVL89: + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1464 .loc 1 785 10 is_stmt 0 view .LVU457 + 1465 012e 0020 movs r0, #0 + 1466 0130 75E7 b .L61 + 1467 .L77: + 1468 0132 C046 .align 2 + 1469 .L76: + ARM GAS /tmp/ccdBjPSF.s page 54 + + + 1470 0134 00000240 .word 1073872896 + 1471 .cfi_endproc + 1472 .LFE303: + 1474 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 1475 .align 1 + 1476 .global HAL_DMA_IRQHandler + 1477 .syntax unified + 1478 .code 16 + 1479 .thumb_func + 1480 .fpu softvfp + 1482 HAL_DMA_IRQHandler: + 1483 .LVL90: + 1484 .LFB304: + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 1485 .loc 1 795 1 is_stmt 1 view -0 + 1486 .cfi_startproc + 1487 @ args = 0, pretend = 0, frame = 0 + 1488 @ frame_needed = 0, uses_anonymous_args = 0 + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #if defined(DMA2) + 1489 .loc 1 795 1 is_stmt 0 view .LVU459 + 1490 0000 70B5 push {r4, r5, r6, lr} + 1491 .LCFI10: + 1492 .cfi_def_cfa_offset 16 + 1493 .cfi_offset 4, -16 + 1494 .cfi_offset 5, -12 + 1495 .cfi_offset 6, -8 + 1496 .cfi_offset 14, -4 + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1497 .loc 1 799 3 is_stmt 1 view .LVU460 + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1498 .loc 1 799 12 is_stmt 0 view .LVU461 + 1499 0002 314B ldr r3, .L84 + 1500 0004 1968 ldr r1, [r3] + 1501 .LVL91: + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1502 .loc 1 801 3 is_stmt 1 view .LVU462 + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1503 .loc 1 801 28 is_stmt 0 view .LVU463 + 1504 0006 0468 ldr r4, [r0] + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1505 .loc 1 801 12 view .LVU464 + 1506 0008 2568 ldr r5, [r4] + 1507 .LVL92: + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1508 .loc 1 804 3 is_stmt 1 view .LVU465 + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1509 .loc 1 804 56 is_stmt 0 view .LVU466 + 1510 000a 1C23 movs r3, #28 + 1511 000c 026C ldr r2, [r0, #64] + 1512 000e 1340 ands r3, r2 + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1513 .loc 1 804 33 view .LVU467 + 1514 0010 0422 movs r2, #4 + 1515 0012 9A40 lsls r2, r2, r3 + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1516 .loc 1 804 6 view .LVU468 + 1517 0014 1142 tst r1, r2 + ARM GAS /tmp/ccdBjPSF.s page 55 + + + 1518 0016 16D0 beq .L79 + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1519 .loc 1 804 74 discriminator 1 view .LVU469 + 1520 0018 6A07 lsls r2, r5, #29 + 1521 001a 14D5 bpl .L79 + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1522 .loc 1 807 7 is_stmt 1 view .LVU470 + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1523 .loc 1 807 26 is_stmt 0 view .LVU471 + 1524 001c 2368 ldr r3, [r4] + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1525 .loc 1 807 10 view .LVU472 + 1526 001e 9B06 lsls r3, r3, #26 + 1527 0020 03D4 bmi .L80 + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1528 .loc 1 810 9 is_stmt 1 view .LVU473 + 1529 0022 2368 ldr r3, [r4] + 1530 0024 0422 movs r2, #4 + 1531 0026 9343 bics r3, r2 + 1532 0028 2360 str r3, [r4] + 1533 .L80: + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1534 .loc 1 816 7 view .LVU474 + 1535 002a 274C ldr r4, .L84 + 1536 002c 6368 ldr r3, [r4, #4] + 1537 002e 1C21 movs r1, #28 + 1538 .LVL93: + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1539 .loc 1 816 7 is_stmt 0 view .LVU475 + 1540 0030 026C ldr r2, [r0, #64] + 1541 0032 1140 ands r1, r2 + 1542 0034 0422 movs r2, #4 + 1543 0036 8A40 lsls r2, r2, r1 + 1544 0038 1343 orrs r3, r2 + 1545 003a 6360 str r3, [r4, #4] + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1546 .loc 1 822 7 is_stmt 1 view .LVU476 + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1547 .loc 1 822 15 is_stmt 0 view .LVU477 + 1548 003c 036B ldr r3, [r0, #48] + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1549 .loc 1 822 10 view .LVU478 + 1550 003e 002B cmp r3, #0 + 1551 0040 00D0 beq .L78 + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1552 .loc 1 825 9 is_stmt 1 view .LVU479 + 1553 0042 9847 blx r3 + 1554 .LVL94: + 1555 .L78: + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1556 .loc 1 888 1 is_stmt 0 view .LVU480 + 1557 @ sp needed + 1558 0044 70BD pop {r4, r5, r6, pc} + 1559 .LVL95: + 1560 .L79: + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1561 .loc 1 830 8 is_stmt 1 view .LVU481 + ARM GAS /tmp/ccdBjPSF.s page 56 + + + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1562 .loc 1 830 44 is_stmt 0 view .LVU482 + 1563 0046 0222 movs r2, #2 + 1564 0048 9A40 lsls r2, r2, r3 + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1565 .loc 1 830 11 view .LVU483 + 1566 004a 1142 tst r1, r2 + 1567 004c 1CD0 beq .L82 + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1568 .loc 1 830 79 discriminator 1 view .LVU484 + 1569 004e AA07 lsls r2, r5, #30 + 1570 0050 1AD5 bpl .L82 + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1571 .loc 1 832 7 is_stmt 1 view .LVU485 + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1572 .loc 1 832 26 is_stmt 0 view .LVU486 + 1573 0052 2368 ldr r3, [r4] + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1574 .loc 1 832 10 view .LVU487 + 1575 0054 9B06 lsls r3, r3, #26 + 1576 0056 06D4 bmi .L83 + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1577 .loc 1 835 9 is_stmt 1 view .LVU488 + 1578 0058 2368 ldr r3, [r4] + 1579 005a 0A22 movs r2, #10 + 1580 005c 9343 bics r3, r2 + 1581 005e 2360 str r3, [r4] + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1582 .loc 1 838 9 view .LVU489 + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1583 .loc 1 838 21 is_stmt 0 view .LVU490 + 1584 0060 2523 movs r3, #37 + 1585 0062 093A subs r2, r2, #9 + 1586 0064 C254 strb r2, [r0, r3] + 1587 .L83: + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1588 .loc 1 841 7 is_stmt 1 view .LVU491 + 1589 0066 184C ldr r4, .L84 + 1590 0068 6368 ldr r3, [r4, #4] + 1591 006a 1C21 movs r1, #28 + 1592 .LVL96: + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1593 .loc 1 841 7 is_stmt 0 view .LVU492 + 1594 006c 026C ldr r2, [r0, #64] + 1595 006e 1140 ands r1, r2 + 1596 0070 0222 movs r2, #2 + 1597 0072 8A40 lsls r2, r2, r1 + 1598 0074 1343 orrs r3, r2 + 1599 0076 6360 str r3, [r4, #4] + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1600 .loc 1 844 7 is_stmt 1 view .LVU493 + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1601 .loc 1 844 7 view .LVU494 + 1602 0078 2423 movs r3, #36 + 1603 007a 0022 movs r2, #0 + 1604 007c C254 strb r2, [r0, r3] + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 57 + + + 1605 .loc 1 844 7 view .LVU495 + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1606 .loc 1 846 7 view .LVU496 + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1607 .loc 1 846 15 is_stmt 0 view .LVU497 + 1608 007e C36A ldr r3, [r0, #44] + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1609 .loc 1 846 10 view .LVU498 + 1610 0080 002B cmp r3, #0 + 1611 0082 DFD0 beq .L78 + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1612 .loc 1 849 9 is_stmt 1 view .LVU499 + 1613 0084 9847 blx r3 + 1614 .LVL97: + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1615 .loc 1 849 9 is_stmt 0 view .LVU500 + 1616 0086 DDE7 b .L78 + 1617 .LVL98: + 1618 .L82: + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1619 .loc 1 854 8 is_stmt 1 view .LVU501 + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1620 .loc 1 854 38 is_stmt 0 view .LVU502 + 1621 0088 0822 movs r2, #8 + 1622 008a 9A40 lsls r2, r2, r3 + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1623 .loc 1 854 11 view .LVU503 + 1624 008c 1142 tst r1, r2 + 1625 008e D9D0 beq .L78 + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1626 .loc 1 854 79 discriminator 1 view .LVU504 + 1627 0090 2B07 lsls r3, r5, #28 + 1628 0092 D7D5 bpl .L78 + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1629 .loc 1 859 5 is_stmt 1 view .LVU505 + 1630 0094 2368 ldr r3, [r4] + 1631 0096 0E22 movs r2, #14 + 1632 0098 9343 bics r3, r2 + 1633 009a 2360 str r3, [r4] + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1634 .loc 1 865 5 view .LVU506 + 1635 009c 0A4C ldr r4, .L84 + 1636 009e 6268 ldr r2, [r4, #4] + 1637 00a0 1C21 movs r1, #28 + 1638 .LVL99: + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1639 .loc 1 865 5 is_stmt 0 view .LVU507 + 1640 00a2 036C ldr r3, [r0, #64] + 1641 00a4 1940 ands r1, r3 + 1642 00a6 0123 movs r3, #1 + 1643 00a8 1D00 movs r5, r3 + 1644 .LVL100: + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** #endif /* DMA2 */ + 1645 .loc 1 865 5 view .LVU508 + 1646 00aa 8D40 lsls r5, r5, r1 + 1647 00ac 2A43 orrs r2, r5 + 1648 00ae 6260 str r2, [r4, #4] + ARM GAS /tmp/ccdBjPSF.s page 58 + + + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1649 .loc 1 869 5 is_stmt 1 view .LVU509 + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1650 .loc 1 869 21 is_stmt 0 view .LVU510 + 1651 00b0 C363 str r3, [r0, #60] + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1652 .loc 1 872 5 is_stmt 1 view .LVU511 + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1653 .loc 1 872 17 is_stmt 0 view .LVU512 + 1654 00b2 2522 movs r2, #37 + 1655 00b4 8354 strb r3, [r0, r2] + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1656 .loc 1 875 5 is_stmt 1 view .LVU513 + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1657 .loc 1 875 5 view .LVU514 + 1658 00b6 2333 adds r3, r3, #35 + 1659 00b8 0022 movs r2, #0 + 1660 00ba C254 strb r2, [r0, r3] + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1661 .loc 1 875 5 view .LVU515 + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1662 .loc 1 877 5 view .LVU516 + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1663 .loc 1 877 13 is_stmt 0 view .LVU517 + 1664 00bc 436B ldr r3, [r0, #52] + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1665 .loc 1 877 8 view .LVU518 + 1666 00be 002B cmp r3, #0 + 1667 00c0 C0D0 beq .L78 + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1668 .loc 1 880 7 is_stmt 1 view .LVU519 + 1669 00c2 9847 blx r3 + 1670 .LVL101: + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** return; + 1671 .loc 1 886 3 view .LVU520 + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1672 .loc 1 887 3 view .LVU521 + 1673 00c4 BEE7 b .L78 + 1674 .L85: + 1675 00c6 C046 .align 2 + 1676 .L84: + 1677 00c8 00000240 .word 1073872896 + 1678 .cfi_endproc + 1679 .LFE304: + 1681 .section .text.HAL_DMA_RegisterCallback,"ax",%progbits + 1682 .align 1 + 1683 .global HAL_DMA_RegisterCallback + 1684 .syntax unified + 1685 .code 16 + 1686 .thumb_func + 1687 .fpu softvfp + 1689 HAL_DMA_RegisterCallback: + 1690 .LVL102: + 1691 .LFB305: + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1692 .loc 1 901 1 view -0 + 1693 .cfi_startproc + ARM GAS /tmp/ccdBjPSF.s page 59 + + + 1694 @ args = 0, pretend = 0, frame = 0 + 1695 @ frame_needed = 0, uses_anonymous_args = 0 + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1696 .loc 1 901 1 is_stmt 0 view .LVU523 + 1697 0000 10B5 push {r4, lr} + 1698 .LCFI11: + 1699 .cfi_def_cfa_offset 8 + 1700 .cfi_offset 4, -8 + 1701 .cfi_offset 14, -4 + 1702 0002 0300 movs r3, r0 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1703 .loc 1 902 3 is_stmt 1 view .LVU524 + 1704 .LVL103: + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1705 .loc 1 905 3 view .LVU525 + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1706 .loc 1 905 3 view .LVU526 + 1707 0004 2420 movs r0, #36 + 1708 .LVL104: + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1709 .loc 1 905 3 is_stmt 0 view .LVU527 + 1710 0006 185C ldrb r0, [r3, r0] + 1711 0008 0128 cmp r0, #1 + 1712 000a 21D0 beq .L94 + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1713 .loc 1 905 3 is_stmt 1 discriminator 2 view .LVU528 + 1714 000c 2420 movs r0, #36 + 1715 000e 0124 movs r4, #1 + 1716 0010 1C54 strb r4, [r3, r0] + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1717 .loc 1 905 3 discriminator 2 view .LVU529 + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1718 .loc 1 907 3 discriminator 2 view .LVU530 + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1719 .loc 1 907 11 is_stmt 0 discriminator 2 view .LVU531 + 1720 0012 0130 adds r0, r0, #1 + 1721 0014 1C5C ldrb r4, [r3, r0] + 1722 0016 E0B2 uxtb r0, r4 + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1723 .loc 1 907 6 discriminator 2 view .LVU532 + 1724 0018 012C cmp r4, #1 + 1725 001a 04D0 beq .L96 + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1726 .loc 1 934 12 view .LVU533 + 1727 001c 0120 movs r0, #1 + 1728 .L88: + 1729 .LVL105: + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1730 .loc 1 938 3 is_stmt 1 view .LVU534 + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1731 .loc 1 938 3 view .LVU535 + 1732 001e 2422 movs r2, #36 + 1733 .LVL106: + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1734 .loc 1 938 3 is_stmt 0 view .LVU536 + 1735 0020 0021 movs r1, #0 + 1736 .LVL107: + ARM GAS /tmp/ccdBjPSF.s page 60 + + + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1737 .loc 1 938 3 view .LVU537 + 1738 0022 9954 strb r1, [r3, r2] + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1739 .loc 1 938 3 is_stmt 1 view .LVU538 + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1740 .loc 1 940 3 view .LVU539 + 1741 .LVL108: + 1742 .L87: + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1743 .loc 1 941 1 is_stmt 0 view .LVU540 + 1744 @ sp needed + 1745 0024 10BD pop {r4, pc} + 1746 .LVL109: + 1747 .L96: + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1748 .loc 1 909 5 is_stmt 1 view .LVU541 + 1749 0026 0229 cmp r1, #2 + 1750 0028 0FD0 beq .L89 + 1751 002a 06D8 bhi .L90 + 1752 002c 0029 cmp r1, #0 + 1753 002e 09D0 beq .L91 + 1754 0030 0129 cmp r1, #1 + 1755 0032 F4D1 bne .L88 + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1756 .loc 1 916 9 view .LVU542 + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1757 .loc 1 916 36 is_stmt 0 view .LVU543 + 1758 0034 1A63 str r2, [r3, #48] + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1759 .loc 1 917 9 is_stmt 1 view .LVU544 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1760 .loc 1 902 21 is_stmt 0 view .LVU545 + 1761 0036 0020 movs r0, #0 + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1762 .loc 1 917 9 view .LVU546 + 1763 0038 F1E7 b .L88 + 1764 .L90: + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1765 .loc 1 909 5 view .LVU547 + 1766 003a 0329 cmp r1, #3 + 1767 003c EFD1 bne .L88 + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1768 .loc 1 924 9 is_stmt 1 view .LVU548 + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1769 .loc 1 924 33 is_stmt 0 view .LVU549 + 1770 003e 9A63 str r2, [r3, #56] + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1771 .loc 1 925 9 is_stmt 1 view .LVU550 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1772 .loc 1 902 21 is_stmt 0 view .LVU551 + 1773 0040 0020 movs r0, #0 + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1774 .loc 1 925 9 view .LVU552 + 1775 0042 ECE7 b .L88 + 1776 .L91: + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + ARM GAS /tmp/ccdBjPSF.s page 61 + + + 1777 .loc 1 912 9 is_stmt 1 view .LVU553 + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1778 .loc 1 912 32 is_stmt 0 view .LVU554 + 1779 0044 DA62 str r2, [r3, #44] + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1780 .loc 1 913 9 is_stmt 1 view .LVU555 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1781 .loc 1 902 21 is_stmt 0 view .LVU556 + 1782 0046 0800 movs r0, r1 + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1783 .loc 1 913 9 view .LVU557 + 1784 0048 E9E7 b .L88 + 1785 .L89: + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1786 .loc 1 920 9 is_stmt 1 view .LVU558 + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1787 .loc 1 920 33 is_stmt 0 view .LVU559 + 1788 004a 5A63 str r2, [r3, #52] + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1789 .loc 1 921 9 is_stmt 1 view .LVU560 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1790 .loc 1 902 21 is_stmt 0 view .LVU561 + 1791 004c 0020 movs r0, #0 + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1792 .loc 1 921 9 view .LVU562 + 1793 004e E6E7 b .L88 + 1794 .L94: + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1795 .loc 1 905 3 view .LVU563 + 1796 0050 0220 movs r0, #2 + 1797 0052 E7E7 b .L87 + 1798 .cfi_endproc + 1799 .LFE305: + 1801 .section .text.HAL_DMA_UnRegisterCallback,"ax",%progbits + 1802 .align 1 + 1803 .global HAL_DMA_UnRegisterCallback + 1804 .syntax unified + 1805 .code 16 + 1806 .thumb_func + 1807 .fpu softvfp + 1809 HAL_DMA_UnRegisterCallback: + 1810 .LVL110: + 1811 .LFB306: + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1812 .loc 1 952 1 is_stmt 1 view -0 + 1813 .cfi_startproc + 1814 @ args = 0, pretend = 0, frame = 0 + 1815 @ frame_needed = 0, uses_anonymous_args = 0 + 1816 @ link register save eliminated. + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1817 .loc 1 952 1 is_stmt 0 view .LVU565 + 1818 0000 0300 movs r3, r0 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1819 .loc 1 953 3 is_stmt 1 view .LVU566 + 1820 .LVL111: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1821 .loc 1 956 3 view .LVU567 + ARM GAS /tmp/ccdBjPSF.s page 62 + + + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1822 .loc 1 956 3 view .LVU568 + 1823 0002 2422 movs r2, #36 + 1824 0004 825C ldrb r2, [r0, r2] + 1825 0006 012A cmp r2, #1 + 1826 0008 29D0 beq .L106 + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1827 .loc 1 956 3 discriminator 2 view .LVU569 + 1828 000a 2422 movs r2, #36 + 1829 000c 0120 movs r0, #1 + 1830 .LVL112: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1831 .loc 1 956 3 is_stmt 0 discriminator 2 view .LVU570 + 1832 000e 9854 strb r0, [r3, r2] + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1833 .loc 1 956 3 is_stmt 1 discriminator 2 view .LVU571 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1834 .loc 1 958 3 discriminator 2 view .LVU572 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1835 .loc 1 958 11 is_stmt 0 discriminator 2 view .LVU573 + 1836 0010 0132 adds r2, r2, #1 + 1837 0012 9A5C ldrb r2, [r3, r2] + 1838 0014 D0B2 uxtb r0, r2 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1839 .loc 1 958 6 discriminator 2 view .LVU574 + 1840 0016 012A cmp r2, #1 + 1841 0018 04D0 beq .L108 + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1842 .loc 1 992 12 view .LVU575 + 1843 001a 0120 movs r0, #1 + 1844 .L99: + 1845 .LVL113: + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1846 .loc 1 996 3 is_stmt 1 view .LVU576 + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1847 .loc 1 996 3 view .LVU577 + 1848 001c 2422 movs r2, #36 + 1849 001e 0021 movs r1, #0 + 1850 .LVL114: + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1851 .loc 1 996 3 is_stmt 0 view .LVU578 + 1852 0020 9954 strb r1, [r3, r2] + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1853 .loc 1 996 3 is_stmt 1 view .LVU579 + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1854 .loc 1 998 3 view .LVU580 + 1855 .LVL115: + 1856 .L98: + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1857 .loc 1 999 1 is_stmt 0 view .LVU581 + 1858 @ sp needed + 1859 0022 7047 bx lr + 1860 .LVL116: + 1861 .L108: + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** { + 1862 .loc 1 960 5 is_stmt 1 view .LVU582 + 1863 0024 0429 cmp r1, #4 + ARM GAS /tmp/ccdBjPSF.s page 63 + + + 1864 0026 F9D8 bhi .L99 + 1865 0028 8A00 lsls r2, r1, #2 + 1866 002a 0E48 ldr r0, .L109 + 1867 002c 8258 ldr r2, [r0, r2] + 1868 002e 9746 mov pc, r2 + 1869 .section .rodata.HAL_DMA_UnRegisterCallback,"a",%progbits + 1870 .align 2 + 1871 .L101: + 1872 0000 30000000 .word .L105 + 1873 0004 38000000 .word .L104 + 1874 0008 40000000 .word .L103 + 1875 000c 48000000 .word .L102 + 1876 0010 50000000 .word .L100 + 1877 .section .text.HAL_DMA_UnRegisterCallback + 1878 .L105: + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1879 .loc 1 963 9 view .LVU583 + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1880 .loc 1 963 32 is_stmt 0 view .LVU584 + 1881 0030 0022 movs r2, #0 + 1882 0032 DA62 str r2, [r3, #44] + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1883 .loc 1 964 9 is_stmt 1 view .LVU585 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1884 .loc 1 953 21 is_stmt 0 view .LVU586 + 1885 0034 0800 movs r0, r1 + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1886 .loc 1 964 9 view .LVU587 + 1887 0036 F1E7 b .L99 + 1888 .L104: + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1889 .loc 1 967 9 is_stmt 1 view .LVU588 + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1890 .loc 1 967 36 is_stmt 0 view .LVU589 + 1891 0038 0022 movs r2, #0 + 1892 003a 1A63 str r2, [r3, #48] + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1893 .loc 1 968 9 is_stmt 1 view .LVU590 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1894 .loc 1 953 21 is_stmt 0 view .LVU591 + 1895 003c 0020 movs r0, #0 + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1896 .loc 1 968 9 view .LVU592 + 1897 003e EDE7 b .L99 + 1898 .L103: + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1899 .loc 1 971 9 is_stmt 1 view .LVU593 + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1900 .loc 1 971 33 is_stmt 0 view .LVU594 + 1901 0040 0022 movs r2, #0 + 1902 0042 5A63 str r2, [r3, #52] + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1903 .loc 1 972 9 is_stmt 1 view .LVU595 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1904 .loc 1 953 21 is_stmt 0 view .LVU596 + 1905 0044 0020 movs r0, #0 + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + ARM GAS /tmp/ccdBjPSF.s page 64 + + + 1906 .loc 1 972 9 view .LVU597 + 1907 0046 E9E7 b .L99 + 1908 .L102: + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1909 .loc 1 975 9 is_stmt 1 view .LVU598 + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1910 .loc 1 975 33 is_stmt 0 view .LVU599 + 1911 0048 0022 movs r2, #0 + 1912 004a 9A63 str r2, [r3, #56] + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1913 .loc 1 976 9 is_stmt 1 view .LVU600 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1914 .loc 1 953 21 is_stmt 0 view .LVU601 + 1915 004c 0020 movs r0, #0 + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1916 .loc 1 976 9 view .LVU602 + 1917 004e E5E7 b .L99 + 1918 .L100: + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1919 .loc 1 979 9 is_stmt 1 view .LVU603 + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1920 .loc 1 979 32 is_stmt 0 view .LVU604 + 1921 0050 0022 movs r2, #0 + 1922 0052 DA62 str r2, [r3, #44] + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1923 .loc 1 980 9 is_stmt 1 view .LVU605 + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1924 .loc 1 980 36 is_stmt 0 view .LVU606 + 1925 0054 1A63 str r2, [r3, #48] + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1926 .loc 1 981 9 is_stmt 1 view .LVU607 + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1927 .loc 1 981 33 is_stmt 0 view .LVU608 + 1928 0056 5A63 str r2, [r3, #52] + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1929 .loc 1 982 9 is_stmt 1 view .LVU609 + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** break; + 1930 .loc 1 982 33 is_stmt 0 view .LVU610 + 1931 0058 9A63 str r2, [r3, #56] + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1932 .loc 1 983 9 is_stmt 1 view .LVU611 + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1933 .loc 1 953 21 is_stmt 0 view .LVU612 + 1934 005a 0020 movs r0, #0 + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1935 .loc 1 983 9 view .LVU613 + 1936 005c DEE7 b .L99 + 1937 .LVL117: + 1938 .L106: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1939 .loc 1 956 3 view .LVU614 + 1940 005e 0220 movs r0, #2 + 1941 .LVL118: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1942 .loc 1 956 3 view .LVU615 + 1943 0060 DFE7 b .L98 + 1944 .L110: + ARM GAS /tmp/ccdBjPSF.s page 65 + + + 1945 0062 C046 .align 2 + 1946 .L109: + 1947 0064 00000000 .word .L101 + 1948 .cfi_endproc + 1949 .LFE306: + 1951 .section .text.HAL_DMA_GetState,"ax",%progbits + 1952 .align 1 + 1953 .global HAL_DMA_GetState + 1954 .syntax unified + 1955 .code 16 + 1956 .thumb_func + 1957 .fpu softvfp + 1959 HAL_DMA_GetState: + 1960 .LVL119: + 1961 .LFB307: +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return DMA handle state */ + 1962 .loc 1 1030 1 is_stmt 1 view -0 + 1963 .cfi_startproc + 1964 @ args = 0, pretend = 0, frame = 0 + 1965 @ frame_needed = 0, uses_anonymous_args = 0 + 1966 @ link register save eliminated. +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1967 .loc 1 1032 3 view .LVU617 +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1968 .loc 1 1032 14 is_stmt 0 view .LVU618 + 1969 0000 2523 movs r3, #37 + 1970 0002 C05C ldrb r0, [r0, r3] + 1971 .LVL120: +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1972 .loc 1 1032 14 view .LVU619 + 1973 0004 C0B2 uxtb r0, r0 +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 1974 .loc 1 1033 1 view .LVU620 + 1975 @ sp needed + 1976 0006 7047 bx lr + 1977 .cfi_endproc + 1978 .LFE307: + 1980 .section .text.HAL_DMA_GetError,"ax",%progbits + 1981 .align 1 + 1982 .global HAL_DMA_GetError + 1983 .syntax unified + 1984 .code 16 + 1985 .thumb_func + 1986 .fpu softvfp + 1988 HAL_DMA_GetError: + 1989 .LVL121: + 1990 .LFB308: +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** /* Return the DMA error code */ + 1991 .loc 1 1042 1 is_stmt 1 view -0 + 1992 .cfi_startproc + 1993 @ args = 0, pretend = 0, frame = 0 + 1994 @ frame_needed = 0, uses_anonymous_args = 0 + 1995 @ link register save eliminated. +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1996 .loc 1 1044 3 view .LVU622 +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** } + 1997 .loc 1 1044 14 is_stmt 0 view .LVU623 + ARM GAS /tmp/ccdBjPSF.s page 66 + + + 1998 0000 C06B ldr r0, [r0, #60] + 1999 .LVL122: +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c **** + 2000 .loc 1 1045 1 view .LVU624 + 2001 @ sp needed + 2002 0002 7047 bx lr + 2003 .cfi_endproc + 2004 .LFE308: + 2006 .text + 2007 .Letext0: + 2008 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 2009 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 2010 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 2011 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 2012 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 2013 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + ARM GAS /tmp/ccdBjPSF.s page 67 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_dma.c + /tmp/ccdBjPSF.s:16 .text.DMA_SetConfig:0000000000000000 $t + /tmp/ccdBjPSF.s:23 .text.DMA_SetConfig:0000000000000000 DMA_SetConfig + /tmp/ccdBjPSF.s:112 .text.DMA_SetConfig:0000000000000044 $d + /tmp/ccdBjPSF.s:118 .text.DMA_CalcDMAMUXChannelBaseAndMask:0000000000000000 $t + /tmp/ccdBjPSF.s:124 .text.DMA_CalcDMAMUXChannelBaseAndMask:0000000000000000 DMA_CalcDMAMUXChannelBaseAndMask + /tmp/ccdBjPSF.s:185 .text.DMA_CalcDMAMUXChannelBaseAndMask:0000000000000030 $d + /tmp/ccdBjPSF.s:191 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000000 $t + /tmp/ccdBjPSF.s:197 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000000 DMA_CalcDMAMUXRequestGenBaseAndMask + /tmp/ccdBjPSF.s:242 .text.DMA_CalcDMAMUXRequestGenBaseAndMask:0000000000000020 $d + /tmp/ccdBjPSF.s:248 .text.HAL_DMA_Init:0000000000000000 $t + /tmp/ccdBjPSF.s:255 .text.HAL_DMA_Init:0000000000000000 HAL_DMA_Init + /tmp/ccdBjPSF.s:429 .text.HAL_DMA_Init:00000000000000a8 $d + /tmp/ccdBjPSF.s:435 .text.HAL_DMA_DeInit:0000000000000000 $t + /tmp/ccdBjPSF.s:442 .text.HAL_DMA_DeInit:0000000000000000 HAL_DMA_DeInit + /tmp/ccdBjPSF.s:593 .text.HAL_DMA_DeInit:0000000000000084 $d + /tmp/ccdBjPSF.s:599 .text.HAL_DMA_Start:0000000000000000 $t + /tmp/ccdBjPSF.s:606 .text.HAL_DMA_Start:0000000000000000 HAL_DMA_Start + /tmp/ccdBjPSF.s:708 .text.HAL_DMA_Start_IT:0000000000000000 $t + /tmp/ccdBjPSF.s:715 .text.HAL_DMA_Start_IT:0000000000000000 HAL_DMA_Start_IT + /tmp/ccdBjPSF.s:874 .text.HAL_DMA_Abort:0000000000000000 $t + /tmp/ccdBjPSF.s:881 .text.HAL_DMA_Abort:0000000000000000 HAL_DMA_Abort + /tmp/ccdBjPSF.s:1007 .text.HAL_DMA_Abort:0000000000000078 $d + /tmp/ccdBjPSF.s:1013 .text.HAL_DMA_Abort_IT:0000000000000000 $t + /tmp/ccdBjPSF.s:1020 .text.HAL_DMA_Abort_IT:0000000000000000 HAL_DMA_Abort_IT + /tmp/ccdBjPSF.s:1147 .text.HAL_DMA_Abort_IT:0000000000000078 $d + /tmp/ccdBjPSF.s:1153 .text.HAL_DMA_PollForTransfer:0000000000000000 $t + /tmp/ccdBjPSF.s:1160 .text.HAL_DMA_PollForTransfer:0000000000000000 HAL_DMA_PollForTransfer + /tmp/ccdBjPSF.s:1470 .text.HAL_DMA_PollForTransfer:0000000000000134 $d + /tmp/ccdBjPSF.s:1475 .text.HAL_DMA_IRQHandler:0000000000000000 $t + /tmp/ccdBjPSF.s:1482 .text.HAL_DMA_IRQHandler:0000000000000000 HAL_DMA_IRQHandler + /tmp/ccdBjPSF.s:1677 .text.HAL_DMA_IRQHandler:00000000000000c8 $d + /tmp/ccdBjPSF.s:1682 .text.HAL_DMA_RegisterCallback:0000000000000000 $t + /tmp/ccdBjPSF.s:1689 .text.HAL_DMA_RegisterCallback:0000000000000000 HAL_DMA_RegisterCallback + /tmp/ccdBjPSF.s:1802 .text.HAL_DMA_UnRegisterCallback:0000000000000000 $t + /tmp/ccdBjPSF.s:1809 .text.HAL_DMA_UnRegisterCallback:0000000000000000 HAL_DMA_UnRegisterCallback + /tmp/ccdBjPSF.s:1870 .rodata.HAL_DMA_UnRegisterCallback:0000000000000000 $d + /tmp/ccdBjPSF.s:1947 .text.HAL_DMA_UnRegisterCallback:0000000000000064 $d + /tmp/ccdBjPSF.s:1952 .text.HAL_DMA_GetState:0000000000000000 $t + /tmp/ccdBjPSF.s:1959 .text.HAL_DMA_GetState:0000000000000000 HAL_DMA_GetState + /tmp/ccdBjPSF.s:1981 .text.HAL_DMA_GetError:0000000000000000 $t + /tmp/ccdBjPSF.s:1988 .text.HAL_DMA_GetError:0000000000000000 HAL_DMA_GetError + +UNDEFINED SYMBOLS +__aeabi_uidiv +HAL_GetTick diff --git a/squero/build/stm32g0xx_hal_dma.o b/squero/build/stm32g0xx_hal_dma.o new file mode 100644 index 0000000000000000000000000000000000000000..9c8d102e818390ce2c62d319b42b8fd4234f321f GIT binary patch literal 23056 zcmc(Hdwf*Yx%S$#XHPOo3?T^+LV!sofgmtR00l8X!h}nJKuAIb!6socFwx1Sxgf0~ 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© Copyright (c) 2018 STMicroelectronics. + ARM GAS /tmp/ccF3B3hr.s page 2 + + + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * All rights reserved.
+ 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the "License"; You may not use this file except in compliance with the + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * License. You may obtain a copy of the License at: + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * opensource.org/licenses/BSD-3-Clause + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ****************************************************************************** + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Includes ------------------------------------------------------------------*/ + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** #include "stm32g0xx_hal.h" + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @{ + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** @defgroup DMAEx DMAEx + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief DMA Extended HAL module driver + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @{ + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** #ifdef HAL_DMA_MODULE_ENABLED + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private define ------------------------------------------------------------*/ + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private macro -------------------------------------------------------------*/ + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private variables ---------------------------------------------------------*/ + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private Constants ---------------------------------------------------------*/ + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Exported functions --------------------------------------------------------*/ + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @{ + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Extended features functions + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** @verbatim + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** =============================================================================== + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ##### Extended features functions ##### + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** =============================================================================== + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** [..] This section provides functions allowing to: + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator func + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can t + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** to respectively enable/disable the request generator. + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** the DMAMUX IRQ handler + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** @endverbatim + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @{ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + ARM GAS /tmp/ccF3B3hr.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the configuration information for the specified DMA channel. + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @retval HAL status + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pS + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 28 .loc 1 97 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 97 1 is_stmt 0 view .LVU1 + 33 0000 70B5 push {r4, r5, r6, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 16 + 36 .cfi_offset 4, -16 + 37 .cfi_offset 5, -12 + 38 .cfi_offset 6, -8 + 39 .cfi_offset 14, -4 + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Check the parameters */ + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 40 .loc 1 99 3 is_stmt 1 view .LVU2 + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + 41 .loc 1 101 3 view .LVU3 + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + 42 .loc 1 103 3 view .LVU4 + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + 43 .loc 1 104 3 view .LVU5 + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + 44 .loc 1 105 3 view .LVU6 + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + 45 .loc 1 106 3 view .LVU7 + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /*Check if the DMA state is ready */ + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if (hdma->State == HAL_DMA_STATE_READY) + 46 .loc 1 109 3 view .LVU8 + 47 .loc 1 109 11 is_stmt 0 view .LVU9 + 48 0002 2523 movs r3, #37 + 49 0004 C35C ldrb r3, [r0, r3] + 50 .loc 1 109 6 view .LVU10 + 51 0006 012B cmp r3, #1 + 52 0008 1DD1 bne .L2 + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Process Locked */ + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + 53 .loc 1 112 5 is_stmt 1 view .LVU11 + 54 .loc 1 112 5 view .LVU12 + 55 000a 2333 adds r3, r3, #35 + 56 000c C35C ldrb r3, [r0, r3] + 57 000e 012B cmp r3, #1 + 58 0010 1DD0 beq .L4 + 59 .loc 1 112 5 discriminator 2 view .LVU13 + 60 0012 2424 movs r4, #36 + ARM GAS /tmp/ccF3B3hr.s page 4 + + + 61 0014 0123 movs r3, #1 + 62 0016 0355 strb r3, [r0, r4] + 63 .loc 1 112 5 discriminator 2 view .LVU14 + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** MODIFY_REG(hdma->DMAmuxChannel->CCR, \ + 64 .loc 1 115 5 discriminator 2 view .LVU15 + 65 0018 456C ldr r5, [r0, #68] + 66 001a 2B68 ldr r3, [r5] + 67 001c 3F22 movs r2, #63 + 68 001e 1A40 ands r2, r3 + 69 0020 CB68 ldr r3, [r1, #12] + 70 0022 013B subs r3, r3, #1 + 71 0024 DB04 lsls r3, r3, #19 + 72 0026 0E68 ldr r6, [r1] + 73 0028 3343 orrs r3, r6 + 74 002a 4E68 ldr r6, [r1, #4] + 75 002c 3343 orrs r3, r6 + 76 002e 0E7A ldrb r6, [r1, #8] + 77 0030 3604 lsls r6, r6, #16 + 78 0032 3343 orrs r3, r6 + 79 0034 497A ldrb r1, [r1, #9] + 80 .LVL1: + 81 .loc 1 115 5 is_stmt 0 discriminator 2 view .LVU16 + 82 0036 4902 lsls r1, r1, #9 + 83 0038 0B43 orrs r3, r1 + 84 003a 1343 orrs r3, r2 + 85 003c 2B60 str r3, [r5] + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** (~DMAMUX_CxCR_DMAREQ_ID), \ + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Po + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos))); + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Process UnLocked */ + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** __HAL_UNLOCK(hdma); + 86 .loc 1 122 5 is_stmt 1 discriminator 2 view .LVU17 + 87 .loc 1 122 5 discriminator 2 view .LVU18 + 88 003e 0023 movs r3, #0 + 89 0040 0355 strb r3, [r0, r4] + 90 .loc 1 122 5 discriminator 2 view .LVU19 + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_OK; + 91 .loc 1 124 5 discriminator 2 view .LVU20 + 92 .loc 1 124 12 is_stmt 0 discriminator 2 view .LVU21 + 93 0042 0020 movs r0, #0 + 94 .LVL2: + 95 .loc 1 124 12 discriminator 2 view .LVU22 + 96 0044 02E0 b .L3 + 97 .LVL3: + 98 .L2: + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** else + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Set the error code to busy */ + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 99 .loc 1 129 5 is_stmt 1 view .LVU23 + 100 .loc 1 129 21 is_stmt 0 view .LVU24 + ARM GAS /tmp/ccF3B3hr.s page 5 + + + 101 0046 8023 movs r3, #128 + 102 0048 C363 str r3, [r0, #60] + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Return error status */ + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_ERROR; + 103 .loc 1 132 5 is_stmt 1 view .LVU25 + 104 .loc 1 132 12 is_stmt 0 view .LVU26 + 105 004a 0120 movs r0, #1 + 106 .LVL4: + 107 .L3: + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 108 .loc 1 134 1 view .LVU27 + 109 @ sp needed + 110 004c 70BD pop {r4, r5, r6, pc} + 111 .LVL5: + 112 .L4: + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 113 .loc 1 112 5 view .LVU28 + 114 004e 0220 movs r0, #2 + 115 .LVL6: + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 116 .loc 1 112 5 view .LVU29 + 117 0050 FCE7 b .L3 + 118 .cfi_endproc + 119 .LFE297: + 121 .section .text.HAL_DMAEx_ConfigMuxRequestGenerator,"ax",%progbits + 122 .align 1 + 123 .global HAL_DMAEx_ConfigMuxRequestGenerator + 124 .syntax unified + 125 .code 16 + 126 .thumb_func + 127 .fpu softvfp + 129 HAL_DMAEx_ConfigMuxRequestGenerator: + 130 .LVL7: + 131 .LFB298: + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the configuration information for the specified DMA channel. + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * contains the request generator parameters. + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @retval HAL status + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGe + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 132 .loc 1 146 1 is_stmt 1 view -0 + 133 .cfi_startproc + 134 @ args = 0, pretend = 0, frame = 0 + 135 @ frame_needed = 0, uses_anonymous_args = 0 + 136 .loc 1 146 1 is_stmt 0 view .LVU31 + 137 0000 30B5 push {r4, r5, lr} + 138 .LCFI1: + 139 .cfi_def_cfa_offset 12 + 140 .cfi_offset 4, -12 + ARM GAS /tmp/ccF3B3hr.s page 6 + + + 141 .cfi_offset 5, -8 + 142 .cfi_offset 14, -4 + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_StatusTypeDef status; + 143 .loc 1 147 3 is_stmt 1 view .LVU32 + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_DMA_StateTypeDef temp_state = hdma->State; + 144 .loc 1 148 3 view .LVU33 + 145 .loc 1 148 24 is_stmt 0 view .LVU34 + 146 0002 2523 movs r3, #37 + 147 0004 C35C ldrb r3, [r0, r3] + 148 0006 DBB2 uxtb r3, r3 + 149 .LVL8: + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Check the parameters */ + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 150 .loc 1 151 3 is_stmt 1 view .LVU35 + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + 151 .loc 1 153 3 view .LVU36 + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + 152 .loc 1 155 3 view .LVU37 + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + 153 .loc 1 156 3 view .LVU38 + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* check if the DMA state is ready + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if (hdma->DMAmuxRequestGen == 0U) + 154 .loc 1 161 3 view .LVU39 + 155 .loc 1 161 11 is_stmt 0 view .LVU40 + 156 0008 026D ldr r2, [r0, #80] + 157 .loc 1 161 6 view .LVU41 + 158 000a 002A cmp r2, #0 + 159 000c 08D0 beq .L10 + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Set the error code to busy */ + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* error status */ + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** status = HAL_ERROR; + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE + 160 .loc 1 169 8 is_stmt 1 view .LVU42 + 161 .loc 1 169 36 is_stmt 0 view .LVU43 + 162 000e 1468 ldr r4, [r2] + 163 .loc 1 169 11 view .LVU44 + 164 0010 E403 lsls r4, r4, #15 + 165 0012 01D4 bmi .L8 + 166 .loc 1 169 69 discriminator 1 view .LVU45 + 167 0014 012B cmp r3, #1 + 168 0016 07D0 beq .L11 + 169 .L8: + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Process Locked */ + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** __HAL_LOCK(hdma); + ARM GAS /tmp/ccF3B3hr.s page 7 + + + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Set the request generator new parameters*/ + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_G + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Process UnLocked */ + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** __HAL_UNLOCK(hdma); + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_OK; + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** else + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Set the error code to busy */ + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 170 .loc 1 188 5 is_stmt 1 view .LVU46 + 171 .loc 1 188 21 is_stmt 0 view .LVU47 + 172 0018 8023 movs r3, #128 + 173 .LVL9: + 174 .loc 1 188 21 view .LVU48 + 175 001a C363 str r3, [r0, #60] + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* error status */ + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** status = HAL_ERROR; + 176 .loc 1 191 5 is_stmt 1 view .LVU49 + 177 .LVL10: + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return status; + 178 .loc 1 194 10 is_stmt 0 view .LVU50 + 179 001c 0120 movs r0, #1 + 180 .LVL11: + 181 .L7: + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 182 .loc 1 195 1 view .LVU51 + 183 @ sp needed + 184 001e 30BD pop {r4, r5, pc} + 185 .LVL12: + 186 .L10: + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 187 .loc 1 164 5 is_stmt 1 view .LVU52 + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 188 .loc 1 164 21 is_stmt 0 view .LVU53 + 189 0020 4023 movs r3, #64 + 190 .LVL13: + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 191 .loc 1 164 21 view .LVU54 + 192 0022 C363 str r3, [r0, #60] + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 193 .loc 1 167 5 is_stmt 1 view .LVU55 + 194 .LVL14: + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 195 .loc 1 194 10 is_stmt 0 view .LVU56 + 196 0024 0120 movs r0, #1 + 197 .LVL15: + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 198 .loc 1 194 10 view .LVU57 + 199 0026 FAE7 b .L7 + ARM GAS /tmp/ccF3B3hr.s page 8 + + + 200 .LVL16: + 201 .L11: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 202 .loc 1 174 5 is_stmt 1 view .LVU58 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 203 .loc 1 174 5 view .LVU59 + 204 0028 2333 adds r3, r3, #35 + 205 .LVL17: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 206 .loc 1 174 5 is_stmt 0 view .LVU60 + 207 002a C35C ldrb r3, [r0, r3] + 208 .LVL18: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 209 .loc 1 174 5 view .LVU61 + 210 002c 012B cmp r3, #1 + 211 002e 0ED0 beq .L9 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 212 .loc 1 174 5 is_stmt 1 discriminator 2 view .LVU62 + 213 0030 2424 movs r4, #36 + 214 0032 0123 movs r3, #1 + 215 0034 0355 strb r3, [r0, r4] + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 216 .loc 1 174 5 discriminator 2 view .LVU63 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_G + 217 .loc 1 177 5 discriminator 2 view .LVU64 + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 218 .loc 1 178 77 is_stmt 0 discriminator 2 view .LVU65 + 219 0036 8B68 ldr r3, [r1, #8] + 220 0038 013B subs r3, r3, #1 + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 221 .loc 1 178 83 discriminator 2 view .LVU66 + 222 003a DB04 lsls r3, r3, #19 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_G + 223 .loc 1 177 70 discriminator 2 view .LVU67 + 224 003c 0D68 ldr r5, [r1] + 225 003e 2B43 orrs r3, r5 + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Process UnLocked */ + 226 .loc 1 179 59 discriminator 2 view .LVU68 + 227 0040 4968 ldr r1, [r1, #4] + 228 .LVL19: + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** pRequestGeneratorConfig->Polarity; + 229 .loc 1 178 111 discriminator 2 view .LVU69 + 230 0042 0B43 orrs r3, r1 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_G + 231 .loc 1 177 34 discriminator 2 view .LVU70 + 232 0044 1360 str r3, [r2] + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 233 .loc 1 181 5 is_stmt 1 discriminator 2 view .LVU71 + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 234 .loc 1 181 5 discriminator 2 view .LVU72 + 235 0046 0023 movs r3, #0 + 236 0048 0355 strb r3, [r0, r4] + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 237 .loc 1 181 5 discriminator 2 view .LVU73 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 238 .loc 1 183 5 discriminator 2 view .LVU74 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + ARM GAS /tmp/ccF3B3hr.s page 9 + + + 239 .loc 1 183 12 is_stmt 0 discriminator 2 view .LVU75 + 240 004a 0020 movs r0, #0 + 241 .LVL20: + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 242 .loc 1 183 12 discriminator 2 view .LVU76 + 243 004c E7E7 b .L7 + 244 .LVL21: + 245 .L9: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 246 .loc 1 174 5 view .LVU77 + 247 004e 0220 movs r0, #2 + 248 .LVL22: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 249 .loc 1 174 5 view .LVU78 + 250 0050 E5E7 b .L7 + 251 .cfi_endproc + 252 .LFE298: + 254 .section .text.HAL_DMAEx_EnableMuxRequestGenerator,"ax",%progbits + 255 .align 1 + 256 .global HAL_DMAEx_EnableMuxRequestGenerator + 257 .syntax unified + 258 .code 16 + 259 .thumb_func + 260 .fpu softvfp + 262 HAL_DMAEx_EnableMuxRequestGenerator: + 263 .LVL23: + 264 .LFB299: + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the configuration information for the specified DMA channel. + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @retval HAL status + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 265 .loc 1 204 1 is_stmt 1 view -0 + 266 .cfi_startproc + 267 @ args = 0, pretend = 0, frame = 0 + 268 @ frame_needed = 0, uses_anonymous_args = 0 + 269 @ link register save eliminated. + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Check the parameters */ + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 270 .loc 1 206 3 view .LVU80 + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* check if the DMA state is ready + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + 271 .loc 1 211 3 view .LVU81 + 272 .loc 1 211 12 is_stmt 0 view .LVU82 + 273 0000 2523 movs r3, #37 + 274 0002 C35C ldrb r3, [r0, r3] + 275 .loc 1 211 6 view .LVU83 + 276 0004 002B cmp r3, #0 + 277 0006 09D0 beq .L14 + 278 .loc 1 211 52 discriminator 1 view .LVU84 + ARM GAS /tmp/ccF3B3hr.s page 10 + + + 279 0008 036D ldr r3, [r0, #80] + 280 .loc 1 211 44 discriminator 1 view .LVU85 + 281 000a 002B cmp r3, #0 + 282 000c 08D0 beq .L15 + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Enable the request generator*/ + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + 283 .loc 1 215 5 is_stmt 1 view .LVU86 + 284 .loc 1 215 34 is_stmt 0 view .LVU87 + 285 000e 1968 ldr r1, [r3] + 286 0010 8022 movs r2, #128 + 287 0012 5202 lsls r2, r2, #9 + 288 0014 0A43 orrs r2, r1 + 289 0016 1A60 str r2, [r3] + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_OK; + 290 .loc 1 217 5 is_stmt 1 view .LVU88 + 291 .loc 1 217 12 is_stmt 0 view .LVU89 + 292 0018 0020 movs r0, #0 + 293 .LVL24: + 294 .L13: + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** else + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_ERROR; + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 295 .loc 1 223 1 view .LVU90 + 296 @ sp needed + 297 001a 7047 bx lr + 298 .LVL25: + 299 .L14: + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 300 .loc 1 221 12 view .LVU91 + 301 001c 0120 movs r0, #1 + 302 .LVL26: + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 303 .loc 1 221 12 view .LVU92 + 304 001e FCE7 b .L13 + 305 .LVL27: + 306 .L15: + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 307 .loc 1 221 12 view .LVU93 + 308 0020 0120 movs r0, #1 + 309 .LVL28: + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 310 .loc 1 221 12 view .LVU94 + 311 0022 FAE7 b .L13 + 312 .cfi_endproc + 313 .LFE299: + 315 .section .text.HAL_DMAEx_DisableMuxRequestGenerator,"ax",%progbits + 316 .align 1 + 317 .global HAL_DMAEx_DisableMuxRequestGenerator + 318 .syntax unified + 319 .code 16 + 320 .thumb_func + ARM GAS /tmp/ccF3B3hr.s page 11 + + + 321 .fpu softvfp + 323 HAL_DMAEx_DisableMuxRequestGenerator: + 324 .LVL29: + 325 .LFB300: + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the configuration information for the specified DMA channel. + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @retval HAL status + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 326 .loc 1 232 1 is_stmt 1 view -0 + 327 .cfi_startproc + 328 @ args = 0, pretend = 0, frame = 0 + 329 @ frame_needed = 0, uses_anonymous_args = 0 + 330 @ link register save eliminated. + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Check the parameters */ + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 331 .loc 1 234 3 view .LVU96 + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* check if the DMA state is ready + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** and DMA is using a DMAMUX request generator block + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + 332 .loc 1 239 3 view .LVU97 + 333 .loc 1 239 12 is_stmt 0 view .LVU98 + 334 0000 2523 movs r3, #37 + 335 0002 C35C ldrb r3, [r0, r3] + 336 .loc 1 239 6 view .LVU99 + 337 0004 002B cmp r3, #0 + 338 0006 08D0 beq .L18 + 339 .loc 1 239 52 discriminator 1 view .LVU100 + 340 0008 036D ldr r3, [r0, #80] + 341 .loc 1 239 44 discriminator 1 view .LVU101 + 342 000a 002B cmp r3, #0 + 343 000c 07D0 beq .L19 + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Disable the request generator*/ + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + 344 .loc 1 243 5 is_stmt 1 view .LVU102 + 345 .loc 1 243 34 is_stmt 0 view .LVU103 + 346 000e 1A68 ldr r2, [r3] + 347 0010 0449 ldr r1, .L20 + 348 0012 0A40 ands r2, r1 + 349 0014 1A60 str r2, [r3] + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_OK; + 350 .loc 1 245 5 is_stmt 1 view .LVU104 + 351 .loc 1 245 12 is_stmt 0 view .LVU105 + 352 0016 0020 movs r0, #0 + 353 .LVL30: + 354 .L17: + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** else + ARM GAS /tmp/ccF3B3hr.s page 12 + + + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** return HAL_ERROR; + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 355 .loc 1 251 1 view .LVU106 + 356 @ sp needed + 357 0018 7047 bx lr + 358 .LVL31: + 359 .L18: + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 360 .loc 1 249 12 view .LVU107 + 361 001a 0120 movs r0, #1 + 362 .LVL32: + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 363 .loc 1 249 12 view .LVU108 + 364 001c FCE7 b .L17 + 365 .LVL33: + 366 .L19: + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 367 .loc 1 249 12 view .LVU109 + 368 001e 0120 movs r0, #1 + 369 .LVL34: + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 370 .loc 1 249 12 view .LVU110 + 371 0020 FAE7 b .L17 + 372 .L21: + 373 0022 C046 .align 2 + 374 .L20: + 375 0024 FFFFFEFF .word -65537 + 376 .cfi_endproc + 377 .LFE300: + 379 .section .text.HAL_DMAEx_MUX_IRQHandler,"ax",%progbits + 380 .align 1 + 381 .global HAL_DMAEx_MUX_IRQHandler + 382 .syntax unified + 383 .code 16 + 384 .thumb_func + 385 .fpu softvfp + 387 HAL_DMAEx_MUX_IRQHandler: + 388 .LVL35: + 389 .LFB301: + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /** + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @brief Handles DMAMUX interrupt request. + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * the configuration information for the specified DMA channel. + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** * @retval None + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** */ + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 390 .loc 1 260 1 is_stmt 1 view -0 + 391 .cfi_startproc + 392 @ args = 0, pretend = 0, frame = 0 + 393 @ frame_needed = 0, uses_anonymous_args = 0 + 394 .loc 1 260 1 is_stmt 0 view .LVU112 + 395 0000 10B5 push {r4, lr} + 396 .LCFI2: + ARM GAS /tmp/ccF3B3hr.s page 13 + + + 397 .cfi_def_cfa_offset 8 + 398 .cfi_offset 4, -8 + 399 .cfi_offset 14, -4 + 400 0002 0400 movs r4, r0 + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Check for DMAMUX Synchronization overrun */ + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + 401 .loc 1 262 3 is_stmt 1 view .LVU113 + 402 .loc 1 262 12 is_stmt 0 view .LVU114 + 403 0004 836C ldr r3, [r0, #72] + 404 .loc 1 262 33 view .LVU115 + 405 0006 1B68 ldr r3, [r3] + 406 .loc 1 262 6 view .LVU116 + 407 0008 C26C ldr r2, [r0, #76] + 408 000a 1A42 tst r2, r3 + 409 000c 10D0 beq .L23 + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Disable the synchro overrun interrupt */ + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 410 .loc 1 265 5 is_stmt 1 view .LVU117 + 411 .loc 1 265 9 is_stmt 0 view .LVU118 + 412 000e 426C ldr r2, [r0, #68] + 413 .loc 1 265 30 view .LVU119 + 414 0010 1368 ldr r3, [r2] + 415 0012 1449 ldr r1, .L25 + 416 0014 0B40 ands r3, r1 + 417 0016 1360 str r3, [r2] + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Clear the DMAMUX synchro overrun flag */ + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 418 .loc 1 268 5 is_stmt 1 view .LVU120 + 419 .loc 1 268 9 is_stmt 0 view .LVU121 + 420 0018 836C ldr r3, [r0, #72] + 421 .loc 1 268 36 view .LVU122 + 422 001a C26C ldr r2, [r0, #76] + 423 001c 5A60 str r2, [r3, #4] + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Update error code */ + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + 424 .loc 1 271 5 is_stmt 1 view .LVU123 + 425 .loc 1 271 21 is_stmt 0 view .LVU124 + 426 001e C26B ldr r2, [r0, #60] + 427 0020 8023 movs r3, #128 + 428 0022 9B00 lsls r3, r3, #2 + 429 0024 1343 orrs r3, r2 + 430 0026 C363 str r3, [r0, #60] + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if (hdma->XferErrorCallback != NULL) + 431 .loc 1 273 5 is_stmt 1 view .LVU125 + 432 .loc 1 273 13 is_stmt 0 view .LVU126 + 433 0028 436B ldr r3, [r0, #52] + 434 .loc 1 273 8 view .LVU127 + 435 002a 002B cmp r3, #0 + 436 002c 00D0 beq .L23 + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Transfer error callback */ + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->XferErrorCallback(hdma); + 437 .loc 1 276 7 is_stmt 1 view .LVU128 + ARM GAS /tmp/ccF3B3hr.s page 14 + + + 438 002e 9847 blx r3 + 439 .LVL36: + 440 .L23: + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if (hdma->DMAmuxRequestGen != 0) + 441 .loc 1 280 3 view .LVU129 + 442 .loc 1 280 11 is_stmt 0 view .LVU130 + 443 0030 236D ldr r3, [r4, #80] + 444 .loc 1 280 6 view .LVU131 + 445 0032 002B cmp r3, #0 + 446 0034 15D0 beq .L22 + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + 447 .loc 1 283 5 is_stmt 1 view .LVU132 + 448 .loc 1 283 14 is_stmt 0 view .LVU133 + 449 0036 626D ldr r2, [r4, #84] + 450 .loc 1 283 38 view .LVU134 + 451 0038 1268 ldr r2, [r2] + 452 .loc 1 283 8 view .LVU135 + 453 003a A16D ldr r1, [r4, #88] + 454 003c 1142 tst r1, r2 + 455 003e 10D0 beq .L22 + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Disable the request gen overrun interrupt */ + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 456 .loc 1 286 7 is_stmt 1 view .LVU136 + 457 .loc 1 286 36 is_stmt 0 view .LVU137 + 458 0040 1A68 ldr r2, [r3] + 459 0042 0849 ldr r1, .L25 + 460 0044 0A40 ands r2, r1 + 461 0046 1A60 str r2, [r3] + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Clear the DMAMUX request generator overrun flag */ + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 462 .loc 1 289 7 is_stmt 1 view .LVU138 + 463 .loc 1 289 11 is_stmt 0 view .LVU139 + 464 0048 636D ldr r3, [r4, #84] + 465 .loc 1 289 43 view .LVU140 + 466 004a A26D ldr r2, [r4, #88] + 467 004c 5A60 str r2, [r3, #4] + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Update error code */ + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + 468 .loc 1 292 7 is_stmt 1 view .LVU141 + 469 .loc 1 292 23 is_stmt 0 view .LVU142 + 470 004e E26B ldr r2, [r4, #60] + 471 0050 8023 movs r3, #128 + 472 0052 DB00 lsls r3, r3, #3 + 473 0054 1343 orrs r3, r2 + 474 0056 E363 str r3, [r4, #60] + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** if (hdma->XferErrorCallback != NULL) + 475 .loc 1 294 7 is_stmt 1 view .LVU143 + 476 .loc 1 294 15 is_stmt 0 view .LVU144 + ARM GAS /tmp/ccF3B3hr.s page 15 + + + 477 0058 636B ldr r3, [r4, #52] + 478 .loc 1 294 10 view .LVU145 + 479 005a 002B cmp r3, #0 + 480 005c 01D0 beq .L22 + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** { + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** /* Transfer error callback */ + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** hdma->XferErrorCallback(hdma); + 481 .loc 1 297 9 is_stmt 1 view .LVU146 + 482 005e 2000 movs r0, r4 + 483 0060 9847 blx r3 + 484 .LVL37: + 485 .L22: + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c **** } + 486 .loc 1 301 1 is_stmt 0 view .LVU147 + 487 @ sp needed + 488 .LVL38: + 489 .loc 1 301 1 view .LVU148 + 490 0062 10BD pop {r4, pc} + 491 .L26: + 492 .align 2 + 493 .L25: + 494 0064 FFFEFFFF .word -257 + 495 .cfi_endproc + 496 .LFE301: + 498 .text + 499 .Letext0: + 500 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 501 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 502 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h" + 503 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 504 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 505 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h" + 506 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccF3B3hr.s page 16 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_dma_ex.c + /tmp/ccF3B3hr.s:16 .text.HAL_DMAEx_ConfigMuxSync:0000000000000000 $t + /tmp/ccF3B3hr.s:24 .text.HAL_DMAEx_ConfigMuxSync:0000000000000000 HAL_DMAEx_ConfigMuxSync + /tmp/ccF3B3hr.s:122 .text.HAL_DMAEx_ConfigMuxRequestGenerator:0000000000000000 $t + /tmp/ccF3B3hr.s:129 .text.HAL_DMAEx_ConfigMuxRequestGenerator:0000000000000000 HAL_DMAEx_ConfigMuxRequestGenerator + /tmp/ccF3B3hr.s:255 .text.HAL_DMAEx_EnableMuxRequestGenerator:0000000000000000 $t + /tmp/ccF3B3hr.s:262 .text.HAL_DMAEx_EnableMuxRequestGenerator:0000000000000000 HAL_DMAEx_EnableMuxRequestGenerator + /tmp/ccF3B3hr.s:316 .text.HAL_DMAEx_DisableMuxRequestGenerator:0000000000000000 $t + /tmp/ccF3B3hr.s:323 .text.HAL_DMAEx_DisableMuxRequestGenerator:0000000000000000 HAL_DMAEx_DisableMuxRequestGenerator + /tmp/ccF3B3hr.s:375 .text.HAL_DMAEx_DisableMuxRequestGenerator:0000000000000024 $d + /tmp/ccF3B3hr.s:380 .text.HAL_DMAEx_MUX_IRQHandler:0000000000000000 $t + /tmp/ccF3B3hr.s:387 .text.HAL_DMAEx_MUX_IRQHandler:0000000000000000 HAL_DMAEx_MUX_IRQHandler + /tmp/ccF3B3hr.s:494 .text.HAL_DMAEx_MUX_IRQHandler:0000000000000064 $d + +NO UNDEFINED SYMBOLS diff --git a/squero/build/stm32g0xx_hal_dma_ex.o b/squero/build/stm32g0xx_hal_dma_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..f67e2e21f9d68e6d5fe2494f2cbbcfb05d9588e3 GIT binary patch literal 10504 zcmb_idvILUeLi>Z-rc?0wUE6MmSqELOSVO1y^U=i#*$aEEhE{oWT)T)@@lp6ZrO*r zyE4Lw!92nQ0x6_~K$wXK(qN}n^E`HNno9vD5!c}{CgSR(2ba==UjE19a z2NXP2#PgG*&Ckb;$jq~z$onU|G~=89;K`_u1Wwc^-!hFK8g2d)j!)OKecJcElTLlL zQs1X^J&TfU(V--`h56)3Pvqw(*+SK3pD;73EpTF4^608DPffJxfQrm)H&CMyc~5)- z+Q)yQDd`=m>6`EI&26Vn{pnQQ6JB+5dU^7>bko+l6I;{aWc^UEFMQzU^mFO`2cEm; zX!8Rq9DP0>y+*aE6ZdUzMx6~OCNoQt4`vplL{l=Lnd6yb~uD&!U=BhkZ(Ubez4$9hOp|c2lX1?#NW2$M9W_LGpO4yP)-WtuIjuSa$-<5c3_4 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© Copyright (c) 2018 STMicroelectronics. + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * All rights reserved.
+ 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * This software component is licensed by ST under BSD 3-Clause license, + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * the "License"; You may not use this file except in compliance with the + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * License. You may obtain a copy of the License at: + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * opensource.org/licenses/BSD-3-Clause + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** ****************************************************************************** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** #include "stm32g0xx_hal.h" + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + ARM GAS /tmp/ccRj6lr2.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @addtogroup STM32G0xx_HAL_Driver + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @addtogroup EXTI + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** MISRA C:2012 deviation rule has been granted for following rule: + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * of bounds [0,3] in following API : + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * HAL_EXTI_SetConfigLine + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * HAL_EXTI_GetConfigLine + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * HAL_EXTI_ClearConfigLine + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/ + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Private defines ------------------------------------------------------------*/ + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** #define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers * + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** #define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling conf + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @} + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/ + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/ + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/ + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1 + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Configuration functions + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** @verbatim + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** =============================================================================== + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** ##### Configuration functions ##### + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** =============================================================================== + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** @endverbatim + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Set configuration of a dedicated Exti line. + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param pExtiConfig Pointer on EXTI configuration to be set. + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval HAL Status. + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + ARM GAS /tmp/ccRj6lr2.s page 4 + + + 28 .loc 1 145 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 145 1 is_stmt 0 view .LVU1 + 33 0000 F0B5 push {r4, r5, r6, r7, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 20 + 36 .cfi_offset 4, -20 + 37 .cfi_offset 5, -16 + 38 .cfi_offset 6, -12 + 39 .cfi_offset 7, -8 + 40 .cfi_offset 14, -4 + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 41 .loc 1 146 3 is_stmt 1 view .LVU2 + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t regval; + 42 .loc 1 147 3 view .LVU3 + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t linepos; + 43 .loc 1 148 3 view .LVU4 + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 44 .loc 1 149 3 view .LVU5 + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 45 .loc 1 150 3 view .LVU6 + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check null pointer */ + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 46 .loc 1 153 3 view .LVU7 + 47 .loc 1 153 6 is_stmt 0 view .LVU8 + 48 0002 0028 cmp r0, #0 + 49 0004 52D0 beq .L12 + 50 .loc 1 153 23 discriminator 1 view .LVU9 + 51 0006 0029 cmp r1, #0 + 52 0008 52D0 beq .L13 + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_ERROR; + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check parameters */ + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + 53 .loc 1 159 3 is_stmt 1 view .LVU10 + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + 54 .loc 1 160 3 view .LVU11 + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Assign line number to handle */ + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->Line = pExtiConfig->Line; + 55 .loc 1 163 3 view .LVU12 + 56 .loc 1 163 28 is_stmt 0 view .LVU13 + 57 000a 0D68 ldr r5, [r1] + 58 .loc 1 163 15 view .LVU14 + 59 000c 0560 str r5, [r0] + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 60 .loc 1 166 3 is_stmt 1 view .LVU15 + 61 .loc 1 166 49 is_stmt 0 view .LVU16 + 62 000e 2B0C lsrs r3, r5, #16 + 63 .loc 1 166 10 view .LVU17 + ARM GAS /tmp/ccRj6lr2.s page 5 + + + 64 0010 0122 movs r2, #1 + 65 0012 1340 ands r3, r2 + 66 .LVL1: + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 67 .loc 1 167 3 is_stmt 1 view .LVU18 + 68 .loc 1 167 11 is_stmt 0 view .LVU19 + 69 0014 1F20 movs r0, #31 + 70 .LVL2: + 71 .loc 1 167 11 view .LVU20 + 72 0016 2840 ands r0, r5 + 73 .LVL3: + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << linepos); + 74 .loc 1 168 3 is_stmt 1 view .LVU21 + 75 .loc 1 168 12 is_stmt 0 view .LVU22 + 76 0018 8240 lsls r2, r2, r0 + 77 .LVL4: + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure triggers for configurable lines */ + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 78 .loc 1 171 3 is_stmt 1 view .LVU23 + 79 .loc 1 171 6 is_stmt 0 view .LVU24 + 80 001a AC01 lsls r4, r5, #6 + 81 001c 19D5 bpl .L3 + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + 82 .loc 1 173 5 is_stmt 1 view .LVU25 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure rising trigger */ + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 83 .loc 1 176 5 view .LVU26 + 84 .loc 1 176 29 is_stmt 0 view .LVU27 + 85 001e 5C01 lsls r4, r3, #5 + 86 .loc 1 176 13 view .LVU28 + 87 0020 244E ldr r6, .L15 + 88 0022 A719 adds r7, r4, r6 + 89 .LVL5: + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 90 .loc 1 177 5 is_stmt 1 view .LVU29 + 91 .loc 1 177 12 is_stmt 0 view .LVU30 + 92 0024 3E68 ldr r6, [r7] + 93 0026 B446 mov ip, r6 + 94 .LVL6: + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Mask or set line */ + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + 95 .loc 1 180 5 is_stmt 1 view .LVU31 + 96 .loc 1 180 8 is_stmt 0 view .LVU32 + 97 0028 8E68 ldr r6, [r1, #8] + 98 .LVL7: + 99 .loc 1 180 8 view .LVU33 + 100 002a F607 lsls r6, r6, #31 + 101 002c 25D5 bpl .L4 + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= maskline; + 102 .loc 1 182 7 is_stmt 1 view .LVU34 + 103 .loc 1 182 14 is_stmt 0 view .LVU35 + 104 002e 6646 mov r6, ip + ARM GAS /tmp/ccRj6lr2.s page 6 + + + 105 0030 1643 orrs r6, r2 + 106 .LVL8: + 107 .L5: + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~maskline; + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store rising trigger mode */ + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 108 .loc 1 190 5 is_stmt 1 view .LVU36 + 109 .loc 1 190 14 is_stmt 0 view .LVU37 + 110 0032 3E60 str r6, [r7] + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure falling trigger */ + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 111 .loc 1 193 5 is_stmt 1 view .LVU38 + 112 .loc 1 193 13 is_stmt 0 view .LVU39 + 113 0034 204E ldr r6, .L15+4 + 114 .LVL9: + 115 .loc 1 193 13 view .LVU40 + 116 0036 B446 mov ip, r6 + 117 0038 6444 add r4, r4, ip + 118 .LVL10: + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 119 .loc 1 194 5 is_stmt 1 view .LVU41 + 120 .loc 1 194 12 is_stmt 0 view .LVU42 + 121 003a 2668 ldr r6, [r4] + 122 .LVL11: + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Mask or set line */ + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + 123 .loc 1 197 5 is_stmt 1 view .LVU43 + 124 .loc 1 197 8 is_stmt 0 view .LVU44 + 125 003c 8F68 ldr r7, [r1, #8] + 126 003e BF07 lsls r7, r7, #30 + 127 0040 1ED5 bpl .L6 + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= maskline; + 128 .loc 1 199 7 is_stmt 1 view .LVU45 + 129 .loc 1 199 14 is_stmt 0 view .LVU46 + 130 0042 1643 orrs r6, r2 + 131 .LVL12: + 132 .L7: + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~maskline; + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store falling trigger mode */ + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 133 .loc 1 207 5 is_stmt 1 view .LVU47 + 134 .loc 1 207 14 is_stmt 0 view .LVU48 + 135 0044 2660 str r6, [r4] + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + ARM GAS /tmp/ccRj6lr2.s page 7 + + + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure gpio port selection in case of gpio exti line */ + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 136 .loc 1 210 5 is_stmt 1 view .LVU49 + 137 .loc 1 210 28 is_stmt 0 view .LVU50 + 138 0046 C026 movs r6, #192 + 139 .LVL13: + 140 .loc 1 210 28 view .LVU51 + 141 0048 F604 lsls r6, r6, #19 + 142 004a 0C68 ldr r4, [r1] + 143 .LVL14: + 144 .loc 1 210 28 view .LVU52 + 145 004c 3440 ands r4, r6 + 146 .loc 1 210 8 view .LVU53 + 147 004e B442 cmp r4, r6 + 148 0050 18D0 beq .L14 + 149 .LVL15: + 150 .L3: + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = EXTI->EXTICR[linepos >> 2u]; + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure interrupt mode : read current mode */ + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 151 .loc 1 223 3 is_stmt 1 view .LVU54 + 152 .loc 1 223 26 is_stmt 0 view .LVU55 + 153 0052 1B01 lsls r3, r3, #4 + 154 .LVL16: + 155 .loc 1 223 11 view .LVU56 + 156 0054 1948 ldr r0, .L15+8 + 157 0056 1C18 adds r4, r3, r0 + 158 .LVL17: + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 159 .loc 1 224 3 is_stmt 1 view .LVU57 + 160 .loc 1 224 10 is_stmt 0 view .LVU58 + 161 0058 2068 ldr r0, [r4] + 162 .LVL18: + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Mask or set line */ + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + 163 .loc 1 227 3 is_stmt 1 view .LVU59 + 164 .loc 1 227 6 is_stmt 0 view .LVU60 + 165 005a 4D68 ldr r5, [r1, #4] + 166 005c ED07 lsls r5, r5, #31 + 167 005e 21D5 bpl .L8 + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= maskline; + 168 .loc 1 229 5 is_stmt 1 view .LVU61 + 169 .loc 1 229 12 is_stmt 0 view .LVU62 + 170 0060 1043 orrs r0, r2 + 171 .LVL19: + ARM GAS /tmp/ccRj6lr2.s page 8 + + + 172 .L9: + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~maskline; + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store interrupt mode */ + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 173 .loc 1 237 3 is_stmt 1 view .LVU63 + 174 .loc 1 237 12 is_stmt 0 view .LVU64 + 175 0062 2060 str r0, [r4] + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Configure event mode : read current mode */ + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 176 .loc 1 240 3 is_stmt 1 view .LVU65 + 177 .loc 1 240 11 is_stmt 0 view .LVU66 + 178 0064 1648 ldr r0, .L15+12 + 179 .LVL20: + 180 .loc 1 240 11 view .LVU67 + 181 0066 8446 mov ip, r0 + 182 0068 6344 add r3, r3, ip + 183 .LVL21: + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 184 .loc 1 241 3 is_stmt 1 view .LVU68 + 185 .loc 1 241 10 is_stmt 0 view .LVU69 + 186 006a 1868 ldr r0, [r3] + 187 .LVL22: + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Mask or set line */ + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + 188 .loc 1 244 3 is_stmt 1 view .LVU70 + 189 .loc 1 244 19 is_stmt 0 view .LVU71 + 190 006c 4968 ldr r1, [r1, #4] + 191 .LVL23: + 192 .loc 1 244 6 view .LVU72 + 193 006e 8907 lsls r1, r1, #30 + 194 0070 1AD5 bpl .L10 + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= maskline; + 195 .loc 1 246 5 is_stmt 1 view .LVU73 + 196 .loc 1 246 12 is_stmt 0 view .LVU74 + 197 0072 1043 orrs r0, r2 + 198 .LVL24: + 199 .L11: + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~maskline; + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store event mode */ + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 200 .loc 1 254 3 is_stmt 1 view .LVU75 + 201 .loc 1 254 12 is_stmt 0 view .LVU76 + 202 0074 1860 str r0, [r3] + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + ARM GAS /tmp/ccRj6lr2.s page 9 + + + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_OK; + 203 .loc 1 256 3 is_stmt 1 view .LVU77 + 204 .loc 1 256 10 is_stmt 0 view .LVU78 + 205 0076 0020 movs r0, #0 + 206 .LVL25: + 207 .L2: + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 208 .loc 1 257 1 view .LVU79 + 209 @ sp needed + 210 0078 F0BD pop {r4, r5, r6, r7, pc} + 211 .LVL26: + 212 .L4: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 213 .loc 1 186 7 is_stmt 1 view .LVU80 + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 214 .loc 1 186 14 is_stmt 0 view .LVU81 + 215 007a 6646 mov r6, ip + 216 007c 9643 bics r6, r2 + 217 .LVL27: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 218 .loc 1 186 14 view .LVU82 + 219 007e D8E7 b .L5 + 220 .LVL28: + 221 .L6: + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 222 .loc 1 203 7 is_stmt 1 view .LVU83 + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 223 .loc 1 203 14 is_stmt 0 view .LVU84 + 224 0080 9643 bics r6, r2 + 225 .LVL29: + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 226 .loc 1 203 14 view .LVU85 + 227 0082 DFE7 b .L7 + 228 .LVL30: + 229 .L14: + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 230 .loc 1 212 7 is_stmt 1 view .LVU86 + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 231 .loc 1 213 7 view .LVU87 + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 232 .loc 1 215 7 view .LVU88 + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 233 .loc 1 215 37 is_stmt 0 view .LVU89 + 234 0084 8008 lsrs r0, r0, #2 + 235 .LVL31: + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 236 .loc 1 215 14 view .LVU90 + 237 0086 0B4E ldr r6, .L15 + 238 0088 1830 adds r0, r0, #24 + 239 008a 8000 lsls r0, r0, #2 + 240 008c 8759 ldr r7, [r0, r6] + 241 .LVL32: + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 242 .loc 1 216 7 is_stmt 1 view .LVU91 + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 243 .loc 1 216 76 is_stmt 0 view .LVU92 + 244 008e 0324 movs r4, #3 + ARM GAS /tmp/ccRj6lr2.s page 10 + + + 245 0090 2540 ands r5, r4 + 246 .LVL33: + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 247 .loc 1 216 65 view .LVU93 + 248 0092 ED00 lsls r5, r5, #3 + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 249 .loc 1 216 38 view .LVU94 + 250 0094 0434 adds r4, r4, #4 + 251 0096 AC40 lsls r4, r4, r5 + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 252 .loc 1 216 14 view .LVU95 + 253 0098 A743 bics r7, r4 + 254 .LVL34: + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 255 .loc 1 217 7 is_stmt 1 view .LVU96 + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 256 .loc 1 217 39 is_stmt 0 view .LVU97 + 257 009a CC68 ldr r4, [r1, #12] + 258 009c AC40 lsls r4, r4, r5 + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 259 .loc 1 217 14 view .LVU98 + 260 009e 3C43 orrs r4, r7 + 261 .LVL35: + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 262 .loc 1 218 7 is_stmt 1 view .LVU99 + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 263 .loc 1 218 35 is_stmt 0 view .LVU100 + 264 00a0 8451 str r4, [r0, r6] + 265 00a2 D6E7 b .L3 + 266 .LVL36: + 267 .L8: + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 268 .loc 1 233 5 is_stmt 1 view .LVU101 + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 269 .loc 1 233 12 is_stmt 0 view .LVU102 + 270 00a4 9043 bics r0, r2 + 271 .LVL37: + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 272 .loc 1 233 12 view .LVU103 + 273 00a6 DCE7 b .L9 + 274 .LVL38: + 275 .L10: + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 276 .loc 1 250 5 is_stmt 1 view .LVU104 + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 277 .loc 1 250 12 is_stmt 0 view .LVU105 + 278 00a8 9043 bics r0, r2 + 279 .LVL39: + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 280 .loc 1 250 12 view .LVU106 + 281 00aa E3E7 b .L11 + 282 .LVL40: + 283 .L12: + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 284 .loc 1 155 12 view .LVU107 + 285 00ac 0120 movs r0, #1 + 286 .LVL41: + ARM GAS /tmp/ccRj6lr2.s page 11 + + + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 287 .loc 1 155 12 view .LVU108 + 288 00ae E3E7 b .L2 + 289 .LVL42: + 290 .L13: + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 291 .loc 1 155 12 view .LVU109 + 292 00b0 0120 movs r0, #1 + 293 .LVL43: + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 294 .loc 1 155 12 view .LVU110 + 295 00b2 E1E7 b .L2 + 296 .L16: + 297 .align 2 + 298 .L15: + 299 00b4 00180240 .word 1073879040 + 300 00b8 04180240 .word 1073879044 + 301 00bc 80180240 .word 1073879168 + 302 00c0 84180240 .word 1073879172 + 303 .cfi_endproc + 304 .LFE297: + 306 .section .text.HAL_EXTI_GetConfigLine,"ax",%progbits + 307 .align 1 + 308 .global HAL_EXTI_GetConfigLine + 309 .syntax unified + 310 .code 16 + 311 .thumb_func + 312 .fpu softvfp + 314 HAL_EXTI_GetConfigLine: + 315 .LVL44: + 316 .LFB298: + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Get configuration of a dedicated Exti line. + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param pExtiConfig Pointer on structure to store Exti configuration. + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval HAL Status. + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 317 .loc 1 267 1 is_stmt 1 view -0 + 318 .cfi_startproc + 319 @ args = 0, pretend = 0, frame = 0 + 320 @ frame_needed = 0, uses_anonymous_args = 0 + 321 .loc 1 267 1 is_stmt 0 view .LVU112 + 322 0000 70B5 push {r4, r5, r6, lr} + 323 .LCFI1: + 324 .cfi_def_cfa_offset 16 + 325 .cfi_offset 4, -16 + 326 .cfi_offset 5, -12 + 327 .cfi_offset 6, -8 + 328 .cfi_offset 14, -4 + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 329 .loc 1 268 3 is_stmt 1 view .LVU113 + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t regval; + 330 .loc 1 269 3 view .LVU114 + ARM GAS /tmp/ccRj6lr2.s page 12 + + + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t linepos; + 331 .loc 1 270 3 view .LVU115 + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 332 .loc 1 271 3 view .LVU116 + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 333 .loc 1 272 3 view .LVU117 + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check null pointer */ + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 334 .loc 1 275 3 view .LVU118 + 335 .loc 1 275 6 is_stmt 0 view .LVU119 + 336 0002 0028 cmp r0, #0 + 337 0004 49D0 beq .L24 + 338 .loc 1 275 23 discriminator 1 view .LVU120 + 339 0006 0029 cmp r1, #0 + 340 0008 49D0 beq .L25 + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_ERROR; + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check the parameter */ + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 341 .loc 1 281 3 is_stmt 1 view .LVU121 + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store handle line number to configiguration structure */ + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Line = hexti->Line; + 342 .loc 1 284 3 view .LVU122 + 343 .loc 1 284 28 is_stmt 0 view .LVU123 + 344 000a 0468 ldr r4, [r0] + 345 .loc 1 284 21 view .LVU124 + 346 000c 0C60 str r4, [r1] + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 347 .loc 1 287 3 is_stmt 1 view .LVU125 + 348 .loc 1 287 49 is_stmt 0 view .LVU126 + 349 000e 220C lsrs r2, r4, #16 + 350 .loc 1 287 10 view .LVU127 + 351 0010 0123 movs r3, #1 + 352 0012 1A40 ands r2, r3 + 353 .LVL45: + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 354 .loc 1 288 3 is_stmt 1 view .LVU128 + 355 .loc 1 288 11 is_stmt 0 view .LVU129 + 356 0014 1F25 movs r5, #31 + 357 0016 2540 ands r5, r4 + 358 .LVL46: + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << linepos); + 359 .loc 1 289 3 is_stmt 1 view .LVU130 + 360 .loc 1 289 12 is_stmt 0 view .LVU131 + 361 0018 AB40 lsls r3, r3, r5 + 362 .LVL47: + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* 1] Get core mode : interrupt */ + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 363 .loc 1 292 3 is_stmt 1 view .LVU132 + 364 .loc 1 292 26 is_stmt 0 view .LVU133 + ARM GAS /tmp/ccRj6lr2.s page 13 + + + 365 001a 1001 lsls r0, r2, #4 + 366 .LVL48: + 367 .loc 1 292 11 view .LVU134 + 368 001c 224E ldr r6, .L29 + 369 001e 8619 adds r6, r0, r6 + 370 .LVL49: + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 371 .loc 1 293 3 is_stmt 1 view .LVU135 + 372 .loc 1 293 10 is_stmt 0 view .LVU136 + 373 0020 3668 ldr r6, [r6] + 374 .LVL50: + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check if selected line is enable */ + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 375 .loc 1 296 3 is_stmt 1 view .LVU137 + 376 .loc 1 296 6 is_stmt 0 view .LVU138 + 377 0022 1E42 tst r6, r3 + 378 0024 29D0 beq .L19 + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + 379 .loc 1 298 5 is_stmt 1 view .LVU139 + 380 .loc 1 298 23 is_stmt 0 view .LVU140 + 381 0026 0126 movs r6, #1 + 382 .LVL51: + 383 .loc 1 298 23 view .LVU141 + 384 0028 4E60 str r6, [r1, #4] + 385 .L20: + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_NONE; + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get event mode */ + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 386 .loc 1 306 3 is_stmt 1 view .LVU142 + 387 .loc 1 306 11 is_stmt 0 view .LVU143 + 388 002a 204E ldr r6, .L29+4 + 389 002c B446 mov ip, r6 + 390 002e 6044 add r0, r0, ip + 391 .LVL52: + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 392 .loc 1 307 3 is_stmt 1 view .LVU144 + 393 .loc 1 307 10 is_stmt 0 view .LVU145 + 394 0030 0068 ldr r0, [r0] + 395 .LVL53: + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check if selected line is enable */ + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 396 .loc 1 310 3 is_stmt 1 view .LVU146 + 397 .loc 1 310 6 is_stmt 0 view .LVU147 + 398 0032 1842 tst r0, r3 + 399 0034 03D0 beq .L21 + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_EVENT; + 400 .loc 1 312 5 is_stmt 1 view .LVU148 + 401 .loc 1 312 23 is_stmt 0 view .LVU149 + ARM GAS /tmp/ccRj6lr2.s page 14 + + + 402 0036 0220 movs r0, #2 + 403 .LVL54: + 404 .loc 1 312 23 view .LVU150 + 405 0038 4E68 ldr r6, [r1, #4] + 406 .LVL55: + 407 .loc 1 312 23 view .LVU151 + 408 003a 3043 orrs r0, r6 + 409 003c 4860 str r0, [r1, #4] + 410 .L21: + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get default Trigger and GPIOSel configuration */ + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 411 .loc 1 316 3 is_stmt 1 view .LVU152 + 412 .loc 1 316 24 is_stmt 0 view .LVU153 + 413 003e 0020 movs r0, #0 + 414 0040 8860 str r0, [r1, #8] + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00u; + 415 .loc 1 317 3 is_stmt 1 view .LVU154 + 416 .loc 1 317 24 is_stmt 0 view .LVU155 + 417 0042 C860 str r0, [r1, #12] + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* 2] Get trigger for configurable lines : rising */ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 418 .loc 1 320 3 is_stmt 1 view .LVU156 + 419 .loc 1 320 6 is_stmt 0 view .LVU157 + 420 0044 A001 lsls r0, r4, #6 + 421 0046 2CD5 bpl .L26 + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 422 .loc 1 322 5 is_stmt 1 view .LVU158 + 423 .loc 1 322 29 is_stmt 0 view .LVU159 + 424 0048 5201 lsls r2, r2, #5 + 425 .LVL56: + 426 .loc 1 322 13 view .LVU160 + 427 004a 1948 ldr r0, .L29+8 + 428 004c 1018 adds r0, r2, r0 + 429 .LVL57: + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 430 .loc 1 323 5 is_stmt 1 view .LVU161 + 431 .loc 1 323 12 is_stmt 0 view .LVU162 + 432 004e 0068 ldr r0, [r0] + 433 .LVL58: + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 434 .loc 1 326 5 is_stmt 1 view .LVU163 + 435 .loc 1 326 8 is_stmt 0 view .LVU164 + 436 0050 1842 tst r0, r3 + 437 0052 01D0 beq .L22 + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + 438 .loc 1 328 7 is_stmt 1 view .LVU165 + 439 .loc 1 328 28 is_stmt 0 view .LVU166 + 440 0054 0120 movs r0, #1 + 441 .LVL59: + 442 .loc 1 328 28 view .LVU167 + ARM GAS /tmp/ccRj6lr2.s page 15 + + + 443 0056 8860 str r0, [r1, #8] + 444 .LVL60: + 445 .L22: + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get falling configuration */ + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 446 .loc 1 332 5 is_stmt 1 view .LVU168 + 447 .loc 1 332 13 is_stmt 0 view .LVU169 + 448 0058 1648 ldr r0, .L29+12 + 449 005a 8446 mov ip, r0 + 450 005c 6244 add r2, r2, ip + 451 .LVL61: + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = *regaddr; + 452 .loc 1 333 5 is_stmt 1 view .LVU170 + 453 .loc 1 333 12 is_stmt 0 view .LVU171 + 454 005e 1268 ldr r2, [r2] + 455 .LVL62: + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 456 .loc 1 336 5 is_stmt 1 view .LVU172 + 457 .loc 1 336 8 is_stmt 0 view .LVU173 + 458 0060 1A42 tst r2, r3 + 459 0062 03D0 beq .L23 + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + 460 .loc 1 338 7 is_stmt 1 view .LVU174 + 461 .loc 1 338 28 is_stmt 0 view .LVU175 + 462 0064 0223 movs r3, #2 + 463 .LVL63: + 464 .loc 1 338 28 view .LVU176 + 465 0066 8A68 ldr r2, [r1, #8] + 466 .LVL64: + 467 .loc 1 338 28 view .LVU177 + 468 0068 1343 orrs r3, r2 + 469 006a 8B60 str r3, [r1, #8] + 470 .L23: + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 471 .loc 1 342 5 is_stmt 1 view .LVU178 + 472 .loc 1 342 28 is_stmt 0 view .LVU179 + 473 006c C022 movs r2, #192 + 474 006e D204 lsls r2, r2, #19 + 475 0070 1440 ands r4, r2 + 476 .LVL65: + 477 .loc 1 342 8 view .LVU180 + 478 0072 9442 cmp r4, r2 + 479 0074 04D0 beq .L28 + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = EXTI->EXTICR[linepos >> 2u]; + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 2 + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + ARM GAS /tmp/ccRj6lr2.s page 16 + + + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_OK; + 480 .loc 1 351 10 view .LVU181 + 481 0076 0020 movs r0, #0 + 482 .LVL66: + 483 .loc 1 351 10 view .LVU182 + 484 0078 14E0 b .L18 + 485 .LVL67: + 486 .L19: + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 487 .loc 1 302 5 is_stmt 1 view .LVU183 + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 488 .loc 1 302 23 is_stmt 0 view .LVU184 + 489 007a 0026 movs r6, #0 + 490 .LVL68: + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 491 .loc 1 302 23 view .LVU185 + 492 007c 4E60 str r6, [r1, #4] + 493 007e D4E7 b .L20 + 494 .LVL69: + 495 .L28: + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 496 .loc 1 344 7 is_stmt 1 view .LVU186 + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 2 + 497 .loc 1 346 7 view .LVU187 + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 2 + 498 .loc 1 346 37 is_stmt 0 view .LVU188 + 499 0080 AB08 lsrs r3, r5, #2 + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 2 + 500 .loc 1 346 14 view .LVU189 + 501 0082 1833 adds r3, r3, #24 + 502 0084 9B00 lsls r3, r3, #2 + 503 0086 0A4A ldr r2, .L29+8 + 504 0088 9B58 ldr r3, [r3, r2] + 505 .LVL70: + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 506 .loc 1 347 7 is_stmt 1 view .LVU190 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 507 .loc 1 347 73 is_stmt 0 view .LVU191 + 508 008a 0322 movs r2, #3 + 509 008c AA43 bics r2, r5 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 510 .loc 1 347 66 view .LVU192 + 511 008e D200 lsls r2, r2, #3 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 512 .loc 1 347 39 view .LVU193 + 513 0090 9340 lsls r3, r3, r2 + 514 .LVL71: + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 515 .loc 1 347 96 view .LVU194 + 516 0092 1B0E lsrs r3, r3, #24 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 517 .loc 1 347 28 view .LVU195 + 518 0094 CB60 str r3, [r1, #12] + 519 .loc 1 351 10 view .LVU196 + 520 0096 0020 movs r0, #0 + ARM GAS /tmp/ccRj6lr2.s page 17 + + + 521 .LVL72: + 522 .loc 1 351 10 view .LVU197 + 523 0098 04E0 b .L18 + 524 .LVL73: + 525 .L24: + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 526 .loc 1 277 12 view .LVU198 + 527 009a 0120 movs r0, #1 + 528 .LVL74: + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 529 .loc 1 277 12 view .LVU199 + 530 009c 02E0 b .L18 + 531 .LVL75: + 532 .L25: + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 533 .loc 1 277 12 view .LVU200 + 534 009e 0120 movs r0, #1 + 535 .LVL76: + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 536 .loc 1 277 12 view .LVU201 + 537 00a0 00E0 b .L18 + 538 .LVL77: + 539 .L26: + 540 .loc 1 351 10 view .LVU202 + 541 00a2 0020 movs r0, #0 + 542 .LVL78: + 543 .L18: + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 544 .loc 1 352 1 view .LVU203 + 545 @ sp needed + 546 00a4 70BD pop {r4, r5, r6, pc} + 547 .L30: + 548 00a6 C046 .align 2 + 549 .L29: + 550 00a8 80180240 .word 1073879168 + 551 00ac 84180240 .word 1073879172 + 552 00b0 00180240 .word 1073879040 + 553 00b4 04180240 .word 1073879044 + 554 .cfi_endproc + 555 .LFE298: + 557 .section .text.HAL_EXTI_ClearConfigLine,"ax",%progbits + 558 .align 1 + 559 .global HAL_EXTI_ClearConfigLine + 560 .syntax unified + 561 .code 16 + 562 .thumb_func + 563 .fpu softvfp + 565 HAL_EXTI_ClearConfigLine: + 566 .LVL79: + 567 .LFB299: + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Clear whole configuration of a dedicated Exti line. + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval HAL Status. + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + ARM GAS /tmp/ccRj6lr2.s page 18 + + + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 568 .loc 1 361 1 is_stmt 1 view -0 + 569 .cfi_startproc + 570 @ args = 0, pretend = 0, frame = 0 + 571 @ frame_needed = 0, uses_anonymous_args = 0 + 572 .loc 1 361 1 is_stmt 0 view .LVU205 + 573 0000 F0B5 push {r4, r5, r6, r7, lr} + 574 .LCFI2: + 575 .cfi_def_cfa_offset 20 + 576 .cfi_offset 4, -20 + 577 .cfi_offset 5, -16 + 578 .cfi_offset 6, -12 + 579 .cfi_offset 7, -8 + 580 .cfi_offset 14, -4 + 581 0002 C646 mov lr, r8 + 582 0004 00B5 push {lr} + 583 .LCFI3: + 584 .cfi_def_cfa_offset 24 + 585 .cfi_offset 8, -24 + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 586 .loc 1 362 3 is_stmt 1 view .LVU206 + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t regval; + 587 .loc 1 363 3 view .LVU207 + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t linepos; + 588 .loc 1 364 3 view .LVU208 + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 589 .loc 1 365 3 view .LVU209 + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 590 .loc 1 366 3 view .LVU210 + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check null pointer */ + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (hexti == NULL) + 591 .loc 1 369 3 view .LVU211 + 592 .loc 1 369 6 is_stmt 0 view .LVU212 + 593 0006 0028 cmp r0, #0 + 594 0008 3ED0 beq .L33 + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_ERROR; + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check the parameter */ + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 595 .loc 1 375 3 is_stmt 1 view .LVU213 + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 596 .loc 1 378 3 view .LVU214 + 597 .loc 1 378 19 is_stmt 0 view .LVU215 + 598 000a 0668 ldr r6, [r0] + 599 .loc 1 378 43 view .LVU216 + 600 000c 330C lsrs r3, r6, #16 + 601 .loc 1 378 10 view .LVU217 + 602 000e 0122 movs r2, #1 + 603 0010 1340 ands r3, r2 + 604 .LVL80: + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + ARM GAS /tmp/ccRj6lr2.s page 19 + + + 605 .loc 1 379 3 is_stmt 1 view .LVU218 + 606 .loc 1 379 11 is_stmt 0 view .LVU219 + 607 0012 1F24 movs r4, #31 + 608 0014 3440 ands r4, r6 + 609 .LVL81: + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << linepos); + 610 .loc 1 380 3 is_stmt 1 view .LVU220 + 611 .loc 1 380 12 is_stmt 0 view .LVU221 + 612 0016 A240 lsls r2, r2, r4 + 613 .LVL82: + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* 1] Clear interrupt mode */ + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + 614 .loc 1 383 3 is_stmt 1 view .LVU222 + 615 .loc 1 383 26 is_stmt 0 view .LVU223 + 616 0018 1901 lsls r1, r3, #4 + 617 .loc 1 383 11 view .LVU224 + 618 001a 1E4D ldr r5, .L37 + 619 001c AC46 mov ip, r5 + 620 001e 8C44 add ip, ip, r1 + 621 .LVL83: + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 622 .loc 1 384 3 is_stmt 1 view .LVU225 + 623 .loc 1 384 13 is_stmt 0 view .LVU226 + 624 0020 6546 mov r5, ip + 625 0022 2D68 ldr r5, [r5] + 626 .loc 1 384 24 view .LVU227 + 627 0024 D743 mvns r7, r2 + 628 0026 B846 mov r8, r7 + 629 .loc 1 384 10 view .LVU228 + 630 0028 9543 bics r5, r2 + 631 .LVL84: + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 632 .loc 1 385 3 is_stmt 1 view .LVU229 + 633 .loc 1 385 12 is_stmt 0 view .LVU230 + 634 002a 6746 mov r7, ip + 635 002c 3D60 str r5, [r7] + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* 2] Clear event mode */ + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + 636 .loc 1 388 3 is_stmt 1 view .LVU231 + 637 .loc 1 388 11 is_stmt 0 view .LVU232 + 638 002e 1A4D ldr r5, .L37+4 + 639 .LVL85: + 640 .loc 1 388 11 view .LVU233 + 641 0030 AC46 mov ip, r5 + 642 .LVL86: + 643 .loc 1 388 11 view .LVU234 + 644 0032 6144 add r1, r1, ip + 645 .LVL87: + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 646 .loc 1 389 3 is_stmt 1 view .LVU235 + 647 .loc 1 389 13 is_stmt 0 view .LVU236 + 648 0034 0D68 ldr r5, [r1] + 649 .loc 1 389 10 view .LVU237 + 650 0036 9543 bics r5, r2 + 651 .LVL88: + ARM GAS /tmp/ccRj6lr2.s page 20 + + + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 652 .loc 1 390 3 is_stmt 1 view .LVU238 + 653 .loc 1 390 12 is_stmt 0 view .LVU239 + 654 0038 0D60 str r5, [r1] + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* 3] Clear triggers in case of configurable lines */ + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((hexti->Line & EXTI_CONFIG) != 0x00u) + 655 .loc 1 393 3 is_stmt 1 view .LVU240 + 656 .loc 1 393 6 is_stmt 0 view .LVU241 + 657 003a 0268 ldr r2, [r0] + 658 .LVL89: + 659 .loc 1 393 6 view .LVU242 + 660 003c 9201 lsls r2, r2, #6 + 661 003e 25D5 bpl .L34 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 662 .loc 1 395 5 is_stmt 1 view .LVU243 + 663 .loc 1 395 29 is_stmt 0 view .LVU244 + 664 0040 5B01 lsls r3, r3, #5 + 665 .LVL90: + 666 .loc 1 395 13 view .LVU245 + 667 0042 164A ldr r2, .L37+8 + 668 0044 9918 adds r1, r3, r2 + 669 .LVL91: + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 670 .loc 1 396 5 is_stmt 1 view .LVU246 + 671 .loc 1 396 15 is_stmt 0 view .LVU247 + 672 0046 0A68 ldr r2, [r1] + 673 .loc 1 396 12 view .LVU248 + 674 0048 4546 mov r5, r8 + 675 .LVL92: + 676 .loc 1 396 12 view .LVU249 + 677 004a 2A40 ands r2, r5 + 678 .LVL93: + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + 679 .loc 1 397 5 is_stmt 1 view .LVU250 + 680 .loc 1 397 14 is_stmt 0 view .LVU251 + 681 004c 0A60 str r2, [r1] + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + 682 .loc 1 399 5 is_stmt 1 view .LVU252 + 683 .loc 1 399 13 is_stmt 0 view .LVU253 + 684 004e 144A ldr r2, .L37+12 + 685 .LVL94: + 686 .loc 1 399 13 view .LVU254 + 687 0050 9446 mov ip, r2 + 688 0052 6344 add r3, r3, ip + 689 .LVL95: + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 690 .loc 1 400 5 is_stmt 1 view .LVU255 + 691 .loc 1 400 15 is_stmt 0 view .LVU256 + 692 0054 1A68 ldr r2, [r3] + 693 .loc 1 400 12 view .LVU257 + 694 0056 4746 mov r7, r8 + 695 0058 1740 ands r7, r2 + 696 .LVL96: + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = regval; + ARM GAS /tmp/ccRj6lr2.s page 21 + + + 697 .loc 1 401 5 is_stmt 1 view .LVU258 + 698 .loc 1 401 14 is_stmt 0 view .LVU259 + 699 005a 1F60 str r7, [r3] + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + 700 .loc 1 404 5 is_stmt 1 view .LVU260 + 701 .loc 1 404 15 is_stmt 0 view .LVU261 + 702 005c 0368 ldr r3, [r0] + 703 .LVL97: + 704 .loc 1 404 22 view .LVU262 + 705 005e C022 movs r2, #192 + 706 0060 D204 lsls r2, r2, #19 + 707 0062 1340 ands r3, r2 + 708 .loc 1 404 8 view .LVU263 + 709 0064 9342 cmp r3, r2 + 710 0066 01D0 beq .L36 + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = EXTI->EXTICR[linepos >> 2u]; + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_OK; + 711 .loc 1 414 10 view .LVU264 + 712 0068 0020 movs r0, #0 + 713 .LVL98: + 714 .loc 1 414 10 view .LVU265 + 715 006a 10E0 b .L32 + 716 .LVL99: + 717 .L36: + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 718 .loc 1 406 7 is_stmt 1 view .LVU266 + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 719 .loc 1 408 7 view .LVU267 + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 720 .loc 1 408 37 is_stmt 0 view .LVU268 + 721 006c A408 lsrs r4, r4, #2 + 722 .LVL100: + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 723 .loc 1 408 14 view .LVU269 + 724 006e 0B49 ldr r1, .L37+8 + 725 .LVL101: + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 726 .loc 1 408 14 view .LVU270 + 727 0070 1834 adds r4, r4, #24 + 728 0072 A400 lsls r4, r4, #2 + 729 0074 6258 ldr r2, [r4, r1] + 730 .LVL102: + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 731 .loc 1 409 7 is_stmt 1 view .LVU271 + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 732 .loc 1 409 76 is_stmt 0 view .LVU272 + 733 0076 0323 movs r3, #3 + ARM GAS /tmp/ccRj6lr2.s page 22 + + + 734 0078 1E40 ands r6, r3 + 735 .LVL103: + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 736 .loc 1 409 65 view .LVU273 + 737 007a F600 lsls r6, r6, #3 + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 738 .loc 1 409 38 view .LVU274 + 739 007c 0433 adds r3, r3, #4 + 740 007e B340 lsls r3, r3, r6 + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** EXTI->EXTICR[linepos >> 2u] = regval; + 741 .loc 1 409 14 view .LVU275 + 742 0080 9A43 bics r2, r3 + 743 .LVL104: + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 744 .loc 1 410 7 is_stmt 1 view .LVU276 + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 745 .loc 1 410 35 is_stmt 0 view .LVU277 + 746 0082 6250 str r2, [r4, r1] + 747 .loc 1 414 10 view .LVU278 + 748 0084 0020 movs r0, #0 + 749 .LVL105: + 750 .loc 1 414 10 view .LVU279 + 751 0086 02E0 b .L32 + 752 .LVL106: + 753 .L33: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 754 .loc 1 371 12 view .LVU280 + 755 0088 0120 movs r0, #1 + 756 .LVL107: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 757 .loc 1 371 12 view .LVU281 + 758 008a 00E0 b .L32 + 759 .LVL108: + 760 .L34: + 761 .loc 1 414 10 view .LVU282 + 762 008c 0020 movs r0, #0 + 763 .LVL109: + 764 .L32: + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 765 .loc 1 415 1 view .LVU283 + 766 @ sp needed + 767 008e 80BC pop {r7} + 768 0090 B846 mov r8, r7 + 769 0092 F0BD pop {r4, r5, r6, r7, pc} + 770 .L38: + 771 .align 2 + 772 .L37: + 773 0094 80180240 .word 1073879168 + 774 0098 84180240 .word 1073879172 + 775 009c 00180240 .word 1073879040 + 776 00a0 04180240 .word 1073879044 + 777 .cfi_endproc + 778 .LFE299: + 780 .section .text.HAL_EXTI_RegisterCallback,"ax",%progbits + 781 .align 1 + 782 .global HAL_EXTI_RegisterCallback + 783 .syntax unified + ARM GAS /tmp/ccRj6lr2.s page 23 + + + 784 .code 16 + 785 .thumb_func + 786 .fpu softvfp + 788 HAL_EXTI_RegisterCallback: + 789 .LVL110: + 790 .LFB300: + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Register callback for a dedicaated Exti line. + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param CallbackID User callback identifier. + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param pPendingCbfn function pointer to be stored as callback. + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval HAL Status. + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 791 .loc 1 427 1 is_stmt 1 view -0 + 792 .cfi_startproc + 793 @ args = 0, pretend = 0, frame = 0 + 794 @ frame_needed = 0, uses_anonymous_args = 0 + 795 @ link register save eliminated. + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef status = HAL_OK; + 796 .loc 1 428 3 view .LVU285 + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** switch (CallbackID) + 797 .loc 1 430 3 view .LVU286 + 798 0000 0129 cmp r1, #1 + 799 0002 09D0 beq .L40 + 800 0004 0229 cmp r1, #2 + 801 0006 0AD0 beq .L41 + 802 0008 0029 cmp r1, #0 + 803 000a 01D0 beq .L44 + 804 000c 0120 movs r0, #1 + 805 .LVL111: + 806 .L42: + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** case HAL_EXTI_COMMON_CB_ID: + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->RisingCallback = pPendingCbfn; + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->FallingCallback = pPendingCbfn; + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** case HAL_EXTI_RISING_CB_ID: + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->RisingCallback = pPendingCbfn; + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** case HAL_EXTI_FALLING_CB_ID: + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->FallingCallback = pPendingCbfn; + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** default: + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** status = HAL_ERROR; + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return status; + ARM GAS /tmp/ccRj6lr2.s page 24 + + + 807 .loc 1 450 3 view .LVU287 + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 808 .loc 1 451 1 is_stmt 0 view .LVU288 + 809 @ sp needed + 810 000e 7047 bx lr + 811 .LVL112: + 812 .L44: + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->FallingCallback = pPendingCbfn; + 813 .loc 1 433 7 is_stmt 1 view .LVU289 + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->FallingCallback = pPendingCbfn; + 814 .loc 1 433 29 is_stmt 0 view .LVU290 + 815 0010 4260 str r2, [r0, #4] + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 816 .loc 1 434 7 is_stmt 1 view .LVU291 + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 817 .loc 1 434 30 is_stmt 0 view .LVU292 + 818 0012 8260 str r2, [r0, #8] + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 819 .loc 1 435 7 is_stmt 1 view .LVU293 + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 820 .loc 1 428 21 is_stmt 0 view .LVU294 + 821 0014 0800 movs r0, r1 + 822 .LVL113: + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 823 .loc 1 435 7 view .LVU295 + 824 0016 FAE7 b .L42 + 825 .LVL114: + 826 .L40: + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 827 .loc 1 438 7 is_stmt 1 view .LVU296 + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 828 .loc 1 438 29 is_stmt 0 view .LVU297 + 829 0018 4260 str r2, [r0, #4] + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 830 .loc 1 439 7 is_stmt 1 view .LVU298 + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 831 .loc 1 428 21 is_stmt 0 view .LVU299 + 832 001a 0020 movs r0, #0 + 833 .LVL115: + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 834 .loc 1 439 7 view .LVU300 + 835 001c F7E7 b .L42 + 836 .LVL116: + 837 .L41: + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 838 .loc 1 442 7 is_stmt 1 view .LVU301 + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** break; + 839 .loc 1 442 30 is_stmt 0 view .LVU302 + 840 001e 8260 str r2, [r0, #8] + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 841 .loc 1 443 7 is_stmt 1 view .LVU303 + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 842 .loc 1 428 21 is_stmt 0 view .LVU304 + 843 0020 0020 movs r0, #0 + 844 .LVL117: + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 845 .loc 1 443 7 view .LVU305 + ARM GAS /tmp/ccRj6lr2.s page 25 + + + 846 0022 F4E7 b .L42 + 847 .cfi_endproc + 848 .LFE300: + 850 .section .text.HAL_EXTI_GetHandle,"ax",%progbits + 851 .align 1 + 852 .global HAL_EXTI_GetHandle + 853 .syntax unified + 854 .code 16 + 855 .thumb_func + 856 .fpu softvfp + 858 HAL_EXTI_GetHandle: + 859 .LVL118: + 860 .LFB301: + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Store line number as handle private field. + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param ExtiLine Exti line number. + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * This parameter can be from 0 to @ref EXTI_LINE_NB. + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval HAL Status. + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 861 .loc 1 462 1 is_stmt 1 view -0 + 862 .cfi_startproc + 863 @ args = 0, pretend = 0, frame = 0 + 864 @ frame_needed = 0, uses_anonymous_args = 0 + 865 @ link register save eliminated. + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check the parameters */ + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(ExtiLine)); + 866 .loc 1 464 3 view .LVU307 + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check null pointer */ + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (hexti == NULL) + 867 .loc 1 467 3 view .LVU308 + 868 .loc 1 467 6 is_stmt 0 view .LVU309 + 869 0000 0028 cmp r0, #0 + 870 0002 02D0 beq .L47 + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_ERROR; + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Store line number as handle private field */ + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->Line = ExtiLine; + 871 .loc 1 474 5 is_stmt 1 view .LVU310 + 872 .loc 1 474 17 is_stmt 0 view .LVU311 + 873 0004 0160 str r1, [r0] + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return HAL_OK; + 874 .loc 1 476 5 is_stmt 1 view .LVU312 + 875 .loc 1 476 12 is_stmt 0 view .LVU313 + 876 0006 0020 movs r0, #0 + 877 .LVL119: + 878 .L46: + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + ARM GAS /tmp/ccRj6lr2.s page 26 + + + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 879 .loc 1 478 1 view .LVU314 + 880 @ sp needed + 881 0008 7047 bx lr + 882 .LVL120: + 883 .L47: + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 884 .loc 1 469 12 view .LVU315 + 885 000a 0120 movs r0, #1 + 886 .LVL121: + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 887 .loc 1 469 12 view .LVU316 + 888 000c FCE7 b .L46 + 889 .cfi_endproc + 890 .LFE301: + 892 .section .text.HAL_EXTI_IRQHandler,"ax",%progbits + 893 .align 1 + 894 .global HAL_EXTI_IRQHandler + 895 .syntax unified + 896 .code 16 + 897 .thumb_func + 898 .fpu softvfp + 900 HAL_EXTI_IRQHandler: + 901 .LVL122: + 902 .LFB302: + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @} + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2 + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief EXTI IO functions. + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** @verbatim + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** =============================================================================== + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** ##### IO operation functions ##### + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** =============================================================================== + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** @endverbatim + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @{ + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Handle EXTI interrupt request. + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval none. + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 903 .loc 1 503 1 is_stmt 1 view -0 + 904 .cfi_startproc + 905 @ args = 0, pretend = 0, frame = 0 + 906 @ frame_needed = 0, uses_anonymous_args = 0 + 907 .loc 1 503 1 is_stmt 0 view .LVU318 + 908 0000 70B5 push {r4, r5, r6, lr} + 909 .LCFI4: + ARM GAS /tmp/ccRj6lr2.s page 27 + + + 910 .cfi_def_cfa_offset 16 + 911 .cfi_offset 4, -16 + 912 .cfi_offset 5, -12 + 913 .cfi_offset 6, -8 + 914 .cfi_offset 14, -4 + 915 0002 0600 movs r6, r0 + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 916 .loc 1 504 3 is_stmt 1 view .LVU319 + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t regval; + 917 .loc 1 505 3 view .LVU320 + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 918 .loc 1 506 3 view .LVU321 + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 919 .loc 1 507 3 view .LVU322 + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Compute line register offset and line mask */ + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 920 .loc 1 510 3 view .LVU323 + 921 .loc 1 510 19 is_stmt 0 view .LVU324 + 922 0004 0268 ldr r2, [r0] + 923 .loc 1 510 43 view .LVU325 + 924 0006 140C lsrs r4, r2, #16 + 925 .loc 1 510 10 view .LVU326 + 926 0008 0125 movs r5, #1 + 927 000a 2C40 ands r4, r5 + 928 .LVL123: + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 929 .loc 1 511 3 is_stmt 1 view .LVU327 + 930 .loc 1 511 35 is_stmt 0 view .LVU328 + 931 000c 1F23 movs r3, #31 + 932 000e 1340 ands r3, r2 + 933 .loc 1 511 12 view .LVU329 + 934 0010 9D40 lsls r5, r5, r3 + 935 .LVL124: + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get rising edge pending bit */ + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + 936 .loc 1 514 3 is_stmt 1 view .LVU330 + 937 .loc 1 514 26 is_stmt 0 view .LVU331 + 938 0012 6401 lsls r4, r4, #5 + 939 .LVL125: + 940 .loc 1 514 11 view .LVU332 + 941 0014 0A4B ldr r3, .L51 + 942 0016 E318 adds r3, r4, r3 + 943 .LVL126: + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & maskline); + 944 .loc 1 515 3 is_stmt 1 view .LVU333 + 945 .loc 1 515 13 is_stmt 0 view .LVU334 + 946 0018 1A68 ldr r2, [r3] + 947 .LVL127: + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (regval != 0x00u) + 948 .loc 1 517 3 is_stmt 1 view .LVU335 + 949 .loc 1 517 6 is_stmt 0 view .LVU336 + 950 001a 1542 tst r5, r2 + 951 001c 04D0 beq .L49 + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + ARM GAS /tmp/ccRj6lr2.s page 28 + + + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Clear pending bit */ + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = maskline; + 952 .loc 1 520 5 is_stmt 1 view .LVU337 + 953 .loc 1 520 14 is_stmt 0 view .LVU338 + 954 001e 1D60 str r5, [r3] + 955 .LVL128: + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Call rising callback */ + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (hexti->RisingCallback != NULL) + 956 .loc 1 523 5 is_stmt 1 view .LVU339 + 957 .loc 1 523 14 is_stmt 0 view .LVU340 + 958 0020 4368 ldr r3, [r0, #4] + 959 .LVL129: + 960 .loc 1 523 8 view .LVU341 + 961 0022 002B cmp r3, #0 + 962 0024 00D0 beq .L49 + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->RisingCallback(); + 963 .loc 1 525 7 is_stmt 1 view .LVU342 + 964 0026 9847 blx r3 + 965 .LVL130: + 966 .L49: + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get falling edge pending bit */ + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + 967 .loc 1 530 3 view .LVU343 + 968 .loc 1 530 11 is_stmt 0 view .LVU344 + 969 0028 064B ldr r3, .L51+4 + 970 002a 9C46 mov ip, r3 + 971 002c 6444 add r4, r4, ip + 972 .LVL131: + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = (*regaddr & maskline); + 973 .loc 1 531 3 is_stmt 1 view .LVU345 + 974 .loc 1 531 13 is_stmt 0 view .LVU346 + 975 002e 2368 ldr r3, [r4] + 976 .LVL132: + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (regval != 0x00u) + 977 .loc 1 533 3 is_stmt 1 view .LVU347 + 978 .loc 1 533 6 is_stmt 0 view .LVU348 + 979 0030 1D42 tst r5, r3 + 980 0032 04D0 beq .L48 + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Clear pending bit */ + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = maskline; + 981 .loc 1 536 5 is_stmt 1 view .LVU349 + 982 .loc 1 536 14 is_stmt 0 view .LVU350 + 983 0034 2560 str r5, [r4] + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Call rising callback */ + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (hexti->FallingCallback != NULL) + 984 .loc 1 539 5 is_stmt 1 view .LVU351 + 985 .loc 1 539 14 is_stmt 0 view .LVU352 + 986 0036 B368 ldr r3, [r6, #8] + 987 .LVL133: + ARM GAS /tmp/ccRj6lr2.s page 29 + + + 988 .loc 1 539 8 view .LVU353 + 989 0038 002B cmp r3, #0 + 990 003a 00D0 beq .L48 + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** hexti->FallingCallback(); + 991 .loc 1 541 7 is_stmt 1 view .LVU354 + 992 003c 9847 blx r3 + 993 .LVL134: + 994 .L48: + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 995 .loc 1 544 1 is_stmt 0 view .LVU355 + 996 @ sp needed + 997 .LVL135: + 998 .LVL136: + 999 .LVL137: + 1000 .loc 1 544 1 view .LVU356 + 1001 003e 70BD pop {r4, r5, r6, pc} + 1002 .L52: + 1003 .align 2 + 1004 .L51: + 1005 0040 0C180240 .word 1073879052 + 1006 0044 10180240 .word 1073879056 + 1007 .cfi_endproc + 1008 .LFE302: + 1010 .section .text.HAL_EXTI_GetPending,"ax",%progbits + 1011 .align 1 + 1012 .global HAL_EXTI_GetPending + 1013 .syntax unified + 1014 .code 16 + 1015 .thumb_func + 1016 .fpu softvfp + 1018 HAL_EXTI_GetPending: + 1019 .LVL138: + 1020 .LFB303: + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Get interrupt pending bit of a dedicated line. + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param Edge Specify which pending edge as to be checked. + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * This parameter can be one of the following values: + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_FALLING + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval 1 if interrupt is pending else 0. + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 1021 .loc 1 557 1 is_stmt 1 view -0 + 1022 .cfi_startproc + 1023 @ args = 0, pretend = 0, frame = 0 + 1024 @ frame_needed = 0, uses_anonymous_args = 0 + 1025 .loc 1 557 1 is_stmt 0 view .LVU358 + 1026 0000 10B5 push {r4, lr} + 1027 .LCFI5: + 1028 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccRj6lr2.s page 30 + + + 1029 .cfi_offset 4, -8 + 1030 .cfi_offset 14, -4 + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 1031 .loc 1 558 3 is_stmt 1 view .LVU359 + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t regval; + 1032 .loc 1 559 3 view .LVU360 + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t linepos; + 1033 .loc 1 560 3 view .LVU361 + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 1034 .loc 1 561 3 view .LVU362 + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 1035 .loc 1 562 3 view .LVU363 + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check parameters */ + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1036 .loc 1 565 3 view .LVU364 + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1037 .loc 1 566 3 view .LVU365 + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 1038 .loc 1 567 3 view .LVU366 + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1039 .loc 1 570 3 view .LVU367 + 1040 .loc 1 570 19 is_stmt 0 view .LVU368 + 1041 0002 0468 ldr r4, [r0] + 1042 .loc 1 570 43 view .LVU369 + 1043 0004 230C lsrs r3, r4, #16 + 1044 .loc 1 570 10 view .LVU370 + 1045 0006 0120 movs r0, #1 + 1046 .LVL139: + 1047 .loc 1 570 10 view .LVU371 + 1048 0008 0340 ands r3, r0 + 1049 .LVL140: + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 1050 .loc 1 571 3 is_stmt 1 view .LVU372 + 1051 .loc 1 571 11 is_stmt 0 view .LVU373 + 1052 000a 1F22 movs r2, #31 + 1053 000c 2240 ands r2, r4 + 1054 .LVL141: + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << linepos); + 1055 .loc 1 572 3 is_stmt 1 view .LVU374 + 1056 .loc 1 572 12 is_stmt 0 view .LVU375 + 1057 000e 9040 lsls r0, r0, r2 + 1058 .LVL142: + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (Edge != EXTI_TRIGGER_RISING) + 1059 .loc 1 574 3 is_stmt 1 view .LVU376 + 1060 .loc 1 574 6 is_stmt 0 view .LVU377 + 1061 0010 0129 cmp r1, #1 + 1062 0012 07D0 beq .L54 + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get falling edge pending bit */ + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + 1063 .loc 1 577 5 is_stmt 1 view .LVU378 + 1064 .loc 1 577 28 is_stmt 0 view .LVU379 + 1065 0014 5B01 lsls r3, r3, #5 + ARM GAS /tmp/ccRj6lr2.s page 31 + + + 1066 .LVL143: + 1067 .loc 1 577 13 view .LVU380 + 1068 0016 0649 ldr r1, .L56 + 1069 .LVL144: + 1070 .loc 1 577 13 view .LVU381 + 1071 0018 8C46 mov ip, r1 + 1072 001a 6344 add r3, r3, ip + 1073 .LVL145: + 1074 .L55: + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get rising edge pending bit */ + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* return 1 if bit is set else 0 */ + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regval = ((*regaddr & maskline) >> linepos); + 1075 .loc 1 586 3 is_stmt 1 view .LVU382 + 1076 .loc 1 586 14 is_stmt 0 view .LVU383 + 1077 001c 1B68 ldr r3, [r3] + 1078 .LVL146: + 1079 .loc 1 586 23 view .LVU384 + 1080 001e 1840 ands r0, r3 + 1081 .LVL147: + 1082 .loc 1 586 10 view .LVU385 + 1083 0020 D040 lsrs r0, r0, r2 + 1084 .LVL148: + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** return regval; + 1085 .loc 1 587 3 is_stmt 1 view .LVU386 + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1086 .loc 1 588 1 is_stmt 0 view .LVU387 + 1087 @ sp needed + 1088 .LVL149: + 1089 .loc 1 588 1 view .LVU388 + 1090 0022 10BD pop {r4, pc} + 1091 .LVL150: + 1092 .L54: + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1093 .loc 1 582 5 is_stmt 1 view .LVU389 + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1094 .loc 1 582 28 is_stmt 0 view .LVU390 + 1095 0024 5B01 lsls r3, r3, #5 + 1096 .LVL151: + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1097 .loc 1 582 13 view .LVU391 + 1098 0026 0349 ldr r1, .L56+4 + 1099 .LVL152: + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1100 .loc 1 582 13 view .LVU392 + 1101 0028 8C46 mov ip, r1 + 1102 002a 6344 add r3, r3, ip + 1103 .LVL153: + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1104 .loc 1 582 13 view .LVU393 + 1105 002c F6E7 b .L55 + 1106 .L57: + ARM GAS /tmp/ccRj6lr2.s page 32 + + + 1107 002e C046 .align 2 + 1108 .L56: + 1109 0030 10180240 .word 1073879056 + 1110 0034 0C180240 .word 1073879052 + 1111 .cfi_endproc + 1112 .LFE303: + 1114 .section .text.HAL_EXTI_ClearPending,"ax",%progbits + 1115 .align 1 + 1116 .global HAL_EXTI_ClearPending + 1117 .syntax unified + 1118 .code 16 + 1119 .thumb_func + 1120 .fpu softvfp + 1122 HAL_EXTI_ClearPending: + 1123 .LVL154: + 1124 .LFB304: + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Clear interrupt pending bit of a dedicated line. + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param Edge Specify which pending edge as to be clear. + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * This parameter can be one of the following values: + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_FALLING + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval None. + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 1125 .loc 1 601 1 is_stmt 1 view -0 + 1126 .cfi_startproc + 1127 @ args = 0, pretend = 0, frame = 0 + 1128 @ frame_needed = 0, uses_anonymous_args = 0 + 1129 .loc 1 601 1 is_stmt 0 view .LVU395 + 1130 0000 10B5 push {r4, lr} + 1131 .LCFI6: + 1132 .cfi_def_cfa_offset 8 + 1133 .cfi_offset 4, -8 + 1134 .cfi_offset 14, -4 + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 1135 .loc 1 602 3 is_stmt 1 view .LVU396 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 1136 .loc 1 603 3 view .LVU397 + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 1137 .loc 1 604 3 view .LVU398 + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check parameters */ + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1138 .loc 1 607 3 view .LVU399 + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1139 .loc 1 608 3 view .LVU400 + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 1140 .loc 1 609 3 view .LVU401 + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1141 .loc 1 612 3 view .LVU402 + ARM GAS /tmp/ccRj6lr2.s page 33 + + + 1142 .loc 1 612 19 is_stmt 0 view .LVU403 + 1143 0002 0468 ldr r4, [r0] + 1144 .loc 1 612 43 view .LVU404 + 1145 0004 230C lsrs r3, r4, #16 + 1146 .loc 1 612 10 view .LVU405 + 1147 0006 0122 movs r2, #1 + 1148 0008 1340 ands r3, r2 + 1149 .LVL155: + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 1150 .loc 1 613 3 is_stmt 1 view .LVU406 + 1151 .loc 1 613 35 is_stmt 0 view .LVU407 + 1152 000a 1F20 movs r0, #31 + 1153 .LVL156: + 1154 .loc 1 613 35 view .LVU408 + 1155 000c 2040 ands r0, r4 + 1156 .loc 1 613 12 view .LVU409 + 1157 000e 8240 lsls r2, r2, r0 + 1158 .LVL157: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** if (Edge != EXTI_TRIGGER_RISING) + 1159 .loc 1 615 3 is_stmt 1 view .LVU410 + 1160 .loc 1 615 6 is_stmt 0 view .LVU411 + 1161 0010 0129 cmp r1, #1 + 1162 0012 05D0 beq .L59 + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get falling edge pending register address */ + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + 1163 .loc 1 618 5 is_stmt 1 view .LVU412 + 1164 .loc 1 618 28 is_stmt 0 view .LVU413 + 1165 0014 5B01 lsls r3, r3, #5 + 1166 .LVL158: + 1167 .loc 1 618 13 view .LVU414 + 1168 0016 0549 ldr r1, .L61 + 1169 .LVL159: + 1170 .loc 1 618 13 view .LVU415 + 1171 0018 8C46 mov ip, r1 + 1172 001a 6344 add r3, r3, ip + 1173 .LVL160: + 1174 .L60: + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** else + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Get falling edge pending register address */ + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Clear Pending bit */ + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = maskline; + 1175 .loc 1 627 3 is_stmt 1 view .LVU416 + 1176 .loc 1 627 12 is_stmt 0 view .LVU417 + 1177 001c 1A60 str r2, [r3] + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1178 .loc 1 628 1 view .LVU418 + 1179 @ sp needed + 1180 .LVL161: + 1181 .loc 1 628 1 view .LVU419 + 1182 001e 10BD pop {r4, pc} + ARM GAS /tmp/ccRj6lr2.s page 34 + + + 1183 .LVL162: + 1184 .L59: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1185 .loc 1 623 5 is_stmt 1 view .LVU420 + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1186 .loc 1 623 28 is_stmt 0 view .LVU421 + 1187 0020 5B01 lsls r3, r3, #5 + 1188 .LVL163: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1189 .loc 1 623 13 view .LVU422 + 1190 0022 0349 ldr r1, .L61+4 + 1191 .LVL164: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1192 .loc 1 623 13 view .LVU423 + 1193 0024 8C46 mov ip, r1 + 1194 0026 6344 add r3, r3, ip + 1195 .LVL165: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1196 .loc 1 623 13 view .LVU424 + 1197 0028 F8E7 b .L60 + 1198 .L62: + 1199 002a C046 .align 2 + 1200 .L61: + 1201 002c 10180240 .word 1073879056 + 1202 0030 0C180240 .word 1073879052 + 1203 .cfi_endproc + 1204 .LFE304: + 1206 .section .text.HAL_EXTI_GenerateSWI,"ax",%progbits + 1207 .align 1 + 1208 .global HAL_EXTI_GenerateSWI + 1209 .syntax unified + 1210 .code 16 + 1211 .thumb_func + 1212 .fpu softvfp + 1214 HAL_EXTI_GenerateSWI: + 1215 .LVL166: + 1216 .LFB305: + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /** + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @brief Generate a software interrupt for a dedicated line. + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @param hexti Exti handle. + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** * @retval None. + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** */ + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** { + 1217 .loc 1 637 1 is_stmt 1 view -0 + 1218 .cfi_startproc + 1219 @ args = 0, pretend = 0, frame = 0 + 1220 @ frame_needed = 0, uses_anonymous_args = 0 + 1221 @ link register save eliminated. + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** __IO uint32_t *regaddr; + 1222 .loc 1 638 3 view .LVU426 + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t maskline; + 1223 .loc 1 639 3 view .LVU427 + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** uint32_t offset; + 1224 .loc 1 640 3 view .LVU428 + ARM GAS /tmp/ccRj6lr2.s page 35 + + + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* Check parameterd */ + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 1225 .loc 1 643 3 view .LVU429 + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 1226 .loc 1 644 3 view .LVU430 + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** /* compute line register offset and line mask */ + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1227 .loc 1 647 3 view .LVU431 + 1228 .loc 1 647 19 is_stmt 0 view .LVU432 + 1229 0000 0068 ldr r0, [r0] + 1230 .LVL167: + 1231 .loc 1 647 43 view .LVU433 + 1232 0002 030C lsrs r3, r0, #16 + 1233 .loc 1 647 10 view .LVU434 + 1234 0004 0122 movs r2, #1 + 1235 0006 1340 ands r3, r2 + 1236 .LVL168: + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 1237 .loc 1 648 3 is_stmt 1 view .LVU435 + 1238 .loc 1 648 35 is_stmt 0 view .LVU436 + 1239 0008 1F21 movs r1, #31 + 1240 000a 0140 ands r1, r0 + 1241 .loc 1 648 12 view .LVU437 + 1242 000c 8A40 lsls r2, r2, r1 + 1243 .LVL169: + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + 1244 .loc 1 650 3 is_stmt 1 view .LVU438 + 1245 .loc 1 650 28 is_stmt 0 view .LVU439 + 1246 000e 5B01 lsls r3, r3, #5 + 1247 .LVL170: + 1248 .loc 1 650 11 view .LVU440 + 1249 0010 0249 ldr r1, .L64 + 1250 0012 8C46 mov ip, r1 + 1251 0014 6344 add r3, r3, ip + 1252 .LVL171: + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** *regaddr = maskline; + 1253 .loc 1 651 3 is_stmt 1 view .LVU441 + 1254 .loc 1 651 12 is_stmt 0 view .LVU442 + 1255 0016 1A60 str r2, [r3] + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c **** } + 1256 .loc 1 652 1 view .LVU443 + 1257 @ sp needed + 1258 0018 7047 bx lr + 1259 .L65: + 1260 001a C046 .align 2 + 1261 .L64: + 1262 001c 08180240 .word 1073879048 + 1263 .cfi_endproc + 1264 .LFE305: + 1266 .text + 1267 .Letext0: + 1268 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1269 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1270 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + ARM GAS /tmp/ccRj6lr2.s page 36 + + + 1271 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h" + 1272 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccRj6lr2.s page 37 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_exti.c + /tmp/ccRj6lr2.s:16 .text.HAL_EXTI_SetConfigLine:0000000000000000 $t + /tmp/ccRj6lr2.s:24 .text.HAL_EXTI_SetConfigLine:0000000000000000 HAL_EXTI_SetConfigLine + /tmp/ccRj6lr2.s:299 .text.HAL_EXTI_SetConfigLine:00000000000000b4 $d + /tmp/ccRj6lr2.s:307 .text.HAL_EXTI_GetConfigLine:0000000000000000 $t + /tmp/ccRj6lr2.s:314 .text.HAL_EXTI_GetConfigLine:0000000000000000 HAL_EXTI_GetConfigLine + /tmp/ccRj6lr2.s:550 .text.HAL_EXTI_GetConfigLine:00000000000000a8 $d + /tmp/ccRj6lr2.s:558 .text.HAL_EXTI_ClearConfigLine:0000000000000000 $t + /tmp/ccRj6lr2.s:565 .text.HAL_EXTI_ClearConfigLine:0000000000000000 HAL_EXTI_ClearConfigLine + /tmp/ccRj6lr2.s:773 .text.HAL_EXTI_ClearConfigLine:0000000000000094 $d + /tmp/ccRj6lr2.s:781 .text.HAL_EXTI_RegisterCallback:0000000000000000 $t + /tmp/ccRj6lr2.s:788 .text.HAL_EXTI_RegisterCallback:0000000000000000 HAL_EXTI_RegisterCallback + /tmp/ccRj6lr2.s:851 .text.HAL_EXTI_GetHandle:0000000000000000 $t + /tmp/ccRj6lr2.s:858 .text.HAL_EXTI_GetHandle:0000000000000000 HAL_EXTI_GetHandle + /tmp/ccRj6lr2.s:893 .text.HAL_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccRj6lr2.s:900 .text.HAL_EXTI_IRQHandler:0000000000000000 HAL_EXTI_IRQHandler + /tmp/ccRj6lr2.s:1005 .text.HAL_EXTI_IRQHandler:0000000000000040 $d + /tmp/ccRj6lr2.s:1011 .text.HAL_EXTI_GetPending:0000000000000000 $t + /tmp/ccRj6lr2.s:1018 .text.HAL_EXTI_GetPending:0000000000000000 HAL_EXTI_GetPending + /tmp/ccRj6lr2.s:1109 .text.HAL_EXTI_GetPending:0000000000000030 $d + /tmp/ccRj6lr2.s:1115 .text.HAL_EXTI_ClearPending:0000000000000000 $t + /tmp/ccRj6lr2.s:1122 .text.HAL_EXTI_ClearPending:0000000000000000 HAL_EXTI_ClearPending + /tmp/ccRj6lr2.s:1201 .text.HAL_EXTI_ClearPending:000000000000002c $d + /tmp/ccRj6lr2.s:1207 .text.HAL_EXTI_GenerateSWI:0000000000000000 $t + /tmp/ccRj6lr2.s:1214 .text.HAL_EXTI_GenerateSWI:0000000000000000 HAL_EXTI_GenerateSWI + /tmp/ccRj6lr2.s:1262 .text.HAL_EXTI_GenerateSWI:000000000000001c $d + +NO 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© Copyright (c) 2018 STMicroelectronics. + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * All rights reserved.
+ 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * This software component is licensed by ST under BSD 3-Clause license, + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * the "License"; You may not use this file except in compliance with the + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * License. You may obtain a copy of the License at: + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * opensource.org/licenses/BSD-3-Clause + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** ****************************************************************************** + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #include "stm32g0xx_hal.h" + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + ARM GAS /tmp/cc6LDhZP.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @addtogroup STM32G0xx_HAL_Driver + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH FLASH + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief FLASH HAL module driver + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private defines -----------------------------------------------------------*/ + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private macros ------------------------------------------------------------*/ + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Private_Variables FLASH Private Variables + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Variable used for Program/Erase sectors under interruption + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .ErrorCode = HAL_FLASH_ERROR_NONE, \ + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .ProcedureOnGoing = FLASH_TYPENONE, \ + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .Address = 0U, \ + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .Banks = 0U, \ + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .Page = 0U, \ + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** .NbPagesToErase = 0U + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** }; + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Private_Functions FLASH Private Functions + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Exported functions --------------------------------------------------------*/ + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Programming operation functions + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @verbatim + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** ##### Programming operation functions ##### + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** [..] + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** This subsection provides a set of functions allowing to manage the FLASH + ARM GAS /tmp/cc6LDhZP.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** program operations. + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @endverbatim + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Program double word or fast program of a row at a specified address. + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Address Specifies the address to be programmed. + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Data Specifies the data to be programmed + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * This parameter is the data for the double word program and the address where + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * are stored the data for the row fast program depending on the TypeProgram: + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Process Locked */ + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Reset error code */ + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (status == HAL_OK) + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Program double-word (64-bit) at a specified address */ + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_Program_DoubleWord(Address, Data); + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Fast program a 32 row double-word (64-bit) at a specified address */ + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_Program_Fast(Address, (uint32_t)Data); + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + ARM GAS /tmp/cc6LDhZP.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* If the program operation is completed, disable the PG or FSTPG Bit */ + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, TypeProgram); + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Process Unlocked */ + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* return status */ + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Program double word or fast program of a row at a specified address with interrupt enab + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Address Specifies the address to be programmed. + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Data Specifies the data to be programmed + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * This parameter is the data for the double word program and the address where + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * are stored the data for the row fast program depending on the TypeProgram: + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Process Locked */ + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Reset error code */ + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for last operation to be completed */ + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (status != HAL_OK) + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Process Unlocked */ + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set internal variables used by the IRQ handler */ + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ProcedureOnGoing = TypeProgram; + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.Address = Address; + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Enable End of Operation and Error interrupts */ + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + ARM GAS /tmp/cc6LDhZP.s page 6 + + + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Program double-word (64-bit) at a specified address */ + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_Program_DoubleWord(Address, Data); + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check the parameters */ + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Fast program a 32 row double-word (64-bit) at a specified address */ + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_Program_Fast(Address, (uint32_t)Data); + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* return status */ + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Handle FLASH interrupt request. + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval None + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t param; + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t error; + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Save flash errors. */ + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** error = (FLASH->SR & FLASH_SR_ERRORS); + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* A] Set parameter for user or error callbacks */ + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* check operation was a program or erase */ + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if ((pFlash.ProcedureOnGoing & FLASH_TYPEERASE_MASS) != 0x00U) + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* return bank number */ + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** param = pFlash.Banks; + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Clear operation only for page erase or program */ + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00 + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* return address being programmed */ + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** param = pFlash.Address; + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* return page number being erased */ + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** param = pFlash.Page; + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* B] Check errors */ + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (error != 0x00U) + ARM GAS /tmp/cc6LDhZP.s page 7 + + + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /*Save the error code*/ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ErrorCode |= error; + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* clear error flags */ + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH->SR = FLASH_SR_ERRORS; + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /*Stop the procedure ongoing*/ + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_TYPENONE; + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Error callback */ + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(param); + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* C] Check FLASH End of Operation flag */ + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if ((FLASH->SR & FLASH_SR_EOP) != 0x00U) + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH->SR = FLASH_SR_EOP; + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES) + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Nb of pages to erased can be decreased */ + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.NbPagesToErase--; + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Check if there are still pages to erase*/ + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (pFlash.NbPagesToErase != 0x00U) + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Increment page number */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.Page++; + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_PageErase(pFlash.Banks, pFlash.Page); + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* No more pages to erase: stop erase pages procedure */ + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_TYPENONE; + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** else + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /*Stop the ongoing procedure */ + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_TYPENONE; + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* User callback */ + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(param); + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Disable End of Operation and Error interrupts */ + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH->CR &= ~(FLASH_CR_EOPIE | FLASH_CR_ERRIE); + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Process Unlocked */ + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + ARM GAS /tmp/cc6LDhZP.s page 8 + + + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback. + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Mass Erase: 0 + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Page Erase: Page which has been erased + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Program: Address which was selected for data program + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval None + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** UNUSED(ReturnValue); + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* NOTE : This function should not be modified, when the callback is needed, + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief FLASH operation error interrupt callback. + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Mass Erase: 0 + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Page Erase: Page number which returned an error + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * Program: Address which was selected for data program + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval None + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** UNUSED(ReturnValue); + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* NOTE : This function should not be modified, when the callback is needed, + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Management functions + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @verbatim + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** ##### Peripheral Control functions ##### + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** [..] + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** memory operations. + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @endverbatim + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + ARM GAS /tmp/cc6LDhZP.s page 9 + + + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Unlock the FLASH control register access. + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Authorize the FLASH Registers access */ + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY1); + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* verify Flash is unlock */ + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = HAL_ERROR; + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Lock the FLASH control register access. + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_LOCK); + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* verify Flash is locked */ + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = HAL_OK; + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Unlock the FLASH Option Bytes Registers access. + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U) + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Authorizes the Option Byte register programming */ + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + ARM GAS /tmp/cc6LDhZP.s page 10 + + + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* verify option bytes are unlocked */ + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U) + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = HAL_OK; + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Lock the FLASH Option Bytes Registers access. + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* verify option bytes are locked */ + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** status = HAL_OK; + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return status; + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Launch the option byte loading. + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL Status + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set the bit to force the option byte reloading */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* We should not reach here : Option byte launch generates Option byte reset + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** so return error */ + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_ERROR; + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Peripheral Errors functions + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @verbatim + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** =============================================================================== + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** [..] + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** This subsection permits to get in run-time Errors of the FLASH peripheral. + ARM GAS /tmp/cc6LDhZP.s page 11 + + + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** @endverbatim + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval FLASH_ErrorCode The returned value can be + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_NONE No error set + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_OP Operation error + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_PROG Programming error + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_WRP Write protection error + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_PGA Programming alignment error + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_SIZ Size error + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_PGS Programming sequence error + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_MIS Fast programming data miss error + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_FAST Fast programming error + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*) + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_OPTV Option validity error + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @arg @ref HAL_FLASH_ERROR_ECCD two ECC errors have been detected + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @note (*) availability depends on devices + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return pFlash.ErrorCode; + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @} + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Private functions ---------------------------------------------------------*/ + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @{ + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t error; + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** flag will be set */ + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t timeout = HAL_GetTick() + Timeout; + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait if any operation is ongoing */ + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #if defined(FLASH_DBANK_SUPPORT) + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); + ARM GAS /tmp/cc6LDhZP.s page 12 + + + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #else + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** error = FLASH_SR_BSY1; + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** while ((FLASH->SR & error) != 0x00U) + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (HAL_GetTick() >= timeout) + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_TIMEOUT; + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* check flash errors */ + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** error = (FLASH->SR & FLASH_SR_ERRORS); + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Clear SR register */ + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH->SR = FLASH_SR_CLEAR; + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (error != 0x00U) + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /*Save the error code*/ + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.ErrorCode = error; + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_ERROR; + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for control register to be written */ + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** timeout = HAL_GetTick() + Timeout; + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** if (HAL_GetTick() >= timeout) + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_TIMEOUT; + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_OK; + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Program double-word (64-bit) at a specified address. + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Address Specifies the address to be programmed. + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Data Specifies the data to be programmed. + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval None + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 27 .loc 1 649 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 .loc 1 649 1 is_stmt 0 view .LVU1 + 32 0000 30B5 push {r4, r5, lr} + 33 .LCFI0: + 34 .cfi_def_cfa_offset 12 + 35 .cfi_offset 4, -12 + 36 .cfi_offset 5, -8 + ARM GAS /tmp/cc6LDhZP.s page 13 + + + 37 .cfi_offset 14, -4 + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set PG bit */ + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_PG); + 38 .loc 1 651 3 is_stmt 1 view .LVU2 + 39 0002 054C ldr r4, .L2 + 40 0004 6169 ldr r1, [r4, #20] + 41 0006 0125 movs r5, #1 + 42 0008 2943 orrs r1, r5 + 43 000a 6161 str r1, [r4, #20] + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Program first word */ + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** *(uint32_t *)Address = (uint32_t)Data; + 44 .loc 1 654 3 view .LVU3 + 45 .loc 1 654 24 is_stmt 0 view .LVU4 + 46 000c 0260 str r2, [r0] + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Barrier to ensure programming is performed in 2 steps, in right order + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** (independently of compiler optimization behavior) */ + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __ISB(); + 47 .loc 1 658 3 is_stmt 1 view .LVU5 + 48 .LBB10: + 49 .LBI10: + 50 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + ARM GAS /tmp/cc6LDhZP.s page 14 + + + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + ARM GAS /tmp/cc6LDhZP.s page 15 + + + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; + ARM GAS /tmp/cc6LDhZP.s page 16 + + + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + ARM GAS /tmp/cc6LDhZP.s page 17 + + + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + ARM GAS /tmp/cc6LDhZP.s page 18 + + + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/cc6LDhZP.s page 19 + + + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/cc6LDhZP.s page 20 + + + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + ARM GAS /tmp/cc6LDhZP.s page 21 + + + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc6LDhZP.s page 22 + + + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + ARM GAS /tmp/cc6LDhZP.s page 23 + + + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/cc6LDhZP.s page 24 + + + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + ARM GAS /tmp/cc6LDhZP.s page 25 + + + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + ARM GAS /tmp/cc6LDhZP.s page 26 + + + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/cc6LDhZP.s page 27 + + + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/cc6LDhZP.s page 28 + + + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + ARM GAS /tmp/cc6LDhZP.s page 29 + + + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 51 .loc 2 933 27 view .LVU6 + 52 .LBB11: + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 53 .loc 2 935 3 view .LVU7 + 54 .syntax divided + 55 @ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 56 000e BFF36F8F isb 0xF + 57 @ 0 "" 2 + 58 .thumb + 59 .syntax unified + 60 .LBE11: + 61 .LBE10: + ARM GAS /tmp/cc6LDhZP.s page 30 + + + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Program second word */ + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); + 62 .loc 1 661 3 view .LVU8 + 63 .loc 1 661 31 is_stmt 0 view .LVU9 + 64 0012 4360 str r3, [r0, #4] + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 65 .loc 1 662 1 view .LVU10 + 66 @ sp needed + 67 0014 30BD pop {r4, r5, pc} + 68 .L3: + 69 0016 C046 .align 2 + 70 .L2: + 71 0018 00200240 .word 1073881088 + 72 .cfi_endproc + 73 .LFE309: + 75 .section .RamFunc,"ax",%progbits + 76 .align 1 + 77 .syntax unified + 78 .code 16 + 79 .thumb_func + 80 .fpu softvfp + 82 FLASH_Program_Fast: + 83 .LVL1: + 84 .LFB310: + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /** + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @brief Fast program a 32 row double-word (64-bit) at a specified address. + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param Address Specifies the address to be programmed. + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @param DataAddress Specifies the address where the data are stored. + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** * @retval None + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** */ + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 85 .loc 1 671 1 is_stmt 1 view -0 + 86 .cfi_startproc + 87 @ args = 0, pretend = 0, frame = 0 + 88 @ frame_needed = 0, uses_anonymous_args = 0 + 89 .loc 1 671 1 is_stmt 0 view .LVU12 + 90 0000 10B5 push {r4, lr} + 91 .LCFI1: + 92 .cfi_def_cfa_offset 8 + 93 .cfi_offset 4, -8 + 94 .cfi_offset 14, -4 + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint8_t index = 0; + 95 .loc 1 672 3 is_stmt 1 view .LVU13 + 96 .LVL2: + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t dest = Address; + 97 .loc 1 673 3 view .LVU14 + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t src = DataAddress; + 98 .loc 1 674 3 view .LVU15 + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t primask_bit; + 99 .loc 1 675 3 view .LVU16 + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set FSTPG bit */ + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_FSTPG); + 100 .loc 1 678 3 view .LVU17 + ARM GAS /tmp/cc6LDhZP.s page 31 + + + 101 0002 0C4A ldr r2, .L8 + 102 0004 5469 ldr r4, [r2, #20] + 103 0006 8023 movs r3, #128 + 104 0008 DB02 lsls r3, r3, #11 + 105 000a 2343 orrs r3, r4 + 106 000c 5361 str r3, [r2, #20] + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Enter critical section: row programming should not be longer than 7 ms */ + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** primask_bit = __get_PRIMASK(); + 107 .loc 1 681 3 view .LVU18 + 108 .LBB12: + 109 .LBI12: + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 110 .loc 2 449 31 view .LVU19 + 111 .LBB13: + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** + 112 .loc 2 451 3 view .LVU20 + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 113 .loc 2 453 3 view .LVU21 + 114 .syntax divided + 115 @ 453 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 116 000e EFF3108C MRS ip, primask + 117 @ 0 "" 2 + 118 .LVL3: + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 119 .loc 2 454 3 view .LVU22 + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 120 .loc 2 454 3 is_stmt 0 view .LVU23 + 121 .thumb + 122 .syntax unified + 123 .LBE13: + 124 .LBE12: + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __disable_irq(); + 125 .loc 1 682 3 is_stmt 1 view .LVU24 + 126 .LBB14: + 127 .LBI14: + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 128 .loc 2 207 27 view .LVU25 + 129 .LBB15: + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 130 .loc 2 209 3 view .LVU26 + 131 .syntax divided + 132 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 133 0012 72B6 cpsid i + 134 @ 0 "" 2 + 135 .thumb + 136 .syntax unified + 137 .LBE15: + 138 .LBE14: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t dest = Address; + 139 .loc 1 672 11 is_stmt 0 view .LVU27 + 140 0014 0023 movs r3, #0 + 141 .LBB17: + 142 .LBB16: + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** + 143 .loc 2 210 1 view .LVU28 + 144 0016 03E0 b .L5 + ARM GAS /tmp/cc6LDhZP.s page 32 + + + 145 .LVL4: + 146 .L6: + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** + 147 .loc 2 210 1 view .LVU29 + 148 .LBE16: + 149 .LBE17: + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Fast Program : 64 words */ + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** while (index < 64U) + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** *(uint32_t *)dest = *(uint32_t *)src; + 150 .loc 1 687 5 is_stmt 1 view .LVU30 + 151 .loc 1 687 25 is_stmt 0 view .LVU31 + 152 0018 04C9 ldmia r1!, {r2} + 153 .LVL5: + 154 .loc 1 687 23 view .LVU32 + 155 001a 04C0 stmia r0!, {r2} + 156 .LVL6: + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** src += 4U; + 157 .loc 1 688 5 is_stmt 1 view .LVU33 + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** dest += 4U; + 158 .loc 1 689 5 view .LVU34 + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** index++; + 159 .loc 1 690 5 view .LVU35 + 160 .loc 1 690 10 is_stmt 0 view .LVU36 + 161 001c 0133 adds r3, r3, #1 + 162 .LVL7: + 163 .loc 1 690 10 view .LVU37 + 164 001e DBB2 uxtb r3, r3 + 165 .LVL8: + 166 .L5: + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 167 .loc 1 685 9 is_stmt 1 view .LVU38 + 168 0020 3F2B cmp r3, #63 + 169 0022 F9D9 bls .L6 + 170 .LVL9: + 171 .L7: + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* wait for BSY1 in order to be sure that flash operation is ended befoire + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** allowing prefetch in flash. Timeout does not return status, as it will + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** be anyway done later */ + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #if defined(FLASH_DBANK_SUPPORT) + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U) + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #else + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 172 .loc 1 703 3 discriminator 1 view .LVU39 + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 173 .loc 1 700 9 discriminator 1 view .LVU40 + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 174 .loc 1 700 16 is_stmt 0 discriminator 1 view .LVU41 + 175 0024 034B ldr r3, .L8 + 176 0026 1B69 ldr r3, [r3, #16] + ARM GAS /tmp/cc6LDhZP.s page 33 + + + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 177 .loc 1 700 9 discriminator 1 view .LVU42 + 178 0028 DB03 lsls r3, r3, #15 + 179 002a FBD4 bmi .L7 + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Exit critical section: restore previous priority mask */ + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** __set_PRIMASK(primask_bit); + 180 .loc 1 706 3 is_stmt 1 view .LVU43 + 181 .LVL10: + 182 .LBB18: + 183 .LBI18: + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 184 .loc 2 479 27 view .LVU44 + 185 .LBB19: + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 186 .loc 2 481 3 view .LVU45 + 187 .syntax divided + 188 @ 481 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 189 002c 8CF31088 MSR primask, ip + 190 @ 0 "" 2 + 191 .LVL11: + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 192 .loc 2 481 3 is_stmt 0 view .LVU46 + 193 .thumb + 194 .syntax unified + 195 .LBE19: + 196 .LBE18: + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 197 .loc 1 707 1 view .LVU47 + 198 @ sp needed + 199 0030 10BD pop {r4, pc} + 200 .L9: + 201 0032 C046 .align 2 + 202 .L8: + 203 0034 00200240 .word 1073881088 + 204 .cfi_endproc + 205 .LFE310: + 207 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 208 .align 1 + 209 .weak HAL_FLASH_EndOfOperationCallback + 210 .syntax unified + 211 .code 16 + 212 .thumb_func + 213 .fpu softvfp + 215 HAL_FLASH_EndOfOperationCallback: + 216 .LVL12: + 217 .LFB300: + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 218 .loc 1 385 1 is_stmt 1 view -0 + 219 .cfi_startproc + 220 @ args = 0, pretend = 0, frame = 0 + 221 @ frame_needed = 0, uses_anonymous_args = 0 + 222 @ link register save eliminated. + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 223 .loc 1 387 3 view .LVU49 + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 224 .loc 1 392 1 is_stmt 0 view .LVU50 + ARM GAS /tmp/cc6LDhZP.s page 34 + + + 225 @ sp needed + 226 0000 7047 bx lr + 227 .cfi_endproc + 228 .LFE300: + 230 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 231 .align 1 + 232 .weak HAL_FLASH_OperationErrorCallback + 233 .syntax unified + 234 .code 16 + 235 .thumb_func + 236 .fpu softvfp + 238 HAL_FLASH_OperationErrorCallback: + 239 .LVL13: + 240 .LFB301: + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 241 .loc 1 403 1 is_stmt 1 view -0 + 242 .cfi_startproc + 243 @ args = 0, pretend = 0, frame = 0 + 244 @ frame_needed = 0, uses_anonymous_args = 0 + 245 @ link register save eliminated. + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 246 .loc 1 405 3 view .LVU52 + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 247 .loc 1 410 1 is_stmt 0 view .LVU53 + 248 @ sp needed + 249 0000 7047 bx lr + 250 .cfi_endproc + 251 .LFE301: + 253 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 254 .align 1 + 255 .global HAL_FLASH_IRQHandler + 256 .syntax unified + 257 .code 16 + 258 .thumb_func + 259 .fpu softvfp + 261 HAL_FLASH_IRQHandler: + 262 .LFB299: + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t param; + 263 .loc 1 285 1 is_stmt 1 view -0 + 264 .cfi_startproc + 265 @ args = 0, pretend = 0, frame = 0 + 266 @ frame_needed = 0, uses_anonymous_args = 0 + 267 0000 10B5 push {r4, lr} + 268 .LCFI2: + 269 .cfi_def_cfa_offset 8 + 270 .cfi_offset 4, -8 + 271 .cfi_offset 14, -4 + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t error; + 272 .loc 1 286 3 view .LVU55 + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 273 .loc 1 287 3 view .LVU56 + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 274 .loc 1 290 3 view .LVU57 + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 275 .loc 1 290 17 is_stmt 0 view .LVU58 + 276 0002 2B4B ldr r3, .L25 + 277 0004 1B69 ldr r3, [r3, #16] + ARM GAS /tmp/cc6LDhZP.s page 35 + + + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 278 .loc 1 290 9 view .LVU59 + 279 0006 2B4A ldr r2, .L25+4 + 280 0008 1340 ands r3, r2 + 281 .LVL14: + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 282 .loc 1 294 3 is_stmt 1 view .LVU60 + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 283 .loc 1 294 14 is_stmt 0 view .LVU61 + 284 000a 2B4A ldr r2, .L25+8 + 285 000c 9268 ldr r2, [r2, #8] + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 286 .loc 1 294 6 view .LVU62 + 287 000e 5107 lsls r1, r2, #29 + 288 0010 21D5 bpl .L13 + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 289 .loc 1 297 5 is_stmt 1 view .LVU63 + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 290 .loc 1 297 11 is_stmt 0 view .LVU64 + 291 0012 294A ldr r2, .L25+8 + 292 0014 1469 ldr r4, [r2, #16] + 293 .LVL15: + 294 .L14: + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 295 .loc 1 317 3 is_stmt 1 view .LVU65 + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 296 .loc 1 317 6 is_stmt 0 view .LVU66 + 297 0016 002B cmp r3, #0 + 298 0018 2AD1 bne .L22 + 299 .LVL16: + 300 .L16: + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 301 .loc 1 333 3 is_stmt 1 view .LVU67 + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 302 .loc 1 333 13 is_stmt 0 view .LVU68 + 303 001a 254B ldr r3, .L25 + 304 001c 1B69 ldr r3, [r3, #16] + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 305 .loc 1 333 6 view .LVU69 + 306 001e DB07 lsls r3, r3, #31 + 307 0020 0CD5 bpl .L17 + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 308 .loc 1 336 5 is_stmt 1 view .LVU70 + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 309 .loc 1 336 15 is_stmt 0 view .LVU71 + 310 0022 234B ldr r3, .L25 + 311 0024 0122 movs r2, #1 + 312 0026 1A61 str r2, [r3, #16] + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 313 .loc 1 338 5 is_stmt 1 view .LVU72 + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 314 .loc 1 338 15 is_stmt 0 view .LVU73 + 315 0028 234B ldr r3, .L25+8 + 316 002a 9B68 ldr r3, [r3, #8] + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 317 .loc 1 338 8 view .LVU74 + 318 002c 022B cmp r3, #2 + ARM GAS /tmp/cc6LDhZP.s page 36 + + + 319 002e 2CD0 beq .L23 + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 320 .loc 1 359 7 is_stmt 1 view .LVU75 + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 321 .loc 1 359 31 is_stmt 0 view .LVU76 + 322 0030 214B ldr r3, .L25+8 + 323 0032 0022 movs r2, #0 + 324 0034 9A60 str r2, [r3, #8] + 325 .L20: + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 326 .loc 1 363 5 is_stmt 1 view .LVU77 + 327 0036 2000 movs r0, r4 + 328 0038 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 329 .LVL17: + 330 .L17: + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 331 .loc 1 366 3 view .LVU78 + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 332 .loc 1 366 13 is_stmt 0 view .LVU79 + 333 003c 1E4B ldr r3, .L25+8 + 334 003e 9B68 ldr r3, [r3, #8] + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 335 .loc 1 366 6 view .LVU80 + 336 0040 002B cmp r3, #0 + 337 0042 07D1 bne .L12 + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 338 .loc 1 369 5 is_stmt 1 view .LVU81 + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 339 .loc 1 369 15 is_stmt 0 view .LVU82 + 340 0044 1A4A ldr r2, .L25 + 341 0046 5369 ldr r3, [r2, #20] + 342 0048 1C49 ldr r1, .L25+12 + 343 004a 0B40 ands r3, r1 + 344 004c 5361 str r3, [r2, #20] + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 345 .loc 1 372 5 is_stmt 1 view .LVU83 + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 346 .loc 1 372 5 view .LVU84 + 347 004e 1A4B ldr r3, .L25+8 + 348 0050 0022 movs r2, #0 + 349 0052 1A70 strb r2, [r3] + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 350 .loc 1 372 5 view .LVU85 + 351 .L12: + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 352 .loc 1 374 1 is_stmt 0 view .LVU86 + 353 @ sp needed + 354 .LVL18: + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 355 .loc 1 374 1 view .LVU87 + 356 0054 10BD pop {r4, pc} + 357 .LVL19: + 358 .L13: + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 359 .loc 1 302 5 is_stmt 1 view .LVU88 + 360 0056 1648 ldr r0, .L25 + 361 0058 4169 ldr r1, [r0, #20] + ARM GAS /tmp/cc6LDhZP.s page 37 + + + 362 005a 9143 bics r1, r2 + 363 005c 4161 str r1, [r0, #20] + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 364 .loc 1 304 5 view .LVU89 + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 365 .loc 1 304 34 is_stmt 0 view .LVU90 + 366 005e 1849 ldr r1, .L25+16 + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 367 .loc 1 304 8 view .LVU91 + 368 0060 0A42 tst r2, r1 + 369 0062 02D0 beq .L15 + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 370 .loc 1 307 7 is_stmt 1 view .LVU92 + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 371 .loc 1 307 13 is_stmt 0 view .LVU93 + 372 0064 144A ldr r2, .L25+8 + 373 0066 D468 ldr r4, [r2, #12] + 374 .LVL20: + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 375 .loc 1 307 13 view .LVU94 + 376 0068 D5E7 b .L14 + 377 .LVL21: + 378 .L15: + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 379 .loc 1 312 7 is_stmt 1 view .LVU95 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 380 .loc 1 312 13 is_stmt 0 view .LVU96 + 381 006a 134A ldr r2, .L25+8 + 382 006c 5469 ldr r4, [r2, #20] + 383 .LVL22: + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 384 .loc 1 312 13 view .LVU97 + 385 006e D2E7 b .L14 + 386 .L22: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 387 .loc 1 320 5 is_stmt 1 view .LVU98 + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 388 .loc 1 320 22 is_stmt 0 view .LVU99 + 389 0070 114A ldr r2, .L25+8 + 390 0072 5168 ldr r1, [r2, #4] + 391 0074 0B43 orrs r3, r1 + 392 .LVL23: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 393 .loc 1 320 22 view .LVU100 + 394 0076 5360 str r3, [r2, #4] + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 395 .loc 1 323 5 is_stmt 1 view .LVU101 + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 396 .loc 1 323 15 is_stmt 0 view .LVU102 + 397 0078 0D4B ldr r3, .L25 + 398 007a 0E49 ldr r1, .L25+4 + 399 007c 1961 str r1, [r3, #16] + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 400 .loc 1 326 5 is_stmt 1 view .LVU103 + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 401 .loc 1 326 29 is_stmt 0 view .LVU104 + 402 007e 0023 movs r3, #0 + ARM GAS /tmp/cc6LDhZP.s page 38 + + + 403 0080 9360 str r3, [r2, #8] + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 404 .loc 1 329 5 is_stmt 1 view .LVU105 + 405 0082 2000 movs r0, r4 + 406 0084 FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 407 .LVL24: + 408 0088 C7E7 b .L16 + 409 .L23: + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 410 .loc 1 341 7 view .LVU106 + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 411 .loc 1 341 13 is_stmt 0 view .LVU107 + 412 008a 0B4A ldr r2, .L25+8 + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 413 .loc 1 341 28 view .LVU108 + 414 008c 9369 ldr r3, [r2, #24] + 415 008e 013B subs r3, r3, #1 + 416 0090 9361 str r3, [r2, #24] + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 417 .loc 1 344 7 is_stmt 1 view .LVU109 + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 418 .loc 1 344 10 is_stmt 0 view .LVU110 + 419 0092 002B cmp r3, #0 + 420 0094 03D1 bne .L24 + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 421 .loc 1 353 9 is_stmt 1 view .LVU111 + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 422 .loc 1 353 33 is_stmt 0 view .LVU112 + 423 0096 084B ldr r3, .L25+8 + 424 0098 0022 movs r2, #0 + 425 009a 9A60 str r2, [r3, #8] + 426 009c CBE7 b .L20 + 427 .L24: + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_PageErase(pFlash.Banks, pFlash.Page); + 428 .loc 1 347 9 is_stmt 1 view .LVU113 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_PageErase(pFlash.Banks, pFlash.Page); + 429 .loc 1 347 15 is_stmt 0 view .LVU114 + 430 009e 1300 movs r3, r2 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** FLASH_PageErase(pFlash.Banks, pFlash.Page); + 431 .loc 1 347 20 view .LVU115 + 432 00a0 5269 ldr r2, [r2, #20] + 433 00a2 511C adds r1, r2, #1 + 434 00a4 5961 str r1, [r3, #20] + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 435 .loc 1 348 9 is_stmt 1 view .LVU116 + 436 00a6 1869 ldr r0, [r3, #16] + 437 00a8 FFF7FEFF bl FLASH_PageErase + 438 .LVL25: + 439 00ac C3E7 b .L20 + 440 .L26: + 441 00ae C046 .align 2 + 442 .L25: + 443 00b0 00200240 .word 1073881088 + 444 00b4 FAC30000 .word 50170 + 445 00b8 00000000 .word .LANCHOR0 + 446 00bc FFFFFFFC .word -50331649 + 447 00c0 01000400 .word 262145 + ARM GAS /tmp/cc6LDhZP.s page 39 + + + 448 .cfi_endproc + 449 .LFE299: + 451 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 452 .align 1 + 453 .global HAL_FLASH_Unlock + 454 .syntax unified + 455 .code 16 + 456 .thumb_func + 457 .fpu softvfp + 459 HAL_FLASH_Unlock: + 460 .LFB302: + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 461 .loc 1 436 1 view -0 + 462 .cfi_startproc + 463 @ args = 0, pretend = 0, frame = 0 + 464 @ frame_needed = 0, uses_anonymous_args = 0 + 465 @ link register save eliminated. + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 466 .loc 1 437 3 view .LVU118 + 467 .LVL26: + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 468 .loc 1 439 3 view .LVU119 + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 469 .loc 1 439 7 is_stmt 0 view .LVU120 + 470 0000 084B ldr r3, .L32 + 471 0002 5B69 ldr r3, [r3, #20] + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 472 .loc 1 439 6 view .LVU121 + 473 0004 002B cmp r3, #0 + 474 0006 01DB blt .L31 + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 475 .loc 1 437 21 view .LVU122 + 476 0008 0020 movs r0, #0 + 477 .L28: + 478 .LVL27: + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 479 .loc 1 452 3 is_stmt 1 view .LVU123 + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 480 .loc 1 453 1 is_stmt 0 view .LVU124 + 481 @ sp needed + 482 000a 7047 bx lr + 483 .LVL28: + 484 .L31: + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 485 .loc 1 442 5 is_stmt 1 view .LVU125 + 486 000c 054B ldr r3, .L32 + 487 000e 064A ldr r2, .L32+4 + 488 0010 9A60 str r2, [r3, #8] + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 489 .loc 1 443 5 view .LVU126 + 490 0012 064A ldr r2, .L32+8 + 491 0014 9A60 str r2, [r3, #8] + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 492 .loc 1 446 5 view .LVU127 + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 493 .loc 1 446 9 is_stmt 0 view .LVU128 + 494 0016 5B69 ldr r3, [r3, #20] + ARM GAS /tmp/cc6LDhZP.s page 40 + + + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 495 .loc 1 446 8 view .LVU129 + 496 0018 002B cmp r3, #0 + 497 001a 01DB blt .L30 + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 498 .loc 1 437 21 view .LVU130 + 499 001c 0020 movs r0, #0 + 500 001e F4E7 b .L28 + 501 .L30: + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 502 .loc 1 448 14 view .LVU131 + 503 0020 0120 movs r0, #1 + 504 0022 F2E7 b .L28 + 505 .L33: + 506 .align 2 + 507 .L32: + 508 0024 00200240 .word 1073881088 + 509 0028 23016745 .word 1164378403 + 510 002c AB89EFCD .word -839939669 + 511 .cfi_endproc + 512 .LFE302: + 514 .section .text.HAL_FLASH_Lock,"ax",%progbits + 515 .align 1 + 516 .global HAL_FLASH_Lock + 517 .syntax unified + 518 .code 16 + 519 .thumb_func + 520 .fpu softvfp + 522 HAL_FLASH_Lock: + 523 .LFB303: + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 524 .loc 1 460 1 is_stmt 1 view -0 + 525 .cfi_startproc + 526 @ args = 0, pretend = 0, frame = 0 + 527 @ frame_needed = 0, uses_anonymous_args = 0 + 528 @ link register save eliminated. + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 529 .loc 1 461 3 view .LVU133 + 530 .LVL29: + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 531 .loc 1 464 3 view .LVU134 + 532 0000 064B ldr r3, .L37 + 533 0002 5969 ldr r1, [r3, #20] + 534 0004 8022 movs r2, #128 + 535 0006 1206 lsls r2, r2, #24 + 536 0008 0A43 orrs r2, r1 + 537 000a 5A61 str r2, [r3, #20] + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 538 .loc 1 467 3 view .LVU135 + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 539 .loc 1 467 7 is_stmt 0 view .LVU136 + 540 000c 5B69 ldr r3, [r3, #20] + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 541 .loc 1 467 6 view .LVU137 + 542 000e 002B cmp r3, #0 + 543 0010 01DB blt .L36 + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + ARM GAS /tmp/cc6LDhZP.s page 41 + + + 544 .loc 1 461 21 view .LVU138 + 545 0012 0120 movs r0, #1 + 546 .L35: + 547 .LVL30: + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 548 .loc 1 472 3 is_stmt 1 view .LVU139 + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 549 .loc 1 473 1 is_stmt 0 view .LVU140 + 550 @ sp needed + 551 0014 7047 bx lr + 552 .LVL31: + 553 .L36: + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 554 .loc 1 469 12 view .LVU141 + 555 0016 0020 movs r0, #0 + 556 0018 FCE7 b .L35 + 557 .L38: + 558 001a C046 .align 2 + 559 .L37: + 560 001c 00200240 .word 1073881088 + 561 .cfi_endproc + 562 .LFE303: + 564 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 565 .align 1 + 566 .global HAL_FLASH_OB_Unlock + 567 .syntax unified + 568 .code 16 + 569 .thumb_func + 570 .fpu softvfp + 572 HAL_FLASH_OB_Unlock: + 573 .LFB304: + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 574 .loc 1 480 1 is_stmt 1 view -0 + 575 .cfi_startproc + 576 @ args = 0, pretend = 0, frame = 0 + 577 @ frame_needed = 0, uses_anonymous_args = 0 + 578 @ link register save eliminated. + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 579 .loc 1 481 3 view .LVU143 + 580 .LVL32: + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 581 .loc 1 483 3 view .LVU144 + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 582 .loc 1 483 7 is_stmt 0 view .LVU145 + 583 0000 084B ldr r3, .L43 + 584 0002 5B69 ldr r3, [r3, #20] + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 585 .loc 1 483 6 view .LVU146 + 586 0004 5B00 lsls r3, r3, #1 + 587 0006 09D5 bpl .L41 + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 588 .loc 1 486 5 is_stmt 1 view .LVU147 + 589 0008 064B ldr r3, .L43 + 590 000a 074A ldr r2, .L43+4 + 591 000c DA60 str r2, [r3, #12] + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 592 .loc 1 487 5 view .LVU148 + ARM GAS /tmp/cc6LDhZP.s page 42 + + + 593 000e 074A ldr r2, .L43+8 + 594 0010 DA60 str r2, [r3, #12] + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 595 .loc 1 490 5 view .LVU149 + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 596 .loc 1 490 9 is_stmt 0 view .LVU150 + 597 0012 5B69 ldr r3, [r3, #20] + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 598 .loc 1 490 8 view .LVU151 + 599 0014 5B00 lsls r3, r3, #1 + 600 0016 03D5 bpl .L42 + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 601 .loc 1 481 21 view .LVU152 + 602 0018 0120 movs r0, #1 + 603 001a 00E0 b .L40 + 604 .L41: + 605 001c 0120 movs r0, #1 + 606 .L40: + 607 .LVL33: + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 608 .loc 1 496 3 is_stmt 1 view .LVU153 + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 609 .loc 1 497 1 is_stmt 0 view .LVU154 + 610 @ sp needed + 611 001e 7047 bx lr + 612 .LVL34: + 613 .L42: + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 614 .loc 1 492 14 view .LVU155 + 615 0020 0020 movs r0, #0 + 616 0022 FCE7 b .L40 + 617 .L44: + 618 .align 2 + 619 .L43: + 620 0024 00200240 .word 1073881088 + 621 0028 3B2A1908 .word 135866939 + 622 002c 7F6E5D4C .word 1281191551 + 623 .cfi_endproc + 624 .LFE304: + 626 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 627 .align 1 + 628 .global HAL_FLASH_OB_Lock + 629 .syntax unified + 630 .code 16 + 631 .thumb_func + 632 .fpu softvfp + 634 HAL_FLASH_OB_Lock: + 635 .LFB305: + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 636 .loc 1 504 1 is_stmt 1 view -0 + 637 .cfi_startproc + 638 @ args = 0, pretend = 0, frame = 0 + 639 @ frame_needed = 0, uses_anonymous_args = 0 + 640 @ link register save eliminated. + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 641 .loc 1 505 3 view .LVU157 + 642 .LVL35: + ARM GAS /tmp/cc6LDhZP.s page 43 + + + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 643 .loc 1 508 3 view .LVU158 + 644 0000 064B ldr r3, .L48 + 645 0002 5A69 ldr r2, [r3, #20] + 646 0004 8021 movs r1, #128 + 647 0006 C905 lsls r1, r1, #23 + 648 0008 0A43 orrs r2, r1 + 649 000a 5A61 str r2, [r3, #20] + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 650 .loc 1 511 3 view .LVU159 + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 651 .loc 1 511 7 is_stmt 0 view .LVU160 + 652 000c 5B69 ldr r3, [r3, #20] + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 653 .loc 1 511 6 view .LVU161 + 654 000e 0B42 tst r3, r1 + 655 0010 01D1 bne .L47 + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 656 .loc 1 505 21 view .LVU162 + 657 0012 0120 movs r0, #1 + 658 .L46: + 659 .LVL36: + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 660 .loc 1 516 3 is_stmt 1 view .LVU163 + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 661 .loc 1 517 1 is_stmt 0 view .LVU164 + 662 @ sp needed + 663 0014 7047 bx lr + 664 .LVL37: + 665 .L47: + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 666 .loc 1 513 12 view .LVU165 + 667 0016 0020 movs r0, #0 + 668 0018 FCE7 b .L46 + 669 .L49: + 670 001a C046 .align 2 + 671 .L48: + 672 001c 00200240 .word 1073881088 + 673 .cfi_endproc + 674 .LFE305: + 676 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 677 .align 1 + 678 .global HAL_FLASH_OB_Launch + 679 .syntax unified + 680 .code 16 + 681 .thumb_func + 682 .fpu softvfp + 684 HAL_FLASH_OB_Launch: + 685 .LFB306: + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Set the bit to force the option byte reloading */ + 686 .loc 1 524 1 is_stmt 1 view -0 + 687 .cfi_startproc + 688 @ args = 0, pretend = 0, frame = 0 + 689 @ frame_needed = 0, uses_anonymous_args = 0 + 690 @ link register save eliminated. + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 691 .loc 1 526 3 view .LVU167 + ARM GAS /tmp/cc6LDhZP.s page 44 + + + 692 0000 034A ldr r2, .L51 + 693 0002 5169 ldr r1, [r2, #20] + 694 0004 8023 movs r3, #128 + 695 0006 1B05 lsls r3, r3, #20 + 696 0008 0B43 orrs r3, r1 + 697 000a 5361 str r3, [r2, #20] + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 698 .loc 1 530 3 view .LVU168 + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 699 .loc 1 531 1 is_stmt 0 view .LVU169 + 700 000c 0120 movs r0, #1 + 701 @ sp needed + 702 000e 7047 bx lr + 703 .L52: + 704 .align 2 + 705 .L51: + 706 0010 00200240 .word 1073881088 + 707 .cfi_endproc + 708 .LFE306: + 710 .section .text.HAL_FLASH_GetError,"ax",%progbits + 711 .align 1 + 712 .global HAL_FLASH_GetError + 713 .syntax unified + 714 .code 16 + 715 .thumb_func + 716 .fpu softvfp + 718 HAL_FLASH_GetError: + 719 .LFB307: + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return pFlash.ErrorCode; + 720 .loc 1 569 1 is_stmt 1 view -0 + 721 .cfi_startproc + 722 @ args = 0, pretend = 0, frame = 0 + 723 @ frame_needed = 0, uses_anonymous_args = 0 + 724 @ link register save eliminated. + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 725 .loc 1 570 3 view .LVU171 + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 726 .loc 1 570 16 is_stmt 0 view .LVU172 + 727 0000 014B ldr r3, .L54 + 728 0002 5868 ldr r0, [r3, #4] + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 729 .loc 1 571 1 view .LVU173 + 730 @ sp needed + 731 0004 7047 bx lr + 732 .L55: + 733 0006 C046 .align 2 + 734 .L54: + 735 0008 00000000 .word .LANCHOR0 + 736 .cfi_endproc + 737 .LFE307: + 739 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 740 .align 1 + 741 .global FLASH_WaitForLastOperation + 742 .syntax unified + 743 .code 16 + 744 .thumb_func + 745 .fpu softvfp + ARM GAS /tmp/cc6LDhZP.s page 45 + + + 747 FLASH_WaitForLastOperation: + 748 .LVL38: + 749 .LFB308: + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t error; + 750 .loc 1 593 1 is_stmt 1 view -0 + 751 .cfi_startproc + 752 @ args = 0, pretend = 0, frame = 0 + 753 @ frame_needed = 0, uses_anonymous_args = 0 + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** uint32_t error; + 754 .loc 1 593 1 is_stmt 0 view .LVU175 + 755 0000 70B5 push {r4, r5, r6, lr} + 756 .LCFI3: + 757 .cfi_def_cfa_offset 16 + 758 .cfi_offset 4, -16 + 759 .cfi_offset 5, -12 + 760 .cfi_offset 6, -8 + 761 .cfi_offset 14, -4 + 762 0002 0500 movs r5, r0 + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + 763 .loc 1 594 3 is_stmt 1 view .LVU176 + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 764 .loc 1 598 3 view .LVU177 + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 765 .loc 1 598 22 is_stmt 0 view .LVU178 + 766 0004 FFF7FEFF bl HAL_GetTick + 767 .LVL39: + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 768 .loc 1 598 12 view .LVU179 + 769 0008 4419 adds r4, r0, r5 + 770 .LVL40: + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** #endif /* FLASH_DBANK_SUPPORT */ + 771 .loc 1 604 3 is_stmt 1 view .LVU180 + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 772 .loc 1 607 3 view .LVU181 + 773 .L57: + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 774 .loc 1 607 9 view .LVU182 + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 775 .loc 1 607 16 is_stmt 0 view .LVU183 + 776 000a 134B ldr r3, .L67 + 777 000c 1B69 ldr r3, [r3, #16] + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 778 .loc 1 607 9 view .LVU184 + 779 000e DB03 lsls r3, r3, #15 + 780 0010 05D5 bpl .L65 + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 781 .loc 1 609 5 is_stmt 1 view .LVU185 + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 782 .loc 1 609 9 is_stmt 0 view .LVU186 + 783 0012 FFF7FEFF bl HAL_GetTick + 784 .LVL41: + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 785 .loc 1 609 8 view .LVU187 + 786 0016 A042 cmp r0, r4 + 787 0018 F7D3 bcc .L57 + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 788 .loc 1 611 14 view .LVU188 + ARM GAS /tmp/cc6LDhZP.s page 46 + + + 789 001a 0320 movs r0, #3 + 790 .LVL42: + 791 .L58: + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 792 .loc 1 640 1 view .LVU189 + 793 @ sp needed + 794 001c 70BD pop {r4, r5, r6, pc} + 795 .LVL43: + 796 .L65: + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 797 .loc 1 616 3 is_stmt 1 view .LVU190 + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 798 .loc 1 616 17 is_stmt 0 view .LVU191 + 799 001e 0E49 ldr r1, .L67 + 800 0020 0A69 ldr r2, [r1, #16] + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 801 .loc 1 616 9 view .LVU192 + 802 0022 0E4B ldr r3, .L67+4 + 803 0024 1400 movs r4, r2 + 804 .LVL44: + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 805 .loc 1 616 9 view .LVU193 + 806 0026 1C40 ands r4, r3 + 807 .LVL45: + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 808 .loc 1 619 3 is_stmt 1 view .LVU194 + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 809 .loc 1 619 13 is_stmt 0 view .LVU195 + 810 0028 0D48 ldr r0, .L67+8 + 811 002a 0861 str r0, [r1, #16] + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 812 .loc 1 621 3 is_stmt 1 view .LVU196 + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 813 .loc 1 621 6 is_stmt 0 view .LVU197 + 814 002c 1A42 tst r2, r3 + 815 002e 03D0 beq .L60 + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_ERROR; + 816 .loc 1 624 5 is_stmt 1 view .LVU198 + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** return HAL_ERROR; + 817 .loc 1 624 22 is_stmt 0 view .LVU199 + 818 0030 0C4B ldr r3, .L67+12 + 819 0032 5C60 str r4, [r3, #4] + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 820 .loc 1 625 5 is_stmt 1 view .LVU200 + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 821 .loc 1 625 12 is_stmt 0 view .LVU201 + 822 0034 0120 movs r0, #1 + 823 0036 F1E7 b .L58 + 824 .L60: + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 825 .loc 1 629 3 is_stmt 1 view .LVU202 + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 826 .loc 1 629 13 is_stmt 0 view .LVU203 + 827 0038 FFF7FEFF bl HAL_GetTick + 828 .LVL46: + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 829 .loc 1 629 11 view .LVU204 + ARM GAS /tmp/cc6LDhZP.s page 47 + + + 830 003c 4519 adds r5, r0, r5 + 831 .LVL47: + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 832 .loc 1 631 3 is_stmt 1 view .LVU205 + 833 .L61: + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 834 .loc 1 631 9 view .LVU206 + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 835 .loc 1 631 16 is_stmt 0 view .LVU207 + 836 003e 064B ldr r3, .L67 + 837 0040 1B69 ldr r3, [r3, #16] + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 838 .loc 1 631 9 view .LVU208 + 839 0042 5B03 lsls r3, r3, #13 + 840 0044 05D5 bpl .L66 + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 841 .loc 1 633 5 is_stmt 1 view .LVU209 + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 842 .loc 1 633 9 is_stmt 0 view .LVU210 + 843 0046 FFF7FEFF bl HAL_GetTick + 844 .LVL48: + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 845 .loc 1 633 8 view .LVU211 + 846 004a A842 cmp r0, r5 + 847 004c F7D3 bcc .L61 + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 848 .loc 1 635 14 view .LVU212 + 849 004e 0320 movs r0, #3 + 850 0050 E4E7 b .L58 + 851 .L66: + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 852 .loc 1 639 10 view .LVU213 + 853 0052 0020 movs r0, #0 + 854 0054 E2E7 b .L58 + 855 .L68: + 856 0056 C046 .align 2 + 857 .L67: + 858 0058 00200240 .word 1073881088 + 859 005c FAC30000 .word 50170 + 860 0060 FBC30000 .word 50171 + 861 0064 00000000 .word .LANCHOR0 + 862 .cfi_endproc + 863 .LFE308: + 865 .section .text.HAL_FLASH_Program,"ax",%progbits + 866 .align 1 + 867 .global HAL_FLASH_Program + 868 .syntax unified + 869 .code 16 + 870 .thumb_func + 871 .fpu softvfp + 873 HAL_FLASH_Program: + 874 .LVL49: + 875 .LFB297: + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 876 .loc 1 167 1 is_stmt 1 view -0 + 877 .cfi_startproc + 878 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/cc6LDhZP.s page 48 + + + 879 @ frame_needed = 0, uses_anonymous_args = 0 + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 880 .loc 1 167 1 is_stmt 0 view .LVU215 + 881 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 882 .LCFI4: + 883 .cfi_def_cfa_offset 24 + 884 .cfi_offset 3, -24 + 885 .cfi_offset 4, -20 + 886 .cfi_offset 5, -16 + 887 .cfi_offset 6, -12 + 888 .cfi_offset 7, -8 + 889 .cfi_offset 14, -4 + 890 0002 0700 movs r7, r0 + 891 0004 0C00 movs r4, r1 + 892 0006 1500 movs r5, r2 + 893 0008 1E00 movs r6, r3 + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 894 .loc 1 168 3 is_stmt 1 view .LVU216 + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 895 .loc 1 171 3 view .LVU217 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 896 .loc 1 174 3 view .LVU218 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 897 .loc 1 174 3 view .LVU219 + 898 000a 144B ldr r3, .L76 + 899 000c 1B78 ldrb r3, [r3] + 900 000e 012B cmp r3, #1 + 901 0010 22D0 beq .L74 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 902 .loc 1 174 3 discriminator 2 view .LVU220 + 903 0012 124B ldr r3, .L76 + 904 0014 0122 movs r2, #1 + 905 .LVL50: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 906 .loc 1 174 3 is_stmt 0 discriminator 2 view .LVU221 + 907 0016 1A70 strb r2, [r3] + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 908 .loc 1 174 3 is_stmt 1 discriminator 2 view .LVU222 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 909 .loc 1 177 3 discriminator 2 view .LVU223 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 910 .loc 1 177 20 is_stmt 0 discriminator 2 view .LVU224 + 911 0018 0022 movs r2, #0 + 912 001a 5A60 str r2, [r3, #4] + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 913 .loc 1 180 3 is_stmt 1 discriminator 2 view .LVU225 + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 914 .loc 1 180 12 is_stmt 0 discriminator 2 view .LVU226 + 915 001c FA20 movs r0, #250 + 916 .LVL51: + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 917 .loc 1 180 12 discriminator 2 view .LVU227 + 918 001e 8000 lsls r0, r0, #2 + 919 0020 FFF7FEFF bl FLASH_WaitForLastOperation + 920 .LVL52: + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 921 .loc 1 182 3 is_stmt 1 discriminator 2 view .LVU228 + ARM GAS /tmp/cc6LDhZP.s page 49 + + + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 922 .loc 1 182 6 is_stmt 0 discriminator 2 view .LVU229 + 923 0024 0028 cmp r0, #0 + 924 0026 0DD1 bne .L71 + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 925 .loc 1 184 5 is_stmt 1 view .LVU230 + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 926 .loc 1 184 8 is_stmt 0 view .LVU231 + 927 0028 012F cmp r7, #1 + 928 002a 0FD0 beq .L75 + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 929 .loc 1 195 7 is_stmt 1 view .LVU232 + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 930 .loc 1 198 7 view .LVU233 + 931 002c 2900 movs r1, r5 + 932 002e 2000 movs r0, r4 + 933 .LVL53: + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 934 .loc 1 198 7 is_stmt 0 view .LVU234 + 935 0030 FFF7FEFF bl FLASH_Program_Fast + 936 .LVL54: + 937 .L73: + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 938 .loc 1 202 5 is_stmt 1 view .LVU235 + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 939 .loc 1 202 14 is_stmt 0 view .LVU236 + 940 0034 FA20 movs r0, #250 + 941 0036 8000 lsls r0, r0, #2 + 942 0038 FFF7FEFF bl FLASH_WaitForLastOperation + 943 .LVL55: + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 944 .loc 1 205 5 is_stmt 1 view .LVU237 + 945 003c 084A ldr r2, .L76+4 + 946 003e 5369 ldr r3, [r2, #20] + 947 0040 BB43 bics r3, r7 + 948 0042 5361 str r3, [r2, #20] + 949 .LVL56: + 950 .L71: + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 951 .loc 1 209 3 view .LVU238 + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 952 .loc 1 209 3 view .LVU239 + 953 0044 054B ldr r3, .L76 + 954 0046 0022 movs r2, #0 + 955 0048 1A70 strb r2, [r3] + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 956 .loc 1 209 3 view .LVU240 + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 957 .loc 1 212 3 view .LVU241 + 958 .LVL57: + 959 .L70: + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 960 .loc 1 213 1 is_stmt 0 view .LVU242 + 961 @ sp needed + 962 .LVL58: + 963 .LVL59: + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + ARM GAS /tmp/cc6LDhZP.s page 50 + + + 964 .loc 1 213 1 view .LVU243 + 965 004a F8BD pop {r3, r4, r5, r6, r7, pc} + 966 .LVL60: + 967 .L75: + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 968 .loc 1 187 7 is_stmt 1 view .LVU244 + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 969 .loc 1 190 7 view .LVU245 + 970 004c 2A00 movs r2, r5 + 971 004e 3300 movs r3, r6 + 972 0050 2000 movs r0, r4 + 973 .LVL61: + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 974 .loc 1 190 7 is_stmt 0 view .LVU246 + 975 0052 FFF7FEFF bl FLASH_Program_DoubleWord + 976 .LVL62: + 977 0056 EDE7 b .L73 + 978 .LVL63: + 979 .L74: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 980 .loc 1 174 3 view .LVU247 + 981 0058 0220 movs r0, #2 + 982 .LVL64: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 983 .loc 1 174 3 view .LVU248 + 984 005a F6E7 b .L70 + 985 .L77: + 986 .align 2 + 987 .L76: + 988 005c 00000000 .word .LANCHOR0 + 989 0060 00200240 .word 1073881088 + 990 .cfi_endproc + 991 .LFE297: + 993 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 994 .align 1 + 995 .global HAL_FLASH_Program_IT + 996 .syntax unified + 997 .code 16 + 998 .thumb_func + 999 .fpu softvfp + 1001 HAL_FLASH_Program_IT: + 1002 .LVL65: + 1003 .LFB298: + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 1004 .loc 1 229 1 is_stmt 1 view -0 + 1005 .cfi_startproc + 1006 @ args = 0, pretend = 0, frame = 8 + 1007 @ frame_needed = 0, uses_anonymous_args = 0 + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** HAL_StatusTypeDef status; + 1008 .loc 1 229 1 is_stmt 0 view .LVU250 + 1009 0000 F0B5 push {r4, r5, r6, r7, lr} + 1010 .LCFI5: + 1011 .cfi_def_cfa_offset 20 + 1012 .cfi_offset 4, -20 + 1013 .cfi_offset 5, -16 + 1014 .cfi_offset 6, -12 + 1015 .cfi_offset 7, -8 + ARM GAS /tmp/cc6LDhZP.s page 51 + + + 1016 .cfi_offset 14, -4 + 1017 0002 83B0 sub sp, sp, #12 + 1018 .LCFI6: + 1019 .cfi_def_cfa_offset 32 + 1020 0004 0500 movs r5, r0 + 1021 0006 0F00 movs r7, r1 + 1022 0008 1600 movs r6, r2 + 1023 000a 0193 str r3, [sp, #4] + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1024 .loc 1 230 3 is_stmt 1 view .LVU251 + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1025 .loc 1 233 3 view .LVU252 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1026 .loc 1 236 3 view .LVU253 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1027 .loc 1 236 3 view .LVU254 + 1028 000c 164B ldr r3, .L84 + 1029 000e 1B78 ldrb r3, [r3] + 1030 0010 012B cmp r3, #1 + 1031 0012 26D0 beq .L82 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1032 .loc 1 236 3 discriminator 2 view .LVU255 + 1033 0014 144B ldr r3, .L84 + 1034 0016 0122 movs r2, #1 + 1035 .LVL66: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1036 .loc 1 236 3 is_stmt 0 discriminator 2 view .LVU256 + 1037 0018 1A70 strb r2, [r3] + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1038 .loc 1 236 3 is_stmt 1 discriminator 2 view .LVU257 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1039 .loc 1 239 3 discriminator 2 view .LVU258 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1040 .loc 1 239 20 is_stmt 0 discriminator 2 view .LVU259 + 1041 001a 0022 movs r2, #0 + 1042 001c 5A60 str r2, [r3, #4] + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1043 .loc 1 242 3 is_stmt 1 discriminator 2 view .LVU260 + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1044 .loc 1 242 12 is_stmt 0 discriminator 2 view .LVU261 + 1045 001e FA20 movs r0, #250 + 1046 .LVL67: + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1047 .loc 1 242 12 discriminator 2 view .LVU262 + 1048 0020 8000 lsls r0, r0, #2 + 1049 0022 FFF7FEFF bl FLASH_WaitForLastOperation + 1050 .LVL68: + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1051 .loc 1 242 12 discriminator 2 view .LVU263 + 1052 0026 041E subs r4, r0, #0 + 1053 .LVL69: + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 1054 .loc 1 244 3 is_stmt 1 discriminator 2 view .LVU264 + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 1055 .loc 1 244 6 is_stmt 0 discriminator 2 view .LVU265 + 1056 0028 05D0 beq .L80 + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + ARM GAS /tmp/cc6LDhZP.s page 52 + + + 1057 .loc 1 247 5 is_stmt 1 view .LVU266 + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 1058 .loc 1 247 5 view .LVU267 + 1059 002a 0F4B ldr r3, .L84 + 1060 002c 0022 movs r2, #0 + 1061 002e 1A70 strb r2, [r3] + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 1062 .loc 1 247 5 view .LVU268 + 1063 .LVL70: + 1064 .L79: + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1065 .loc 1 278 1 is_stmt 0 view .LVU269 + 1066 0030 2000 movs r0, r4 + 1067 0032 03B0 add sp, sp, #12 + 1068 @ sp needed + 1069 .LVL71: + 1070 .LVL72: + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1071 .loc 1 278 1 view .LVU270 + 1072 0034 F0BD pop {r4, r5, r6, r7, pc} + 1073 .LVL73: + 1074 .L80: + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.Address = Address; + 1075 .loc 1 252 5 is_stmt 1 view .LVU271 + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** pFlash.Address = Address; + 1076 .loc 1 252 29 is_stmt 0 view .LVU272 + 1077 0036 0C4B ldr r3, .L84 + 1078 0038 9D60 str r5, [r3, #8] + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1079 .loc 1 253 5 is_stmt 1 view .LVU273 + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1080 .loc 1 253 20 is_stmt 0 view .LVU274 + 1081 003a DF60 str r7, [r3, #12] + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1082 .loc 1 256 5 is_stmt 1 view .LVU275 + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1083 .loc 1 256 15 is_stmt 0 view .LVU276 + 1084 003c 0B4A ldr r2, .L84+4 + 1085 003e 5169 ldr r1, [r2, #20] + 1086 0040 C023 movs r3, #192 + 1087 0042 9B04 lsls r3, r3, #18 + 1088 0044 0B43 orrs r3, r1 + 1089 0046 5361 str r3, [r2, #20] + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 1090 .loc 1 258 5 is_stmt 1 view .LVU277 + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** { + 1091 .loc 1 258 8 is_stmt 0 view .LVU278 + 1092 0048 012D cmp r5, #1 + 1093 004a 04D0 beq .L83 + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1094 .loc 1 269 7 is_stmt 1 view .LVU279 + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 1095 .loc 1 272 7 view .LVU280 + 1096 004c 3100 movs r1, r6 + 1097 004e 3800 movs r0, r7 + 1098 .LVL74: + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + ARM GAS /tmp/cc6LDhZP.s page 53 + + + 1099 .loc 1 272 7 is_stmt 0 view .LVU281 + 1100 0050 FFF7FEFF bl FLASH_Program_Fast + 1101 .LVL75: + 1102 0054 ECE7 b .L79 + 1103 .LVL76: + 1104 .L83: + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1105 .loc 1 261 7 is_stmt 1 view .LVU282 + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 1106 .loc 1 264 7 view .LVU283 + 1107 0056 3200 movs r2, r6 + 1108 0058 019B ldr r3, [sp, #4] + 1109 005a 3800 movs r0, r7 + 1110 .LVL77: + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** } + 1111 .loc 1 264 7 is_stmt 0 view .LVU284 + 1112 005c FFF7FEFF bl FLASH_Program_DoubleWord + 1113 .LVL78: + 1114 0060 E6E7 b .L79 + 1115 .LVL79: + 1116 .L82: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c **** + 1117 .loc 1 236 3 view .LVU285 + 1118 0062 0224 movs r4, #2 + 1119 0064 E4E7 b .L79 + 1120 .L85: + 1121 0066 C046 .align 2 + 1122 .L84: + 1123 0068 00000000 .word .LANCHOR0 + 1124 006c 00200240 .word 1073881088 + 1125 .cfi_endproc + 1126 .LFE298: + 1128 .global pFlash + 1129 .section .bss.pFlash,"aw",%nobits + 1130 .align 2 + 1131 .set .LANCHOR0,. + 0 + 1134 pFlash: + 1135 0000 00000000 .space 28 + 1135 00000000 + 1135 00000000 + 1135 00000000 + 1135 00000000 + 1136 .text + 1137 .Letext0: + 1138 .file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1139 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1140 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1141 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h" + 1142 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + 1143 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h" + 1144 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/cc6LDhZP.s page 54 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_flash.c + /tmp/cc6LDhZP.s:16 .text.FLASH_Program_DoubleWord:0000000000000000 $t + /tmp/cc6LDhZP.s:23 .text.FLASH_Program_DoubleWord:0000000000000000 FLASH_Program_DoubleWord + /tmp/cc6LDhZP.s:71 .text.FLASH_Program_DoubleWord:0000000000000018 $d + /tmp/cc6LDhZP.s:76 .RamFunc:0000000000000000 $t + /tmp/cc6LDhZP.s:82 .RamFunc:0000000000000000 FLASH_Program_Fast + /tmp/cc6LDhZP.s:203 .RamFunc:0000000000000034 $d + /tmp/cc6LDhZP.s:208 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 $t + /tmp/cc6LDhZP.s:215 .text.HAL_FLASH_EndOfOperationCallback:0000000000000000 HAL_FLASH_EndOfOperationCallback + /tmp/cc6LDhZP.s:231 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 $t + /tmp/cc6LDhZP.s:238 .text.HAL_FLASH_OperationErrorCallback:0000000000000000 HAL_FLASH_OperationErrorCallback + /tmp/cc6LDhZP.s:254 .text.HAL_FLASH_IRQHandler:0000000000000000 $t + /tmp/cc6LDhZP.s:261 .text.HAL_FLASH_IRQHandler:0000000000000000 HAL_FLASH_IRQHandler + /tmp/cc6LDhZP.s:443 .text.HAL_FLASH_IRQHandler:00000000000000b0 $d + /tmp/cc6LDhZP.s:452 .text.HAL_FLASH_Unlock:0000000000000000 $t + /tmp/cc6LDhZP.s:459 .text.HAL_FLASH_Unlock:0000000000000000 HAL_FLASH_Unlock + /tmp/cc6LDhZP.s:508 .text.HAL_FLASH_Unlock:0000000000000024 $d + /tmp/cc6LDhZP.s:515 .text.HAL_FLASH_Lock:0000000000000000 $t + /tmp/cc6LDhZP.s:522 .text.HAL_FLASH_Lock:0000000000000000 HAL_FLASH_Lock + /tmp/cc6LDhZP.s:560 .text.HAL_FLASH_Lock:000000000000001c $d + /tmp/cc6LDhZP.s:565 .text.HAL_FLASH_OB_Unlock:0000000000000000 $t + /tmp/cc6LDhZP.s:572 .text.HAL_FLASH_OB_Unlock:0000000000000000 HAL_FLASH_OB_Unlock + /tmp/cc6LDhZP.s:620 .text.HAL_FLASH_OB_Unlock:0000000000000024 $d + /tmp/cc6LDhZP.s:627 .text.HAL_FLASH_OB_Lock:0000000000000000 $t + /tmp/cc6LDhZP.s:634 .text.HAL_FLASH_OB_Lock:0000000000000000 HAL_FLASH_OB_Lock + /tmp/cc6LDhZP.s:672 .text.HAL_FLASH_OB_Lock:000000000000001c $d + /tmp/cc6LDhZP.s:677 .text.HAL_FLASH_OB_Launch:0000000000000000 $t + /tmp/cc6LDhZP.s:684 .text.HAL_FLASH_OB_Launch:0000000000000000 HAL_FLASH_OB_Launch + /tmp/cc6LDhZP.s:706 .text.HAL_FLASH_OB_Launch:0000000000000010 $d + /tmp/cc6LDhZP.s:711 .text.HAL_FLASH_GetError:0000000000000000 $t + /tmp/cc6LDhZP.s:718 .text.HAL_FLASH_GetError:0000000000000000 HAL_FLASH_GetError + /tmp/cc6LDhZP.s:735 .text.HAL_FLASH_GetError:0000000000000008 $d + /tmp/cc6LDhZP.s:740 .text.FLASH_WaitForLastOperation:0000000000000000 $t + /tmp/cc6LDhZP.s:747 .text.FLASH_WaitForLastOperation:0000000000000000 FLASH_WaitForLastOperation + /tmp/cc6LDhZP.s:858 .text.FLASH_WaitForLastOperation:0000000000000058 $d + /tmp/cc6LDhZP.s:866 .text.HAL_FLASH_Program:0000000000000000 $t + /tmp/cc6LDhZP.s:873 .text.HAL_FLASH_Program:0000000000000000 HAL_FLASH_Program + /tmp/cc6LDhZP.s:988 .text.HAL_FLASH_Program:000000000000005c $d + /tmp/cc6LDhZP.s:994 .text.HAL_FLASH_Program_IT:0000000000000000 $t + /tmp/cc6LDhZP.s:1001 .text.HAL_FLASH_Program_IT:0000000000000000 HAL_FLASH_Program_IT + /tmp/cc6LDhZP.s:1123 .text.HAL_FLASH_Program_IT:0000000000000068 $d + /tmp/cc6LDhZP.s:1134 .bss.pFlash:0000000000000000 pFlash + /tmp/cc6LDhZP.s:1130 .bss.pFlash:0000000000000000 $d + +UNDEFINED SYMBOLS +FLASH_PageErase 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© Copyright (c) 2018 STMicroelectronics. + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * All rights reserved.
+ 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the "License"; You may not use this file except in compliance with the + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * License. You may obtain a copy of the License at: + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * opensource.org/licenses/BSD-3-Clause + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ****************************************************************************** + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #include "stm32g0xx_hal.h" + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief FLASH Extended HAL module driver + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + ARM GAS /tmp/ccHUARcC.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_MassErase(uint32_t Banks); + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void FLASH_FlushCaches(void); + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WR + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRD + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPL + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void); + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void); + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_PCROP_SUPPORT) + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t PCROP1AEndAddr); + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t *PCROP1AEndAddr); + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr) + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr) + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_PCROP_SUPPORT */ + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecS + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecS + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #else + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize); + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize); + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @} + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Exported functions -------------------------------------------------------*/ + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Extended IO operation functions + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** @verbatim + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** =============================================================================== + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ##### Extended programming operation functions ##### + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** =============================================================================== + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** [..] + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** This subsection provides a set of functions allowing to manage the Extended FLASH + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** programming operations Operations. + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** @endverbatim + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + ARM GAS /tmp/ccHUARcC.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages. + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param[out] PageError Pointer to variable that contains the configuration + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * information on faulty page in case of error (0xFFFFFFFF means that all + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the pages have been correctly erased) + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval HAL Status + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t index; + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Locked */ + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Reset error code */ + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (status == HAL_OK) + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if !defined(FLASH_DBANK_SUPPORT) + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* For single bank product force Banks to Bank 1 */ + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pEraseInit->Banks = FLASH_BANK_1; + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Proceed to Mass Erase */ + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_MassErase(pEraseInit->Banks); + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /*Initialization of PageError variable*/ + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PageError = 0xFFFFFFFFU; + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Start erase page */ + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_PageErase(pEraseInit->Banks, index); + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (status != HAL_OK) + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty address */ + ARM GAS /tmp/ccHUARcC.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PageError = index; + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** break; + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* If operation is completed or interrupted, disable the Page Erase Bit */ + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Unlocked */ + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* return status */ + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return status; + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval HAL Status + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Locked */ + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Reset error code */ + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* save procedure for interrupt treatment */ + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (status != HAL_OK) + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Unlocked */ + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if !defined(FLASH_DBANK_SUPPORT) + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* For single bank product force Banks to Bank 1 */ + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pEraseInit->Banks = FLASH_BANK_1; + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Store Bank number */ + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.Banks = pEraseInit->Banks; + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + ARM GAS /tmp/ccHUARcC.s page 6 + + + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable End of Operation and Error interrupts */ + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Page to 0 for Interrupt callback management */ + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.Page = 0; + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Proceed to Mass Erase */ + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_MassErase(pEraseInit->Banks); + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Erase by page to be done */ + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.NbPagesToErase = pEraseInit->NbPages; + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.Page = pEraseInit->Page; + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /*Erase 1st page and wait for IT */ + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_PageErase(pEraseInit->Banks, pEraseInit->Page); + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* return status */ + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return status; + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Program Option bytes. + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note To configure any option bytes, the option lock bit OPTLOCK must be + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note New option bytes configuration will be taken into account only + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * - a Power On Reset + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * - an exit from Standby or Shutdown mode. + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval HAL Status + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t optr; + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Locked */ + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Write protection configuration */ + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U) + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure of Write protection on the selected area */ + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 7 + + + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Option register */ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_US + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Fully modify OPTR register with RDP & user data */ + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel); + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U) + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Only modify RDP so get current user data */ + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** optr = FLASH_OB_GetUser(); + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U) + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Only modify user so get current RDP level */ + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** optr = FLASH_OB_GetRDP(); + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* nothing to do */ + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_PCROP_SUPPORT) + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* PCROP Configuration */ + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U) + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U) + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the 1A Proprietary code readout protection */ + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAd + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U) + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the 1B Proprietary code readout protection */ + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_A) != 0x00U) + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the 2A Proprietary code readout protection */ + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_PCROP2AConfig(pOBInit->PCROP2AStartAddr, pOBInit->PCROP2AEndAddr); + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_B) != 0x00U) + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the 2B Proprietary code readout protection */ + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr); + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 8 + + + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_PCROP_SUPPORT */ + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Securable Memory Area Configuration */ + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U) + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the securable memory area protection */ + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize, pOBInit->SecSize2); + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #else + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the securable memory area protection */ + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (status == HAL_OK) + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set OPTSTRT Bit */ + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Process Unlocked */ + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* return status */ + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return status; + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Get the Option bytes configuration. + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note warning: this API only read flash register, it does not reflect any + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * change that would have been programmed between previous Option byte + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * loading and current call. + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * configuration information. The fields pOBInit->WRPArea should + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * indicate which area is requested for the WRP. + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_ALL; + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get write protection on the selected area */ + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get Read protection level */ + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + ARM GAS /tmp/ccHUARcC.s page 9 + + + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get the user option bytes */ + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->USERType = OB_USER_ALL; + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_PCROP_SUPPORT) + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get the Proprietary code readout protection */ + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndA + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr)); + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr)); + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B); + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_PCROP_SUPPORT */ + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get the Securable Memory Area protection */ + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize), &(pOBInit->SecSize2)); + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #else + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get the Securable Memory Area protection */ + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize)); + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_ACR_DBG_SWEN) + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Enable Debugger. + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note After calling this API, flash interface allow debugger intrusion. + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void HAL_FLASHEx_EnableDebugger(void) + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR |= FLASH_ACR_DBG_SWEN; + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Disable Debugger. + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note After calling this API, Debugger is disabled: it is no more possible to + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * break, see CPU register, etc... + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void HAL_FLASHEx_DisableDebugger(void) + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_ACR_DBG_SWEN */ + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Flash Empty check + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note This API checks if first location in Flash is programmed or not. + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This check is done once by Option Byte Loader. + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval 0 if 1st location is not programmed else + ARM GAS /tmp/ccHUARcC.s page 10 + + + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t HAL_FLASHEx_FlashEmptyCheck(void) + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return ((FLASH->ACR & FLASH_ACR_PROGEMPTY)); + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Force Empty check value. + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note Allows to modify program empty check value in order to force this + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * infrmation in Flash Interface, for all next reset that do not launch + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * Option Byte Loader. + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty) + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t acr; + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY); + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR = (acr | FlashEmpty); + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Securable memory area protection enable + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param Banks Select Bank to be secured. + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be a value of @ref FLASH_Banks + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1. + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note This API locks Securable memory area which is defined in SEC_SIZE option byte + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * Secsize). + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note SEC_PROT bit can only be set, it will be reset by system reset. + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks) + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (Banks == (FLASH_BANK_2 | FLASH_BANK_1)) + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR |= (FLASH_CR_SEC_PROT2 | FLASH_CR_SEC_PROT); + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if (Banks == FLASH_BANK_2) + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_SEC_PROT2; + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #else + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** UNUSED(Banks); + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR |= FLASH_CR_SEC_PROT; + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 11 + + + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @} + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @} + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Private functions ---------------------------------------------------------*/ + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @{ + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Mass erase of FLASH memory. + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param Banks: Banks to be erased + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be a combination of the following values: + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Bank1 to be erased + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Bank2 to be erased* + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_MassErase(uint32_t Banks) + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 27 .loc 1 571 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 32 .loc 1 573 3 view .LVU1 + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set the Mass Erase Bit and start bit */ + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR |= (FLASH_CR_STRT | Banks); + 33 .loc 1 576 3 view .LVU2 + 34 .loc 1 576 13 is_stmt 0 view .LVU3 + 35 0000 034A ldr r2, .L2 + 36 0002 5369 ldr r3, [r2, #20] + 37 0004 0343 orrs r3, r0 + 38 0006 8020 movs r0, #128 + 39 .LVL1: + 40 .loc 1 576 13 view .LVU4 + 41 0008 4002 lsls r0, r0, #9 + 42 000a 1843 orrs r0, r3 + 43 000c 5061 str r0, [r2, #20] + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 44 .loc 1 577 1 view .LVU5 + 45 @ sp needed + 46 000e 7047 bx lr + 47 .L3: + 48 .align 2 + 49 .L2: + 50 0010 00200240 .word 1073881088 + 51 .cfi_endproc + ARM GAS /tmp/ccHUARcC.s page 12 + + + 52 .LFE306: + 54 .section .text.FLASH_OB_WRPConfig,"ax",%progbits + 55 .align 1 + 56 .syntax unified + 57 .code 16 + 58 .thumb_func + 59 .fpu softvfp + 61 FLASH_OB_WRPConfig: + 62 .LVL2: + 63 .LFB309: + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory page. + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param Banks: Banks to be erased + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can one of the following values: + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg FLASH_BANK_1: Bank1 to be erased + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg FLASH_BANK_2: Bank2 to be erased* + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param Page FLASH page to erase + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter must be a value between 0 and (max number of pages in Flash - 1) + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t Banks, uint32_t Page) + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t tmp; + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_BANK(Banks)); + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PAGE(Page)); + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get configuration register, then clear page number */ + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** tmp = (FLASH->CR & ~FLASH_CR_PNB); + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if page has to be erased in bank 1 or 2 */ + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (Banks != FLASH_BANK_1) + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** tmp |= FLASH_CR_BKER; + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** tmp &= ~FLASH_CR_BKER; + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set page number, Page Erase bit & Start bit */ + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Flush the instruction cache. + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** void FLASH_FlushCaches(void) + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Flush instruction cache */ + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) + ARM GAS /tmp/ccHUARcC.s page 13 + + + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Disable instruction cache */ + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Reset instruction cache */ + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable instruction cache */ + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure the write protection of the desired pages. + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note When WRP is active in a zone, it cannot be erased or programmed. + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * Consequently, a software mass erase cannot be performed if one zone + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * is write-protected. + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * it is not possible to program or erase Flash memory if the CPU debug + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * features are connected (JTAG or single wire) or boot code is being + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * executed from RAM or System flash, even if WRP is not activated. + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param WRPArea Specifies the area to be configured. + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param WRPStartOffset Specifies the start page of the write protected area + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be page number between 0 and (max number of pages in the Flash Bank + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param WRDPEndOffset Specifies the end page of the write protected area + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be page number between WRPStartOffset and (max number of pages in th + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 64 .loc 1 659 1 is_stmt 1 view -0 + 65 .cfi_startproc + 66 @ args = 0, pretend = 0, frame = 0 + 67 @ frame_needed = 0, uses_anonymous_args = 0 + 68 @ link register save eliminated. + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_WRPAREA(WRPArea)); + 69 .loc 1 661 3 view .LVU7 + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PAGE(WRPStartOffset)); + 70 .loc 1 662 3 view .LVU8 + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PAGE(WRDPEndOffset)); + 71 .loc 1 663 3 view .LVU9 + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the write protected area */ + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (WRPArea == OB_WRPAREA_ZONE_A) + 72 .loc 1 666 3 view .LVU10 + 73 .loc 1 666 6 is_stmt 0 view .LVU11 + 74 0000 0128 cmp r0, #1 + 75 0002 04D0 beq .L7 + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 14 + + + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if (WRPArea == OB_WRPAREA_ZONE2_A) + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset); + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if (WRPArea == OB_WRPAREA_ZONE2_B) + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); + 76 .loc 1 682 5 is_stmt 1 view .LVU12 + 77 .loc 1 682 37 is_stmt 0 view .LVU13 + 78 0004 1204 lsls r2, r2, #16 + 79 .LVL3: + 80 .loc 1 682 68 view .LVU14 + 81 0006 0A43 orrs r2, r1 + 82 .loc 1 682 19 view .LVU15 + 83 0008 034B ldr r3, .L8 + 84 000a 1A63 str r2, [r3, #48] + 85 .L4: + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 86 .loc 1 684 1 view .LVU16 + 87 @ sp needed + 88 000c 7047 bx lr + 89 .LVL4: + 90 .L7: + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 91 .loc 1 668 5 is_stmt 1 view .LVU17 + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 92 .loc 1 668 37 is_stmt 0 view .LVU18 + 93 000e 1204 lsls r2, r2, #16 + 94 .LVL5: + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 95 .loc 1 668 68 view .LVU19 + 96 0010 0A43 orrs r2, r1 + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 97 .loc 1 668 19 view .LVU20 + 98 0012 014B ldr r3, .L8 + 99 0014 DA62 str r2, [r3, #44] + 100 0016 F9E7 b .L4 + 101 .L9: + 102 .align 2 + 103 .L8: + 104 0018 00200240 .word 1073881088 + 105 .cfi_endproc + 106 .LFE309: + 108 .section .text.FLASH_OB_GetWRP,"ax",%progbits + 109 .align 1 + 110 .syntax unified + 111 .code 16 + 112 .thumb_func + 113 .fpu softvfp + 115 FLASH_OB_GetWRP: + ARM GAS /tmp/ccHUARcC.s page 15 + + + 116 .LVL6: + 117 .LFB310: + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH Write Protection Option Bytes value. + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param[in] WRPArea Specifies the area to be returned. + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param[out] WRPStartOffset Specifies the address where to copied the start page + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * of the write protected area + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the write protected area + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 118 .loc 1 702 1 is_stmt 1 view -0 + 119 .cfi_startproc + 120 @ args = 0, pretend = 0, frame = 0 + 121 @ frame_needed = 0, uses_anonymous_args = 0 + 122 .loc 1 702 1 is_stmt 0 view .LVU22 + 123 0000 10B5 push {r4, lr} + 124 .LCFI0: + 125 .cfi_def_cfa_offset 8 + 126 .cfi_offset 4, -8 + 127 .cfi_offset 14, -4 + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_WRPAREA(WRPArea)); + 128 .loc 1 704 3 is_stmt 1 view .LVU23 + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Get the configuration of the write protected area */ + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (WRPArea == OB_WRPAREA_ZONE_A) + 129 .loc 1 707 3 view .LVU24 + 130 .loc 1 707 6 is_stmt 0 view .LVU25 + 131 0002 0128 cmp r0, #1 + 132 0004 09D0 beq .L13 + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if (WRPArea == OB_WRPAREA_ZONE2_A) + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else if (WRPArea == OB_WRPAREA_ZONE2_B) + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + ARM GAS /tmp/ccHUARcC.s page 16 + + + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); + 133 .loc 1 726 5 is_stmt 1 view .LVU26 + 134 .loc 1 726 23 is_stmt 0 view .LVU27 + 135 0006 0A4C ldr r4, .L14 + 136 0008 206B ldr r0, [r4, #48] + 137 .LVL7: + 138 .loc 1 726 23 view .LVU28 + 139 000a 1F23 movs r3, #31 + 140 000c 1840 ands r0, r3 + 141 .loc 1 726 21 view .LVU29 + 142 000e 0860 str r0, [r1] + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos + 143 .loc 1 727 5 is_stmt 1 view .LVU30 + 144 .loc 1 727 23 is_stmt 0 view .LVU31 + 145 0010 216B ldr r1, [r4, #48] + 146 .LVL8: + 147 .loc 1 727 71 view .LVU32 + 148 0012 090C lsrs r1, r1, #16 + 149 0014 0B40 ands r3, r1 + 150 .loc 1 727 20 view .LVU33 + 151 0016 1360 str r3, [r2] + 152 .L10: + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 153 .loc 1 729 1 view .LVU34 + 154 @ sp needed + 155 0018 10BD pop {r4, pc} + 156 .LVL9: + 157 .L13: + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos + 158 .loc 1 709 5 is_stmt 1 view .LVU35 + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos + 159 .loc 1 709 23 is_stmt 0 view .LVU36 + 160 001a 054C ldr r4, .L14 + 161 001c E06A ldr r0, [r4, #44] + 162 .LVL10: + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos + 163 .loc 1 709 23 view .LVU37 + 164 001e 1F23 movs r3, #31 + 165 0020 1840 ands r0, r3 + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos + 166 .loc 1 709 21 view .LVU38 + 167 0022 0860 str r0, [r1] + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 168 .loc 1 710 5 is_stmt 1 view .LVU39 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 169 .loc 1 710 23 is_stmt 0 view .LVU40 + 170 0024 E16A ldr r1, [r4, #44] + 171 .LVL11: + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 172 .loc 1 710 71 view .LVU41 + 173 0026 090C lsrs r1, r1, #16 + 174 0028 0B40 ands r3, r1 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 175 .loc 1 710 20 view .LVU42 + 176 002a 1360 str r3, [r2] + ARM GAS /tmp/ccHUARcC.s page 17 + + + 177 002c F4E7 b .L10 + 178 .L15: + 179 002e C046 .align 2 + 180 .L14: + 181 0030 00200240 .word 1073881088 + 182 .cfi_endproc + 183 .LFE310: + 185 .section .text.FLASH_OB_OptrConfig,"ax",%progbits + 186 .align 1 + 187 .syntax unified + 188 .code 16 + 189 .thumb_func + 190 .fpu softvfp + 192 FLASH_OB_OptrConfig: + 193 .LVL12: + 194 .LFB311: + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Set user & RDP configuration + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * to go back to level 1 or 0 !!! + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param UserType The FLASH User Option Bytes to be modified. + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be a combination of @ref FLASH_OB_USER_Type + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param UserConfig The FLASH User Option Bytes values. + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be a combination of: + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_STOP + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_STANDBY + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_SW + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_STOP + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_STANDBY + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_WWDG_SW + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_SRAM_PARITY + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT_SEL + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT1 + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT0 + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param RDPLevel specifies the read protection level. + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Memory Read protection + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 195 .loc 1 765 1 is_stmt 1 view -0 + 196 .cfi_startproc + 197 @ args = 0, pretend = 0, frame = 0 + 198 @ frame_needed = 0, uses_anonymous_args = 0 + 199 .loc 1 765 1 is_stmt 0 view .LVU44 + ARM GAS /tmp/ccHUARcC.s page 18 + + + 200 0000 30B5 push {r4, r5, lr} + 201 .LCFI1: + 202 .cfi_def_cfa_offset 12 + 203 .cfi_offset 4, -12 + 204 .cfi_offset 5, -8 + 205 .cfi_offset 14, -4 + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t optr; + 206 .loc 1 766 3 is_stmt 1 view .LVU45 + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_USER_TYPE(UserType)); + 207 .loc 1 769 3 view .LVU46 + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_USER_CONFIG(UserType, UserConfig)); + 208 .loc 1 770 3 view .LVU47 + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + 209 .loc 1 771 3 view .LVU48 + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the RDP level in the option bytes register */ + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** optr = FLASH->OPTR; + 210 .loc 1 774 3 view .LVU49 + 211 .loc 1 774 8 is_stmt 0 view .LVU50 + 212 0002 044C ldr r4, .L17 + 213 0004 236A ldr r3, [r4, #32] + 214 .LVL13: + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** optr &= ~(UserType | FLASH_OPTR_RDP); + 215 .loc 1 775 3 is_stmt 1 view .LVU51 + 216 .loc 1 775 22 is_stmt 0 view .LVU52 + 217 0006 FF25 movs r5, #255 + 218 0008 2843 orrs r0, r5 + 219 .LVL14: + 220 .loc 1 775 8 view .LVU53 + 221 000a 8343 bics r3, r0 + 222 .LVL15: + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->OPTR = (optr | UserConfig | RDPLevel); + 223 .loc 1 776 3 is_stmt 1 view .LVU54 + 224 .loc 1 776 23 is_stmt 0 view .LVU55 + 225 000c 0B43 orrs r3, r1 + 226 .LVL16: + 227 .loc 1 776 36 view .LVU56 + 228 000e 1343 orrs r3, r2 + 229 .loc 1 776 15 view .LVU57 + 230 0010 2362 str r3, [r4, #32] + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 231 .loc 1 777 1 view .LVU58 + 232 @ sp needed + 233 0012 30BD pop {r4, r5, pc} + 234 .L18: + 235 .align 2 + 236 .L17: + 237 0014 00200240 .word 1073881088 + 238 .cfi_endproc + 239 .LFE311: + 241 .section .text.FLASH_OB_GetRDP,"ax",%progbits + 242 .align 1 + 243 .syntax unified + 244 .code 16 + 245 .thumb_func + ARM GAS /tmp/ccHUARcC.s page 19 + + + 246 .fpu softvfp + 248 FLASH_OB_GetRDP: + 249 .LFB312: + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH Read Protection level. + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval FLASH ReadOut Protection Status: + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This return value can be one of the following values: + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void) + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 250 .loc 1 788 1 is_stmt 1 view -0 + 251 .cfi_startproc + 252 @ args = 0, pretend = 0, frame = 0 + 253 @ frame_needed = 0, uses_anonymous_args = 0 + 254 @ link register save eliminated. + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + 255 .loc 1 789 3 view .LVU60 + 256 .loc 1 789 21 is_stmt 0 view .LVU61 + 257 0000 044B ldr r3, .L22 + 258 0002 1B6A ldr r3, [r3, #32] + 259 .loc 1 789 12 view .LVU62 + 260 0004 FF20 movs r0, #255 + 261 0006 1840 ands r0, r3 + 262 .LVL17: + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2)) + 263 .loc 1 791 3 is_stmt 1 view .LVU63 + 264 .loc 1 791 6 is_stmt 0 view .LVU64 + 265 0008 AA28 cmp r0, #170 + 266 000a 02D0 beq .L19 + 267 .loc 1 791 34 discriminator 1 view .LVU65 + 268 000c CC28 cmp r0, #204 + 269 000e 00D0 beq .L19 + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return (OB_RDP_LEVEL_1); + 270 .loc 1 793 12 view .LVU66 + 271 0010 BB20 movs r0, #187 + 272 .LVL18: + 273 .L19: + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return rdplvl; + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 274 .loc 1 799 1 view .LVU67 + 275 @ sp needed + 276 0012 7047 bx lr + 277 .L23: + 278 .align 2 + 279 .L22: + 280 0014 00200240 .word 1073881088 + 281 .cfi_endproc + ARM GAS /tmp/ccHUARcC.s page 20 + + + 282 .LFE312: + 284 .section .text.FLASH_OB_GetUser,"ax",%progbits + 285 .align 1 + 286 .syntax unified + 287 .code 16 + 288 .thumb_func + 289 .fpu softvfp + 291 FLASH_OB_GetUser: + 292 .LFB313: + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values. It will be a combination of all the following value + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_STOP + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_STANDBY + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_SW + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_STOP + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_IWDG_STANDBY + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_WWDG_SW + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_SRAM_PARITY + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT_SEL + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT1 + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_nBOOT0 + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note (*) availability depends on devices + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetUser(void) + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 293 .loc 1 824 1 is_stmt 1 view -0 + 294 .cfi_startproc + 295 @ args = 0, pretend = 0, frame = 0 + 296 @ frame_needed = 0, uses_anonymous_args = 0 + 297 @ link register save eliminated. + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL); + 298 .loc 1 825 3 view .LVU69 + 299 .loc 1 825 26 is_stmt 0 view .LVU70 + 300 0000 024B ldr r3, .L25 + 301 0002 186A ldr r0, [r3, #32] + 302 .loc 1 825 12 view .LVU71 + 303 0004 024B ldr r3, .L25+4 + 304 0006 1840 ands r0, r3 + 305 .LVL19: + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return user; + 306 .loc 1 826 3 is_stmt 1 view .LVU72 + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 307 .loc 1 827 1 is_stmt 0 view .LVU73 + 308 @ sp needed + 309 0008 7047 bx lr + 310 .L26: + 311 000a C046 .align 2 + 312 .L25: + ARM GAS /tmp/ccHUARcC.s page 21 + + + 313 000c 00200240 .word 1073881088 + 314 0010 00FF4F3F .word 1062207232 + 315 .cfi_endproc + 316 .LFE313: + 318 .section .text.FLASH_OB_PCROP1AConfig,"ax",%progbits + 319 .align 1 + 320 .syntax unified + 321 .code 16 + 322 .thumb_func + 323 .fpu softvfp + 325 FLASH_OB_PCROP1AConfig: + 326 .LVL20: + 327 .LFB314: + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_PCROP_SUPPORT) + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure the 1A Proprietary code readout protection & erase configuration on RDP regre + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avo + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * having some executable code in a page where PCROP zone starts or ends. + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * has to be set to 512 Bytes + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * on RDP level 1 regression. + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout pr + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between begin and end of the flash + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protec + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between PCROP1AStartAddr and end of the flash + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1 + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 328 .loc 1 846 1 is_stmt 1 view -0 + 329 .cfi_startproc + 330 @ args = 0, pretend = 0, frame = 0 + 331 @ frame_needed = 0, uses_anonymous_args = 0 + 332 .loc 1 846 1 is_stmt 0 view .LVU75 + 333 0000 10B5 push {r4, lr} + 334 .LCFI2: + 335 .cfi_def_cfa_offset 8 + 336 .cfi_offset 4, -8 + 337 .cfi_offset 14, -4 + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t startoffset; + 338 .loc 1 847 3 is_stmt 1 view .LVU76 + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t endoffset; + 339 .loc 1 848 3 view .LVU77 + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t pcrop1aend; + 340 .loc 1 849 3 view .LVU78 + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; + 341 .loc 1 850 3 view .LVU79 + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); + 342 .loc 1 853 3 view .LVU80 + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped (valid if only one bank) */ + ARM GAS /tmp/ccHUARcC.s page 22 + + + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AStartAddr)); + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AEndAddr)); + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 1 read only protection is on second half of Flash */ + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr)); + 343 .loc 1 870 5 view .LVU81 + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AEndAddr)); + 344 .loc 1 871 5 view .LVU82 + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 1 read only protection is on first half of Flash */ + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; + 345 .loc 1 874 5 view .LVU83 + 346 .LVL21: + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* get pcrop 1A end register */ + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop1aend = FLASH->PCROP1AER; + 347 .loc 1 878 3 view .LVU84 + 348 .loc 1 878 14 is_stmt 0 view .LVU85 + 349 0002 0C4B ldr r3, .L31 + 350 0004 9B6A ldr r3, [r3, #40] + 351 .LVL22: + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection offset */ + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U) + 352 .loc 1 881 3 is_stmt 1 view .LVU86 + 353 .loc 1 881 6 is_stmt 0 view .LVU87 + 354 0006 C407 lsls r4, r0, #31 + 355 0008 0BD5 bpl .L28 + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Compute offset depending on pcrop granularity */ + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** startoffset = ((PCROP1AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + 356 .loc 1 884 5 is_stmt 1 view .LVU88 + 357 .loc 1 884 38 is_stmt 0 view .LVU89 + 358 000a F824 movs r4, #248 + 359 000c 2406 lsls r4, r4, #24 + 360 000e A446 mov ip, r4 + 361 0010 6144 add r1, r1, ip + 362 .LVL23: + 363 .loc 1 884 17 view .LVU90 + 364 0012 490A lsrs r1, r1, #9 + 365 .LVL24: + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** endoffset = ((PCROP1AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + 366 .loc 1 885 5 is_stmt 1 view .LVU91 + 367 .loc 1 885 34 is_stmt 0 view .LVU92 + 368 0014 6244 add r2, r2, ip + 369 .LVL25: + 370 .loc 1 885 15 view .LVU93 + ARM GAS /tmp/ccHUARcC.s page 23 + + + 371 0016 520A lsrs r2, r2, #9 + 372 .LVL26: + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone A start offset */ + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP1ASR = startoffset; + 373 .loc 1 888 5 is_stmt 1 view .LVU94 + 374 .loc 1 888 22 is_stmt 0 view .LVU95 + 375 0018 064C ldr r4, .L31 + 376 001a 6162 str r1, [r4, #36] + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone A end offset */ + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END; + 377 .loc 1 891 5 is_stmt 1 view .LVU96 + 378 .loc 1 891 16 is_stmt 0 view .LVU97 + 379 001c 7F21 movs r1, #127 + 380 .LVL27: + 381 .loc 1 891 16 view .LVU98 + 382 001e 8B43 bics r3, r1 + 383 .LVL28: + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop1aend |= endoffset; + 384 .loc 1 892 5 is_stmt 1 view .LVU99 + 385 .loc 1 892 16 is_stmt 0 view .LVU100 + 386 0020 1343 orrs r3, r2 + 387 .LVL29: + 388 .L28: + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U) + 389 .loc 1 896 3 is_stmt 1 view .LVU101 + 390 .loc 1 896 6 is_stmt 0 view .LVU102 + 391 0022 0028 cmp r0, #0 + 392 0024 02DB blt .L30 + 393 .L29: + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* set 1A End register */ + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP1AER = pcrop1aend; + 394 .loc 1 902 3 is_stmt 1 view .LVU103 + 395 .loc 1 902 20 is_stmt 0 view .LVU104 + 396 0026 034A ldr r2, .L31 + 397 0028 9362 str r3, [r2, #40] + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 398 .loc 1 903 1 view .LVU105 + 399 @ sp needed + 400 002a 10BD pop {r4, pc} + 401 .L30: + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 402 .loc 1 898 5 is_stmt 1 view .LVU106 + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 403 .loc 1 898 16 is_stmt 0 view .LVU107 + 404 002c 8022 movs r2, #128 + 405 002e 1206 lsls r2, r2, #24 + 406 0030 1343 orrs r3, r2 + 407 .LVL30: + ARM GAS /tmp/ccHUARcC.s page 24 + + + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 408 .loc 1 898 16 view .LVU108 + 409 0032 F8E7 b .L29 + 410 .L32: + 411 .align 2 + 412 .L31: + 413 0034 00200240 .word 1073881088 + 414 .cfi_endproc + 415 .LFE314: + 417 .section .text.FLASH_OB_PCROP1BConfig,"ax",%progbits + 418 .align 1 + 419 .syntax unified + 420 .code 16 + 421 .thumb_func + 422 .fpu softvfp + 424 FLASH_OB_PCROP1BConfig: + 425 .LVL31: + 426 .LFB315: + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure the 1B Proprietary code readout protection. + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avo + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * having some executable code in a page where PCROP zone starts or ends. + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPB_STRT and PCROPB_END. + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * has to be set to 512 Bytes + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout p + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between begin and end of the flash + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout prote + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between PCROP1BStartAddr and end of the flash + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 427 .loc 1 919 1 is_stmt 1 view -0 + 428 .cfi_startproc + 429 @ args = 0, pretend = 0, frame = 0 + 430 @ frame_needed = 0, uses_anonymous_args = 0 + 431 @ link register save eliminated. + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t startoffset; + 432 .loc 1 920 3 view .LVU110 + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t endoffset; + 433 .loc 1 921 3 view .LVU111 + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; + 434 .loc 1 922 3 view .LVU112 + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped (valid if only one bank) */ + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BStartAddr)); + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BEndAddr)); + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 1 read only protection is on second half of Flash */ + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 25 + + + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr)); + 435 .loc 1 939 5 view .LVU113 + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BEndAddr)); + 436 .loc 1 940 5 view .LVU114 + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 1 read only protection is on first half of Flash */ + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; + 437 .loc 1 943 5 view .LVU115 + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection offset */ + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** startoffset = ((PCROP1BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + 438 .loc 1 947 3 view .LVU116 + 439 .loc 1 947 36 is_stmt 0 view .LVU117 + 440 0000 F823 movs r3, #248 + 441 0002 1B06 lsls r3, r3, #24 + 442 0004 9C46 mov ip, r3 + 443 0006 6044 add r0, r0, ip + 444 .LVL32: + 445 .loc 1 947 15 view .LVU118 + 446 0008 400A lsrs r0, r0, #9 + 447 .LVL33: + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** endoffset = ((PCROP1BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + 448 .loc 1 948 3 is_stmt 1 view .LVU119 + 449 .loc 1 948 32 is_stmt 0 view .LVU120 + 450 000a 6144 add r1, r1, ip + 451 .LVL34: + 452 .loc 1 948 13 view .LVU121 + 453 000c 490A lsrs r1, r1, #9 + 454 .LVL35: + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone B start offset */ + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP1BSR = startoffset; + 455 .loc 1 951 3 is_stmt 1 view .LVU122 + 456 .loc 1 951 20 is_stmt 0 view .LVU123 + 457 000e 024B ldr r3, .L34 + 458 0010 5863 str r0, [r3, #52] + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone B end offset */ + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP1BER = endoffset; + 459 .loc 1 953 3 is_stmt 1 view .LVU124 + 460 .loc 1 953 20 is_stmt 0 view .LVU125 + 461 0012 9963 str r1, [r3, #56] + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 462 .loc 1 954 1 view .LVU126 + 463 @ sp needed + 464 0014 7047 bx lr + 465 .L35: + 466 0016 C046 .align 2 + 467 .L34: + 468 0018 00200240 .word 1073881088 + 469 .cfi_endproc + 470 .LFE315: + 472 .section .text.FLASH_OB_GetPCROP1A,"ax",%progbits + ARM GAS /tmp/ccHUARcC.s page 26 + + + 473 .align 1 + 474 .syntax unified + 475 .code 16 + 476 .thumb_func + 477 .fpu softvfp + 479 FLASH_OB_GetPCROP1A: + 480 .LVL36: + 481 .LFB316: + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH PCROP Protection Option Bytes value. + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option. + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * of the 1A Proprietary code readout protection + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the 1A Proprietary code readout protection + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1 + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 482 .loc 1 966 1 is_stmt 1 view -0 + 483 .cfi_startproc + 484 @ args = 0, pretend = 0, frame = 0 + 485 @ frame_needed = 0, uses_anonymous_args = 0 + 486 .loc 1 966 1 is_stmt 0 view .LVU128 + 487 0000 30B5 push {r4, r5, lr} + 488 .LCFI3: + 489 .cfi_def_cfa_offset 12 + 490 .cfi_offset 4, -12 + 491 .cfi_offset 5, -8 + 492 .cfi_offset 14, -4 + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t pcrop; + 493 .loc 1 967 3 is_stmt 1 view .LVU129 + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; + 494 .loc 1 968 3 view .LVU130 + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped (valid if only one bank) */ + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 1 read only protection is on second half of Flash */ + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 1 read only protection is on first half of Flash */ + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; + 495 .loc 1 981 5 view .LVU131 + 496 .LVL37: + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT); + 497 .loc 1 984 3 view .LVU132 + 498 .loc 1 984 17 is_stmt 0 view .LVU133 + 499 0002 0D4C ldr r4, .L37 + 500 0004 636A ldr r3, [r4, #36] + ARM GAS /tmp/ccHUARcC.s page 27 + + + 501 .LVL38: + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + 502 .loc 1 985 3 is_stmt 1 view .LVU134 + 503 .loc 1 985 30 is_stmt 0 view .LVU135 + 504 0006 5B06 lsls r3, r3, #25 + 505 .LVL39: + 506 .loc 1 985 30 view .LVU136 + 507 0008 1B0C lsrs r3, r3, #16 + 508 .loc 1 985 21 view .LVU137 + 509 000a 0B60 str r3, [r1] + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1AStartAddr += ropbase; + 510 .loc 1 986 3 is_stmt 1 view .LVU138 + 511 .loc 1 986 21 is_stmt 0 view .LVU139 + 512 000c 8025 movs r5, #128 + 513 000e 2D05 lsls r5, r5, #20 + 514 0010 AC46 mov ip, r5 + 515 0012 6344 add r3, r3, ip + 516 0014 0B60 str r3, [r1] + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = FLASH->PCROP1AER; + 517 .loc 1 988 3 is_stmt 1 view .LVU140 + 518 .loc 1 988 9 is_stmt 0 view .LVU141 + 519 0016 A16A ldr r1, [r4, #40] + 520 .LVL40: + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET); + 521 .loc 1 989 3 is_stmt 1 view .LVU142 + 522 .loc 1 989 60 is_stmt 0 view .LVU143 + 523 0018 4B06 lsls r3, r1, #25 + 524 001a 1B0C lsrs r3, r3, #16 + 525 .loc 1 989 19 view .LVU144 + 526 001c 1360 str r3, [r2] + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); + 527 .loc 1 990 3 is_stmt 1 view .LVU145 + 528 .loc 1 990 19 is_stmt 0 view .LVU146 + 529 001e 074C ldr r4, .L37+4 + 530 0020 A446 mov ip, r4 + 531 0022 6344 add r3, r3, ip + 532 0024 1360 str r3, [r2] + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROPConfig &= ~OB_PCROP_RDP_ERASE; + 533 .loc 1 992 3 is_stmt 1 view .LVU147 + 534 .loc 1 992 16 is_stmt 0 view .LVU148 + 535 0026 0368 ldr r3, [r0] + 536 0028 5B00 lsls r3, r3, #1 + 537 002a 5B08 lsrs r3, r3, #1 + 538 002c 0360 str r3, [r0] + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP); + 539 .loc 1 993 3 is_stmt 1 view .LVU149 + 540 .loc 1 993 26 is_stmt 0 view .LVU150 + 541 002e C90F lsrs r1, r1, #31 + 542 .LVL41: + 543 .loc 1 993 26 view .LVU151 + 544 0030 C907 lsls r1, r1, #31 + 545 .loc 1 993 16 view .LVU152 + 546 0032 0B43 orrs r3, r1 + 547 0034 0360 str r3, [r0] + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccHUARcC.s page 28 + + + 548 .loc 1 994 1 view .LVU153 + 549 @ sp needed + 550 0036 30BD pop {r4, r5, pc} + 551 .L38: + 552 .align 2 + 553 .L37: + 554 0038 00200240 .word 1073881088 + 555 003c FF010008 .word 134218239 + 556 .cfi_endproc + 557 .LFE316: + 559 .section .text.FLASH_OB_GetPCROP1B,"ax",%progbits + 560 .align 1 + 561 .syntax unified + 562 .code 16 + 563 .thumb_func + 564 .fpu softvfp + 566 FLASH_OB_GetPCROP1B: + 567 .LVL42: + 568 .LFB317: + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH PCROP Protection Option Bytes value. + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * of the 1B Proprietary code readout protection +1000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of +1001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the 1B Proprietary code readout protection +1002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +1005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 569 .loc 1 1005 1 is_stmt 1 view -0 + 570 .cfi_startproc + 571 @ args = 0, pretend = 0, frame = 0 + 572 @ frame_needed = 0, uses_anonymous_args = 0 + 573 .loc 1 1005 1 is_stmt 0 view .LVU155 + 574 0000 10B5 push {r4, lr} + 575 .LCFI4: + 576 .cfi_def_cfa_offset 8 + 577 .cfi_offset 4, -8 + 578 .cfi_offset 14, -4 +1006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t pcrop; + 579 .loc 1 1006 3 is_stmt 1 view .LVU156 +1007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; + 580 .loc 1 1007 3 view .LVU157 +1008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) +1010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped (valid if only one bank) */ +1011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) +1012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 1 read only protection is on second half of Flash */ +1014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); +1015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else +1017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ +1018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 1 read only protection is on first half of Flash */ +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; + ARM GAS /tmp/ccHUARcC.s page 29 + + + 581 .loc 1 1020 5 view .LVU158 + 582 .LVL43: +1021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT); + 583 .loc 1 1023 3 view .LVU159 + 584 .loc 1 1023 17 is_stmt 0 view .LVU160 + 585 0002 094A ldr r2, .L40 + 586 0004 536B ldr r3, [r2, #52] + 587 .LVL44: +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + 588 .loc 1 1024 3 is_stmt 1 view .LVU161 + 589 .loc 1 1024 30 is_stmt 0 view .LVU162 + 590 0006 5B06 lsls r3, r3, #25 + 591 .LVL45: + 592 .loc 1 1024 30 view .LVU163 + 593 0008 1B0C lsrs r3, r3, #16 + 594 .loc 1 1024 21 view .LVU164 + 595 000a 0360 str r3, [r0] +1025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1BStartAddr += ropbase; + 596 .loc 1 1025 3 is_stmt 1 view .LVU165 + 597 .loc 1 1025 21 is_stmt 0 view .LVU166 + 598 000c 8024 movs r4, #128 + 599 000e 2405 lsls r4, r4, #20 + 600 0010 A446 mov ip, r4 + 601 0012 6344 add r3, r3, ip + 602 0014 0360 str r3, [r0] +1026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END); + 603 .loc 1 1027 3 is_stmt 1 view .LVU167 + 604 .loc 1 1027 17 is_stmt 0 view .LVU168 + 605 0016 936B ldr r3, [r2, #56] + 606 .LVL46: +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + 607 .loc 1 1028 3 is_stmt 1 view .LVU169 + 608 .loc 1 1028 28 is_stmt 0 view .LVU170 + 609 0018 5B06 lsls r3, r3, #25 + 610 .LVL47: + 611 .loc 1 1028 28 view .LVU171 + 612 001a 1B0C lsrs r3, r3, #16 + 613 .loc 1 1028 19 view .LVU172 + 614 001c 0B60 str r3, [r1] +1029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP1BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); + 615 .loc 1 1029 3 is_stmt 1 view .LVU173 + 616 .loc 1 1029 19 is_stmt 0 view .LVU174 + 617 001e 034A ldr r2, .L40+4 + 618 0020 9446 mov ip, r2 + 619 0022 6344 add r3, r3, ip + 620 0024 0B60 str r3, [r1] +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 621 .loc 1 1030 1 view .LVU175 + 622 @ sp needed + 623 0026 10BD pop {r4, pc} + 624 .L41: + 625 .align 2 + 626 .L40: + 627 0028 00200240 .word 1073881088 + ARM GAS /tmp/ccHUARcC.s page 30 + + + 628 002c FF010008 .word 134218239 + 629 .cfi_endproc + 630 .LFE317: + 632 .section .text.FLASH_OB_SecMemConfig,"ax",%progbits + 633 .align 1 + 634 .syntax unified + 635 .code 16 + 636 .thumb_func + 637 .fpu softvfp + 639 FLASH_OB_SecMemConfig: + 640 .LVL48: + 641 .LFB318: +1031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure the 2A Proprietary code readout protection. +1035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avo +1036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * having some executable code in a page where PCROP zone starts or ends. +1037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. +1038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity +1039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * has to be set to 512 Bytes +1040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2AStartAddr Specifies the Zone 2A Start address of the Proprietary code readout p +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between begin and end of the flash +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2AEndAddr Specifies the Zone 2A end address of the Proprietary code readout prote +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between PCROP2AStartAddr and end of the flash +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr) +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t startoffset; +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t endoffset; +1050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped */ +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AStartAddr)); +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AEndAddr)); +1058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 2 read only protection is on second half of Flash */ +1060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); +1061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else +1063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AStartAddr)); +1066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AEndAddr)); +1067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 2 read only protection is on first half of Flash */ +1069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection offset */ +1073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** startoffset = ((PCROP2AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** endoffset = ((PCROP2AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); +1075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + ARM GAS /tmp/ccHUARcC.s page 31 + + +1076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone A start offset */ +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP2ASR = startoffset; +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone A end offset */ +1079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP2AER = endoffset; +1080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure the 2B Proprietary code readout protection. +1084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avo +1085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * having some executable code in a page where PCROP zone starts or ends. +1086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @note Minimum PCROP area size is 2 times the chosen granularity: PCROP_STRT and PCROP_END. +1087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity +1088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * has to be set to 512 Bytes +1089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2BStartAddr Specifies the Zone 2B Start address of the Proprietary code readout p +1090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between begin and end of the flash +1091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2BEndAddr Specifies the Zone 2B end address of the Proprietary code readout prote +1092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be an address between PCROP2BStartAddr and end of the flash +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr) +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t startoffset; +1098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t endoffset; +1099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; +1100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped */ +1102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) +1103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BStartAddr)); +1106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BEndAddr)); +1107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 2 read only protection is on second half of Flash */ +1109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); +1110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else +1112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BStartAddr)); +1115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BEndAddr)); +1116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 2 read only protection is on first half of Flash */ +1118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Configure the Proprietary code readout protection offset */ +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** startoffset = ((PCROP2BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); +1123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** endoffset = ((PCROP2BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); +1124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone B start offset */ +1126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP2BSR = startoffset; +1127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set Zone B end offset */ +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->PCROP2BER = endoffset; +1129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH PCROP Protection Option Bytes value. + ARM GAS /tmp/ccHUARcC.s page 32 + + +1133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2AStartAddr [out] Specifies the address where to copied the start address +1134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * of the 2A Proprietary code readout protection +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2AEndAddr [out] Specifies the address where to copied the end address of +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the 2A Proprietary code readout protection +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr) +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t pcrop; +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped */ +1145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 2 read only protection is on second half of Flash */ +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 2 read only protection is on first half of Flash */ +1153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP2ASR & FLASH_PCROP2ASR_PCROP2A_STRT); +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); +1158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2AStartAddr += ropbase; +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP2AER & FLASH_PCROP2AER_PCROP2A_END); +1161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2AEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +1163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH PCROP Protection Option Bytes value. +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2BStartAddr [out] Specifies the address where to copied the start address +1168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * of the 2B Proprietary code readout protection +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param PCROP2BEndAddr [out] Specifies the address where to copied the end address of +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * the 2B Proprietary code readout protection +1171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr) +1174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t pcrop; +1176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t ropbase; +1177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check if banks are swapped */ +1179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) +1180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* No Bank swap, bank 2 read only protection is on second half of Flash */ +1182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = (FLASH_BASE + FLASH_BANK_SIZE); +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** else +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Bank swap, bank 2 read only protection is on first half of Flash */ +1187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** ropbase = FLASH_BASE; +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + ARM GAS /tmp/ccHUARcC.s page 33 + + +1190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP2BSR & FLASH_PCROP2BSR_PCROP2B_STRT); +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); +1192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2BStartAddr += ropbase; +1193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pcrop = (FLASH->PCROP2BER & FLASH_PCROP2BER_PCROP2B_END); +1195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); +1196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +1197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ +1199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_PCROP_SUPPORT */ +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +1202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) +1203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure Securable Memory area feature. +1205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not +1206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced +1208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH Flash selected as unique entry boot +1209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize specifies number of pages to protect as securable memory area, starting from +1210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of Bank1 (page 0). +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize2 specifies number of pages to protect as securable memory area, starting from +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of Bank2 (page 0). +1213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2) +1216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t secmem; +1218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_SEC_SIZE(SecSize)); +1222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** if ((FLASH_BANK_NB == 2U)) +1224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_SEC_SIZE(SecSize2)); +1226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set securable memory area configuration */ +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE | FLASH_SECR_SEC_SIZE2)); +1230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->SECR = (secmem | BootEntry | SecSize | (SecSize2 << FLASH_SECR_SEC_SIZE2_Pos)); +1231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH Securable memory area protection Option Bytes value. +1235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param BootEntry specifies boot scheme configuration +1236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize specifies number of pages to protect as secure memory area, starting from +1237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of Bank1 (page 0). +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize2 specifies number of pages to protect as secure memory area, starting from +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of Bank2 (page 0). +1240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2) +1243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t secmem = FLASH->SECR; +1245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + ARM GAS /tmp/ccHUARcC.s page 34 + + +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *SecSize = (secmem & FLASH_SECR_SEC_SIZE); +1248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *SecSize2 = (secmem & FLASH_SECR_SEC_SIZE2) >> FLASH_SECR_SEC_SIZE2_Pos; +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } +1250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #else +1252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Configure Securable Memory area feature. +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * This parameter can be one of the following values: +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced +1257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot +1258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize specifies number of pages to protect as securable memory area, starting from +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of the Flash (page 0). +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) +1263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 642 .loc 1 1263 1 is_stmt 1 view -0 + 643 .cfi_startproc + 644 @ args = 0, pretend = 0, frame = 0 + 645 @ frame_needed = 0, uses_anonymous_args = 0 + 646 .loc 1 1263 1 is_stmt 0 view .LVU177 + 647 0000 30B5 push {r4, r5, lr} + 648 .LCFI5: + 649 .cfi_def_cfa_offset 12 + 650 .cfi_offset 4, -12 + 651 .cfi_offset 5, -8 + 652 .cfi_offset 14, -4 +1264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t secmem; + 653 .loc 1 1264 3 is_stmt 1 view .LVU178 +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Check the parameters */ +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + 654 .loc 1 1267 3 view .LVU179 +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_OB_SEC_SIZE(SecSize)); + 655 .loc 1 1268 3 view .LVU180 +1269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Set securable memory area configuration */ +1271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE)); + 656 .loc 1 1271 3 view .LVU181 + 657 .loc 1 1271 18 is_stmt 0 view .LVU182 + 658 0002 044C ldr r4, .L43 + 659 0004 8022 movs r2, #128 + 660 0006 A358 ldr r3, [r4, r2] + 661 .loc 1 1271 10 view .LVU183 + 662 0008 034D ldr r5, .L43+4 + 663 000a 2B40 ands r3, r5 + 664 .LVL49: +1272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->SECR = (secmem | BootEntry | SecSize); + 665 .loc 1 1272 3 is_stmt 1 view .LVU184 + 666 .loc 1 1272 25 is_stmt 0 view .LVU185 + 667 000c 0343 orrs r3, r0 + 668 .LVL50: + 669 .loc 1 1272 37 view .LVU186 + 670 000e 0B43 orrs r3, r1 + 671 .loc 1 1272 15 view .LVU187 + 672 0010 A350 str r3, [r4, r2] + ARM GAS /tmp/ccHUARcC.s page 35 + + +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 673 .loc 1 1273 1 view .LVU188 + 674 @ sp needed + 675 0012 30BD pop {r4, r5, pc} + 676 .L44: + 677 .align 2 + 678 .L43: + 679 0014 00200240 .word 1073881088 + 680 0018 C0FFFEFF .word -65600 + 681 .cfi_endproc + 682 .LFE318: + 684 .section .text.FLASH_OB_GetSecMem,"ax",%progbits + 685 .align 1 + 686 .syntax unified + 687 .code 16 + 688 .thumb_func + 689 .fpu softvfp + 691 FLASH_OB_GetSecMem: + 692 .LVL51: + 693 .LFB319: +1274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /** +1276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @brief Return the FLASH Securable memory area protection Option Bytes value. +1277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param BootEntry specifies boot scheme configuration +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @param SecSize specifies number of pages to protect as secure memory area, starting from +1279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * beginning of the Flash (page 0). +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** * @retval None +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** */ +1282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize) +1283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 694 .loc 1 1283 1 is_stmt 1 view -0 + 695 .cfi_startproc + 696 @ args = 0, pretend = 0, frame = 0 + 697 @ frame_needed = 0, uses_anonymous_args = 0 + 698 .loc 1 1283 1 is_stmt 0 view .LVU190 + 699 0000 10B5 push {r4, lr} + 700 .LCFI6: + 701 .cfi_def_cfa_offset 8 + 702 .cfi_offset 4, -8 + 703 .cfi_offset 14, -4 +1284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t secmem = FLASH->SECR; + 704 .loc 1 1284 3 is_stmt 1 view .LVU191 + 705 .loc 1 1284 12 is_stmt 0 view .LVU192 + 706 0002 054A ldr r2, .L46 + 707 0004 8023 movs r3, #128 + 708 0006 D458 ldr r4, [r2, r3] + 709 .LVL52: +1285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** +1286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + 710 .loc 1 1286 3 is_stmt 1 view .LVU193 + 711 .loc 1 1286 24 is_stmt 0 view .LVU194 + 712 0008 8022 movs r2, #128 + 713 000a 5202 lsls r2, r2, #9 + 714 000c 2240 ands r2, r4 + 715 .loc 1 1286 14 view .LVU195 + 716 000e 0260 str r2, [r0] +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** *SecSize = (secmem & FLASH_SECR_SEC_SIZE); + ARM GAS /tmp/ccHUARcC.s page 36 + + + 717 .loc 1 1287 3 is_stmt 1 view .LVU196 + 718 .loc 1 1287 22 is_stmt 0 view .LVU197 + 719 0010 413B subs r3, r3, #65 + 720 0012 2340 ands r3, r4 + 721 .loc 1 1287 12 view .LVU198 + 722 0014 0B60 str r3, [r1] +1288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 723 .loc 1 1288 1 view .LVU199 + 724 @ sp needed + 725 .LVL53: + 726 .loc 1 1288 1 view .LVU200 + 727 0016 10BD pop {r4, pc} + 728 .L47: + 729 .align 2 + 730 .L46: + 731 0018 00200240 .word 1073881088 + 732 .cfi_endproc + 733 .LFE319: + 735 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 736 .align 1 + 737 .global HAL_FLASHEx_OBProgram + 738 .syntax unified + 739 .code 16 + 740 .thumb_func + 741 .fpu softvfp + 743 HAL_FLASHEx_OBProgram: + 744 .LVL54: + 745 .LFB299: + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t optr; + 746 .loc 1 300 1 is_stmt 1 view -0 + 747 .cfi_startproc + 748 @ args = 0, pretend = 0, frame = 0 + 749 @ frame_needed = 0, uses_anonymous_args = 0 + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t optr; + 750 .loc 1 300 1 is_stmt 0 view .LVU202 + 751 0000 10B5 push {r4, lr} + 752 .LCFI7: + 753 .cfi_def_cfa_offset 8 + 754 .cfi_offset 4, -8 + 755 .cfi_offset 14, -4 + 756 0002 0400 movs r4, r0 + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 757 .loc 1 301 3 is_stmt 1 view .LVU203 + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 758 .loc 1 302 3 view .LVU204 + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 759 .loc 1 305 3 view .LVU205 + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 760 .loc 1 308 3 view .LVU206 + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 761 .loc 1 308 3 view .LVU207 + 762 0004 334B ldr r3, .L67 + 763 0006 1B78 ldrb r3, [r3] + 764 0008 012B cmp r3, #1 + 765 000a 60D0 beq .L58 + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 766 .loc 1 308 3 discriminator 2 view .LVU208 + ARM GAS /tmp/ccHUARcC.s page 37 + + + 767 000c 314A ldr r2, .L67 + 768 000e 0123 movs r3, #1 + 769 0010 1370 strb r3, [r2] + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 770 .loc 1 308 3 discriminator 2 view .LVU209 + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 771 .loc 1 310 3 discriminator 2 view .LVU210 + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 772 .loc 1 310 20 is_stmt 0 discriminator 2 view .LVU211 + 773 0012 0021 movs r1, #0 + 774 0014 5160 str r1, [r2, #4] + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 775 .loc 1 313 3 is_stmt 1 discriminator 2 view .LVU212 + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 776 .loc 1 313 6 is_stmt 0 discriminator 2 view .LVU213 + 777 0016 0268 ldr r2, [r0] + 778 0018 1342 tst r3, r2 + 779 001a 1FD1 bne .L59 + 780 .LVL55: + 781 .L50: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 782 .loc 1 320 3 is_stmt 1 view .LVU214 + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 783 .loc 1 320 15 is_stmt 0 view .LVU215 + 784 001c 2268 ldr r2, [r4] + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 785 .loc 1 320 28 view .LVU216 + 786 001e 0623 movs r3, #6 + 787 0020 1340 ands r3, r2 + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 788 .loc 1 320 6 view .LVU217 + 789 0022 062B cmp r3, #6 + 790 0024 20D0 beq .L60 + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 791 .loc 1 325 8 is_stmt 1 view .LVU218 + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 792 .loc 1 325 11 is_stmt 0 view .LVU219 + 793 0026 9307 lsls r3, r2, #30 + 794 0028 24D4 bmi .L61 + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 795 .loc 1 331 8 is_stmt 1 view .LVU220 + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 796 .loc 1 331 11 is_stmt 0 view .LVU221 + 797 002a 5307 lsls r3, r2, #29 + 798 002c 29D4 bmi .L62 + 799 .L52: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 800 .loc 1 340 3 is_stmt 1 view .LVU222 + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 801 .loc 1 344 3 view .LVU223 + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 802 .loc 1 344 6 is_stmt 0 view .LVU224 + 803 002e 2368 ldr r3, [r4] + 804 0030 1B07 lsls r3, r3, #28 + 805 0032 06D5 bpl .L54 + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 806 .loc 1 347 5 is_stmt 1 view .LVU225 + ARM GAS /tmp/ccHUARcC.s page 38 + + + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 807 .loc 1 349 5 view .LVU226 + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 808 .loc 1 349 17 is_stmt 0 view .LVU227 + 809 0034 E069 ldr r0, [r4, #28] + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 810 .loc 1 349 31 view .LVU228 + 811 0036 284B ldr r3, .L67+4 + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 812 .loc 1 349 8 view .LVU229 + 813 0038 1842 tst r0, r3 + 814 003a 2AD1 bne .L63 + 815 .L55: + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 816 .loc 1 355 5 is_stmt 1 view .LVU230 + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 817 .loc 1 355 8 is_stmt 0 view .LVU231 + 818 003c E369 ldr r3, [r4, #28] + 819 003e 9B07 lsls r3, r3, #30 + 820 0040 2CD4 bmi .L64 + 821 .L54: + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 822 .loc 1 379 3 is_stmt 1 view .LVU232 + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 823 .loc 1 379 6 is_stmt 0 view .LVU233 + 824 0042 2368 ldr r3, [r4] + 825 0044 DB06 lsls r3, r3, #27 + 826 0046 2ED4 bmi .L65 + 827 .L56: + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 828 .loc 1 392 3 is_stmt 1 view .LVU234 + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 829 .loc 1 392 12 is_stmt 0 view .LVU235 + 830 0048 FA20 movs r0, #250 + 831 004a 8000 lsls r0, r0, #2 + 832 004c FFF7FEFF bl FLASH_WaitForLastOperation + 833 .LVL56: + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 834 .loc 1 394 3 is_stmt 1 view .LVU236 + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 835 .loc 1 394 6 is_stmt 0 view .LVU237 + 836 0050 0028 cmp r0, #0 + 837 0052 2DD0 beq .L66 + 838 .LVL57: + 839 .L57: + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 840 .loc 1 407 3 is_stmt 1 view .LVU238 + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 841 .loc 1 407 3 view .LVU239 + 842 0054 1F4B ldr r3, .L67 + 843 0056 0022 movs r2, #0 + 844 0058 1A70 strb r2, [r3] + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 845 .loc 1 407 3 view .LVU240 + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 846 .loc 1 410 3 view .LVU241 + 847 .LVL58: + ARM GAS /tmp/ccHUARcC.s page 39 + + + 848 .L49: + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 849 .loc 1 411 1 is_stmt 0 view .LVU242 + 850 @ sp needed + 851 005a 10BD pop {r4, pc} + 852 .LVL59: + 853 .L59: + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 854 .loc 1 316 5 is_stmt 1 view .LVU243 + 855 005c C268 ldr r2, [r0, #12] + 856 005e 8168 ldr r1, [r0, #8] + 857 0060 4068 ldr r0, [r0, #4] + 858 .LVL60: + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 859 .loc 1 316 5 is_stmt 0 view .LVU244 + 860 0062 FFF7FEFF bl FLASH_OB_WRPConfig + 861 .LVL61: + 862 0066 D9E7 b .L50 + 863 .L60: + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 864 .loc 1 323 5 is_stmt 1 view .LVU245 + 865 0068 2269 ldr r2, [r4, #16] + 866 006a A169 ldr r1, [r4, #24] + 867 006c 6069 ldr r0, [r4, #20] + 868 006e FFF7FEFF bl FLASH_OB_OptrConfig + 869 .LVL62: + 870 0072 DCE7 b .L52 + 871 .L61: + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + 872 .loc 1 328 5 view .LVU246 + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + 873 .loc 1 328 12 is_stmt 0 view .LVU247 + 874 0074 FFF7FEFF bl FLASH_OB_GetUser + 875 .LVL63: + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 876 .loc 1 329 5 is_stmt 1 view .LVU248 + 877 0078 2269 ldr r2, [r4, #16] + 878 007a 0100 movs r1, r0 + 879 007c FFF7FEFF bl FLASH_OB_OptrConfig + 880 .LVL64: + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 881 .loc 1 329 5 is_stmt 0 view .LVU249 + 882 0080 D5E7 b .L52 + 883 .L62: + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + 884 .loc 1 334 5 is_stmt 1 view .LVU250 + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + 885 .loc 1 334 12 is_stmt 0 view .LVU251 + 886 0082 FFF7FEFF bl FLASH_OB_GetRDP + 887 .LVL65: + 888 0086 0200 movs r2, r0 + 889 .LVL66: + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 890 .loc 1 335 5 is_stmt 1 view .LVU252 + 891 0088 A169 ldr r1, [r4, #24] + 892 008a 6069 ldr r0, [r4, #20] + 893 .LVL67: + ARM GAS /tmp/ccHUARcC.s page 40 + + + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 894 .loc 1 335 5 is_stmt 0 view .LVU253 + 895 008c FFF7FEFF bl FLASH_OB_OptrConfig + 896 .LVL68: + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 897 .loc 1 335 5 view .LVU254 + 898 0090 CDE7 b .L52 + 899 .L63: + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 900 .loc 1 352 7 is_stmt 1 view .LVU255 + 901 0092 626A ldr r2, [r4, #36] + 902 0094 216A ldr r1, [r4, #32] + 903 0096 FFF7FEFF bl FLASH_OB_PCROP1AConfig + 904 .LVL69: + 905 009a CFE7 b .L55 + 906 .L64: + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 907 .loc 1 358 7 view .LVU256 + 908 009c E16A ldr r1, [r4, #44] + 909 009e A06A ldr r0, [r4, #40] + 910 00a0 FFF7FEFF bl FLASH_OB_PCROP1BConfig + 911 .LVL70: + 912 00a4 CDE7 b .L54 + 913 .L65: + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 914 .loc 1 386 5 view .LVU257 + 915 00a6 616B ldr r1, [r4, #52] + 916 00a8 206B ldr r0, [r4, #48] + 917 00aa FFF7FEFF bl FLASH_OB_SecMemConfig + 918 .LVL71: + 919 00ae CBE7 b .L56 + 920 .LVL72: + 921 .L66: + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 922 .loc 1 397 5 view .LVU258 + 923 00b0 0A4C ldr r4, .L67+8 + 924 .LVL73: + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 925 .loc 1 397 5 is_stmt 0 view .LVU259 + 926 00b2 6269 ldr r2, [r4, #20] + 927 00b4 8023 movs r3, #128 + 928 00b6 9B02 lsls r3, r3, #10 + 929 00b8 1343 orrs r3, r2 + 930 00ba 6361 str r3, [r4, #20] + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 931 .loc 1 400 5 is_stmt 1 view .LVU260 + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 932 .loc 1 400 14 is_stmt 0 view .LVU261 + 933 00bc FA30 adds r0, r0, #250 + 934 .LVL74: + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 935 .loc 1 400 14 view .LVU262 + 936 00be 8000 lsls r0, r0, #2 + 937 .LVL75: + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 938 .loc 1 400 14 view .LVU263 + 939 00c0 FFF7FEFF bl FLASH_WaitForLastOperation + ARM GAS /tmp/ccHUARcC.s page 41 + + + 940 .LVL76: + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 941 .loc 1 403 5 is_stmt 1 view .LVU264 + 942 00c4 6369 ldr r3, [r4, #20] + 943 00c6 064A ldr r2, .L67+12 + 944 00c8 1340 ands r3, r2 + 945 00ca 6361 str r3, [r4, #20] + 946 00cc C2E7 b .L57 + 947 .LVL77: + 948 .L58: + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 949 .loc 1 308 3 is_stmt 0 view .LVU265 + 950 00ce 0220 movs r0, #2 + 951 .LVL78: + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 952 .loc 1 308 3 view .LVU266 + 953 00d0 C3E7 b .L49 + 954 .L68: + 955 00d2 C046 .align 2 + 956 .L67: + 957 00d4 00000000 .word pFlash + 958 00d8 01000080 .word -2147483647 + 959 00dc 00200240 .word 1073881088 + 960 00e0 FFFFFDFF .word -131073 + 961 .cfi_endproc + 962 .LFE299: + 964 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 965 .align 1 + 966 .global HAL_FLASHEx_OBGetConfig + 967 .syntax unified + 968 .code 16 + 969 .thumb_func + 970 .fpu softvfp + 972 HAL_FLASHEx_OBGetConfig: + 973 .LVL79: + 974 .LFB300: + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_ALL; + 975 .loc 1 424 1 is_stmt 1 view -0 + 976 .cfi_startproc + 977 @ args = 0, pretend = 0, frame = 0 + 978 @ frame_needed = 0, uses_anonymous_args = 0 + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_ALL; + 979 .loc 1 424 1 is_stmt 0 view .LVU268 + 980 0000 10B5 push {r4, lr} + 981 .LCFI8: + 982 .cfi_def_cfa_offset 8 + 983 .cfi_offset 4, -8 + 984 .cfi_offset 14, -4 + 985 0002 0400 movs r4, r0 + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 986 .loc 1 425 3 is_stmt 1 view .LVU269 + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 987 .loc 1 425 23 is_stmt 0 view .LVU270 + 988 0004 1F23 movs r3, #31 + 989 0006 0360 str r3, [r0] + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 990 .loc 1 428 3 is_stmt 1 view .LVU271 + ARM GAS /tmp/ccHUARcC.s page 42 + + + 991 0008 0200 movs r2, r0 + 992 000a 0C32 adds r2, r2, #12 + 993 000c 0100 movs r1, r0 + 994 000e 0831 adds r1, r1, #8 + 995 0010 4068 ldr r0, [r0, #4] + 996 .LVL80: + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 997 .loc 1 428 3 is_stmt 0 view .LVU272 + 998 0012 FFF7FEFF bl FLASH_OB_GetWRP + 999 .LVL81: + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1000 .loc 1 431 3 is_stmt 1 view .LVU273 + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1001 .loc 1 431 23 is_stmt 0 view .LVU274 + 1002 0016 FFF7FEFF bl FLASH_OB_GetRDP + 1003 .LVL82: + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1004 .loc 1 431 21 view .LVU275 + 1005 001a 2061 str r0, [r4, #16] + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->USERType = OB_USER_ALL; + 1006 .loc 1 434 3 is_stmt 1 view .LVU276 + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->USERType = OB_USER_ALL; + 1007 .loc 1 434 25 is_stmt 0 view .LVU277 + 1008 001c FFF7FEFF bl FLASH_OB_GetUser + 1009 .LVL83: + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->USERType = OB_USER_ALL; + 1010 .loc 1 434 23 view .LVU278 + 1011 0020 A061 str r0, [r4, #24] + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1012 .loc 1 435 3 is_stmt 1 view .LVU279 + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1013 .loc 1 435 21 is_stmt 0 view .LVU280 + 1014 0022 0D4B ldr r3, .L70 + 1015 0024 6361 str r3, [r4, #20] + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + 1016 .loc 1 439 3 is_stmt 1 view .LVU281 + 1017 0026 2200 movs r2, r4 + 1018 0028 2432 adds r2, r2, #36 + 1019 002a 2100 movs r1, r4 + 1020 002c 2031 adds r1, r1, #32 + 1021 002e 2000 movs r0, r4 + 1022 0030 1C30 adds r0, r0, #28 + 1023 0032 FFF7FEFF bl FLASH_OB_GetPCROP1A + 1024 .LVL84: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); + 1025 .loc 1 440 3 view .LVU282 + 1026 0036 2100 movs r1, r4 + 1027 0038 2C31 adds r1, r1, #44 + 1028 003a 2000 movs r0, r4 + 1029 003c 2830 adds r0, r0, #40 + 1030 003e FFF7FEFF bl FLASH_OB_GetPCROP1B + 1031 .LVL85: + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 1032 .loc 1 441 3 view .LVU283 + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 1033 .loc 1 441 24 is_stmt 0 view .LVU284 + 1034 0042 0323 movs r3, #3 + ARM GAS /tmp/ccHUARcC.s page 43 + + + 1035 0044 E269 ldr r2, [r4, #28] + 1036 0046 1343 orrs r3, r2 + 1037 0048 E361 str r3, [r4, #28] + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1038 .loc 1 455 3 is_stmt 1 view .LVU285 + 1039 004a 2100 movs r1, r4 + 1040 004c 3431 adds r1, r1, #52 + 1041 004e 2000 movs r0, r4 + 1042 0050 3030 adds r0, r0, #48 + 1043 0052 FFF7FEFF bl FLASH_OB_GetSecMem + 1044 .LVL86: + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1045 .loc 1 458 1 is_stmt 0 view .LVU286 + 1046 @ sp needed + 1047 .LVL87: + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1048 .loc 1 458 1 view .LVU287 + 1049 0056 10BD pop {r4, pc} + 1050 .L71: + 1051 .align 2 + 1052 .L70: + 1053 0058 00FF4F3F .word 1062207232 + 1054 .cfi_endproc + 1055 .LFE300: + 1057 .section .text.HAL_FLASHEx_EnableDebugger,"ax",%progbits + 1058 .align 1 + 1059 .global HAL_FLASHEx_EnableDebugger + 1060 .syntax unified + 1061 .code 16 + 1062 .thumb_func + 1063 .fpu softvfp + 1065 HAL_FLASHEx_EnableDebugger: + 1066 .LFB301: + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR |= FLASH_ACR_DBG_SWEN; + 1067 .loc 1 467 1 is_stmt 1 view -0 + 1068 .cfi_startproc + 1069 @ args = 0, pretend = 0, frame = 0 + 1070 @ frame_needed = 0, uses_anonymous_args = 0 + 1071 @ link register save eliminated. + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1072 .loc 1 468 3 view .LVU289 + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1073 .loc 1 468 14 is_stmt 0 view .LVU290 + 1074 0000 034A ldr r2, .L73 + 1075 0002 1168 ldr r1, [r2] + 1076 0004 8023 movs r3, #128 + 1077 0006 DB02 lsls r3, r3, #11 + 1078 0008 0B43 orrs r3, r1 + 1079 000a 1360 str r3, [r2] + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1080 .loc 1 469 1 view .LVU291 + 1081 @ sp needed + 1082 000c 7047 bx lr + 1083 .L74: + 1084 000e C046 .align 2 + 1085 .L73: + 1086 0010 00200240 .word 1073881088 + ARM GAS /tmp/ccHUARcC.s page 44 + + + 1087 .cfi_endproc + 1088 .LFE301: + 1090 .section .text.HAL_FLASHEx_DisableDebugger,"ax",%progbits + 1091 .align 1 + 1092 .global HAL_FLASHEx_DisableDebugger + 1093 .syntax unified + 1094 .code 16 + 1095 .thumb_func + 1096 .fpu softvfp + 1098 HAL_FLASHEx_DisableDebugger: + 1099 .LFB302: + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; + 1100 .loc 1 479 1 is_stmt 1 view -0 + 1101 .cfi_startproc + 1102 @ args = 0, pretend = 0, frame = 0 + 1103 @ frame_needed = 0, uses_anonymous_args = 0 + 1104 @ link register save eliminated. + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1105 .loc 1 480 3 view .LVU293 + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1106 .loc 1 480 14 is_stmt 0 view .LVU294 + 1107 0000 024A ldr r2, .L76 + 1108 0002 1368 ldr r3, [r2] + 1109 0004 0249 ldr r1, .L76+4 + 1110 0006 0B40 ands r3, r1 + 1111 0008 1360 str r3, [r2] + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_ACR_DBG_SWEN */ + 1112 .loc 1 481 1 view .LVU295 + 1113 @ sp needed + 1114 000a 7047 bx lr + 1115 .L77: + 1116 .align 2 + 1117 .L76: + 1118 000c 00200240 .word 1073881088 + 1119 0010 FFFFFBFF .word -262145 + 1120 .cfi_endproc + 1121 .LFE302: + 1123 .section .text.HAL_FLASHEx_FlashEmptyCheck,"ax",%progbits + 1124 .align 1 + 1125 .global HAL_FLASHEx_FlashEmptyCheck + 1126 .syntax unified + 1127 .code 16 + 1128 .thumb_func + 1129 .fpu softvfp + 1131 HAL_FLASHEx_FlashEmptyCheck: + 1132 .LFB303: + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** return ((FLASH->ACR & FLASH_ACR_PROGEMPTY)); + 1133 .loc 1 491 1 is_stmt 1 view -0 + 1134 .cfi_startproc + 1135 @ args = 0, pretend = 0, frame = 0 + 1136 @ frame_needed = 0, uses_anonymous_args = 0 + 1137 @ link register save eliminated. + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1138 .loc 1 492 3 view .LVU297 + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1139 .loc 1 492 17 is_stmt 0 view .LVU298 + 1140 0000 024B ldr r3, .L79 + ARM GAS /tmp/ccHUARcC.s page 45 + + + 1141 0002 1868 ldr r0, [r3] + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1142 .loc 1 492 23 view .LVU299 + 1143 0004 8023 movs r3, #128 + 1144 0006 5B02 lsls r3, r3, #9 + 1145 0008 1840 ands r0, r3 + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1146 .loc 1 493 1 view .LVU300 + 1147 @ sp needed + 1148 000a 7047 bx lr + 1149 .L80: + 1150 .align 2 + 1151 .L79: + 1152 000c 00200240 .word 1073881088 + 1153 .cfi_endproc + 1154 .LFE303: + 1156 .section .text.HAL_FLASHEx_ForceFlashEmpty,"ax",%progbits + 1157 .align 1 + 1158 .global HAL_FLASHEx_ForceFlashEmpty + 1159 .syntax unified + 1160 .code 16 + 1161 .thumb_func + 1162 .fpu softvfp + 1164 HAL_FLASHEx_ForceFlashEmpty: + 1165 .LVL88: + 1166 .LFB304: + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t acr; + 1167 .loc 1 505 1 is_stmt 1 view -0 + 1168 .cfi_startproc + 1169 @ args = 0, pretend = 0, frame = 0 + 1170 @ frame_needed = 0, uses_anonymous_args = 0 + 1171 @ link register save eliminated. + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + 1172 .loc 1 506 3 view .LVU302 + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1173 .loc 1 507 3 view .LVU303 + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR = (acr | FlashEmpty); + 1174 .loc 1 509 3 view .LVU304 + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR = (acr | FlashEmpty); + 1175 .loc 1 509 15 is_stmt 0 view .LVU305 + 1176 0000 034A ldr r2, .L82 + 1177 0002 1368 ldr r3, [r2] + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** FLASH->ACR = (acr | FlashEmpty); + 1178 .loc 1 509 7 view .LVU306 + 1179 0004 0349 ldr r1, .L82+4 + 1180 0006 0B40 ands r3, r1 + 1181 .LVL89: + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1182 .loc 1 510 3 is_stmt 1 view .LVU307 + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1183 .loc 1 510 21 is_stmt 0 view .LVU308 + 1184 0008 0343 orrs r3, r0 + 1185 .LVL90: + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1186 .loc 1 510 14 view .LVU309 + 1187 000a 1360 str r3, [r2] + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + ARM GAS /tmp/ccHUARcC.s page 46 + + + 1188 .loc 1 511 1 view .LVU310 + 1189 @ sp needed + 1190 000c 7047 bx lr + 1191 .L83: + 1192 000e C046 .align 2 + 1193 .L82: + 1194 0010 00200240 .word 1073881088 + 1195 0014 FFFFFEFF .word -65537 + 1196 .cfi_endproc + 1197 .LFE304: + 1199 .section .text.HAL_FLASHEx_EnableSecMemProtection,"ax",%progbits + 1200 .align 1 + 1201 .global HAL_FLASHEx_EnableSecMemProtection + 1202 .syntax unified + 1203 .code 16 + 1204 .thumb_func + 1205 .fpu softvfp + 1207 HAL_FLASHEx_EnableSecMemProtection: + 1208 .LVL91: + 1209 .LFB305: + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #if defined(FLASH_DBANK_SUPPORT) + 1210 .loc 1 527 1 is_stmt 1 view -0 + 1211 .cfi_startproc + 1212 @ args = 0, pretend = 0, frame = 0 + 1213 @ frame_needed = 0, uses_anonymous_args = 0 + 1214 @ link register save eliminated. + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1215 .loc 1 541 3 view .LVU312 + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1216 .loc 1 544 5 view .LVU313 + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1217 .loc 1 544 15 is_stmt 0 view .LVU314 + 1218 0000 034A ldr r2, .L85 + 1219 0002 5169 ldr r1, [r2, #20] + 1220 0004 8023 movs r3, #128 + 1221 0006 5B05 lsls r3, r3, #21 + 1222 0008 0B43 orrs r3, r1 + 1223 000a 5361 str r3, [r2, #20] + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ + 1224 .loc 1 546 1 view .LVU315 + 1225 @ sp needed + 1226 000c 7047 bx lr + 1227 .L86: + 1228 000e C046 .align 2 + 1229 .L85: + 1230 0010 00200240 .word 1073881088 + 1231 .cfi_endproc + 1232 .LFE305: + 1234 .section .text.FLASH_PageErase,"ax",%progbits + 1235 .align 1 + 1236 .global FLASH_PageErase + 1237 .syntax unified + 1238 .code 16 + 1239 .thumb_func + 1240 .fpu softvfp + 1242 FLASH_PageErase: + 1243 .LVL92: + ARM GAS /tmp/ccHUARcC.s page 47 + + + 1244 .LFB307: + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t tmp; + 1245 .loc 1 591 1 is_stmt 1 view -0 + 1246 .cfi_startproc + 1247 @ args = 0, pretend = 0, frame = 0 + 1248 @ frame_needed = 0, uses_anonymous_args = 0 + 1249 @ link register save eliminated. + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1250 .loc 1 592 3 view .LVU317 + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** assert_param(IS_FLASH_PAGE(Page)); + 1251 .loc 1 595 3 view .LVU318 + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1252 .loc 1 596 3 view .LVU319 + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1253 .loc 1 599 3 view .LVU320 + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1254 .loc 1 599 15 is_stmt 0 view .LVU321 + 1255 0000 044A ldr r2, .L88 + 1256 0002 5369 ldr r3, [r2, #20] + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1257 .loc 1 599 7 view .LVU322 + 1258 0004 F820 movs r0, #248 + 1259 .LVL93: + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1260 .loc 1 599 7 view .LVU323 + 1261 0006 8343 bics r3, r0 + 1262 .LVL94: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1263 .loc 1 614 3 is_stmt 1 view .LVU324 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1264 .loc 1 614 45 is_stmt 0 view .LVU325 + 1265 0008 C900 lsls r1, r1, #3 + 1266 .LVL95: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1267 .loc 1 614 20 view .LVU326 + 1268 000a 1943 orrs r1, r3 + 1269 000c 024B ldr r3, .L88+4 + 1270 .LVL96: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1271 .loc 1 614 20 view .LVU327 + 1272 000e 1943 orrs r1, r3 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1273 .loc 1 614 13 view .LVU328 + 1274 0010 5161 str r1, [r2, #20] + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1275 .loc 1 615 1 view .LVU329 + 1276 @ sp needed + 1277 0012 7047 bx lr + 1278 .L89: + 1279 .align 2 + 1280 .L88: + 1281 0014 00200240 .word 1073881088 + 1282 0018 02000100 .word 65538 + 1283 .cfi_endproc + 1284 .LFE307: + 1286 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 1287 .align 1 + ARM GAS /tmp/ccHUARcC.s page 48 + + + 1288 .global HAL_FLASHEx_Erase + 1289 .syntax unified + 1290 .code 16 + 1291 .thumb_func + 1292 .fpu softvfp + 1294 HAL_FLASHEx_Erase: + 1295 .LVL97: + 1296 .LFB297: + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1297 .loc 1 157 1 is_stmt 1 view -0 + 1298 .cfi_startproc + 1299 @ args = 0, pretend = 0, frame = 0 + 1300 @ frame_needed = 0, uses_anonymous_args = 0 + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1301 .loc 1 157 1 is_stmt 0 view .LVU331 + 1302 0000 70B5 push {r4, r5, r6, lr} + 1303 .LCFI9: + 1304 .cfi_def_cfa_offset 16 + 1305 .cfi_offset 4, -16 + 1306 .cfi_offset 5, -12 + 1307 .cfi_offset 6, -8 + 1308 .cfi_offset 14, -4 + 1309 0002 0400 movs r4, r0 + 1310 0004 0E00 movs r6, r1 + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** uint32_t index; + 1311 .loc 1 158 3 is_stmt 1 view .LVU332 + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1312 .loc 1 159 3 view .LVU333 + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1313 .loc 1 162 3 view .LVU334 + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1314 .loc 1 165 3 view .LVU335 + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1315 .loc 1 165 3 view .LVU336 + 1316 0006 1F4B ldr r3, .L101 + 1317 0008 1B78 ldrb r3, [r3] + 1318 000a 012B cmp r3, #1 + 1319 000c 37D0 beq .L98 + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1320 .loc 1 165 3 discriminator 2 view .LVU337 + 1321 000e 1D4B ldr r3, .L101 + 1322 0010 0122 movs r2, #1 + 1323 0012 1A70 strb r2, [r3] + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1324 .loc 1 165 3 discriminator 2 view .LVU338 + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1325 .loc 1 168 3 discriminator 2 view .LVU339 + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1326 .loc 1 168 20 is_stmt 0 discriminator 2 view .LVU340 + 1327 0014 0022 movs r2, #0 + 1328 0016 5A60 str r2, [r3, #4] + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1329 .loc 1 171 3 is_stmt 1 discriminator 2 view .LVU341 + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1330 .loc 1 171 12 is_stmt 0 discriminator 2 view .LVU342 + 1331 0018 FA20 movs r0, #250 + 1332 .LVL98: + ARM GAS /tmp/ccHUARcC.s page 49 + + + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1333 .loc 1 171 12 discriminator 2 view .LVU343 + 1334 001a 8000 lsls r0, r0, #2 + 1335 001c FFF7FEFF bl FLASH_WaitForLastOperation + 1336 .LVL99: + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1337 .loc 1 173 3 is_stmt 1 discriminator 2 view .LVU344 + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1338 .loc 1 173 6 is_stmt 0 discriminator 2 view .LVU345 + 1339 0020 0028 cmp r0, #0 + 1340 0022 28D1 bne .L92 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1341 .loc 1 177 5 is_stmt 1 view .LVU346 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1342 .loc 1 177 23 is_stmt 0 view .LVU347 + 1343 0024 0423 movs r3, #4 + 1344 0026 6360 str r3, [r4, #4] + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1345 .loc 1 180 5 is_stmt 1 view .LVU348 + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1346 .loc 1 180 8 is_stmt 0 view .LVU349 + 1347 0028 2368 ldr r3, [r4] + 1348 002a 042B cmp r3, #4 + 1349 002c 15D0 beq .L99 + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1350 .loc 1 191 7 is_stmt 1 view .LVU350 + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1351 .loc 1 191 18 is_stmt 0 view .LVU351 + 1352 002e 0123 movs r3, #1 + 1353 0030 5B42 rsbs r3, r3, #0 + 1354 0032 3360 str r3, [r6] + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1355 .loc 1 193 7 is_stmt 1 view .LVU352 + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1356 .loc 1 193 18 is_stmt 0 view .LVU353 + 1357 0034 A568 ldr r5, [r4, #8] + 1358 .LVL100: + 1359 .L94: + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1360 .loc 1 193 38 is_stmt 1 discriminator 1 view .LVU354 + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1361 .loc 1 193 64 is_stmt 0 discriminator 1 view .LVU355 + 1362 0036 A368 ldr r3, [r4, #8] + 1363 0038 E268 ldr r2, [r4, #12] + 1364 003a 9446 mov ip, r2 + 1365 003c 6344 add r3, r3, ip + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1366 .loc 1 193 7 discriminator 1 view .LVU356 + 1367 003e AB42 cmp r3, r5 + 1368 0040 14D9 bls .L96 + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1369 .loc 1 196 9 is_stmt 1 view .LVU357 + 1370 0042 2900 movs r1, r5 + 1371 0044 6068 ldr r0, [r4, #4] + 1372 .LVL101: + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1373 .loc 1 196 9 is_stmt 0 view .LVU358 + ARM GAS /tmp/ccHUARcC.s page 50 + + + 1374 0046 FFF7FEFF bl FLASH_PageErase + 1375 .LVL102: + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1376 .loc 1 199 9 is_stmt 1 view .LVU359 + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1377 .loc 1 199 18 is_stmt 0 view .LVU360 + 1378 004a FA20 movs r0, #250 + 1379 004c 8000 lsls r0, r0, #2 + 1380 004e FFF7FEFF bl FLASH_WaitForLastOperation + 1381 .LVL103: + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1382 .loc 1 201 9 is_stmt 1 view .LVU361 + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1383 .loc 1 201 12 is_stmt 0 view .LVU362 + 1384 0052 0028 cmp r0, #0 + 1385 0054 09D1 bne .L100 + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1386 .loc 1 193 88 is_stmt 1 discriminator 2 view .LVU363 + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1387 .loc 1 193 93 is_stmt 0 discriminator 2 view .LVU364 + 1388 0056 0135 adds r5, r5, #1 + 1389 .LVL104: + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1390 .loc 1 193 93 discriminator 2 view .LVU365 + 1391 0058 EDE7 b .L94 + 1392 .LVL105: + 1393 .L99: + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1394 .loc 1 183 7 is_stmt 1 view .LVU366 + 1395 005a 0430 adds r0, r0, #4 + 1396 .LVL106: + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1397 .loc 1 183 7 is_stmt 0 view .LVU367 + 1398 005c FFF7FEFF bl FLASH_MassErase + 1399 .LVL107: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1400 .loc 1 186 7 is_stmt 1 view .LVU368 + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1401 .loc 1 186 16 is_stmt 0 view .LVU369 + 1402 0060 FA20 movs r0, #250 + 1403 0062 8000 lsls r0, r0, #2 + 1404 0064 FFF7FEFF bl FLASH_WaitForLastOperation + 1405 .LVL108: + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1406 .loc 1 186 16 view .LVU370 + 1407 0068 05E0 b .L92 + 1408 .LVL109: + 1409 .L100: + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** break; + 1410 .loc 1 204 11 is_stmt 1 view .LVU371 + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** break; + 1411 .loc 1 204 22 is_stmt 0 view .LVU372 + 1412 006a 3560 str r5, [r6] + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1413 .loc 1 205 11 is_stmt 1 view .LVU373 + 1414 .LVL110: + 1415 .L96: + ARM GAS /tmp/ccHUARcC.s page 51 + + + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1416 .loc 1 210 7 view .LVU374 + 1417 006c 064A ldr r2, .L101+4 + 1418 006e 5369 ldr r3, [r2, #20] + 1419 0070 0221 movs r1, #2 + 1420 0072 8B43 bics r3, r1 + 1421 0074 5361 str r3, [r2, #20] + 1422 .LVL111: + 1423 .L92: + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1424 .loc 1 215 3 view .LVU375 + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1425 .loc 1 215 3 view .LVU376 + 1426 0076 034B ldr r3, .L101 + 1427 0078 0022 movs r2, #0 + 1428 007a 1A70 strb r2, [r3] + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1429 .loc 1 215 3 view .LVU377 + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1430 .loc 1 218 3 view .LVU378 + 1431 .LVL112: + 1432 .L91: + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1433 .loc 1 219 1 is_stmt 0 view .LVU379 + 1434 @ sp needed + 1435 .LVL113: + 1436 .LVL114: + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1437 .loc 1 219 1 view .LVU380 + 1438 007c 70BD pop {r4, r5, r6, pc} + 1439 .LVL115: + 1440 .L98: + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1441 .loc 1 165 3 view .LVU381 + 1442 007e 0220 movs r0, #2 + 1443 .LVL116: + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1444 .loc 1 165 3 view .LVU382 + 1445 0080 FCE7 b .L91 + 1446 .L102: + 1447 0082 C046 .align 2 + 1448 .L101: + 1449 0084 00000000 .word pFlash + 1450 0088 00200240 .word 1073881088 + 1451 .cfi_endproc + 1452 .LFE297: + 1454 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 1455 .align 1 + 1456 .global HAL_FLASHEx_Erase_IT + 1457 .syntax unified + 1458 .code 16 + 1459 .thumb_func + 1460 .fpu softvfp + 1462 HAL_FLASHEx_Erase_IT: + 1463 .LVL117: + 1464 .LFB298: + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + ARM GAS /tmp/ccHUARcC.s page 52 + + + 1465 .loc 1 229 1 is_stmt 1 view -0 + 1466 .cfi_startproc + 1467 @ args = 0, pretend = 0, frame = 0 + 1468 @ frame_needed = 0, uses_anonymous_args = 0 + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** HAL_StatusTypeDef status; + 1469 .loc 1 229 1 is_stmt 0 view .LVU384 + 1470 0000 70B5 push {r4, r5, r6, lr} + 1471 .LCFI10: + 1472 .cfi_def_cfa_offset 16 + 1473 .cfi_offset 4, -16 + 1474 .cfi_offset 5, -12 + 1475 .cfi_offset 6, -8 + 1476 .cfi_offset 14, -4 + 1477 0002 0400 movs r4, r0 + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1478 .loc 1 230 3 is_stmt 1 view .LVU385 + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1479 .loc 1 233 3 view .LVU386 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1480 .loc 1 236 3 view .LVU387 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1481 .loc 1 236 3 view .LVU388 + 1482 0004 1A4B ldr r3, .L109 + 1483 0006 1B78 ldrb r3, [r3] + 1484 0008 012B cmp r3, #1 + 1485 000a 2ED0 beq .L107 + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1486 .loc 1 236 3 discriminator 2 view .LVU389 + 1487 000c 184B ldr r3, .L109 + 1488 000e 0122 movs r2, #1 + 1489 0010 1A70 strb r2, [r3] + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1490 .loc 1 236 3 discriminator 2 view .LVU390 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1491 .loc 1 239 3 discriminator 2 view .LVU391 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1492 .loc 1 239 20 is_stmt 0 discriminator 2 view .LVU392 + 1493 0012 0022 movs r2, #0 + 1494 0014 5A60 str r2, [r3, #4] + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1495 .loc 1 242 3 is_stmt 1 discriminator 2 view .LVU393 + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1496 .loc 1 242 27 is_stmt 0 discriminator 2 view .LVU394 + 1497 0016 0268 ldr r2, [r0] + 1498 0018 9A60 str r2, [r3, #8] + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1499 .loc 1 245 3 is_stmt 1 discriminator 2 view .LVU395 + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1500 .loc 1 245 12 is_stmt 0 discriminator 2 view .LVU396 + 1501 001a FA20 movs r0, #250 + 1502 .LVL118: + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1503 .loc 1 245 12 discriminator 2 view .LVU397 + 1504 001c 8000 lsls r0, r0, #2 + 1505 001e FFF7FEFF bl FLASH_WaitForLastOperation + 1506 .LVL119: + 1507 0022 051E subs r5, r0, #0 + ARM GAS /tmp/ccHUARcC.s page 53 + + + 1508 .LVL120: + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1509 .loc 1 247 3 is_stmt 1 discriminator 2 view .LVU398 + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1510 .loc 1 247 6 is_stmt 0 discriminator 2 view .LVU399 + 1511 0024 04D0 beq .L105 + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1512 .loc 1 250 5 is_stmt 1 view .LVU400 + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1513 .loc 1 250 5 view .LVU401 + 1514 0026 124B ldr r3, .L109 + 1515 0028 0022 movs r2, #0 + 1516 002a 1A70 strb r2, [r3] + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1517 .loc 1 250 5 view .LVU402 + 1518 .LVL121: + 1519 .L104: + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1520 .loc 1 285 1 is_stmt 0 view .LVU403 + 1521 002c 2800 movs r0, r5 + 1522 @ sp needed + 1523 .LVL122: + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1524 .loc 1 285 1 view .LVU404 + 1525 002e 70BD pop {r4, r5, r6, pc} + 1526 .LVL123: + 1527 .L105: + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1528 .loc 1 256 5 is_stmt 1 view .LVU405 + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** #endif /* FLASH_DBANK_SUPPORT */ + 1529 .loc 1 256 23 is_stmt 0 view .LVU406 + 1530 0030 0423 movs r3, #4 + 1531 0032 6360 str r3, [r4, #4] + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1532 .loc 1 259 5 is_stmt 1 view .LVU407 + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1533 .loc 1 259 18 is_stmt 0 view .LVU408 + 1534 0034 0E4A ldr r2, .L109 + 1535 0036 1361 str r3, [r2, #16] + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1536 .loc 1 262 5 is_stmt 1 view .LVU409 + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1537 .loc 1 262 15 is_stmt 0 view .LVU410 + 1538 0038 0E4A ldr r2, .L109+4 + 1539 003a 5169 ldr r1, [r2, #20] + 1540 003c C023 movs r3, #192 + 1541 003e 9B04 lsls r3, r3, #18 + 1542 0040 0B43 orrs r3, r1 + 1543 0042 5361 str r3, [r2, #20] + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1544 .loc 1 264 5 is_stmt 1 view .LVU411 + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1545 .loc 1 264 8 is_stmt 0 view .LVU412 + 1546 0044 2368 ldr r3, [r4] + 1547 0046 042B cmp r3, #4 + 1548 0048 08D0 beq .L108 + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.Page = pEraseInit->Page; + ARM GAS /tmp/ccHUARcC.s page 54 + + + 1549 .loc 1 275 7 is_stmt 1 view .LVU413 + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** pFlash.Page = pEraseInit->Page; + 1550 .loc 1 275 29 is_stmt 0 view .LVU414 + 1551 004a 094B ldr r3, .L109 + 1552 004c E268 ldr r2, [r4, #12] + 1553 004e 9A61 str r2, [r3, #24] + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1554 .loc 1 276 7 is_stmt 1 view .LVU415 + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1555 .loc 1 276 31 is_stmt 0 view .LVU416 + 1556 0050 A168 ldr r1, [r4, #8] + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1557 .loc 1 276 19 view .LVU417 + 1558 0052 5961 str r1, [r3, #20] + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1559 .loc 1 279 7 is_stmt 1 view .LVU418 + 1560 0054 6068 ldr r0, [r4, #4] + 1561 .LVL124: + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1562 .loc 1 279 7 is_stmt 0 view .LVU419 + 1563 0056 FFF7FEFF bl FLASH_PageErase + 1564 .LVL125: + 1565 005a E7E7 b .L104 + 1566 .LVL126: + 1567 .L108: + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1568 .loc 1 267 7 is_stmt 1 view .LVU420 + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1569 .loc 1 267 19 is_stmt 0 view .LVU421 + 1570 005c 044B ldr r3, .L109 + 1571 005e 0022 movs r2, #0 + 1572 0060 5A61 str r2, [r3, #20] + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1573 .loc 1 270 7 is_stmt 1 view .LVU422 + 1574 0062 6068 ldr r0, [r4, #4] + 1575 .LVL127: + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1576 .loc 1 270 7 is_stmt 0 view .LVU423 + 1577 0064 FFF7FEFF bl FLASH_MassErase + 1578 .LVL128: + 1579 0068 E0E7 b .L104 + 1580 .LVL129: + 1581 .L107: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1582 .loc 1 236 3 view .LVU424 + 1583 006a 0225 movs r5, #2 + 1584 006c DEE7 b .L104 + 1585 .L110: + 1586 006e C046 .align 2 + 1587 .L109: + 1588 0070 00000000 .word pFlash + 1589 0074 00200240 .word 1073881088 + 1590 .cfi_endproc + 1591 .LFE298: + 1593 .section .text.FLASH_FlushCaches,"ax",%progbits + 1594 .align 1 + 1595 .global FLASH_FlushCaches + ARM GAS /tmp/ccHUARcC.s page 55 + + + 1596 .syntax unified + 1597 .code 16 + 1598 .thumb_func + 1599 .fpu softvfp + 1601 FLASH_FlushCaches: + 1602 .LFB308: + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Flush instruction cache */ + 1603 .loc 1 622 1 is_stmt 1 view -0 + 1604 .cfi_startproc + 1605 @ args = 0, pretend = 0, frame = 0 + 1606 @ frame_needed = 0, uses_anonymous_args = 0 + 1607 @ link register save eliminated. + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1608 .loc 1 624 3 view .LVU426 + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1609 .loc 1 624 7 is_stmt 0 view .LVU427 + 1610 0000 0B4B ldr r3, .L113 + 1611 0002 1B68 ldr r3, [r3] + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** { + 1612 .loc 1 624 6 view .LVU428 + 1613 0004 9B05 lsls r3, r3, #22 + 1614 0006 12D5 bpl .L111 + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Reset instruction cache */ + 1615 .loc 1 627 5 is_stmt 1 view .LVU429 + 1616 0008 094B ldr r3, .L113 + 1617 000a 1A68 ldr r2, [r3] + 1618 000c 0949 ldr r1, .L113+4 + 1619 000e 0A40 ands r2, r1 + 1620 0010 1A60 str r2, [r3] + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable instruction cache */ + 1621 .loc 1 629 5 view .LVU430 + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable instruction cache */ + 1622 .loc 1 629 5 view .LVU431 + 1623 0012 1968 ldr r1, [r3] + 1624 0014 8022 movs r2, #128 + 1625 0016 1201 lsls r2, r2, #4 + 1626 0018 0A43 orrs r2, r1 + 1627 001a 1A60 str r2, [r3] + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable instruction cache */ + 1628 .loc 1 629 5 view .LVU432 + 1629 001c 1A68 ldr r2, [r3] + 1630 001e 0649 ldr r1, .L113+8 + 1631 0020 0A40 ands r2, r1 + 1632 0022 1A60 str r2, [r3] + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** /* Enable instruction cache */ + 1633 .loc 1 629 5 view .LVU433 + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** } + 1634 .loc 1 631 5 view .LVU434 + 1635 0024 1968 ldr r1, [r3] + 1636 0026 8022 movs r2, #128 + 1637 0028 9200 lsls r2, r2, #2 + 1638 002a 0A43 orrs r2, r1 + 1639 002c 1A60 str r2, [r3] + 1640 .L111: + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c **** + 1641 .loc 1 633 1 is_stmt 0 view .LVU435 + 1642 @ sp needed + ARM GAS /tmp/ccHUARcC.s page 56 + + + 1643 002e 7047 bx lr + 1644 .L114: + 1645 .align 2 + 1646 .L113: + 1647 0030 00200240 .word 1073881088 + 1648 0034 FFFDFFFF .word -513 + 1649 0038 FFF7FFFF .word -2049 + 1650 .cfi_endproc + 1651 .LFE308: + 1653 .text + 1654 .Letext0: + 1655 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1656 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1657 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1658 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h" + 1659 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccHUARcC.s page 57 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_flash_ex.c + /tmp/ccHUARcC.s:16 .text.FLASH_MassErase:0000000000000000 $t + /tmp/ccHUARcC.s:23 .text.FLASH_MassErase:0000000000000000 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+++ b/squero/build/stm32g0xx_hal_gpio.d @@ -0,0 +1,59 @@ +build/stm32g0xx_hal_gpio.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_gpio.lst b/squero/build/stm32g0xx_hal_gpio.lst new file mode 100644 index 0000000..5a7e593 --- /dev/null +++ b/squero/build/stm32g0xx_hal_gpio.lst @@ -0,0 +1,1774 @@ +ARM GAS /tmp/ccUoVykV.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_gpio.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_GPIO_Init,"ax",%progbits + 16 .align 1 + 17 .global HAL_GPIO_Init + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_GPIO_Init: + 25 .LVL0: + 26 .LFB297: + 27 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @file stm32g0xx_hal_gpio.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief GPIO HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * functionalities of the General Purpose Input/Output (GPIO) peripheral: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + IO operation functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @verbatim + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ============================================================================== + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ##### GPIO Peripheral features ##### + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ============================================================================== + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** [..] + 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** configured by software in several modes: + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Input mode + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Analog mode + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Output mode + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Alternate function mode + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) External interrupt/event lines + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) During and just after reset, the alternate functions and external interrupt + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** lines are not active and the I/O ports are configured in input floating mode. + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** activated or not. + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** type and the IO speed can be selected depending on the VDD value. + ARM GAS /tmp/ccUoVykV.s page 2 + + + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** multiplexer that allows only one peripheral alternate function (AF) connected + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** to an IO pin at a time. In this way, there can be no conflict between peripherals + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** sharing the same IO pin. + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) All ports have external interrupt/event capability. To use external interrupt + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** lines, the port must be configured in input mode. All available GPIO pins are + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (+) The external interrupt/event controller consists of up to 28 edge detectors + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (16 lines are connected to GPIO) for generating event/interrupt requests (each + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** input line can be independently configured to select the type (interrupt or event) + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** and the corresponding trigger event (rising or falling or both). Each line can + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** also be masked independently. + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ##### How to use this driver ##### + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ============================================================================== + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** [..] + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** structure. + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) In case of Output or alternate function mode selection: the speed is + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** configured through "Speed" member from GPIO_InitTypeDef structure. + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) In alternate mode is selection, the alternate function connected to the IO + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** is configured through "Alternate" member from GPIO_InitTypeDef structure. + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) Analog mode is required when a pin is to be used as ADC channel + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** or DAC output. + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (++) In case of external interrupt/event selection the "Mode" member from + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIO_InitTypeDef structure select the type (interrupt or event) and + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** the corresponding trigger event (rising or falling or both). + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_NVIC_EnableIRQ(). + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) During and just after reset, the alternate functions are not + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** active and the GPIO pins are configured in input floating mode (except JTAG + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** pins). + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** priority over the GPIO function. + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** The HSE has priority over the GPIO function. + ARM GAS /tmp/ccUoVykV.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @endverbatim + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ****************************************************************************** + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @attention + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** *

© Copyright (c) 2018 STMicroelectronics. + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * All rights reserved.

+ 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This software component is licensed by ST under BSD 3-Clause license, + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * the "License"; You may not use this file except in compliance with the + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * License. You may obtain a copy of the License at: + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * opensource.org/licenses/BSD-3-Clause + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ****************************************************************************** + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** #include "stm32g0xx_hal.h" + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup STM32G0xx_HAL_Driver + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup GPIO + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** MISRA C:2012 deviation rule has been granted for following rules: + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * range of the shift operator in following API : + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * HAL_GPIO_Init + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * HAL_GPIO_DeInit + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Private defines ------------------------------------------------------------*/ + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** #define GPIO_NUMBER (16u) + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @} + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/ + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions_Group1 + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Initialization and Configuration functions + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + ARM GAS /tmp/ccUoVykV.s page 4 + + + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @verbatim + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** =============================================================================== + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** =============================================================================== + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @endverbatim + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 28 .loc 1 163 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 163 1 is_stmt 0 view .LVU1 + 33 0000 F0B5 push {r4, r5, r6, r7, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 20 + 36 .cfi_offset 4, -20 + 37 .cfi_offset 5, -16 + 38 .cfi_offset 6, -12 + 39 .cfi_offset 7, -8 + 40 .cfi_offset 14, -4 + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t position = 0x00u; + 41 .loc 1 164 3 is_stmt 1 view .LVU2 + 42 .LVL1: + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t iocurrent; + 43 .loc 1 165 3 view .LVU3 + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t temp; + 44 .loc 1 166 3 view .LVU4 + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 45 .loc 1 169 3 view .LVU5 + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 46 .loc 1 170 3 view .LVU6 + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 47 .loc 1 171 3 view .LVU7 + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the port pins */ + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** while (((GPIO_Init->Pin) >> position) != 0x00u) + 48 .loc 1 174 3 view .LVU8 + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t iocurrent; + 49 .loc 1 164 12 is_stmt 0 view .LVU9 + 50 0002 0023 movs r3, #0 + 51 .loc 1 174 9 view .LVU10 + 52 0004 5AE0 b .L2 + 53 .LVL2: + 54 .L18: + ARM GAS /tmp/ccUoVykV.s page 5 + + + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Get current io position */ + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** iocurrent = (GPIO_Init->Pin) & (1uL << position); + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (iocurrent != 0x00u) + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_ + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the Speed parameter */ + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 55 .loc 1 186 9 is_stmt 1 view .LVU11 + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the IO Speed */ + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 56 .loc 1 189 9 view .LVU12 + 57 .loc 1 189 14 is_stmt 0 view .LVU13 + 58 0006 8468 ldr r4, [r0, #8] + 59 .LVL3: + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 60 .loc 1 190 9 is_stmt 1 view .LVU14 + 61 .loc 1 190 53 is_stmt 0 view .LVU15 + 62 0008 5F00 lsls r7, r3, #1 + 63 .loc 1 190 40 view .LVU16 + 64 000a 0326 movs r6, #3 + 65 000c BE40 lsls r6, r6, r7 + 66 .loc 1 190 14 view .LVU17 + 67 000e B443 bics r4, r6 + 68 .LVL4: + 69 .loc 1 190 14 view .LVU18 + 70 0010 2600 movs r6, r4 + 71 .LVL5: + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2u)); + 72 .loc 1 191 9 is_stmt 1 view .LVU19 + 73 .loc 1 191 35 is_stmt 0 view .LVU20 + 74 0012 CC68 ldr r4, [r1, #12] + 75 .LVL6: + 76 .loc 1 191 35 view .LVU21 + 77 0014 BC40 lsls r4, r4, r7 + 78 .loc 1 191 14 view .LVU22 + 79 0016 3443 orrs r4, r6 + 80 .LVL7: + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 81 .loc 1 192 9 is_stmt 1 view .LVU23 + 82 .loc 1 192 24 is_stmt 0 view .LVU24 + 83 0018 8460 str r4, [r0, #8] + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the IO Output Type */ + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = GPIOx->OTYPER; + 84 .loc 1 195 9 is_stmt 1 view .LVU25 + 85 .loc 1 195 14 is_stmt 0 view .LVU26 + 86 001a 4468 ldr r4, [r0, #4] + 87 .LVL8: + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT0 << position) ; + 88 .loc 1 196 9 is_stmt 1 view .LVU27 + 89 .loc 1 196 14 is_stmt 0 view .LVU28 + ARM GAS /tmp/ccUoVykV.s page 6 + + + 90 001c 9443 bics r4, r2 + 91 .LVL9: + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 92 .loc 1 197 9 is_stmt 1 view .LVU29 + 93 .loc 1 197 51 is_stmt 0 view .LVU30 + 94 001e 4A68 ldr r2, [r1, #4] + 95 0020 1609 lsrs r6, r2, #4 + 96 0022 0122 movs r2, #1 + 97 0024 3240 ands r2, r6 + 98 .loc 1 197 71 view .LVU31 + 99 0026 9A40 lsls r2, r2, r3 + 100 .loc 1 197 14 view .LVU32 + 101 0028 2243 orrs r2, r4 + 102 .LVL10: + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 103 .loc 1 198 9 is_stmt 1 view .LVU33 + 104 .loc 1 198 23 is_stmt 0 view .LVU34 + 105 002a 4260 str r2, [r0, #4] + 106 002c 56E0 b .L4 + 107 .LVL11: + 108 .L19: + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the Pull parameter */ + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the Alternate function parameters */ + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + 109 .loc 1 217 9 is_stmt 1 view .LVU35 + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 110 .loc 1 218 9 view .LVU36 + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3u]; + 111 .loc 1 221 9 view .LVU37 + 112 .loc 1 221 36 is_stmt 0 view .LVU38 + 113 002e DC08 lsrs r4, r3, #3 + 114 .loc 1 221 14 view .LVU39 + 115 0030 0834 adds r4, r4, #8 + 116 0032 A400 lsls r4, r4, #2 + 117 0034 2658 ldr r6, [r4, r0] + 118 .LVL12: + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 119 .loc 1 222 9 is_stmt 1 view .LVU40 + 120 .loc 1 222 38 is_stmt 0 view .LVU41 + ARM GAS /tmp/ccUoVykV.s page 7 + + + 121 0036 0532 adds r2, r2, #5 + 122 0038 1A40 ands r2, r3 + 123 .loc 1 222 47 view .LVU42 + 124 003a 9200 lsls r2, r2, #2 + 125 .loc 1 222 24 view .LVU43 + 126 003c 0F27 movs r7, #15 + 127 003e 9740 lsls r7, r7, r2 + 128 .loc 1 222 14 view .LVU44 + 129 0040 BE43 bics r6, r7 + 130 .LVL13: + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 131 .loc 1 223 9 is_stmt 1 view .LVU45 + 132 .loc 1 223 41 is_stmt 0 view .LVU46 + 133 0042 0F69 ldr r7, [r1, #16] + 134 0044 9740 lsls r7, r7, r2 + 135 0046 3A00 movs r2, r7 + 136 .loc 1 223 14 view .LVU47 + 137 0048 3243 orrs r2, r6 + 138 .LVL14: + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] = temp; + 139 .loc 1 224 9 is_stmt 1 view .LVU48 + 140 .loc 1 224 36 is_stmt 0 view .LVU49 + 141 004a 2250 str r2, [r4, r0] + 142 004c 5AE0 b .L6 + 143 .LVL15: + 144 .L20: + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = GPIOx->MODER; + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER = temp; + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = EXTI->EXTICR[position >> 2u]; + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(0x0FuL << (8u * (position & 0x03u))); + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 145 .loc 1 239 18 view .LVU50 + 146 004e 0326 movs r6, #3 + 147 0050 00E0 b .L7 + 148 .L13: + 149 0052 0026 movs r6, #0 + 150 .L7: + 151 .loc 1 239 40 discriminator 16 view .LVU51 + 152 0054 A640 lsls r6, r6, r4 + 153 0056 3400 movs r4, r6 + 154 .loc 1 239 14 discriminator 16 view .LVU52 + 155 0058 3C43 orrs r4, r7 + 156 .LVL16: + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 157 .loc 1 240 9 is_stmt 1 discriminator 16 view .LVU53 + 158 .loc 1 240 38 is_stmt 0 discriminator 16 view .LVU54 + 159 005a 434E ldr r6, .L21 + ARM GAS /tmp/ccUoVykV.s page 8 + + + 160 005c 1832 adds r2, r2, #24 + 161 005e 9200 lsls r2, r2, #2 + 162 0060 9451 str r4, [r2, r6] + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = EXTI->IMR1; + 163 .loc 1 243 9 is_stmt 1 discriminator 16 view .LVU55 + 164 .loc 1 243 14 is_stmt 0 discriminator 16 view .LVU56 + 165 0062 8022 movs r2, #128 + 166 0064 B458 ldr r4, [r6, r2] + 167 .LVL17: + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(iocurrent); + 168 .loc 1 244 9 is_stmt 1 discriminator 16 view .LVU57 + 169 .loc 1 244 17 is_stmt 0 discriminator 16 view .LVU58 + 170 0066 EA43 mvns r2, r5 + 171 .loc 1 244 14 discriminator 16 view .LVU59 + 172 0068 2600 movs r6, r4 + 173 006a AE43 bics r6, r5 + 174 .LVL18: + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 175 .loc 1 245 9 is_stmt 1 discriminator 16 view .LVU60 + 176 .loc 1 245 12 is_stmt 0 discriminator 16 view .LVU61 + 177 006c 4F68 ldr r7, [r1, #4] + 178 006e FF03 lsls r7, r7, #15 + 179 0070 01D5 bpl .L8 + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= iocurrent; + 180 .loc 1 247 11 is_stmt 1 view .LVU62 + 181 .loc 1 247 16 is_stmt 0 view .LVU63 + 182 0072 2C43 orrs r4, r5 + 183 0074 2600 movs r6, r4 + 184 .LVL19: + 185 .L8: + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->IMR1 = temp; + 186 .loc 1 249 9 is_stmt 1 view .LVU64 + 187 .loc 1 249 20 is_stmt 0 view .LVU65 + 188 0076 3C4C ldr r4, .L21 + 189 0078 8027 movs r7, #128 + 190 007a E651 str r6, [r4, r7] + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = EXTI->EMR1; + 191 .loc 1 251 9 is_stmt 1 view .LVU66 + 192 .loc 1 251 14 is_stmt 0 view .LVU67 + 193 007c 8426 movs r6, #132 + 194 .LVL20: + 195 .loc 1 251 14 view .LVU68 + 196 007e A459 ldr r4, [r4, r6] + 197 .LVL21: + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(iocurrent); + 198 .loc 1 252 9 is_stmt 1 view .LVU69 + 199 .loc 1 252 14 is_stmt 0 view .LVU70 + 200 0080 2600 movs r6, r4 + 201 0082 1640 ands r6, r2 + 202 .LVL22: + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 203 .loc 1 253 9 is_stmt 1 view .LVU71 + ARM GAS /tmp/ccUoVykV.s page 9 + + + 204 .loc 1 253 12 is_stmt 0 view .LVU72 + 205 0084 4F68 ldr r7, [r1, #4] + 206 0086 BF03 lsls r7, r7, #14 + 207 0088 01D5 bpl .L9 + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= iocurrent; + 208 .loc 1 255 11 is_stmt 1 view .LVU73 + 209 .loc 1 255 16 is_stmt 0 view .LVU74 + 210 008a 2C43 orrs r4, r5 + 211 008c 2600 movs r6, r4 + 212 .LVL23: + 213 .L9: + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EMR1 = temp; + 214 .loc 1 257 9 is_stmt 1 view .LVU75 + 215 .loc 1 257 20 is_stmt 0 view .LVU76 + 216 008e 364C ldr r4, .L21 + 217 0090 8427 movs r7, #132 + 218 0092 E651 str r6, [r4, r7] + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = EXTI->RTSR1; + 219 .loc 1 260 9 is_stmt 1 view .LVU77 + 220 .loc 1 260 14 is_stmt 0 view .LVU78 + 221 0094 2468 ldr r4, [r4] + 222 .LVL24: + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(iocurrent); + 223 .loc 1 261 9 is_stmt 1 view .LVU79 + 224 .loc 1 261 14 is_stmt 0 view .LVU80 + 225 0096 2600 movs r6, r4 + 226 0098 1640 ands r6, r2 + 227 .LVL25: + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 228 .loc 1 262 9 is_stmt 1 view .LVU81 + 229 .loc 1 262 12 is_stmt 0 view .LVU82 + 230 009a 4F68 ldr r7, [r1, #4] + 231 009c FF02 lsls r7, r7, #11 + 232 009e 01D5 bpl .L10 + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= iocurrent; + 233 .loc 1 264 11 is_stmt 1 view .LVU83 + 234 .loc 1 264 16 is_stmt 0 view .LVU84 + 235 00a0 2C43 orrs r4, r5 + 236 00a2 2600 movs r6, r4 + 237 .LVL26: + 238 .L10: + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->RTSR1 = temp; + 239 .loc 1 266 9 is_stmt 1 view .LVU85 + 240 .loc 1 266 21 is_stmt 0 view .LVU86 + 241 00a4 304C ldr r4, .L21 + 242 00a6 2660 str r6, [r4] + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp = EXTI->FTSR1; + 243 .loc 1 268 9 is_stmt 1 view .LVU87 + 244 .loc 1 268 14 is_stmt 0 view .LVU88 + 245 00a8 6468 ldr r4, [r4, #4] + ARM GAS /tmp/ccUoVykV.s page 10 + + + 246 .LVL27: + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(iocurrent); + 247 .loc 1 269 9 is_stmt 1 view .LVU89 + 248 .loc 1 269 14 is_stmt 0 view .LVU90 + 249 00aa 2240 ands r2, r4 + 250 .LVL28: + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 251 .loc 1 270 9 is_stmt 1 view .LVU91 + 252 .loc 1 270 12 is_stmt 0 view .LVU92 + 253 00ac 4E68 ldr r6, [r1, #4] + 254 00ae B602 lsls r6, r6, #10 + 255 00b0 01D5 bpl .L11 + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= iocurrent; + 256 .loc 1 272 11 is_stmt 1 view .LVU93 + 257 .loc 1 272 16 is_stmt 0 view .LVU94 + 258 00b2 2A00 movs r2, r5 + 259 .LVL29: + 260 .loc 1 272 16 view .LVU95 + 261 00b4 2243 orrs r2, r4 + 262 .LVL30: + 263 .L11: + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->FTSR1 = temp; + 264 .loc 1 274 9 is_stmt 1 view .LVU96 + 265 .loc 1 274 21 is_stmt 0 view .LVU97 + 266 00b6 2C4C ldr r4, .L21 + 267 00b8 6260 str r2, [r4, #4] + 268 .LVL31: + 269 .L3: + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** position++; + 270 .loc 1 278 5 is_stmt 1 view .LVU98 + 271 .loc 1 278 13 is_stmt 0 view .LVU99 + 272 00ba 0133 adds r3, r3, #1 + 273 .LVL32: + 274 .L2: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 275 .loc 1 174 9 is_stmt 1 view .LVU100 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 276 .loc 1 174 21 is_stmt 0 view .LVU101 + 277 00bc 0C68 ldr r4, [r1] + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 278 .loc 1 174 28 view .LVU102 + 279 00be 2200 movs r2, r4 + 280 00c0 DA40 lsrs r2, r2, r3 + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 281 .loc 1 174 9 view .LVU103 + 282 00c2 4FD0 beq .L17 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 283 .loc 1 177 5 is_stmt 1 view .LVU104 + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 284 .loc 1 177 41 is_stmt 0 view .LVU105 + 285 00c4 0122 movs r2, #1 + 286 00c6 9A40 lsls r2, r2, r3 + ARM GAS /tmp/ccUoVykV.s page 11 + + + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 287 .loc 1 177 15 view .LVU106 + 288 00c8 2500 movs r5, r4 + 289 00ca 1540 ands r5, r2 + 290 .LVL33: + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 291 .loc 1 179 5 is_stmt 1 view .LVU107 + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 292 .loc 1 179 8 is_stmt 0 view .LVU108 + 293 00cc 1442 tst r4, r2 + 294 00ce F4D0 beq .L3 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 295 .loc 1 183 7 is_stmt 1 view .LVU109 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 296 .loc 1 183 29 is_stmt 0 view .LVU110 + 297 00d0 0324 movs r4, #3 + 298 00d2 4E68 ldr r6, [r1, #4] + 299 00d4 3440 ands r4, r6 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 300 .loc 1 183 58 view .LVU111 + 301 00d6 013C subs r4, r4, #1 + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 302 .loc 1 183 10 view .LVU112 + 303 00d8 012C cmp r4, #1 + 304 00da 94D9 bls .L18 + 305 .L4: + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 306 .loc 1 201 7 is_stmt 1 view .LVU113 + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 307 .loc 1 201 28 is_stmt 0 view .LVU114 + 308 00dc 0322 movs r2, #3 + 309 00de 4C68 ldr r4, [r1, #4] + 310 00e0 2240 ands r2, r4 + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 311 .loc 1 201 10 view .LVU115 + 312 00e2 032A cmp r2, #3 + 313 00e4 09D0 beq .L5 + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 314 .loc 1 204 9 is_stmt 1 view .LVU116 + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 315 .loc 1 207 9 view .LVU117 + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 316 .loc 1 207 14 is_stmt 0 view .LVU118 + 317 00e6 C268 ldr r2, [r0, #12] + 318 .LVL34: + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 319 .loc 1 208 9 is_stmt 1 view .LVU119 + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 320 .loc 1 208 49 is_stmt 0 view .LVU120 + 321 00e8 5E00 lsls r6, r3, #1 + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 322 .loc 1 208 36 view .LVU121 + 323 00ea 0324 movs r4, #3 + 324 00ec B440 lsls r4, r4, r6 + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 325 .loc 1 208 14 view .LVU122 + 326 00ee A243 bics r2, r4 + ARM GAS /tmp/ccUoVykV.s page 12 + + + 327 .LVL35: + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 328 .loc 1 208 14 view .LVU123 + 329 00f0 1400 movs r4, r2 + 330 .LVL36: + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 331 .loc 1 209 9 is_stmt 1 view .LVU124 + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 332 .loc 1 209 36 is_stmt 0 view .LVU125 + 333 00f2 8A68 ldr r2, [r1, #8] + 334 .LVL37: + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 335 .loc 1 209 36 view .LVU126 + 336 00f4 B240 lsls r2, r2, r6 + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 337 .loc 1 209 14 view .LVU127 + 338 00f6 2243 orrs r2, r4 + 339 .LVL38: + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 340 .loc 1 210 9 is_stmt 1 view .LVU128 + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 341 .loc 1 210 22 is_stmt 0 view .LVU129 + 342 00f8 C260 str r2, [r0, #12] + 343 .LVL39: + 344 .L5: + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 345 .loc 1 214 7 is_stmt 1 view .LVU130 + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 346 .loc 1 214 28 is_stmt 0 view .LVU131 + 347 00fa 0322 movs r2, #3 + 348 00fc 4C68 ldr r4, [r1, #4] + 349 00fe 2240 ands r2, r4 + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 350 .loc 1 214 10 view .LVU132 + 351 0100 022A cmp r2, #2 + 352 0102 94D0 beq .L19 + 353 .L6: + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 354 .loc 1 228 7 is_stmt 1 view .LVU133 + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + 355 .loc 1 228 12 is_stmt 0 view .LVU134 + 356 0104 0468 ldr r4, [r0] + 357 .LVL40: + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 358 .loc 1 229 7 is_stmt 1 view .LVU135 + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 359 .loc 1 229 47 is_stmt 0 view .LVU136 + 360 0106 5E00 lsls r6, r3, #1 + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 361 .loc 1 229 34 view .LVU137 + 362 0108 0322 movs r2, #3 + 363 010a 1700 movs r7, r2 + 364 010c B740 lsls r7, r7, r6 + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 365 .loc 1 229 12 view .LVU138 + 366 010e BC43 bics r4, r7 + 367 .LVL41: + ARM GAS /tmp/ccUoVykV.s page 13 + + + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER = temp; + 368 .loc 1 230 7 is_stmt 1 view .LVU139 + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER = temp; + 369 .loc 1 230 33 is_stmt 0 view .LVU140 + 370 0110 4F68 ldr r7, [r1, #4] + 371 0112 3A40 ands r2, r7 + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER = temp; + 372 .loc 1 230 46 view .LVU141 + 373 0114 B240 lsls r2, r2, r6 + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER = temp; + 374 .loc 1 230 12 view .LVU142 + 375 0116 2243 orrs r2, r4 + 376 .LVL42: + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 377 .loc 1 231 7 is_stmt 1 view .LVU143 + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 378 .loc 1 231 20 is_stmt 0 view .LVU144 + 379 0118 0260 str r2, [r0] + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 380 .loc 1 235 7 is_stmt 1 view .LVU145 + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 381 .loc 1 235 28 is_stmt 0 view .LVU146 + 382 011a C022 movs r2, #192 + 383 .LVL43: + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 384 .loc 1 235 28 view .LVU147 + 385 011c 9202 lsls r2, r2, #10 + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 386 .loc 1 235 10 view .LVU148 + 387 011e 4C68 ldr r4, [r1, #4] + 388 0120 1442 tst r4, r2 + 389 0122 CAD0 beq .L3 + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(0x0FuL << (8u * (position & 0x03u))); + 390 .loc 1 237 9 is_stmt 1 view .LVU149 + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(0x0FuL << (8u * (position & 0x03u))); + 391 .loc 1 237 38 is_stmt 0 view .LVU150 + 392 0124 9A08 lsrs r2, r3, #2 + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp &= ~(0x0FuL << (8u * (position & 0x03u))); + 393 .loc 1 237 14 view .LVU151 + 394 0126 1400 movs r4, r2 + 395 0128 1834 adds r4, r4, #24 + 396 012a A400 lsls r4, r4, #2 + 397 012c 0E4E ldr r6, .L21 + 398 012e A759 ldr r7, [r4, r6] + 399 .LVL44: + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 400 .loc 1 238 9 is_stmt 1 view .LVU152 + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 401 .loc 1 238 45 is_stmt 0 view .LVU153 + 402 0130 0324 movs r4, #3 + 403 0132 1C40 ands r4, r3 + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 404 .loc 1 238 33 view .LVU154 + 405 0134 E400 lsls r4, r4, #3 + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 406 .loc 1 238 26 view .LVU155 + 407 0136 0F26 movs r6, #15 + ARM GAS /tmp/ccUoVykV.s page 14 + + + 408 0138 A640 lsls r6, r6, r4 + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + 409 .loc 1 238 14 view .LVU156 + 410 013a B743 bics r7, r6 + 411 .LVL45: + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 412 .loc 1 239 9 is_stmt 1 view .LVU157 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 413 .loc 1 239 18 is_stmt 0 view .LVU158 + 414 013c A026 movs r6, #160 + 415 013e F605 lsls r6, r6, #23 + 416 0140 B042 cmp r0, r6 + 417 0142 86D0 beq .L13 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 418 .loc 1 239 18 discriminator 1 view .LVU159 + 419 0144 094E ldr r6, .L21+4 + 420 0146 B042 cmp r0, r6 + 421 0148 08D0 beq .L14 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 422 .loc 1 239 18 discriminator 3 view .LVU160 + 423 014a 094E ldr r6, .L21+8 + 424 014c B042 cmp r0, r6 + 425 014e 07D0 beq .L15 + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 426 .loc 1 239 18 discriminator 5 view .LVU161 + 427 0150 084E ldr r6, .L21+12 + 428 0152 B042 cmp r0, r6 + 429 0154 00D1 bne .LCB395 + 430 0156 7AE7 b .L20 @long jump + 431 .LCB395: + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] = temp; + 432 .loc 1 239 18 view .LVU162 + 433 0158 0526 movs r6, #5 + 434 015a 7BE7 b .L7 + 435 .L14: + 436 015c 0126 movs r6, #1 + 437 015e 79E7 b .L7 + 438 .L15: + 439 0160 0226 movs r6, #2 + 440 0162 77E7 b .L7 + 441 .LVL46: + 442 .L17: + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 443 .loc 1 280 1 view .LVU163 + 444 @ sp needed + 445 0164 F0BD pop {r4, r5, r6, r7, pc} + 446 .L22: + 447 0166 C046 .align 2 + 448 .L21: + 449 0168 00180240 .word 1073879040 + 450 016c 00040050 .word 1342178304 + 451 0170 00080050 .word 1342179328 + 452 0174 000C0050 .word 1342180352 + 453 .cfi_endproc + 454 .LFE297: + 456 .section .text.HAL_GPIO_DeInit,"ax",%progbits + ARM GAS /tmp/ccUoVykV.s page 15 + + + 457 .align 1 + 458 .global HAL_GPIO_DeInit + 459 .syntax unified + 460 .code 16 + 461 .thumb_func + 462 .fpu softvfp + 464 HAL_GPIO_DeInit: + 465 .LVL47: + 466 .LFB298: + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief De-initialize the GPIOx peripheral registers to their default reset values. + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 467 .loc 1 290 1 is_stmt 1 view -0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 0 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 471 .loc 1 290 1 is_stmt 0 view .LVU165 + 472 0000 F0B5 push {r4, r5, r6, r7, lr} + 473 .LCFI1: + 474 .cfi_def_cfa_offset 20 + 475 .cfi_offset 4, -20 + 476 .cfi_offset 5, -16 + 477 .cfi_offset 6, -12 + 478 .cfi_offset 7, -8 + 479 .cfi_offset 14, -4 + 480 0002 CE46 mov lr, r9 + 481 0004 4746 mov r7, r8 + 482 0006 80B5 push {r7, lr} + 483 .LCFI2: + 484 .cfi_def_cfa_offset 28 + 485 .cfi_offset 8, -28 + 486 .cfi_offset 9, -24 + 487 0008 8946 mov r9, r1 + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t position = 0x00u; + 488 .loc 1 291 3 is_stmt 1 view .LVU166 + 489 .LVL48: + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t iocurrent; + 490 .loc 1 292 3 view .LVU167 + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t tmp; + 491 .loc 1 293 3 view .LVU168 + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 492 .loc 1 296 3 view .LVU169 + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 493 .loc 1 297 3 view .LVU170 + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the port pins */ + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** while ((GPIO_Pin >> position) != 0x00u) + 494 .loc 1 300 3 view .LVU171 + ARM GAS /tmp/ccUoVykV.s page 16 + + + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t iocurrent; + 495 .loc 1 291 12 is_stmt 0 view .LVU172 + 496 000a 0023 movs r3, #0 + 497 .loc 1 300 9 view .LVU173 + 498 000c 23E0 b .L24 + 499 .LVL49: + 500 .L35: + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Get current io position */ + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** iocurrent = (GPIO_Pin) & (1uL << position); + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (iocurrent != 0x00u) + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Clear the External Interrupt or Event for the current IO */ + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp = EXTI->EXTICR[position >> 2u]; + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp &= (0x0FuL << (8u * (position & 0x03u))); + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 501 .loc 1 312 19 view .LVU174 + 502 000e 0321 movs r1, #3 + 503 0010 8846 mov r8, r1 + 504 0012 01E0 b .L26 + 505 .L29: + 506 0014 0021 movs r1, #0 + 507 0016 8846 mov r8, r1 + 508 .L26: + 509 .loc 1 312 41 discriminator 16 view .LVU175 + 510 0018 4146 mov r1, r8 + 511 001a A140 lsls r1, r1, r4 + 512 .loc 1 312 10 discriminator 16 view .LVU176 + 513 001c A942 cmp r1, r5 + 514 001e 47D0 beq .L33 + 515 .LVL50: + 516 .L27: + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->IMR1 &= ~(iocurrent); + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EMR1 &= ~(iocurrent); + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->RTSR1 &= ~(iocurrent); + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp = 0x0FuL << (8u * (position & 0x03u)); + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] &= ~tmp; + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure IO in Analog Mode */ + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + 517 .loc 1 328 7 is_stmt 1 view .LVU177 + 518 .loc 1 328 20 is_stmt 0 view .LVU178 + 519 0020 0468 ldr r4, [r0] + 520 .loc 1 328 54 view .LVU179 + 521 0022 5E00 lsls r6, r3, #1 + 522 .loc 1 328 41 view .LVU180 + ARM GAS /tmp/ccUoVykV.s page 17 + + + 523 0024 0325 movs r5, #3 + 524 0026 B540 lsls r5, r5, r6 + 525 .loc 1 328 20 view .LVU181 + 526 0028 2C43 orrs r4, r5 + 527 002a 0460 str r4, [r0] + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + 528 .loc 1 331 7 is_stmt 1 view .LVU182 + 529 .loc 1 331 34 is_stmt 0 view .LVU183 + 530 002c DC08 lsrs r4, r3, #3 + 531 002e 0834 adds r4, r4, #8 + 532 0030 A400 lsls r4, r4, #2 + 533 0032 2758 ldr r7, [r4, r0] + 534 .loc 1 331 58 view .LVU184 + 535 0034 0726 movs r6, #7 + 536 0036 1E40 ands r6, r3 + 537 .loc 1 331 67 view .LVU185 + 538 0038 B600 lsls r6, r6, #2 + 539 .loc 1 331 44 view .LVU186 + 540 003a 0F21 movs r1, #15 + 541 003c B140 lsls r1, r1, r6 + 542 .loc 1 331 34 view .LVU187 + 543 003e 8F43 bics r7, r1 + 544 0040 2750 str r7, [r4, r0] + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + 545 .loc 1 334 7 is_stmt 1 view .LVU188 + 546 .loc 1 334 22 is_stmt 0 view .LVU189 + 547 0042 8468 ldr r4, [r0, #8] + 548 0044 AC43 bics r4, r5 + 549 0046 8460 str r4, [r0, #8] + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 550 .loc 1 337 7 is_stmt 1 view .LVU190 + 551 .loc 1 337 22 is_stmt 0 view .LVU191 + 552 0048 4468 ldr r4, [r0, #4] + 553 004a 9443 bics r4, r2 + 554 004c 4460 str r4, [r0, #4] + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + 555 .loc 1 340 7 is_stmt 1 view .LVU192 + 556 .loc 1 340 20 is_stmt 0 view .LVU193 + 557 004e C268 ldr r2, [r0, #12] + 558 0050 AA43 bics r2, r5 + 559 0052 C260 str r2, [r0, #12] + 560 .L25: + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** position++; + 561 .loc 1 343 5 is_stmt 1 view .LVU194 + 562 .loc 1 343 13 is_stmt 0 view .LVU195 + 563 0054 0133 adds r3, r3, #1 + 564 .LVL51: + ARM GAS /tmp/ccUoVykV.s page 18 + + + 565 .L24: + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 566 .loc 1 300 9 is_stmt 1 view .LVU196 + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 567 .loc 1 300 20 is_stmt 0 view .LVU197 + 568 0056 4A46 mov r2, r9 + 569 0058 DA40 lsrs r2, r2, r3 + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 570 .loc 1 300 9 view .LVU198 + 571 005a 46D0 beq .L34 + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 572 .loc 1 303 5 is_stmt 1 view .LVU199 + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 573 .loc 1 303 35 is_stmt 0 view .LVU200 + 574 005c 0122 movs r2, #1 + 575 005e 9A40 lsls r2, r2, r3 + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 576 .loc 1 303 15 view .LVU201 + 577 0060 4C46 mov r4, r9 + 578 0062 1440 ands r4, r2 + 579 0064 A446 mov ip, r4 + 580 .LVL52: + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 581 .loc 1 305 5 is_stmt 1 view .LVU202 + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 582 .loc 1 305 8 is_stmt 0 view .LVU203 + 583 0066 4946 mov r1, r9 + 584 0068 1142 tst r1, r2 + 585 006a F3D0 beq .L25 + 586 .LVL53: + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp &= (0x0FuL << (8u * (position & 0x03u))); + 587 .loc 1 310 7 is_stmt 1 view .LVU204 + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp &= (0x0FuL << (8u * (position & 0x03u))); + 588 .loc 1 310 35 is_stmt 0 view .LVU205 + 589 006c 9F08 lsrs r7, r3, #2 + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp &= (0x0FuL << (8u * (position & 0x03u))); + 590 .loc 1 310 11 view .LVU206 + 591 006e 3C00 movs r4, r7 + 592 .LVL54: + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp &= (0x0FuL << (8u * (position & 0x03u))); + 593 .loc 1 310 11 view .LVU207 + 594 0070 1834 adds r4, r4, #24 + 595 0072 A400 lsls r4, r4, #2 + 596 0074 1F4D ldr r5, .L36 + 597 0076 6559 ldr r5, [r4, r5] + 598 .LVL55: + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 599 .loc 1 311 7 is_stmt 1 view .LVU208 + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 600 .loc 1 311 41 is_stmt 0 view .LVU209 + 601 0078 0324 movs r4, #3 + 602 007a 1C40 ands r4, r3 + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 603 .loc 1 311 29 view .LVU210 + 604 007c E400 lsls r4, r4, #3 + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 605 .loc 1 311 22 view .LVU211 + ARM GAS /tmp/ccUoVykV.s page 19 + + + 606 007e 0F26 movs r6, #15 + 607 0080 A640 lsls r6, r6, r4 + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + 608 .loc 1 311 11 view .LVU212 + 609 0082 3540 ands r5, r6 + 610 .LVL56: + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 611 .loc 1 312 7 is_stmt 1 view .LVU213 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 612 .loc 1 312 19 is_stmt 0 view .LVU214 + 613 0084 A021 movs r1, #160 + 614 .LVL57: + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 615 .loc 1 312 19 view .LVU215 + 616 0086 C905 lsls r1, r1, #23 + 617 0088 8842 cmp r0, r1 + 618 008a C3D0 beq .L29 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 619 .loc 1 312 19 discriminator 1 view .LVU216 + 620 008c 1A49 ldr r1, .L36+4 + 621 008e 8842 cmp r0, r1 + 622 0090 08D0 beq .L30 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 623 .loc 1 312 19 discriminator 3 view .LVU217 + 624 0092 1A49 ldr r1, .L36+8 + 625 0094 8842 cmp r0, r1 + 626 0096 08D0 beq .L31 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 627 .loc 1 312 19 discriminator 5 view .LVU218 + 628 0098 1949 ldr r1, .L36+12 + 629 009a 8842 cmp r0, r1 + 630 009c B7D0 beq .L35 + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 631 .loc 1 312 19 view .LVU219 + 632 009e 0521 movs r1, #5 + 633 00a0 8846 mov r8, r1 + 634 00a2 B9E7 b .L26 + 635 .L30: + 636 00a4 0121 movs r1, #1 + 637 00a6 8846 mov r8, r1 + 638 00a8 B6E7 b .L26 + 639 .L31: + 640 00aa 0221 movs r1, #2 + 641 00ac 8846 mov r8, r1 + 642 00ae B3E7 b .L26 + 643 .L33: + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EMR1 &= ~(iocurrent); + 644 .loc 1 315 9 is_stmt 1 view .LVU220 + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EMR1 &= ~(iocurrent); + 645 .loc 1 315 20 is_stmt 0 view .LVU221 + 646 00b0 104D ldr r5, .L36 + 647 .LVL58: + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EMR1 &= ~(iocurrent); + 648 .loc 1 315 20 view .LVU222 + 649 00b2 8021 movs r1, #128 + 650 00b4 8846 mov r8, r1 + 651 00b6 6C58 ldr r4, [r5, r1] + ARM GAS /tmp/ccUoVykV.s page 20 + + + 652 00b8 6146 mov r1, ip + 653 00ba 8C43 bics r4, r1 + 654 00bc 4146 mov r1, r8 + 655 00be 6C50 str r4, [r5, r1] + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 656 .loc 1 316 9 is_stmt 1 view .LVU223 + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 657 .loc 1 316 20 is_stmt 0 view .LVU224 + 658 00c0 0431 adds r1, r1, #4 + 659 00c2 8846 mov r8, r1 + 660 00c4 6C58 ldr r4, [r5, r1] + 661 00c6 6146 mov r1, ip + 662 00c8 8C43 bics r4, r1 + 663 00ca 4146 mov r1, r8 + 664 00cc 6C50 str r4, [r5, r1] + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 665 .loc 1 319 9 is_stmt 1 view .LVU225 + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->FTSR1 &= ~(iocurrent); + 666 .loc 1 319 21 is_stmt 0 view .LVU226 + 667 00ce 2C68 ldr r4, [r5] + 668 00d0 6146 mov r1, ip + 669 00d2 8C43 bics r4, r1 + 670 00d4 2C60 str r4, [r5] + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 671 .loc 1 320 9 is_stmt 1 view .LVU227 + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 672 .loc 1 320 21 is_stmt 0 view .LVU228 + 673 00d6 6C68 ldr r4, [r5, #4] + 674 00d8 8C43 bics r4, r1 + 675 00da 6C60 str r4, [r5, #4] + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** EXTI->EXTICR[position >> 2u] &= ~tmp; + 676 .loc 1 322 9 is_stmt 1 view .LVU229 + 677 .LVL59: + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 678 .loc 1 323 9 view .LVU230 + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 679 .loc 1 323 38 is_stmt 0 view .LVU231 + 680 00dc 3C00 movs r4, r7 + 681 00de 1834 adds r4, r4, #24 + 682 00e0 A400 lsls r4, r4, #2 + 683 00e2 6759 ldr r7, [r4, r5] + 684 00e4 B743 bics r7, r6 + 685 00e6 6751 str r7, [r4, r5] + 686 00e8 9AE7 b .L27 + 687 .LVL60: + 688 .L34: + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 689 .loc 1 345 1 view .LVU232 + 690 @ sp needed + 691 .LVL61: + 692 .loc 1 345 1 view .LVU233 + 693 00ea C0BC pop {r6, r7} + 694 00ec B946 mov r9, r7 + 695 00ee B046 mov r8, r6 + 696 00f0 F0BD pop {r4, r5, r6, r7, pc} + 697 .L37: + ARM GAS /tmp/ccUoVykV.s page 21 + + + 698 00f2 C046 .align 2 + 699 .L36: + 700 00f4 00180240 .word 1073879040 + 701 00f8 00040050 .word 1342178304 + 702 00fc 00080050 .word 1342179328 + 703 0100 000C0050 .word 1342180352 + 704 .cfi_endproc + 705 .LFE298: + 707 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 708 .align 1 + 709 .global HAL_GPIO_ReadPin + 710 .syntax unified + 711 .code 16 + 712 .thumb_func + 713 .fpu softvfp + 715 HAL_GPIO_ReadPin: + 716 .LVL62: + 717 .LFB299: + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @} + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** @addtogroup GPIO_Exported_Functions_Group2 + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @verbatim + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** =============================================================================== + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** ##### IO operation functions ##### + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** =============================================================================== + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** @endverbatim + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @{ + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Read the specified input port pin. + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to read. + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval The input port pin value. + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 718 .loc 1 371 1 is_stmt 1 view -0 + 719 .cfi_startproc + 720 @ args = 0, pretend = 0, frame = 0 + 721 @ frame_needed = 0, uses_anonymous_args = 0 + 722 @ link register save eliminated. + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIO_PinState bitstatus; + 723 .loc 1 372 3 view .LVU235 + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 724 .loc 1 375 3 view .LVU236 + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + ARM GAS /tmp/ccUoVykV.s page 22 + + + 725 .loc 1 377 3 view .LVU237 + 726 .loc 1 377 13 is_stmt 0 view .LVU238 + 727 0000 0369 ldr r3, [r0, #16] + 728 .loc 1 377 6 view .LVU239 + 729 0002 0B42 tst r3, r1 + 730 0004 01D0 beq .L40 + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 731 .loc 1 379 15 view .LVU240 + 732 0006 0120 movs r0, #1 + 733 .LVL63: + 734 .L39: + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** else + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** return bitstatus; + 735 .loc 1 385 3 is_stmt 1 view .LVU241 + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 736 .loc 1 386 1 is_stmt 0 view .LVU242 + 737 @ sp needed + 738 0008 7047 bx lr + 739 .LVL64: + 740 .L40: + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 741 .loc 1 383 15 view .LVU243 + 742 000a 0020 movs r0, #0 + 743 .LVL65: + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 744 .loc 1 383 15 view .LVU244 + 745 000c FCE7 b .L39 + 746 .cfi_endproc + 747 .LFE299: + 749 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 750 .align 1 + 751 .global HAL_GPIO_WritePin + 752 .syntax unified + 753 .code 16 + 754 .thumb_func + 755 .fpu softvfp + 757 HAL_GPIO_WritePin: + 758 .LVL66: + 759 .LFB300: + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Set or clear the selected data port bit. + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * the read and the modify access. + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param PinState specifies the value to be written to the selected bit. + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + ARM GAS /tmp/ccUoVykV.s page 23 + + + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @arg GPIO_PIN_RESET: to clear the port pin + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @arg GPIO_PIN_SET: to set the port pin + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 760 .loc 1 405 1 is_stmt 1 view -0 + 761 .cfi_startproc + 762 @ args = 0, pretend = 0, frame = 0 + 763 @ frame_needed = 0, uses_anonymous_args = 0 + 764 @ link register save eliminated. + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 765 .loc 1 407 3 view .LVU246 + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 766 .loc 1 408 3 view .LVU247 + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (PinState != GPIO_PIN_RESET) + 767 .loc 1 410 3 view .LVU248 + 768 .loc 1 410 6 is_stmt 0 view .LVU249 + 769 0000 002A cmp r2, #0 + 770 0002 01D0 beq .L42 + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin; + 771 .loc 1 412 5 is_stmt 1 view .LVU250 + 772 .loc 1 412 17 is_stmt 0 view .LVU251 + 773 0004 8161 str r1, [r0, #24] + 774 .L41: + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** else + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->BRR = (uint32_t)GPIO_Pin; + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 775 .loc 1 418 1 view .LVU252 + 776 @ sp needed + 777 0006 7047 bx lr + 778 .L42: + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 779 .loc 1 416 5 is_stmt 1 view .LVU253 + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 780 .loc 1 416 16 is_stmt 0 view .LVU254 + 781 0008 8162 str r1, [r0, #40] + 782 .loc 1 418 1 view .LVU255 + 783 000a FCE7 b .L41 + 784 .cfi_endproc + 785 .LFE300: + 787 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 788 .align 1 + 789 .global HAL_GPIO_TogglePin + 790 .syntax unified + 791 .code 16 + 792 .thumb_func + 793 .fpu softvfp + 795 HAL_GPIO_TogglePin: + 796 .LVL67: + 797 .LFB301: + ARM GAS /tmp/ccUoVykV.s page 24 + + + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Toggle the specified GPIO pin. + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin specifies the pin to be toggled. + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 798 .loc 1 428 1 is_stmt 1 view -0 + 799 .cfi_startproc + 800 @ args = 0, pretend = 0, frame = 0 + 801 @ frame_needed = 0, uses_anonymous_args = 0 + 802 @ link register save eliminated. + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** uint32_t odr; + 803 .loc 1 429 3 view .LVU257 + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 804 .loc 1 432 3 view .LVU258 + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* get current Output Data Register value */ + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** odr = GPIOx->ODR; + 805 .loc 1 435 3 view .LVU259 + 806 .loc 1 435 7 is_stmt 0 view .LVU260 + 807 0000 4269 ldr r2, [r0, #20] + 808 .LVL68: + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Set selected pins that were at low level, and reset ones that were high */ + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 809 .loc 1 438 3 is_stmt 1 view .LVU261 + 810 .loc 1 438 23 is_stmt 0 view .LVU262 + 811 0002 1300 movs r3, r2 + 812 0004 0B40 ands r3, r1 + 813 .loc 1 438 35 view .LVU263 + 814 0006 1B04 lsls r3, r3, #16 + 815 .loc 1 438 59 view .LVU264 + 816 0008 9143 bics r1, r2 + 817 .LVL69: + 818 .loc 1 438 51 view .LVU265 + 819 000a 1943 orrs r1, r3 + 820 .loc 1 438 15 view .LVU266 + 821 000c 8161 str r1, [r0, #24] + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 822 .loc 1 439 1 view .LVU267 + 823 @ sp needed + 824 000e 7047 bx lr + 825 .cfi_endproc + 826 .LFE301: + 828 .section .text.HAL_GPIO_LockPin,"ax",%progbits + 829 .align 1 + 830 .global HAL_GPIO_LockPin + 831 .syntax unified + 832 .code 16 + 833 .thumb_func + 834 .fpu softvfp + ARM GAS /tmp/ccUoVykV.s page 25 + + + 836 HAL_GPIO_LockPin: + 837 .LVL70: + 838 .LFB302: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Lock GPIO Pins configuration registers. + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * until the next reset. + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bits to be locked. + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 839 .loc 1 453 1 is_stmt 1 view -0 + 840 .cfi_startproc + 841 @ args = 0, pretend = 0, frame = 8 + 842 @ frame_needed = 0, uses_anonymous_args = 0 + 843 @ link register save eliminated. + 844 .loc 1 453 1 is_stmt 0 view .LVU269 + 845 0000 82B0 sub sp, sp, #8 + 846 .LCFI3: + 847 .cfi_def_cfa_offset 8 + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 848 .loc 1 454 3 is_stmt 1 view .LVU270 + 849 .loc 1 454 17 is_stmt 0 view .LVU271 + 850 0002 8022 movs r2, #128 + 851 0004 5202 lsls r2, r2, #9 + 852 0006 0192 str r2, [sp, #4] + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Check the parameters */ + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + 853 .loc 1 457 3 is_stmt 1 view .LVU272 + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 854 .loc 1 458 3 view .LVU273 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Apply lock key write sequence */ + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp |= GPIO_Pin; + 855 .loc 1 461 3 view .LVU274 + 856 .loc 1 461 7 is_stmt 0 view .LVU275 + 857 0008 019B ldr r3, [sp, #4] + 858 000a 0B43 orrs r3, r1 + 859 000c 0193 str r3, [sp, #4] + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 860 .loc 1 463 3 is_stmt 1 view .LVU276 + 861 .loc 1 463 15 is_stmt 0 view .LVU277 + 862 000e 019B ldr r3, [sp, #4] + 863 0010 C361 str r3, [r0, #28] + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 864 .loc 1 465 3 is_stmt 1 view .LVU278 + 865 .loc 1 465 15 is_stmt 0 view .LVU279 + 866 0012 C161 str r1, [r0, #28] + ARM GAS /tmp/ccUoVykV.s page 26 + + + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 867 .loc 1 467 3 is_stmt 1 view .LVU280 + 868 .loc 1 467 15 is_stmt 0 view .LVU281 + 869 0014 019B ldr r3, [sp, #4] + 870 0016 C361 str r3, [r0, #28] + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Read LCKK register. This read is mandatory to complete key lock sequence */ + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** tmp = GPIOx->LCKR; + 871 .loc 1 469 3 is_stmt 1 view .LVU282 + 872 .loc 1 469 14 is_stmt 0 view .LVU283 + 873 0018 C369 ldr r3, [r0, #28] + 874 .loc 1 469 7 view .LVU284 + 875 001a 0193 str r3, [sp, #4] + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* read again in order to confirm lock is active */ + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + 876 .loc 1 472 3 is_stmt 1 view .LVU285 + 877 .loc 1 472 13 is_stmt 0 view .LVU286 + 878 001c C369 ldr r3, [r0, #28] + 879 .loc 1 472 6 view .LVU287 + 880 001e 1342 tst r3, r2 + 881 0020 02D0 beq .L47 + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** return HAL_OK; + 882 .loc 1 474 12 view .LVU288 + 883 0022 0020 movs r0, #0 + 884 .LVL71: + 885 .L46: + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** else + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** return HAL_ERROR; + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 886 .loc 1 480 1 view .LVU289 + 887 0024 02B0 add sp, sp, #8 + 888 @ sp needed + 889 0026 7047 bx lr + 890 .LVL72: + 891 .L47: + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 892 .loc 1 478 12 view .LVU290 + 893 0028 0120 movs r0, #1 + 894 .LVL73: + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 895 .loc 1 478 12 view .LVU291 + 896 002a FBE7 b .L46 + 897 .cfi_endproc + 898 .LFE302: + 900 .section .text.HAL_GPIO_EXTI_Rising_Callback,"ax",%progbits + 901 .align 1 + 902 .weak HAL_GPIO_EXTI_Rising_Callback + 903 .syntax unified + 904 .code 16 + 905 .thumb_func + 906 .fpu softvfp + 908 HAL_GPIO_EXTI_Rising_Callback: + ARM GAS /tmp/ccUoVykV.s page 27 + + + 909 .LVL74: + 910 .LFB304: + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief Handle EXTI interrupt request. + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief EXTI line detection callback. + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 911 .loc 1 509 1 is_stmt 1 view -0 + 912 .cfi_startproc + 913 @ args = 0, pretend = 0, frame = 0 + 914 @ frame_needed = 0, uses_anonymous_args = 0 + 915 @ link register save eliminated. + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 916 .loc 1 511 3 view .LVU293 + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* NOTE: This function should not be modified, when the callback is needed, + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 917 .loc 1 516 1 is_stmt 0 view .LVU294 + 918 @ sp needed + 919 0000 7047 bx lr + 920 .cfi_endproc + 921 .LFE304: + 923 .section .text.HAL_GPIO_EXTI_Falling_Callback,"ax",%progbits + 924 .align 1 + 925 .weak HAL_GPIO_EXTI_Falling_Callback + 926 .syntax unified + 927 .code 16 + 928 .thumb_func + 929 .fpu softvfp + 931 HAL_GPIO_EXTI_Falling_Callback: + ARM GAS /tmp/ccUoVykV.s page 28 + + + 932 .LVL75: + 933 .LFB305: + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /** + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @brief EXTI line detection callback. + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** * @retval None + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 934 .loc 1 524 1 is_stmt 1 view -0 + 935 .cfi_startproc + 936 @ args = 0, pretend = 0, frame = 0 + 937 @ frame_needed = 0, uses_anonymous_args = 0 + 938 @ link register save eliminated. + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 939 .loc 1 526 3 view .LVU296 + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* NOTE: This function should not be modified, when the callback is needed, + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** */ + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 940 .loc 1 531 1 is_stmt 0 view .LVU297 + 941 @ sp needed + 942 0000 7047 bx lr + 943 .cfi_endproc + 944 .LFE305: + 946 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 947 .align 1 + 948 .global HAL_GPIO_EXTI_IRQHandler + 949 .syntax unified + 950 .code 16 + 951 .thumb_func + 952 .fpu softvfp + 954 HAL_GPIO_EXTI_IRQHandler: + 955 .LVL76: + 956 .LFB303: + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 957 .loc 1 488 1 is_stmt 1 view -0 + 958 .cfi_startproc + 959 @ args = 0, pretend = 0, frame = 0 + 960 @ frame_needed = 0, uses_anonymous_args = 0 + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 961 .loc 1 488 1 is_stmt 0 view .LVU299 + 962 0000 10B5 push {r4, lr} + 963 .LCFI4: + 964 .cfi_def_cfa_offset 8 + 965 .cfi_offset 4, -8 + 966 .cfi_offset 14, -4 + 967 0002 0400 movs r4, r0 + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 968 .loc 1 490 3 is_stmt 1 view .LVU300 + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 969 .loc 1 490 7 is_stmt 0 view .LVU301 + 970 0004 094B ldr r3, .L55 + 971 0006 DB68 ldr r3, [r3, #12] + ARM GAS /tmp/ccUoVykV.s page 29 + + + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 972 .loc 1 490 6 view .LVU302 + 973 0008 1842 tst r0, r3 + 974 000a 04D1 bne .L53 + 975 .LVL77: + 976 .L51: + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 977 .loc 1 496 3 is_stmt 1 view .LVU303 + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 978 .loc 1 496 7 is_stmt 0 view .LVU304 + 979 000c 074B ldr r3, .L55 + 980 000e 1B69 ldr r3, [r3, #16] + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** { + 981 .loc 1 496 6 view .LVU305 + 982 0010 2342 tst r3, r4 + 983 0012 05D1 bne .L54 + 984 .L50: + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 985 .loc 1 501 1 view .LVU306 + 986 @ sp needed + 987 0014 10BD pop {r4, pc} + 988 .LVL78: + 989 .L53: + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + 990 .loc 1 492 5 is_stmt 1 view .LVU307 + 991 0016 054B ldr r3, .L55 + 992 0018 D860 str r0, [r3, #12] + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 993 .loc 1 493 5 view .LVU308 + 994 001a FFF7FEFF bl HAL_GPIO_EXTI_Rising_Callback + 995 .LVL79: + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 996 .loc 1 493 5 is_stmt 0 view .LVU309 + 997 001e F5E7 b .L51 + 998 .L54: + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + 999 .loc 1 498 5 is_stmt 1 view .LVU310 + 1000 0020 024B ldr r3, .L55 + 1001 0022 1C61 str r4, [r3, #16] + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** } + 1002 .loc 1 499 5 view .LVU311 + 1003 0024 2000 movs r0, r4 + 1004 0026 FFF7FEFF bl HAL_GPIO_EXTI_Falling_Callback + 1005 .LVL80: + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c **** + 1006 .loc 1 501 1 is_stmt 0 view .LVU312 + 1007 002a F3E7 b .L50 + 1008 .L56: + 1009 .align 2 + 1010 .L55: + 1011 002c 00180240 .word 1073879040 + 1012 .cfi_endproc + 1013 .LFE303: + 1015 .text + 1016 .Letext0: + 1017 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1018 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + ARM GAS /tmp/ccUoVykV.s page 30 + + + 1019 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1020 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h" + 1021 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccUoVykV.s page 31 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_gpio.c + /tmp/ccUoVykV.s:16 .text.HAL_GPIO_Init:0000000000000000 $t + /tmp/ccUoVykV.s:24 .text.HAL_GPIO_Init:0000000000000000 HAL_GPIO_Init + /tmp/ccUoVykV.s:449 .text.HAL_GPIO_Init:0000000000000168 $d + /tmp/ccUoVykV.s:457 .text.HAL_GPIO_DeInit:0000000000000000 $t + /tmp/ccUoVykV.s:464 .text.HAL_GPIO_DeInit:0000000000000000 HAL_GPIO_DeInit + /tmp/ccUoVykV.s:700 .text.HAL_GPIO_DeInit:00000000000000f4 $d + /tmp/ccUoVykV.s:708 .text.HAL_GPIO_ReadPin:0000000000000000 $t + /tmp/ccUoVykV.s:715 .text.HAL_GPIO_ReadPin:0000000000000000 HAL_GPIO_ReadPin + /tmp/ccUoVykV.s:750 .text.HAL_GPIO_WritePin:0000000000000000 $t + /tmp/ccUoVykV.s:757 .text.HAL_GPIO_WritePin:0000000000000000 HAL_GPIO_WritePin + /tmp/ccUoVykV.s:788 .text.HAL_GPIO_TogglePin:0000000000000000 $t + /tmp/ccUoVykV.s:795 .text.HAL_GPIO_TogglePin:0000000000000000 HAL_GPIO_TogglePin + /tmp/ccUoVykV.s:829 .text.HAL_GPIO_LockPin:0000000000000000 $t + /tmp/ccUoVykV.s:836 .text.HAL_GPIO_LockPin:0000000000000000 HAL_GPIO_LockPin + /tmp/ccUoVykV.s:901 .text.HAL_GPIO_EXTI_Rising_Callback:0000000000000000 $t + /tmp/ccUoVykV.s:908 .text.HAL_GPIO_EXTI_Rising_Callback:0000000000000000 HAL_GPIO_EXTI_Rising_Callback + /tmp/ccUoVykV.s:924 .text.HAL_GPIO_EXTI_Falling_Callback:0000000000000000 $t + /tmp/ccUoVykV.s:931 .text.HAL_GPIO_EXTI_Falling_Callback:0000000000000000 HAL_GPIO_EXTI_Falling_Callback + /tmp/ccUoVykV.s:947 .text.HAL_GPIO_EXTI_IRQHandler:0000000000000000 $t + /tmp/ccUoVykV.s:954 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--- /dev/null +++ b/squero/build/stm32g0xx_hal_i2c.d @@ -0,0 +1,59 @@ +build/stm32g0xx_hal_i2c.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_i2c.lst b/squero/build/stm32g0xx_hal_i2c.lst new file mode 100644 index 0000000..78e3f37 --- /dev/null +++ b/squero/build/stm32g0xx_hal_i2c.lst @@ -0,0 +1,26463 @@ +ARM GAS /tmp/ccth6daj.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_i2c.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.I2C_Flush_TXDR,"ax",%progbits + 16 .align 1 + 17 .arch armv6s-m + 18 .syntax unified + 19 .code 16 + 20 .thumb_func + 21 .fpu softvfp + 23 I2C_Flush_TXDR: + 24 .LVL0: + 25 .LFB360: + 26 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @file stm32g0xx_hal_i2c.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + IO operation functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @verbatim + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ============================================================================== + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ##### How to use this driver ##### + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ============================================================================== + 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (##) I2C pins configuration + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the transmit or receive channel + ARM GAS /tmp/ccth6daj.s page 2 + + + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx channel + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the DMA Tx or Rx channel + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low le + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDevic + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Polling mode IO operation *** + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ================================= + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Tran + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Recei + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transm + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ===================================== + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_ + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =================================== + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_ + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallbac + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_R + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users c + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallbac + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Tr + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Rec + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users ca + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users ca + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_I + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Interrupt mode or DMA mode IO sequential operation *** + ARM GAS /tmp/ccth6daj.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ========================================================== + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** when a direction change during transfer + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** no sequential mode + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and data to transfer without a final stop condition + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** start condition, address and data to transfer without a final stop cond + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** an then permit a call the same master sequential interface several time + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Se + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_ + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** transfer + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** transfer + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** after several call of the same master sequential interface several time + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (link with option I2C_FIRST_AND_NEXT_FRAME). + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Usage can, transfer several bytes one by one using + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Receive sequence permit to call the opposite interface Receive or Tra + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** without stopping the communication and so generate a restart conditio + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** each call of the same master sequential + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** interface. + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Usage can, transfer several bytes one by one with a restart with slave + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** each bytes using + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** generation of STOP condition. + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Different sequential I2C interfaces are listed below: + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is e + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** users can add their own code by customization of function pointer @ref HAL_I2C_MasterTx + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA() + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is exec + ARM GAS /tmp/ccth6daj.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallbac + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Mas + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_DisableListen_IT() + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and users can + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code to check the Address Match Code and the transmission direction reques + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (Write/Read). + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and users can + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Slave_Seq_Transmit_IT() + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is ex + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** users can add their own code by customization of function pointer @ref HAL_I2C_SlaveTxC + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Slave_Seq_Receive_IT() + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or using @ref HAL_I2C_Slave_Seq_Receive_DMA() + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is execu + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users c + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ======================================= + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Mem_Write_IT() + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users c + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Mem_Read_IT() + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users ca + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users ca + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** DMA mode IO operation *** + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ============================== + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Master_Transmit_DMA() + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallbac + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Master_Receive_DMA() + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users c + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallbac + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Slave_Transmit_DMA() + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Slave_Receive_DMA() + ARM GAS /tmp/ccth6daj.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users ca + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users ca + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_I + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ================================= + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Mem_Write_DMA() + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users c + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_Mem_Read_DMA() + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users ca + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users ca + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ================================== + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *** Callback registration *** + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ============================================= + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** allows the user to configure dynamically the driver callbacks. + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to register an interrupt callback. + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + ARM GAS /tmp/ccth6daj.s page 6 + + + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and a pointer to the user callback function. + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAdd + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** weak function. + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and the Callback ID. + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This function allows to reset following callbacks: + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallba + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** all callbacks are set to the corresponding weak functions: + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Exception done for MspInit and MspDeInit functions that are + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** these callbacks are null (not registered beforehand). + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or @ref HAL_I2C_Init() function. + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** not defined, the callback registration feature is not available and all callbacks + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** are set to the corresponding weak functions. + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @endverbatim + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ****************************************************************************** + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @attention + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *

© Copyright (c) 2018 STMicroelectronics. + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * All rights reserved.

+ 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This software component is licensed by ST under BSD 3-Clause license, + ARM GAS /tmp/ccth6daj.s page 7 + + + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the "License"; You may not use this file except in compliance with the + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * License. You may obtain a copy of the License at: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * opensource.org/licenses/BSD-3-Clause + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ****************************************************************************** + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #include "stm32g0xx_hal.h" + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @addtogroup STM32G0xx_HAL_Driver + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C I2C + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C HAL module driver + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT 7U + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define SLAVE_ADDR_MSK 0x06U + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */ + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Default Value */ + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */ + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */ + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + ARM GAS /tmp/ccth6daj.s page 8 + + + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2 + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and @ref I2C_XFER_RX_IT */ + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of glo + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and NACK treatment */ + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evene + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private macro -------------------------------------------------------------*/ + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + ARM GAS /tmp/ccth6daj.s page 9 + + + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32 + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_ + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources); + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources); + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources); + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources); + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart); + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart); + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private function to treat different error callback */ + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private function to flush TXDR register */ + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private function to handle start, restart or stop a transfer */ + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Request); + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Private function to Convert Specific options */ + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * + ARM GAS /tmp/ccth6daj.s page 10 + + + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @verbatim + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the selected configuration: + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Clock Timing + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Own Address 1 + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Dual Addressing mode + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Own Address 2 + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Own Address 2 Mask + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) General call mode + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Nostretch mode + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** of the selected I2Cx peripheral. + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @endverbatim + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c == NULL) + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + ARM GAS /tmp/ccth6daj.s page 11 + + + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init the I2C Callback settings */ + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->MspInitCallback == NULL) + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback(hi2c); + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + ARM GAS /tmp/ccth6daj.s page 12 + + + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c == NULL) + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->MspDeInitCallback == NULL) + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback(hi2c); + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + ARM GAS /tmp/ccth6daj.s page 13 + + + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Release Lock */ + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Register a User I2C Callback + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * To be used instead of the weak predefined callback + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param CallbackID ID of the callback to be registered + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter can be one of the following values: + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + ARM GAS /tmp/ccth6daj.s page 14 + + + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pCallback pointer to the Callback function + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** pI2C_CallbackTypeDef pCallback) + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (pCallback == NULL) + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** switch (CallbackID) + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = pCallback; + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = pCallback; + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = pCallback; + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = pCallback; + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ListenCpltCallback = pCallback; + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemTxCpltCallback = pCallback; + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemRxCpltCallback = pCallback; + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + ARM GAS /tmp/ccth6daj.s page 15 + + + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCallback = pCallback; + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AbortCpltCallback = pCallback; + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** default : + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** switch (CallbackID) + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** default : + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Release Lock */ + ARM GAS /tmp/ccth6daj.s page 16 + + + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return status; + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Unregister an I2C Callback + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * I2C callback is redirected to the weak predefined callback + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param CallbackID ID of the callback to be unregistered + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter can be one of the following values: + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter can be one of the following values: + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** switch (CallbackID) + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallba + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallba + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallbac + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + ARM GAS /tmp/ccth6daj.s page 17 + + + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** default : + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** switch (CallbackID) + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** default : + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** break; + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + ARM GAS /tmp/ccth6daj.s page 18 + + + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Release Lock */ + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return status; + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Register the Slave Address Match I2C Callback + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pCallback pointer to the Address Match Callback function + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (pCallback == NULL) + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback = pCallback; + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Release Lock */ + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return status; + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief UnRegister the Slave Address Match I2C Callback + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + ARM GAS /tmp/ccth6daj.s page 19 + + +1002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +1003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +1005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ +1007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) +1010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ +1012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update the error code */ +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; +1017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return error status */ +1019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** status = HAL_ERROR; +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Release Lock */ +1023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return status; +1025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} +1031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions +1034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Data transfers functions +1035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * +1036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @verbatim +1037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== +1038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ##### IO operation functions ##### +1039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== +1040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** transfers. +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) There are two modes of transfer: +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. +1046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** The status of all data processing is returned by the same function +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** after finishing transfer. +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. +1050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** The end of the data processing will be indicated through the +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when +1052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** using DMA mode. +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) Blocking mode functions are : +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() +1056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() +1058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() + ARM GAS /tmp/ccth6daj.s page 20 + + +1059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() +1060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() +1061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() +1062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : +1064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() +1065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() +1066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() +1067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() +1068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() +1069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_IT() +1071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_IT() +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_IT() +1073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_IT() +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_EnableListen_IT() +1075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_DisableListen_IT() +1076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Abort_IT() +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : +1079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() +1080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() +1082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() +1084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() +1085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_DMA() +1086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_DMA() +1087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_DMA() +1088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_DMA() +1089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: +1091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() +1092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() +1094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() +1095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() +1097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_AddrCallback() +1098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_ListenCpltCallback() +1099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() +1100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (++) HAL_I2C_AbortCpltCallback() +1101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @endverbatim +1103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ +1104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. +1108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +1115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccth6daj.s page 21 + + +1116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD +1118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +1121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR */ +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +1171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + ARM GAS /tmp/ccth6daj.s page 22 + + +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +1174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +1206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. +1227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + ARM GAS /tmp/ccth6daj.s page 23 + + +1230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +1234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa +1237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +1240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +1250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ + ARM GAS /tmp/ccth6daj.s page 24 + + +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +1290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +1291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +1294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +1296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +1299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +1307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +1326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +1330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 25 + + +1344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. +1347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +1352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Timeout) +1356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +1358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag */ +1393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ +1396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +1397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 26 + + +1401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag */ +1407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ +1411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) +1412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR */ +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +1430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +1432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +1433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +1435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) +1444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Normal use case for Transmitter mode */ +1446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* A NACK is generated to confirm the end of transfer */ +1447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP flag */ +1456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 27 + + +1458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +1490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Timeout) +1494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +1496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +1500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +1502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +1509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ + ARM GAS /tmp/ccth6daj.s page 28 + + +1515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +1518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) +1524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag */ +1531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +1532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) +1535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store Last receive data if any */ +1550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) +1551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +1553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +1556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +1557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +1559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +1565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +1566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +1568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +1569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +1571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 29 + + +1572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +1575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP flag */ +1582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +1583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) +1586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +1594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size) +1621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +1623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccth6daj.s page 30 + + +1629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRIT +1658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +1668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccth6daj.s page 31 + + +1686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * +1691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size) +1692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +1694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +1714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +1729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +1739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +1742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 32 + + +1743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +1789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +1792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 33 + + +1800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +1817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +1818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +1822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +1829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +1839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +1842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +1855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccth6daj.s page 34 + + +1857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +1858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +1859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +1860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +1861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size) +1863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +1865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +1868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +1870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +1876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +1878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +1879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +1880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +1882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +1883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +1884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +1885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +1886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +1888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +1890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +1891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +1895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +1896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +1899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +1901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +1904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +1906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +1907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +1910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +1911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +1913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> + ARM GAS /tmp/ccth6daj.s page 35 + + +1914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +1915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +1919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +1923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +1924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +1932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART +1935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +1936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +1938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +1939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +1948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +1950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +1951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +1955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +1959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +1960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +1965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +1970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + ARM GAS /tmp/ccth6daj.s page 36 + + +1971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +1973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +1974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +1975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +1978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +1983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +1985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +1988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +1991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +1993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +1994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +1995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +1997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +1998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +1999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +2000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +2009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size) +2010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +2012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +2026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 37 + + +2028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +2046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +2051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +2053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +2060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +2061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +2062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +2081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART * +2082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ +2083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ + ARM GAS /tmp/ccth6daj.s page 38 + + +2085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +2097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +2120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +2121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +2132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +2135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; + ARM GAS /tmp/ccth6daj.s page 39 + + +2142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +2147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +2154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +2182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +2184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +2191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +2193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccth6daj.s page 40 + + +2199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +2224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +2251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccth6daj.s page 41 + + +2256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +2258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +2273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +2281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +2283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +2286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +2288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +2289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +2292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +2293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +2296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +2297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 42 + + +2313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +2317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +2326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +2328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +2329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +2354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +2363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +2366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti +2367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 43 + + +2370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +2400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL +2403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +2410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST +2414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS +2419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do +2422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +2424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccth6daj.s page 44 + + +2427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR */ +2430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +2431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +2433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +2434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +2436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +2437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +2470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else + ARM GAS /tmp/ccth6daj.s page 45 + + +2484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +2491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +2500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +2503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim +2504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK +2525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +2537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ +2540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 46 + + +2541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +2547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, +2552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do +2562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +2564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) +2565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +2570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +2571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +2573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +2574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +2576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +2577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +2579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) +2582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, +2590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +2596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 47 + + +2598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); +2600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) +2604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +2609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +2610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +2613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +2644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 48 + + +2655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) +2691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +2709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + ARM GAS /tmp/ccth6daj.s page 49 + + +2712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +2738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +2762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + ARM GAS /tmp/ccth6daj.s page 50 + + +2769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +2770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +2784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ +2792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +2802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +2805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +2823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA + ARM GAS /tmp/ccth6daj.s page 51 + + +2826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +2830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +2850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +2853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +2855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +2856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +2857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +2859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +2860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +2861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +2862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +2863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +2865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +2867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +2868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +2872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +2873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstar +2877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) +2878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 52 + + +2883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +2886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +2889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +2891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +2892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +2895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +2896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +2898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +2899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +2900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +2904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +2917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +2919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +2921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +2923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +2924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +2931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +2933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +2935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +2936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ + ARM GAS /tmp/ccth6daj.s page 53 + + +2940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +2944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +2947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +2953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +2955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +2961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +2962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +2964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +2967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +2969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be read +2970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +2971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +2972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +2976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +2977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +2980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +2983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +2985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +2987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +2988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +2991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +2992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +2993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +2994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); + ARM GAS /tmp/ccth6daj.s page 54 + + +2997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +2998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +3000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; +3003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +3009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +3020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +3023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart +3024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +3036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +3043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa +3044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +3045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + ARM GAS /tmp/ccth6daj.s page 55 + + +3054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +3064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_RE +3065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +3067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +3079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +3106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This function is used with Memory devices +3107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccth6daj.s page 56 + + +3111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Trials Number of trials +3112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +3113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +3116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Timeout) +3117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; +3119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0UL; +3121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** FlagStatus tmp1; +3123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** FlagStatus tmp2; +3124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) +3128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; +3136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do +3139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate Start */ +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); +3142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +3144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +3145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tickstart = HAL_GetTick(); +3146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while ((tmp1 == RESET) && (tmp2 == RESET)) +3151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +3153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) +3155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 57 + + +3168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); +3170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); +3171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +3174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) +3175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +3183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Device is ready */ +3186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +3202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +3203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +3205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if the maximum allowed number of trials has been reached */ +3209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_Trials == Trials) +3210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate Stop */ +3212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +3213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) +3216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +3221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +3222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Trials */ + ARM GAS /tmp/ccth6daj.s page 58 + + +3225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Trials++; +3226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } while (I2C_Trials < Trials); +3227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +3233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +3247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +3261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + ARM GAS /tmp/ccth6daj.s page 59 + + +3282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do not generate Restart Condition */ +3295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. +3334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface + ARM GAS /tmp/ccth6daj.s page 60 + + +3339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin +3345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +3348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; +3349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; +3360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do not generate Restart Condition */ +3383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ +3385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + ARM GAS /tmp/ccth6daj.s page 61 + + +3396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; +3407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +3409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +3416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> +3417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +3418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +3440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +3452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + ARM GAS /tmp/ccth6daj.s page 62 + + +3453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +3475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +3476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +3477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +3478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +3487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter +3502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + ARM GAS /tmp/ccth6daj.s page 63 + + +3510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8 +3513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +3516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do not generate Restart Condition */ +3550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 64 + + +3567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); +3578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA +3589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +3603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; +3604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +3610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; +3615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; +3616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; +3623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 65 + + +3624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +3626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +3628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +3629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** do not generate Restart Condition */ +3638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ +3640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) +3641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; +3643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); +3648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) +3651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +3653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferSize > 0U) +3657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; +3662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +3664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +3665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +3668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +3669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +3671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p +3672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); +3673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccth6daj.s page 66 + + +3681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); +3693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +3695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); +3705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +3707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +3708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; +3728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Slave Address */ +3730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +3731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, +3732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); +3733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process + ARM GAS /tmp/ccth6daj.s page 67 + + +3738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* possible to enable all of these */ +3742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); +3745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +3752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +3756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +3766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t XferOptions) +3767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable associated Interrupts */ +3790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 68 + + +3795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA RX */ +3804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +3826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +3828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +3832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +3840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* REnable ADDR interrupt */ +3841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); +3842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +3844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + ARM GAS /tmp/ccth6daj.s page 69 + + +3852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +3856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +3857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +3858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +3860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +3861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t +3862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t XferOptions) +3863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +3867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +3870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +3872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +3874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +3879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +3882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +3886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable associated Interrupts */ +3888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +3889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +3891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +3894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +3896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +3900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA RX */ +3902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +3903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +3906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 70 + + +3909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +3911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +3913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +3915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +3922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA TX */ +3924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +3925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +3928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +3935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; +3938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +3939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +3940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +3943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +3945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +3946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +3947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +3948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +3949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +3950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +3952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; +3955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +3957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; +3958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; +3961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +3962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +3964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX +3965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + ARM GAS /tmp/ccth6daj.s page 71 + + +3966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +3977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +3980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +3983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +3985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +3986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset XferSize */ +3988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = 0; +3989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +3990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +3991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +3992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +3993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +3994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +3997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +3999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) +4006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +4018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +4019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +4022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + ARM GAS /tmp/ccth6daj.s page 72 + + +4023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +4038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +4039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si +4043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t XferOptions) +4044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +4046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable associated Interrupts */ +4067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 73 + + +4080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA TX */ +4081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +4098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +4100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +4105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +4117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param pData Pointer to data buffer +4134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Amount of data to be sent +4135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status + ARM GAS /tmp/ccth6daj.s page 74 + + +4137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +4139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t XferOptions) +4140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +4144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +4147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) +4149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; +4151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +4156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +4163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable associated Interrupts */ +4165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +4168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +4171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +4173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +4177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA TX */ +4179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +4180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +4183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +4188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +4190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +4192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA Xfer if any */ + ARM GAS /tmp/ccth6daj.s page 75 + + +4194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +4199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA RX */ +4201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +4202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +4205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +4212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; +4215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; +4216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +4217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; +4220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare transfer parameters */ +4222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr = pData; +4223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; +4224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; +4226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; +4227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +4229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; +4232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the DMA error callback */ +4234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; +4235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; +4238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +4239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +4241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, +4242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); +4243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +4247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ + ARM GAS /tmp/ccth6daj.s page 76 + + +4251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) +4260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +4262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +4263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset XferSize */ +4265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = 0; +4266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C state */ +4270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update I2C error code */ +4274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) +4283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +4287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +4295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); +4297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +4299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +4300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 77 + + +4308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +4311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +4316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) +4318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +4321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +4323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +4330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +4335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C +4337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +4340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmp; +4343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +4345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +4346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); +4349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +4350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +4352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +4354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +4355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_BUSY; +4361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + ARM GAS /tmp/ccth6daj.s page 78 + + +4365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Abort a master I2C IT or DMA process communication with Interrupt. +4366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +4369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +4370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +4373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) +4375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +4380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +4381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +4383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +4384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +4386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +4388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +4389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +4393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +4396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; +4397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +4399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +4400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); +4401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** process unlock */ +4408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +4409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wrong usage of abort function */ +4415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +4416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +4417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} + ARM GAS /tmp/ccth6daj.s page 79 + + +4422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +4425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ +4426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +4430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +4435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +4437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +4441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferISR != NULL) +4442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); +4444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +4449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +4454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); +4456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); +4457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; +4458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +4460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ +4461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; +4464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear BERR flag */ +4466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); +4467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +4470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ +4471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; +4474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear OVR flag */ +4476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); +4477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 80 + + +4479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +4480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ +4481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) +4482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; +4484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ARLO flag */ +4486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); +4487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +4490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +4491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +4493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_ +4494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, tmperror); +4496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +4501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +4506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +4512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +4517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +4522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +4528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +4532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + ARM GAS /tmp/ccth6daj.s page 81 + + +4536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +4537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +4543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +4548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +4553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file +4559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Slave Address Match callback. +4564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +4567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +4568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +4571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(TransferDirection); +4575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(AddrMatchCode); +4576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +4579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Listen Complete callback. +4584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +4589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 82 + + +4593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +4595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +4600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +4605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +4611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. +4616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +4621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +4627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C error callback. +4632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +4637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +4643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C abort callback. +4648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/ccth6daj.s page 83 + + +4650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +4651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +4653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(hi2c); +4656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +4659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} +4664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +4667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +4668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * +4669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @verbatim +4670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== +4671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +4672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** =============================================================================== +4673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** [..] +4674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +4675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** and the data flow. +4676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** @endverbatim +4678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ +4679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Return the I2C handle state. +4683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL state +4686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +4688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return I2C handle state */ +4690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return hi2c->State; +4691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +4695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for I2C module +4697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL mode +4698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +4700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return hi2c->Mode; +4702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Return the I2C error code. +4706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + ARM GAS /tmp/ccth6daj.s page 84 + + +4707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval I2C Error Code +4709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +4711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return hi2c->ErrorCode; +4713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} +4717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @} +4721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +4724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @{ +4725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +4729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources) +4737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; +4739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +4745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +4746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +4748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set corresponding Error Code */ +4751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +4756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +4759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +4760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +4763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 85 + + +4764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +4765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +4768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +4769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +4771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +4772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +4774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +4775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR */ +4777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +4780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +4781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +4783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +4784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ +4786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +4787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) +4789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +4791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +4793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +4795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START +4796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +4800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +4801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +4803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); +4804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, +4808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +4809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +4815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else + ARM GAS /tmp/ccth6daj.s page 86 + + +4821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +4823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ +4829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +4830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +4834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +4836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +4837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate Stop */ +4839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +4840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +4845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +4851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +4853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +4858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +4861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +4862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master complete process */ +4864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); +4865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +4868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +4871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +4874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +4875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +4877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. + ARM GAS /tmp/ccth6daj.s page 87 + + +4878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +4880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +4881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources) +4883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +4885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +4886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +4889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if STOPF is set */ +4891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ +4892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +4893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave complete process */ +4895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, tmpITFlags); +4896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ +4899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +4900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check that I2C transfer finished */ +4902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +4903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean XferCount == 0*/ +4904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* So clear Flag NACKF only */ +4905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +4906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +4908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +4909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +4910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Listen complete process */ +4912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +4913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) +4915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +4917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +4920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +4921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +4929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + ARM GAS /tmp/ccth6daj.s page 88 + + +4935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +4936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +4937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +4939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +4940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +4942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +4945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ +4949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) +4950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +4954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +4955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +4957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +4958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +4960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +4961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ +4964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +4965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +4968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ +4971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +4972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, tmpITFlags); +4974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ +4976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) +4977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +4979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +4980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if all Data have already been sent */ +4981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +4982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > 0U) +4983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write data to TXDR */ +4985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; +4986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +4988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +4989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +4990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +4991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/ccth6daj.s page 89 + + +4992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +4993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +4994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +4996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +4997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +4998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +4999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +5006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +5012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +5016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +5018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +5021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources) +5024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; +5026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; +5027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Locked */ +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set corresponding Error Code */ +5038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +5044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +5046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + ARM GAS /tmp/ccth6daj.s page 90 + + +5049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable TC interrupt */ +5052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); +5053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Recover Slave address */ +5057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); +5058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +5061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +5063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; +5064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +5068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; +5071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; +5075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ +5079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); +5080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update XferCount value */ +5082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; +5083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable DMA Request */ +5085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; +5088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; +5092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +5097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ + ARM GAS /tmp/ccth6daj.s page 91 + + +5106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ +5111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) +5112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +5114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +5116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +5118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) +5119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate Stop */ +5121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +5122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); +5127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +5133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); +5135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Master complete process */ +5141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); +5142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +5146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +5152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +5156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +5158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +5161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + ARM GAS /tmp/ccth6daj.s page 92 + + +5163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t ITSources) +5164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +5166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t treatdmanack = 0U; +5167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; +5168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process locked */ +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_LOCK(hi2c); +5171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if STOPF is set */ +5173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ +5174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) +5175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); +5178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ +5181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) +5182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean XferCount == 0 */ +5186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || +5188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) +5189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Split check of hdmarx, for MISRA compliance */ +5191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) +5194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) +5196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** treatdmanack = 1U; +5198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Split check of hdmatx, for MISRA compliance */ +5203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) +5206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U) +5208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** treatdmanack = 1U; +5210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (treatdmanack == 1U) +5215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) +5217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 93 + + +5220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); +5222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM +5224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +5229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ +5251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpstate = hi2c->State; +5252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) +5254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN +5260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +5266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Only Clear NACK Flag, no DMA treatment is pending */ +5276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + ARM GAS /tmp/ccth6daj.s page 94 + + +5277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ +5280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) +5281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); +5283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +5287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +5293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques +5297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +5299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +5302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +5304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +5305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +5306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32 +5309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart) +5310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI +5312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Memory Address */ +5323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 95 + + +5334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TCR flag is set */ +5342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) +5343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +5348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +5352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +5354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddress Internal memory address +5357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +5359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +5360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +5361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_ +5364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart) +5365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR +5367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) +5376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send Memory Address */ +5378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); +5385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) +5388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 96 + + +5391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); +5394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until TC flag is set */ +5397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) +5398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +5400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +5403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Address complete process callback. +5407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint8_t transferdirection; +5414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t slaveaddrcode; +5415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t ownadd1code; +5416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t ownadd2code; +5417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +5419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(ITFlags); +5420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ +5422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) +5423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); +5425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); +5426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); +5427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); +5428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +5430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) +5431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) +5433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = ownadd1code; +5435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrEventCount++; +5436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) +5437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset Address Event counter */ +5439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; +5440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag */ +5442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Slave Addr callback */ + ARM GAS /tmp/ccth6daj.s page 97 + + +5448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +5458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Slave Addr callback */ +5466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +5474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Slave Addr callback */ +5483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Else clear address flag only */ +5491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear ADDR flag */ +5494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +5503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None + ARM GAS /tmp/ccth6daj.s page 98 + + +5505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +5507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset I2C handle mode */ +5509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +5512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +5513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +5518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts */ +5520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +5538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts */ +5540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +5556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +5560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + ARM GAS /tmp/ccth6daj.s page 99 + + +5562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset I2C handle mode */ +5564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +5570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +5575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +5580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) +5583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ +5585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; +5587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts */ +5589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +5603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +5605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts */ +5609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); + ARM GAS /tmp/ccth6daj.s page 100 + + +5619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +5624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Master complete process. +5629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; +5636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __IO uint32_t tmpreg; +5638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +5640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); +5646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; +5647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +5656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset handle parameters */ +5662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +5663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) +5666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set acknowledge error code */ +5671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Fetch Last receive data if any */ +5675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + ARM GAS /tmp/ccth6daj.s page 101 + + +5676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +5678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpreg = (uint8_t)hi2c->Instance->RXDR; +5679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(tmpreg); +5680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +5683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +5686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; +5687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) +5690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +5695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +5696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemTxCpltCallback(hi2c); +5710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +5712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +5726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccth6daj.s page 102 + + +5733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +5736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MemRxCpltCallback(hi2c); +5745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +5747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +5767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Slave complete process. +5772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); +5779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; +5780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +5783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +5784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) +5787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); +5789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + ARM GAS /tmp/ccth6daj.s page 103 + + +5790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +5792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); +5794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +5799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Address Acknowledge */ +5802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +5803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +5805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +5806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +5808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +5809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) +5812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +5814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +5815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +5817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); +5819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) +5822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +5824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +5825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +5827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); +5829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Do nothing */ +5834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store Last receive data if any */ +5837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) +5838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +5840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; +5841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +5843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +5846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/ccth6daj.s page 104 + + +5847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +5851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +5852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +5856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount != 0U) +5857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +5864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) +5866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); +5869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) +5872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); +5875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +5878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ +5880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +5881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +5898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/ccth6daj.s page 105 + + +5904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +5910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +5913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +5925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Listen complete process. +5931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset handle parameters */ +5938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +5940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +5943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store Last receive data if any */ +5945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) +5946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Read data from RXDR */ +5948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; +5949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Increment Buffer pointer */ +5951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr++; +5952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) +5954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; +5956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; +5957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +5960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 106 + + +5961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable all Interrupts*/ +5964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +5965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACK Flag */ +5967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +5968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +5970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +5973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +5975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +5976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +5977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +5979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +5981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C interrupts error process. +5982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +5983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param ErrorCode Error code to handle. +5984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +5985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +5986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +5987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +5988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; +5989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmppreviousstate; +5990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset handle parameters */ +5992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +5993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +5994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = 0U; +5995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set new error code */ +5997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; +5998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +5999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Interrupts */ +6000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_LISTEN) || +6001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || +6002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +6003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +6005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +6008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +6009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; +6010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable all interrupts */ +6014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); +6015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If state is an abort treatment on going, don't change state */ +6017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* This change will be do later */ + ARM GAS /tmp/ccth6daj.s page 107 + + +6018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) +6019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +6021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; +6024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +6027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmppreviousstate = hi2c->PreviousState; +6028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ +6029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) +6030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) +6032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) +6037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; +6041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA TX */ +6046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) +6047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +6049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); +6050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +6058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ +6059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) +6060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) +6062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) +6067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; +6071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 108 + + +6075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Abort DMA RX */ +6076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) +6077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ +6079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); +6080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Error callback treatment. +6095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +6096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +6099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) +6101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AbortCpltCallback(hi2c); +6111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +6112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); +6113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCallback(hi2c); +6125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #else +6126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +6127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + ARM GAS /tmp/ccth6daj.s page 109 + + +6132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +6133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +6134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +6137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 27 .loc 1 6137 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. +6138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +6139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +6140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 32 .loc 1 6140 3 view .LVU1 + 33 .loc 1 6140 7 is_stmt 0 view .LVU2 + 34 0000 0368 ldr r3, [r0] + 35 0002 9A69 ldr r2, [r3, #24] + 36 .loc 1 6140 6 view .LVU3 + 37 0004 9207 lsls r2, r2, #30 + 38 0006 01D5 bpl .L2 +6141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; + 39 .loc 1 6142 5 is_stmt 1 view .LVU4 + 40 .loc 1 6142 26 is_stmt 0 view .LVU5 + 41 0008 0022 movs r2, #0 + 42 000a 9A62 str r2, [r3, #40] + 43 .L2: +6143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register if not empty */ +6146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 44 .loc 1 6146 3 is_stmt 1 view .LVU6 + 45 .loc 1 6146 7 is_stmt 0 view .LVU7 + 46 000c 0368 ldr r3, [r0] + 47 000e 9A69 ldr r2, [r3, #24] + 48 .loc 1 6146 6 view .LVU8 + 49 0010 D207 lsls r2, r2, #31 + 50 0012 03D4 bmi .L1 +6147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 51 .loc 1 6148 5 is_stmt 1 view .LVU9 + 52 0014 9A69 ldr r2, [r3, #24] + 53 0016 0121 movs r1, #1 + 54 0018 0A43 orrs r2, r1 + 55 001a 9A61 str r2, [r3, #24] + 56 .L1: +6149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 57 .loc 1 6150 1 is_stmt 0 view .LVU10 + 58 @ sp needed + 59 001c 7047 bx lr + 60 .cfi_endproc + 61 .LFE360: + 63 .section .text.I2C_TransferConfig,"ax",%progbits + 64 .align 1 + 65 .syntax unified + ARM GAS /tmp/ccth6daj.s page 110 + + + 66 .code 16 + 67 .thumb_func + 68 .fpu softvfp + 70 I2C_TransferConfig: + 71 .LVL1: + 72 .LFB372: +6151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +6154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle +6155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +6158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +6163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable STOP interrupt */ +6169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Buffer pointer */ +6175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, +6189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable TC interrupts */ +6197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 111 + + +6202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +6204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle +6205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +6208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) +6214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +6216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; +6217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +6232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle +6233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +6236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +6241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount == 0U) +6245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable STOP interrupt */ +6247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); +6248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Update Buffer pointer */ +6253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + ARM GAS /tmp/ccth6daj.s page 112 + + +6259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable the DMA channel */ +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, +6267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable TC interrupts */ +6275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +6282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle +6283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +6286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; +6290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ +6292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +6293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable DMA Request */ +6295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; +6296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +6310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle +6311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +6314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + ARM GAS /tmp/ccth6daj.s page 113 + + +6316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable Acknowledge */ +6319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; +6320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +6327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +6328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hdma DMA handle. +6329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +6332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); +6335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +6337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) +6338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; +6340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) +6342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; +6344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); +6347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. +6351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +6354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Status The new Flag status (SET or RESET). +6355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +6356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +6357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +6358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +6360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart) +6361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) +6363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check for the Timeout */ +6365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 114 + + +6373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +6384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +6387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +6388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +6389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart) +6392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) +6394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if a NACK is detected */ +6396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check for the Timeout */ +6402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +6422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +6425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +6426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +6427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart) + ARM GAS /tmp/ccth6daj.s page 115 + + +6430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if a NACK is detected */ +6434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check for the Timeout */ +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +6457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +6460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +6461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +6462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Tickstart) +6465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) +6467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if a NACK is detected */ +6469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) +6470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) +6476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check if an RXNE is pending */ +6478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Store Last receive data if any */ +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) +6480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return HAL_OK */ +6482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* The Reading of data from RXDR will be done in caller function */ +6483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 116 + + +6487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +6488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; +6494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check for the Timeout */ +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief This function handles Acknowledge failed detection during an I2C Communication. +6521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Timeout Timeout duration +6524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Tickstart Tick start value +6525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval HAL status +6526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_ +6528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) +6530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* In case of Soft End condition, generate the STOP condition */ +6532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) +6533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Generate Stop */ +6535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; +6536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Wait until STOP Flag is reset */ +6538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +6539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) +6540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check for the Timeout */ +6542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) +6543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 117 + + +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) +6545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; +6547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear NACKF Flag */ +6559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); +6560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear STOP Flag */ +6562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); +6563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Flush TX register */ +6565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); +6566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); +6569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; +6571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Process Unlocked */ +6575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; +6578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_OK; +6580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +6584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +6585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +6586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. +6587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +6588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +6589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter can be one of the following values: +6590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . +6591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +6592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +6593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +6594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * This parameter can be one of the following values: +6595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +6596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +6597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +6598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +6599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ + ARM GAS /tmp/ccth6daj.s page 118 + + +6601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t +6602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t Request) +6603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 73 .loc 1 6603 1 is_stmt 1 view -0 + 74 .cfi_startproc + 75 @ args = 4, pretend = 0, frame = 0 + 76 @ frame_needed = 0, uses_anonymous_args = 0 + 77 .loc 1 6603 1 is_stmt 0 view .LVU12 + 78 0000 70B5 push {r4, r5, r6, lr} + 79 .LCFI0: + 80 .cfi_def_cfa_offset 16 + 81 .cfi_offset 4, -16 + 82 .cfi_offset 5, -12 + 83 .cfi_offset 6, -8 + 84 .cfi_offset 14, -4 +6604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ +6605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 85 .loc 1 6605 3 is_stmt 1 view .LVU13 +6606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); + 86 .loc 1 6606 3 view .LVU14 +6607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); + 87 .loc 1 6607 3 view .LVU15 +6608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* update CR2 register */ +6610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, + 88 .loc 1 6610 3 view .LVU16 + 89 0002 0468 ldr r4, [r0] + 90 0004 6068 ldr r0, [r4, #4] + 91 .LVL2: + 92 .loc 1 6610 3 is_stmt 0 view .LVU17 + 93 0006 049D ldr r5, [sp, #16] + 94 0008 6D0D lsrs r5, r5, #21 + 95 000a 8026 movs r6, #128 + 96 000c F600 lsls r6, r6, #3 + 97 000e 2E40 ands r6, r5 + 98 0010 064D ldr r5, .L5 + 99 0012 3543 orrs r5, r6 + 100 0014 A843 bics r0, r5 + 101 0016 8905 lsls r1, r1, #22 + 102 .LVL3: + 103 .loc 1 6610 3 view .LVU18 + 104 0018 890D lsrs r1, r1, #22 + 105 001a 1204 lsls r2, r2, #16 + 106 .LVL4: + 107 .loc 1 6610 3 view .LVU19 + 108 001c 1143 orrs r1, r2 + 109 001e 1943 orrs r1, r3 + 110 0020 049B ldr r3, [sp, #16] + 111 .LVL5: + 112 .loc 1 6610 3 view .LVU20 + 113 0022 1943 orrs r1, r3 + 114 0024 0143 orrs r1, r0 + 115 0026 6160 str r1, [r4, #4] +6611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ +6612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ +6613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_CR2_START | I2C_CR2_STOP)), \ +6614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + ARM GAS /tmp/ccth6daj.s page 119 + + +6615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ +6616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)Mode | (uint32_t)Request)); +6617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 116 .loc 1 6617 1 view .LVU21 + 117 @ sp needed + 118 0028 70BD pop {r4, r5, r6, pc} + 119 .L6: + 120 002a C046 .align 2 + 121 .L5: + 122 002c FF63FF03 .word 67068927 + 123 .cfi_endproc + 124 .LFE372: + 126 .section .text.I2C_Enable_IRQ,"ax",%progbits + 127 .align 1 + 128 .syntax unified + 129 .code 16 + 130 .thumb_func + 131 .fpu softvfp + 133 I2C_Enable_IRQ: + 134 .LVL6: + 135 .LFB373: +6618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +6621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 136 .loc 1 6627 1 is_stmt 1 view -0 + 137 .cfi_startproc + 138 @ args = 0, pretend = 0, frame = 0 + 139 @ frame_needed = 0, uses_anonymous_args = 0 + 140 @ link register save eliminated. +6628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 141 .loc 1 6628 3 view .LVU23 +6629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + 142 .loc 1 6630 3 view .LVU24 + 143 .loc 1 6630 12 is_stmt 0 view .LVU25 + 144 0000 436B ldr r3, [r0, #52] + 145 .loc 1 6630 6 view .LVU26 + 146 0002 194A ldr r2, .L22 + 147 0004 9342 cmp r3, r2 + 148 0006 13D0 beq .L8 + 149 .loc 1 6630 45 discriminator 1 view .LVU27 + 150 0008 184A ldr r2, .L22+4 + 151 000a 9342 cmp r3, r2 + 152 000c 10D0 beq .L8 +6631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->XferISR == I2C_Slave_ISR_DMA)) +6632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) +6634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +6636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + ARM GAS /tmp/ccth6daj.s page 120 + + +6637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) +6640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) +6646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable STOP interrupts */ +6648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); +6649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) +6652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable TC interrupts */ +6654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 153 .loc 1 6659 5 is_stmt 1 view .LVU28 + 154 .loc 1 6659 49 is_stmt 0 view .LVU29 + 155 000e 0BB2 sxth r3, r1 + 156 .loc 1 6659 8 view .LVU30 + 157 0010 002B cmp r3, #0 + 158 0012 27DB blt .L18 +6628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 159 .loc 1 6628 12 view .LVU31 + 160 0014 0023 movs r3, #0 + 161 .L14: + 162 .LVL7: +6660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, and ADDR interrupts */ +6662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 163 .loc 1 6665 5 is_stmt 1 view .LVU32 + 164 .loc 1 6665 8 is_stmt 0 view .LVU33 + 165 0016 CA07 lsls r2, r1, #31 + 166 0018 01D5 bpl .L15 +6666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +6668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 167 .loc 1 6668 7 is_stmt 1 view .LVU34 + 168 .loc 1 6668 14 is_stmt 0 view .LVU35 + 169 001a F222 movs r2, #242 + 170 001c 1343 orrs r3, r2 + 171 .LVL8: + 172 .L15: +6669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 173 .loc 1 6671 5 is_stmt 1 view .LVU36 + ARM GAS /tmp/ccth6daj.s page 121 + + + 174 .loc 1 6671 8 is_stmt 0 view .LVU37 + 175 001e 8A07 lsls r2, r1, #30 + 176 0020 01D5 bpl .L16 +6672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +6674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 177 .loc 1 6674 7 is_stmt 1 view .LVU38 + 178 .loc 1 6674 14 is_stmt 0 view .LVU39 + 179 0022 F422 movs r2, #244 + 180 0024 1343 orrs r3, r2 + 181 .LVL9: + 182 .L16: +6675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 183 .loc 1 6677 5 is_stmt 1 view .LVU40 + 184 .loc 1 6677 8 is_stmt 0 view .LVU41 + 185 0026 2029 cmp r1, #32 + 186 0028 0CD1 bne .L13 +6678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable STOP interrupts */ +6680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 187 .loc 1 6680 7 is_stmt 1 view .LVU42 + 188 .loc 1 6680 14 is_stmt 0 view .LVU43 + 189 002a 2022 movs r2, #32 + 190 002c 1343 orrs r3, r2 + 191 .LVL10: + 192 .loc 1 6680 14 view .LVU44 + 193 002e 09E0 b .L13 + 194 .LVL11: + 195 .L8: +6633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 196 .loc 1 6633 5 is_stmt 1 view .LVU45 +6633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 197 .loc 1 6633 49 is_stmt 0 view .LVU46 + 198 0030 0BB2 sxth r3, r1 +6633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 199 .loc 1 6633 8 view .LVU47 + 200 0032 002B cmp r3, #0 + 201 0034 0BDB blt .L17 +6628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 202 .loc 1 6628 12 view .LVU48 + 203 0036 0023 movs r3, #0 + 204 .L10: + 205 .LVL12: +6639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 206 .loc 1 6639 5 is_stmt 1 view .LVU49 +6639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 207 .loc 1 6639 8 is_stmt 0 view .LVU50 + 208 0038 1029 cmp r1, #16 + 209 003a 0AD0 beq .L19 + 210 .L11: +6645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 211 .loc 1 6645 5 is_stmt 1 view .LVU51 +6645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 212 .loc 1 6645 8 is_stmt 0 view .LVU52 + 213 003c 2029 cmp r1, #32 + ARM GAS /tmp/ccth6daj.s page 122 + + + 214 003e 0BD0 beq .L20 + 215 .L12: +6651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 216 .loc 1 6651 5 is_stmt 1 view .LVU53 +6651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 217 .loc 1 6651 8 is_stmt 0 view .LVU54 + 218 0040 4029 cmp r1, #64 + 219 0042 0CD0 beq .L21 + 220 .L13: +6681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable interrupts only at the end */ +6685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +6686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* all interrupts requested done */ +6687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + 221 .loc 1 6687 3 is_stmt 1 view .LVU55 + 222 0044 0168 ldr r1, [r0] + 223 .LVL13: + 224 .loc 1 6687 3 is_stmt 0 view .LVU56 + 225 0046 0A68 ldr r2, [r1] + 226 0048 1343 orrs r3, r2 + 227 .LVL14: + 228 .loc 1 6687 3 view .LVU57 + 229 004a 0B60 str r3, [r1] +6688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 230 .loc 1 6688 1 view .LVU58 + 231 @ sp needed + 232 004c 7047 bx lr + 233 .LVL15: + 234 .L17: +6636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 235 .loc 1 6636 14 view .LVU59 + 236 004e B823 movs r3, #184 + 237 0050 F2E7 b .L10 + 238 .LVL16: + 239 .L19: +6642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 240 .loc 1 6642 7 is_stmt 1 view .LVU60 +6642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 241 .loc 1 6642 14 is_stmt 0 view .LVU61 + 242 0052 9022 movs r2, #144 + 243 0054 1343 orrs r3, r2 + 244 .LVL17: +6642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 245 .loc 1 6642 14 view .LVU62 + 246 0056 F1E7 b .L11 + 247 .L20: +6648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 248 .loc 1 6648 7 is_stmt 1 view .LVU63 +6648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 249 .loc 1 6648 14 is_stmt 0 view .LVU64 + 250 0058 6022 movs r2, #96 + 251 005a 1343 orrs r3, r2 + 252 .LVL18: +6648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 253 .loc 1 6648 14 view .LVU65 + ARM GAS /tmp/ccth6daj.s page 123 + + + 254 005c F0E7 b .L12 + 255 .L21: +6654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 256 .loc 1 6654 7 is_stmt 1 view .LVU66 +6654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 257 .loc 1 6654 14 is_stmt 0 view .LVU67 + 258 005e 4022 movs r2, #64 + 259 0060 1343 orrs r3, r2 + 260 .LVL19: +6654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 261 .loc 1 6654 14 view .LVU68 + 262 0062 EFE7 b .L13 + 263 .LVL20: + 264 .L18: +6662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 265 .loc 1 6662 14 view .LVU69 + 266 0064 B823 movs r3, #184 + 267 0066 D6E7 b .L14 + 268 .L23: + 269 .align 2 + 270 .L22: + 271 0068 00000000 .word I2C_Master_ISR_DMA + 272 006c 00000000 .word I2C_Slave_ISR_DMA + 273 .cfi_endproc + 274 .LFE373: + 276 .section .text.I2C_Disable_IRQ,"ax",%progbits + 277 .align 1 + 278 .syntax unified + 279 .code 16 + 280 .thumb_func + 281 .fpu softvfp + 283 I2C_Disable_IRQ: + 284 .LVL21: + 285 .LFB374: +6689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +6692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * the configuration information for the specified I2C. +6694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +6695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +6698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 286 .loc 1 6698 1 is_stmt 1 view -0 + 287 .cfi_startproc + 288 @ args = 0, pretend = 0, frame = 0 + 289 @ frame_needed = 0, uses_anonymous_args = 0 + 290 .loc 1 6698 1 is_stmt 0 view .LVU71 + 291 0000 30B5 push {r4, r5, lr} + 292 .LCFI1: + 293 .cfi_def_cfa_offset 12 + 294 .cfi_offset 4, -12 + 295 .cfi_offset 5, -8 + 296 .cfi_offset 14, -4 +6699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 297 .loc 1 6699 3 is_stmt 1 view .LVU72 + ARM GAS /tmp/ccth6daj.s page 124 + + + 298 .LVL22: +6700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 299 .loc 1 6701 3 view .LVU73 + 300 .loc 1 6701 6 is_stmt 0 view .LVU74 + 301 0002 CB07 lsls r3, r1, #31 + 302 0004 09D5 bpl .L31 +6702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +6704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 303 .loc 1 6704 5 is_stmt 1 view .LVU75 + 304 .LVL23: +6705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 305 .loc 1 6706 5 view .LVU76 + 306 .loc 1 6706 24 is_stmt 0 view .LVU77 + 307 0006 4123 movs r3, #65 + 308 0008 C35C ldrb r3, [r0, r3] + 309 .loc 1 6706 8 view .LVU78 + 310 000a 2822 movs r2, #40 + 311 000c 1340 ands r3, r2 + 312 000e 282B cmp r3, #40 + 313 0010 01D0 beq .L34 +6707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 314 .loc 1 6709 14 view .LVU79 + 315 0012 F223 movs r3, #242 + 316 0014 02E0 b .L25 + 317 .L34: +6704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 318 .loc 1 6704 12 view .LVU80 + 319 0016 1A33 adds r3, r3, #26 + 320 0018 00E0 b .L25 + 321 .LVL24: + 322 .L31: +6699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 323 .loc 1 6699 12 view .LVU81 + 324 001a 0023 movs r3, #0 + 325 .LVL25: + 326 .L25: +6710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 327 .loc 1 6713 3 is_stmt 1 view .LVU82 + 328 .loc 1 6713 6 is_stmt 0 view .LVU83 + 329 001c 8A07 lsls r2, r1, #30 + 330 001e 09D5 bpl .L26 +6714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +6716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 331 .loc 1 6716 5 is_stmt 1 view .LVU84 + 332 .loc 1 6716 12 is_stmt 0 view .LVU85 + 333 0020 4424 movs r4, #68 + 334 0022 1C43 orrs r4, r3 + 335 .LVL26: + ARM GAS /tmp/ccth6daj.s page 125 + + +6717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 336 .loc 1 6718 5 is_stmt 1 view .LVU86 + 337 .loc 1 6718 24 is_stmt 0 view .LVU87 + 338 0024 4122 movs r2, #65 + 339 0026 825C ldrb r2, [r0, r2] + 340 .loc 1 6718 8 view .LVU88 + 341 0028 2825 movs r5, #40 + 342 002a 2A40 ands r2, r5 + 343 002c 282A cmp r2, #40 + 344 002e 0FD0 beq .L33 +6719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +6721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 345 .loc 1 6721 7 is_stmt 1 view .LVU89 + 346 .loc 1 6721 14 is_stmt 0 view .LVU90 + 347 0030 F422 movs r2, #244 + 348 0032 1343 orrs r3, r2 + 349 .LVL27: + 350 .L26: +6722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 351 .loc 1 6725 3 is_stmt 1 view .LVU91 + 352 .loc 1 6725 47 is_stmt 0 view .LVU92 + 353 0034 0AB2 sxth r2, r1 + 354 .loc 1 6725 6 view .LVU93 + 355 0036 002A cmp r2, #0 + 356 0038 0CDB blt .L35 + 357 .L27: +6726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +6728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; +6729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 358 .loc 1 6731 3 is_stmt 1 view .LVU94 + 359 .loc 1 6731 6 is_stmt 0 view .LVU95 + 360 003a 1029 cmp r1, #16 + 361 003c 0DD0 beq .L36 + 362 .L28: +6732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +6734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; +6735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 363 .loc 1 6737 3 is_stmt 1 view .LVU96 + 364 .loc 1 6737 6 is_stmt 0 view .LVU97 + 365 003e 2029 cmp r1, #32 + 366 0040 0ED0 beq .L37 + 367 .L29: +6738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable STOP interrupts */ +6740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; +6741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 126 + + +6742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 368 .loc 1 6743 3 is_stmt 1 view .LVU98 + 369 .loc 1 6743 6 is_stmt 0 view .LVU99 + 370 0042 4029 cmp r1, #64 + 371 0044 0FD0 beq .L38 + 372 .L30: +6744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Enable TC interrupts */ +6746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; +6747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Disable interrupts only at the end */ +6750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +6751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* all disable interrupts request are not done */ +6752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 373 .loc 1 6752 3 is_stmt 1 view .LVU100 + 374 0046 0168 ldr r1, [r0] + 375 .LVL28: + 376 .loc 1 6752 3 is_stmt 0 view .LVU101 + 377 0048 0A68 ldr r2, [r1] + 378 004a 9A43 bics r2, r3 + 379 004c 0A60 str r2, [r1] +6753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 380 .loc 1 6753 1 view .LVU102 + 381 @ sp needed + 382 004e 30BD pop {r4, r5, pc} + 383 .LVL29: + 384 .L33: +6716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 385 .loc 1 6716 12 view .LVU103 + 386 0050 2300 movs r3, r4 + 387 0052 EFE7 b .L26 + 388 .LVL30: + 389 .L35: +6728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 390 .loc 1 6728 5 is_stmt 1 view .LVU104 +6728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 391 .loc 1 6728 12 is_stmt 0 view .LVU105 + 392 0054 B822 movs r2, #184 + 393 0056 1343 orrs r3, r2 + 394 .LVL31: +6728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 395 .loc 1 6728 12 view .LVU106 + 396 0058 EFE7 b .L27 + 397 .L36: +6734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 398 .loc 1 6734 5 is_stmt 1 view .LVU107 +6734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 399 .loc 1 6734 12 is_stmt 0 view .LVU108 + 400 005a 9022 movs r2, #144 + 401 005c 1343 orrs r3, r2 + 402 .LVL32: +6734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 403 .loc 1 6734 12 view .LVU109 + 404 005e EEE7 b .L28 + 405 .L37: + ARM GAS /tmp/ccth6daj.s page 127 + + +6740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 406 .loc 1 6740 5 is_stmt 1 view .LVU110 +6740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 407 .loc 1 6740 12 is_stmt 0 view .LVU111 + 408 0060 2022 movs r2, #32 + 409 0062 1343 orrs r3, r2 + 410 .LVL33: +6740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 411 .loc 1 6740 12 view .LVU112 + 412 0064 EDE7 b .L29 + 413 .L38: +6746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 414 .loc 1 6746 5 is_stmt 1 view .LVU113 +6746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 415 .loc 1 6746 12 is_stmt 0 view .LVU114 + 416 0066 4022 movs r2, #64 + 417 0068 1343 orrs r3, r2 + 418 .LVL34: +6746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 419 .loc 1 6746 12 view .LVU115 + 420 006a ECE7 b .L30 + 421 .cfi_endproc + 422 .LFE374: + 424 .section .text.I2C_ConvertOtherXferOptions,"ax",%progbits + 425 .align 1 + 426 .syntax unified + 427 .code 16 + 428 .thumb_func + 429 .fpu softvfp + 431 I2C_ConvertOtherXferOptions: + 432 .LVL35: + 433 .LFB375: +6754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** +6755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** +6756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. +6757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @param hi2c I2C handle. +6758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** * @retval None +6759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** */ +6760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +6761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 434 .loc 1 6761 1 is_stmt 1 view -0 + 435 .cfi_startproc + 436 @ args = 0, pretend = 0, frame = 0 + 437 @ frame_needed = 0, uses_anonymous_args = 0 + 438 @ link register save eliminated. +6762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* if user set XferOptions to I2C_OTHER_FRAME */ +6763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_FRAME */ +6765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_OTHER_FRAME) + 439 .loc 1 6765 3 view .LVU117 + 440 .loc 1 6765 11 is_stmt 0 view .LVU118 + 441 0000 C36A ldr r3, [r0, #44] + 442 .loc 1 6765 6 view .LVU119 + 443 0002 AA2B cmp r3, #170 + 444 0004 05D0 beq .L42 +6766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_FRAME; + ARM GAS /tmp/ccth6daj.s page 128 + + +6768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ +6770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +6771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* then generate a stop condition at the end of transfer */ +6772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ +6773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + 445 .loc 1 6773 8 is_stmt 1 view .LVU120 + 446 .loc 1 6773 16 is_stmt 0 view .LVU121 + 447 0006 C26A ldr r2, [r0, #44] + 448 .loc 1 6773 11 view .LVU122 + 449 0008 AA23 movs r3, #170 + 450 000a 1B02 lsls r3, r3, #8 + 451 000c 9A42 cmp r2, r3 + 452 000e 03D0 beq .L43 + 453 .L39: +6774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; +6776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** else +6778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { +6779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Nothing to do */ +6780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } +6781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 454 .loc 1 6781 1 view .LVU123 + 455 @ sp needed + 456 0010 7047 bx lr + 457 .L42: +6767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 458 .loc 1 6767 5 is_stmt 1 view .LVU124 +6767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 459 .loc 1 6767 23 is_stmt 0 view .LVU125 + 460 0012 0023 movs r3, #0 + 461 0014 C362 str r3, [r0, #44] + 462 0016 FBE7 b .L39 + 463 .L43: +6775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 464 .loc 1 6775 5 is_stmt 1 view .LVU126 +6775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 465 .loc 1 6775 23 is_stmt 0 view .LVU127 + 466 0018 8023 movs r3, #128 + 467 001a 9B04 lsls r3, r3, #18 + 468 001c C362 str r3, [r0, #44] +6780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 469 .loc 1 6780 3 is_stmt 1 view .LVU128 + 470 .loc 1 6781 1 is_stmt 0 view .LVU129 + 471 001e F7E7 b .L39 + 472 .cfi_endproc + 473 .LFE375: + 475 .section .text.I2C_IsAcknowledgeFailed,"ax",%progbits + 476 .align 1 + 477 .syntax unified + 478 .code 16 + 479 .thumb_func + 480 .fpu softvfp + 482 I2C_IsAcknowledgeFailed: + 483 .LVL36: + 484 .LFB371: + ARM GAS /tmp/ccth6daj.s page 129 + + +6528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 485 .loc 1 6528 1 is_stmt 1 view -0 + 486 .cfi_startproc + 487 @ args = 0, pretend = 0, frame = 0 + 488 @ frame_needed = 0, uses_anonymous_args = 0 +6528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 489 .loc 1 6528 1 is_stmt 0 view .LVU131 + 490 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 491 .LCFI2: + 492 .cfi_def_cfa_offset 24 + 493 .cfi_offset 3, -24 + 494 .cfi_offset 4, -20 + 495 .cfi_offset 5, -16 + 496 .cfi_offset 6, -12 + 497 .cfi_offset 7, -8 + 498 .cfi_offset 14, -4 + 499 0002 0500 movs r5, r0 + 500 0004 0F00 movs r7, r1 + 501 0006 1600 movs r6, r2 +6529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 502 .loc 1 6529 3 is_stmt 1 view .LVU132 +6529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 503 .loc 1 6529 7 is_stmt 0 view .LVU133 + 504 0008 0368 ldr r3, [r0] + 505 000a 9A69 ldr r2, [r3, #24] + 506 .LVL37: +6529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 507 .loc 1 6529 6 view .LVU134 + 508 000c D206 lsls r2, r2, #27 + 509 000e 3BD5 bpl .L51 +6532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 510 .loc 1 6532 5 is_stmt 1 view .LVU135 +6532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 511 .loc 1 6532 9 is_stmt 0 view .LVU136 + 512 0010 5A68 ldr r2, [r3, #4] +6532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 513 .loc 1 6532 8 view .LVU137 + 514 0012 9201 lsls r2, r2, #6 + 515 0014 04D4 bmi .L47 +6535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 516 .loc 1 6535 7 is_stmt 1 view .LVU138 +6535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 517 .loc 1 6535 27 is_stmt 0 view .LVU139 + 518 0016 5968 ldr r1, [r3, #4] + 519 .LVL38: +6535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 520 .loc 1 6535 27 view .LVU140 + 521 0018 8022 movs r2, #128 + 522 001a D201 lsls r2, r2, #7 + 523 001c 0A43 orrs r2, r1 + 524 001e 5A60 str r2, [r3, #4] + 525 .LVL39: + 526 .L47: +6539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 527 .loc 1 6539 11 is_stmt 1 view .LVU141 +6539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 528 .loc 1 6539 12 is_stmt 0 view .LVU142 + ARM GAS /tmp/ccth6daj.s page 130 + + + 529 0020 2B68 ldr r3, [r5] + 530 0022 9C69 ldr r4, [r3, #24] +6539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 531 .loc 1 6539 11 view .LVU143 + 532 0024 A206 lsls r2, r4, #26 + 533 0026 15D4 bmi .L52 +6542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 534 .loc 1 6542 7 is_stmt 1 view .LVU144 +6542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 535 .loc 1 6542 10 is_stmt 0 view .LVU145 + 536 0028 7B1C adds r3, r7, #1 + 537 002a F9D0 beq .L47 +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 538 .loc 1 6544 9 is_stmt 1 view .LVU146 +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 539 .loc 1 6544 15 is_stmt 0 view .LVU147 + 540 002c FFF7FEFF bl HAL_GetTick + 541 .LVL40: +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 542 .loc 1 6544 29 view .LVU148 + 543 0030 801B subs r0, r0, r6 +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 544 .loc 1 6544 12 view .LVU149 + 545 0032 B842 cmp r0, r7 + 546 0034 01D8 bhi .L48 +6544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 547 .loc 1 6544 53 discriminator 1 view .LVU150 + 548 0036 002F cmp r7, #0 + 549 0038 F2D1 bne .L47 + 550 .L48: +6546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 551 .loc 1 6546 11 is_stmt 1 view .LVU151 +6546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 552 .loc 1 6546 27 is_stmt 0 view .LVU152 + 553 003a 6B6C ldr r3, [r5, #68] + 554 003c 2022 movs r2, #32 + 555 003e 1343 orrs r3, r2 + 556 0040 6B64 str r3, [r5, #68] +6547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 557 .loc 1 6547 11 is_stmt 1 view .LVU153 +6547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 558 .loc 1 6547 23 is_stmt 0 view .LVU154 + 559 0042 4123 movs r3, #65 + 560 0044 EA54 strb r2, [r5, r3] +6548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 561 .loc 1 6548 11 is_stmt 1 view .LVU155 +6548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 562 .loc 1 6548 22 is_stmt 0 view .LVU156 + 563 0046 0023 movs r3, #0 + 564 0048 2232 adds r2, r2, #34 + 565 004a AB54 strb r3, [r5, r2] +6551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 566 .loc 1 6551 11 is_stmt 1 view .LVU157 +6551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 567 .loc 1 6551 11 view .LVU158 + 568 004c 023A subs r2, r2, #2 + 569 004e AB54 strb r3, [r5, r2] + ARM GAS /tmp/ccth6daj.s page 131 + + +6551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 570 .loc 1 6551 11 view .LVU159 +6553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 571 .loc 1 6553 11 view .LVU160 +6553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 572 .loc 1 6553 18 is_stmt 0 view .LVU161 + 573 0050 0120 movs r0, #1 + 574 0052 1AE0 b .L45 + 575 .L52: +6559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 576 .loc 1 6559 5 is_stmt 1 view .LVU162 + 577 0054 1022 movs r2, #16 + 578 0056 DA61 str r2, [r3, #28] +6562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 579 .loc 1 6562 5 view .LVU163 + 580 0058 2B68 ldr r3, [r5] + 581 005a 2024 movs r4, #32 + 582 005c DC61 str r4, [r3, #28] +6565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 583 .loc 1 6565 5 view .LVU164 + 584 005e 2800 movs r0, r5 + 585 0060 FFF7FEFF bl I2C_Flush_TXDR + 586 .LVL41: +6568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 587 .loc 1 6568 5 view .LVU165 + 588 0064 2A68 ldr r2, [r5] + 589 0066 5368 ldr r3, [r2, #4] + 590 0068 0849 ldr r1, .L53 + 591 006a 0B40 ands r3, r1 + 592 006c 5360 str r3, [r2, #4] +6570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 593 .loc 1 6570 5 view .LVU166 +6570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 594 .loc 1 6570 21 is_stmt 0 view .LVU167 + 595 006e 6B6C ldr r3, [r5, #68] + 596 0070 0422 movs r2, #4 + 597 0072 1343 orrs r3, r2 + 598 0074 6B64 str r3, [r5, #68] +6571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 599 .loc 1 6571 5 is_stmt 1 view .LVU168 +6571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 600 .loc 1 6571 17 is_stmt 0 view .LVU169 + 601 0076 4123 movs r3, #65 + 602 0078 EC54 strb r4, [r5, r3] +6572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 603 .loc 1 6572 5 is_stmt 1 view .LVU170 +6572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 604 .loc 1 6572 16 is_stmt 0 view .LVU171 + 605 007a 0023 movs r3, #0 + 606 007c 3E32 adds r2, r2, #62 + 607 007e AB54 strb r3, [r5, r2] +6575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 608 .loc 1 6575 5 is_stmt 1 view .LVU172 +6575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 609 .loc 1 6575 5 view .LVU173 + 610 0080 023A subs r2, r2, #2 + 611 0082 AB54 strb r3, [r5, r2] + ARM GAS /tmp/ccth6daj.s page 132 + + +6575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 612 .loc 1 6575 5 view .LVU174 +6577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 613 .loc 1 6577 5 view .LVU175 +6577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 614 .loc 1 6577 12 is_stmt 0 view .LVU176 + 615 0084 0120 movs r0, #1 + 616 0086 00E0 b .L45 + 617 .LVL42: + 618 .L51: +6579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 619 .loc 1 6579 10 view .LVU177 + 620 0088 0020 movs r0, #0 + 621 .LVL43: + 622 .L45: +6580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 623 .loc 1 6580 1 view .LVU178 + 624 @ sp needed + 625 .LVL44: + 626 .LVL45: + 627 .LVL46: +6580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 628 .loc 1 6580 1 view .LVU179 + 629 008a F8BD pop {r3, r4, r5, r6, r7, pc} + 630 .L54: + 631 .align 2 + 632 .L53: + 633 008c 00E800FE .word -33495040 + 634 .cfi_endproc + 635 .LFE371: + 637 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 638 .align 1 + 639 .syntax unified + 640 .code 16 + 641 .thumb_func + 642 .fpu softvfp + 644 I2C_WaitOnTXISFlagUntilTimeout: + 645 .LVL47: + 646 .LFB368: +6392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 647 .loc 1 6392 1 is_stmt 1 view -0 + 648 .cfi_startproc + 649 @ args = 0, pretend = 0, frame = 0 + 650 @ frame_needed = 0, uses_anonymous_args = 0 +6392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 651 .loc 1 6392 1 is_stmt 0 view .LVU181 + 652 0000 70B5 push {r4, r5, r6, lr} + 653 .LCFI3: + 654 .cfi_def_cfa_offset 16 + 655 .cfi_offset 4, -16 + 656 .cfi_offset 5, -12 + 657 .cfi_offset 6, -8 + 658 .cfi_offset 14, -4 + 659 0002 0400 movs r4, r0 + 660 0004 0D00 movs r5, r1 + 661 0006 1600 movs r6, r2 +6393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 133 + + + 662 .loc 1 6393 3 is_stmt 1 view .LVU182 + 663 .LVL48: + 664 .L58: +6393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 665 .loc 1 6393 9 view .LVU183 +6393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 666 .loc 1 6393 10 is_stmt 0 view .LVU184 + 667 0008 2368 ldr r3, [r4] + 668 000a 9B69 ldr r3, [r3, #24] +6393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 669 .loc 1 6393 9 view .LVU185 + 670 000c 9B07 lsls r3, r3, #30 + 671 000e 1CD4 bmi .L62 +6396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 672 .loc 1 6396 5 is_stmt 1 view .LVU186 +6396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 673 .loc 1 6396 9 is_stmt 0 view .LVU187 + 674 0010 3200 movs r2, r6 + 675 0012 2900 movs r1, r5 + 676 0014 2000 movs r0, r4 + 677 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 678 .LVL49: +6396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 679 .loc 1 6396 8 view .LVU188 + 680 001a 0028 cmp r0, #0 + 681 001c 17D1 bne .L61 +6402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 682 .loc 1 6402 5 is_stmt 1 view .LVU189 +6402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 683 .loc 1 6402 8 is_stmt 0 view .LVU190 + 684 001e 6B1C adds r3, r5, #1 + 685 0020 F2D0 beq .L58 +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 686 .loc 1 6404 7 is_stmt 1 view .LVU191 +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 687 .loc 1 6404 13 is_stmt 0 view .LVU192 + 688 0022 FFF7FEFF bl HAL_GetTick + 689 .LVL50: +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 690 .loc 1 6404 27 view .LVU193 + 691 0026 801B subs r0, r0, r6 +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 692 .loc 1 6404 10 view .LVU194 + 693 0028 A842 cmp r0, r5 + 694 002a 01D8 bhi .L59 +6404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 695 .loc 1 6404 51 discriminator 1 view .LVU195 + 696 002c 002D cmp r5, #0 + 697 002e EBD1 bne .L58 + 698 .L59: +6406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 699 .loc 1 6406 9 is_stmt 1 view .LVU196 +6406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 700 .loc 1 6406 25 is_stmt 0 view .LVU197 + 701 0030 636C ldr r3, [r4, #68] + 702 0032 2022 movs r2, #32 + 703 0034 1343 orrs r3, r2 + ARM GAS /tmp/ccth6daj.s page 134 + + + 704 0036 6364 str r3, [r4, #68] +6407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 705 .loc 1 6407 9 is_stmt 1 view .LVU198 +6407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 706 .loc 1 6407 21 is_stmt 0 view .LVU199 + 707 0038 4123 movs r3, #65 + 708 003a E254 strb r2, [r4, r3] +6408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 709 .loc 1 6408 9 is_stmt 1 view .LVU200 +6408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 710 .loc 1 6408 20 is_stmt 0 view .LVU201 + 711 003c 0023 movs r3, #0 + 712 003e 2232 adds r2, r2, #34 + 713 0040 A354 strb r3, [r4, r2] +6411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 714 .loc 1 6411 9 is_stmt 1 view .LVU202 +6411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 715 .loc 1 6411 9 view .LVU203 + 716 0042 023A subs r2, r2, #2 + 717 0044 A354 strb r3, [r4, r2] +6411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 718 .loc 1 6411 9 view .LVU204 +6413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 719 .loc 1 6413 9 view .LVU205 +6413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 720 .loc 1 6413 16 is_stmt 0 view .LVU206 + 721 0046 0120 movs r0, #1 + 722 0048 00E0 b .L57 + 723 .L62: +6417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 724 .loc 1 6417 10 view .LVU207 + 725 004a 0020 movs r0, #0 + 726 .L57: +6418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 727 .loc 1 6418 1 view .LVU208 + 728 @ sp needed + 729 .LVL51: + 730 .LVL52: + 731 .LVL53: +6418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 732 .loc 1 6418 1 view .LVU209 + 733 004c 70BD pop {r4, r5, r6, pc} + 734 .LVL54: + 735 .L61: +6398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 736 .loc 1 6398 14 view .LVU210 + 737 004e 0120 movs r0, #1 + 738 0050 FCE7 b .L57 + 739 .cfi_endproc + 740 .LFE368: + 742 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 743 .align 1 + 744 .syntax unified + 745 .code 16 + 746 .thumb_func + 747 .fpu softvfp + 749 I2C_WaitOnFlagUntilTimeout: + ARM GAS /tmp/ccth6daj.s page 135 + + + 750 .LVL55: + 751 .LFB367: +6361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 752 .loc 1 6361 1 is_stmt 1 view -0 + 753 .cfi_startproc + 754 @ args = 4, pretend = 0, frame = 0 + 755 @ frame_needed = 0, uses_anonymous_args = 0 +6361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 756 .loc 1 6361 1 is_stmt 0 view .LVU212 + 757 0000 F0B5 push {r4, r5, r6, r7, lr} + 758 .LCFI4: + 759 .cfi_def_cfa_offset 20 + 760 .cfi_offset 4, -20 + 761 .cfi_offset 5, -16 + 762 .cfi_offset 6, -12 + 763 .cfi_offset 7, -8 + 764 .cfi_offset 14, -4 + 765 0002 C646 mov lr, r8 + 766 0004 00B5 push {lr} + 767 .LCFI5: + 768 .cfi_def_cfa_offset 24 + 769 .cfi_offset 8, -24 + 770 0006 0700 movs r7, r0 + 771 0008 0D00 movs r5, r1 + 772 000a 9046 mov r8, r2 + 773 000c 1E00 movs r6, r3 +6362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 774 .loc 1 6362 3 is_stmt 1 view .LVU213 + 775 .LVL56: + 776 .L65: +6362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 777 .loc 1 6362 9 view .LVU214 +6362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 778 .loc 1 6362 10 is_stmt 0 view .LVU215 + 779 000e 3B68 ldr r3, [r7] + 780 0010 9C69 ldr r4, [r3, #24] + 781 0012 2C40 ands r4, r5 + 782 0014 641B subs r4, r4, r5 + 783 0016 6342 rsbs r3, r4, #0 + 784 0018 5C41 adcs r4, r4, r3 +6362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 785 .loc 1 6362 9 view .LVU216 + 786 001a 4445 cmp r4, r8 + 787 001c 16D1 bne .L69 +6365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 788 .loc 1 6365 5 is_stmt 1 view .LVU217 +6365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 789 .loc 1 6365 8 is_stmt 0 view .LVU218 + 790 001e 731C adds r3, r6, #1 + 791 0020 F5D0 beq .L65 +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 792 .loc 1 6367 7 is_stmt 1 view .LVU219 +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 793 .loc 1 6367 13 is_stmt 0 view .LVU220 + 794 0022 FFF7FEFF bl HAL_GetTick + 795 .LVL57: +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 136 + + + 796 .loc 1 6367 27 view .LVU221 + 797 0026 069B ldr r3, [sp, #24] + 798 0028 C01A subs r0, r0, r3 +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 799 .loc 1 6367 10 view .LVU222 + 800 002a B042 cmp r0, r6 + 801 002c 01D8 bhi .L66 +6367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 802 .loc 1 6367 51 discriminator 1 view .LVU223 + 803 002e 002E cmp r6, #0 + 804 0030 EDD1 bne .L65 + 805 .L66: +6369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 806 .loc 1 6369 9 is_stmt 1 view .LVU224 +6369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 807 .loc 1 6369 25 is_stmt 0 view .LVU225 + 808 0032 7B6C ldr r3, [r7, #68] + 809 0034 2022 movs r2, #32 + 810 0036 1343 orrs r3, r2 + 811 0038 7B64 str r3, [r7, #68] +6370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 812 .loc 1 6370 9 is_stmt 1 view .LVU226 +6370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 813 .loc 1 6370 21 is_stmt 0 view .LVU227 + 814 003a 4123 movs r3, #65 + 815 003c FA54 strb r2, [r7, r3] +6371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 816 .loc 1 6371 9 is_stmt 1 view .LVU228 +6371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 817 .loc 1 6371 20 is_stmt 0 view .LVU229 + 818 003e 0023 movs r3, #0 + 819 0040 2232 adds r2, r2, #34 + 820 0042 BB54 strb r3, [r7, r2] +6374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 821 .loc 1 6374 9 is_stmt 1 view .LVU230 +6374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 822 .loc 1 6374 9 view .LVU231 + 823 0044 023A subs r2, r2, #2 + 824 0046 BB54 strb r3, [r7, r2] +6374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 825 .loc 1 6374 9 view .LVU232 +6375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 826 .loc 1 6375 9 view .LVU233 +6375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 827 .loc 1 6375 16 is_stmt 0 view .LVU234 + 828 0048 0120 movs r0, #1 + 829 004a 00E0 b .L67 + 830 .L69: +6379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 831 .loc 1 6379 10 view .LVU235 + 832 004c 0020 movs r0, #0 + 833 .L67: +6380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 834 .loc 1 6380 1 view .LVU236 + 835 @ sp needed + 836 .LVL58: + 837 .LVL59: + ARM GAS /tmp/ccth6daj.s page 137 + + + 838 .LVL60: +6380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 839 .loc 1 6380 1 view .LVU237 + 840 004e 80BC pop {r7} + 841 0050 B846 mov r8, r7 + 842 0052 F0BD pop {r4, r5, r6, r7, pc} + 843 .cfi_endproc + 844 .LFE367: + 846 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 847 .align 1 + 848 .syntax unified + 849 .code 16 + 850 .thumb_func + 851 .fpu softvfp + 853 I2C_RequestMemoryWrite: + 854 .LVL61: + 855 .LFB350: +5310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 856 .loc 1 5310 1 is_stmt 1 view -0 + 857 .cfi_startproc + 858 @ args = 8, pretend = 0, frame = 0 + 859 @ frame_needed = 0, uses_anonymous_args = 0 +5310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 860 .loc 1 5310 1 is_stmt 0 view .LVU239 + 861 0000 70B5 push {r4, r5, r6, lr} + 862 .LCFI6: + 863 .cfi_def_cfa_offset 16 + 864 .cfi_offset 4, -16 + 865 .cfi_offset 5, -12 + 866 .cfi_offset 6, -8 + 867 .cfi_offset 14, -4 + 868 0002 82B0 sub sp, sp, #8 + 869 .LCFI7: + 870 .cfi_def_cfa_offset 24 + 871 0004 0400 movs r4, r0 + 872 0006 1500 movs r5, r2 + 873 0008 1E00 movs r6, r3 +5311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 874 .loc 1 5311 3 is_stmt 1 view .LVU240 + 875 000a 8023 movs r3, #128 + 876 .LVL62: +5311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 877 .loc 1 5311 3 is_stmt 0 view .LVU241 + 878 000c F2B2 uxtb r2, r6 + 879 .LVL63: +5311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 880 .loc 1 5311 3 view .LVU242 + 881 000e 1948 ldr r0, .L78 + 882 .LVL64: +5311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 883 .loc 1 5311 3 view .LVU243 + 884 0010 0090 str r0, [sp] + 885 0012 5B04 lsls r3, r3, #17 + 886 0014 2000 movs r0, r4 + 887 0016 FFF7FEFF bl I2C_TransferConfig + 888 .LVL65: +5314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 138 + + + 889 .loc 1 5314 3 is_stmt 1 view .LVU244 +5314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 890 .loc 1 5314 7 is_stmt 0 view .LVU245 + 891 001a 079A ldr r2, [sp, #28] + 892 001c 0699 ldr r1, [sp, #24] + 893 001e 2000 movs r0, r4 + 894 0020 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 895 .LVL66: +5314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 896 .loc 1 5314 6 view .LVU246 + 897 0024 0028 cmp r0, #0 + 898 0026 1ED1 bne .L74 +5320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 899 .loc 1 5320 3 is_stmt 1 view .LVU247 +5320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 900 .loc 1 5320 6 is_stmt 0 view .LVU248 + 901 0028 012E cmp r6, #1 + 902 002a 0ED1 bne .L72 +5323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 903 .loc 1 5323 5 is_stmt 1 view .LVU249 +5323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 904 .loc 1 5323 9 is_stmt 0 view .LVU250 + 905 002c 2368 ldr r3, [r4] +5323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 906 .loc 1 5323 28 view .LVU251 + 907 002e EDB2 uxtb r5, r5 +5323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 908 .loc 1 5323 26 view .LVU252 + 909 0030 9D62 str r5, [r3, #40] + 910 .L73: +5342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 911 .loc 1 5342 3 is_stmt 1 view .LVU253 +5342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 912 .loc 1 5342 7 is_stmt 0 view .LVU254 + 913 0032 079B ldr r3, [sp, #28] + 914 0034 0093 str r3, [sp] + 915 0036 069B ldr r3, [sp, #24] + 916 0038 0022 movs r2, #0 + 917 003a 8021 movs r1, #128 + 918 003c 2000 movs r0, r4 + 919 003e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 920 .LVL67: +5342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 921 .loc 1 5342 6 view .LVU255 + 922 0042 0028 cmp r0, #0 + 923 0044 13D1 bne .L77 + 924 .L71: +5348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 925 .loc 1 5348 1 view .LVU256 + 926 0046 02B0 add sp, sp, #8 + 927 @ sp needed + 928 .LVL68: +5348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 929 .loc 1 5348 1 view .LVU257 + 930 0048 70BD pop {r4, r5, r6, pc} + 931 .LVL69: + 932 .L72: + ARM GAS /tmp/ccth6daj.s page 139 + + +5329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 933 .loc 1 5329 5 is_stmt 1 view .LVU258 +5329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 934 .loc 1 5329 9 is_stmt 0 view .LVU259 + 935 004a 2368 ldr r3, [r4] +5329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 936 .loc 1 5329 28 view .LVU260 + 937 004c 2A0A lsrs r2, r5, #8 +5329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 938 .loc 1 5329 26 view .LVU261 + 939 004e 9A62 str r2, [r3, #40] +5332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 940 .loc 1 5332 5 is_stmt 1 view .LVU262 +5332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 941 .loc 1 5332 9 is_stmt 0 view .LVU263 + 942 0050 079A ldr r2, [sp, #28] + 943 0052 0699 ldr r1, [sp, #24] + 944 0054 2000 movs r0, r4 + 945 0056 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 946 .LVL70: +5332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 947 .loc 1 5332 8 view .LVU264 + 948 005a 0028 cmp r0, #0 + 949 005c 05D1 bne .L75 +5338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 950 .loc 1 5338 5 is_stmt 1 view .LVU265 +5338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 951 .loc 1 5338 9 is_stmt 0 view .LVU266 + 952 005e 2368 ldr r3, [r4] +5338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 953 .loc 1 5338 28 view .LVU267 + 954 0060 EDB2 uxtb r5, r5 +5338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 955 .loc 1 5338 26 view .LVU268 + 956 0062 9D62 str r5, [r3, #40] + 957 0064 E5E7 b .L73 + 958 .L74: +5316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 959 .loc 1 5316 12 view .LVU269 + 960 0066 0120 movs r0, #1 + 961 0068 EDE7 b .L71 + 962 .L75: +5334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 963 .loc 1 5334 14 view .LVU270 + 964 006a 0120 movs r0, #1 + 965 006c EBE7 b .L71 + 966 .L77: +5344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 967 .loc 1 5344 12 view .LVU271 + 968 006e 0120 movs r0, #1 + 969 0070 E9E7 b .L71 + 970 .L79: + 971 0072 C046 .align 2 + 972 .L78: + 973 0074 00200080 .word -2147475456 + 974 .cfi_endproc + 975 .LFE350: + ARM GAS /tmp/ccth6daj.s page 140 + + + 977 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 978 .align 1 + 979 .syntax unified + 980 .code 16 + 981 .thumb_func + 982 .fpu softvfp + 984 I2C_RequestMemoryRead: + 985 .LVL71: + 986 .LFB351: +5365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 987 .loc 1 5365 1 is_stmt 1 view -0 + 988 .cfi_startproc + 989 @ args = 8, pretend = 0, frame = 0 + 990 @ frame_needed = 0, uses_anonymous_args = 0 +5365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 991 .loc 1 5365 1 is_stmt 0 view .LVU273 + 992 0000 70B5 push {r4, r5, r6, lr} + 993 .LCFI8: + 994 .cfi_def_cfa_offset 16 + 995 .cfi_offset 4, -16 + 996 .cfi_offset 5, -12 + 997 .cfi_offset 6, -8 + 998 .cfi_offset 14, -4 + 999 0002 82B0 sub sp, sp, #8 + 1000 .LCFI9: + 1001 .cfi_def_cfa_offset 24 + 1002 0004 0400 movs r4, r0 + 1003 0006 1500 movs r5, r2 + 1004 0008 1E00 movs r6, r3 +5366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1005 .loc 1 5366 3 is_stmt 1 view .LVU274 + 1006 000a DAB2 uxtb r2, r3 + 1007 .LVL72: +5366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1008 .loc 1 5366 3 is_stmt 0 view .LVU275 + 1009 000c 184B ldr r3, .L88 + 1010 .LVL73: +5366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1011 .loc 1 5366 3 view .LVU276 + 1012 000e 0093 str r3, [sp] + 1013 0010 0023 movs r3, #0 + 1014 0012 FFF7FEFF bl I2C_TransferConfig + 1015 .LVL74: +5369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1016 .loc 1 5369 3 is_stmt 1 view .LVU277 +5369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1017 .loc 1 5369 7 is_stmt 0 view .LVU278 + 1018 0016 079A ldr r2, [sp, #28] + 1019 0018 0699 ldr r1, [sp, #24] + 1020 001a 2000 movs r0, r4 + 1021 001c FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1022 .LVL75: +5369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1023 .loc 1 5369 6 view .LVU279 + 1024 0020 0028 cmp r0, #0 + 1025 0022 1ED1 bne .L84 +5375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 141 + + + 1026 .loc 1 5375 3 is_stmt 1 view .LVU280 +5375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1027 .loc 1 5375 6 is_stmt 0 view .LVU281 + 1028 0024 012E cmp r6, #1 + 1029 0026 0ED1 bne .L82 +5378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1030 .loc 1 5378 5 is_stmt 1 view .LVU282 +5378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1031 .loc 1 5378 9 is_stmt 0 view .LVU283 + 1032 0028 2368 ldr r3, [r4] +5378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1033 .loc 1 5378 28 view .LVU284 + 1034 002a EDB2 uxtb r5, r5 +5378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1035 .loc 1 5378 26 view .LVU285 + 1036 002c 9D62 str r5, [r3, #40] + 1037 .L83: +5397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1038 .loc 1 5397 3 is_stmt 1 view .LVU286 +5397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1039 .loc 1 5397 7 is_stmt 0 view .LVU287 + 1040 002e 079B ldr r3, [sp, #28] + 1041 0030 0093 str r3, [sp] + 1042 0032 069B ldr r3, [sp, #24] + 1043 0034 0022 movs r2, #0 + 1044 0036 4021 movs r1, #64 + 1045 0038 2000 movs r0, r4 + 1046 003a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1047 .LVL76: +5397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1048 .loc 1 5397 6 view .LVU288 + 1049 003e 0028 cmp r0, #0 + 1050 0040 13D1 bne .L87 + 1051 .L81: +5403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1052 .loc 1 5403 1 view .LVU289 + 1053 0042 02B0 add sp, sp, #8 + 1054 @ sp needed + 1055 .LVL77: +5403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1056 .loc 1 5403 1 view .LVU290 + 1057 0044 70BD pop {r4, r5, r6, pc} + 1058 .LVL78: + 1059 .L82: +5384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1060 .loc 1 5384 5 is_stmt 1 view .LVU291 +5384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1061 .loc 1 5384 9 is_stmt 0 view .LVU292 + 1062 0046 2368 ldr r3, [r4] +5384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1063 .loc 1 5384 28 view .LVU293 + 1064 0048 2A0A lsrs r2, r5, #8 +5384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1065 .loc 1 5384 26 view .LVU294 + 1066 004a 9A62 str r2, [r3, #40] +5387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1067 .loc 1 5387 5 is_stmt 1 view .LVU295 + ARM GAS /tmp/ccth6daj.s page 142 + + +5387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1068 .loc 1 5387 9 is_stmt 0 view .LVU296 + 1069 004c 079A ldr r2, [sp, #28] + 1070 004e 0699 ldr r1, [sp, #24] + 1071 0050 2000 movs r0, r4 + 1072 0052 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1073 .LVL79: +5387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1074 .loc 1 5387 8 view .LVU297 + 1075 0056 0028 cmp r0, #0 + 1076 0058 05D1 bne .L85 +5393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1077 .loc 1 5393 5 is_stmt 1 view .LVU298 +5393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1078 .loc 1 5393 9 is_stmt 0 view .LVU299 + 1079 005a 2368 ldr r3, [r4] +5393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1080 .loc 1 5393 28 view .LVU300 + 1081 005c EDB2 uxtb r5, r5 +5393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1082 .loc 1 5393 26 view .LVU301 + 1083 005e 9D62 str r5, [r3, #40] + 1084 0060 E5E7 b .L83 + 1085 .L84: +5371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1086 .loc 1 5371 12 view .LVU302 + 1087 0062 0120 movs r0, #1 + 1088 0064 EDE7 b .L81 + 1089 .L85: +5389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1090 .loc 1 5389 14 view .LVU303 + 1091 0066 0120 movs r0, #1 + 1092 0068 EBE7 b .L81 + 1093 .L87: +5399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1094 .loc 1 5399 12 view .LVU304 + 1095 006a 0120 movs r0, #1 + 1096 006c E9E7 b .L81 + 1097 .L89: + 1098 006e C046 .align 2 + 1099 .L88: + 1100 0070 00200080 .word -2147475456 + 1101 .cfi_endproc + 1102 .LFE351: + 1104 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 1105 .align 1 + 1106 .syntax unified + 1107 .code 16 + 1108 .thumb_func + 1109 .fpu softvfp + 1111 I2C_WaitOnSTOPFlagUntilTimeout: + 1112 .LVL80: + 1113 .LFB369: +6430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1114 .loc 1 6430 1 is_stmt 1 view -0 + 1115 .cfi_startproc + 1116 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccth6daj.s page 143 + + + 1117 @ frame_needed = 0, uses_anonymous_args = 0 +6430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 1118 .loc 1 6430 1 is_stmt 0 view .LVU306 + 1119 0000 70B5 push {r4, r5, r6, lr} + 1120 .LCFI10: + 1121 .cfi_def_cfa_offset 16 + 1122 .cfi_offset 4, -16 + 1123 .cfi_offset 5, -12 + 1124 .cfi_offset 6, -8 + 1125 .cfi_offset 14, -4 + 1126 0002 0500 movs r5, r0 + 1127 0004 0C00 movs r4, r1 + 1128 0006 1600 movs r6, r2 +6431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1129 .loc 1 6431 3 is_stmt 1 view .LVU307 + 1130 .LVL81: + 1131 .L91: +6431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1132 .loc 1 6431 9 view .LVU308 +6431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1133 .loc 1 6431 10 is_stmt 0 view .LVU309 + 1134 0008 2B68 ldr r3, [r5] + 1135 000a 9B69 ldr r3, [r3, #24] +6431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1136 .loc 1 6431 9 view .LVU310 + 1137 000c 9B06 lsls r3, r3, #26 + 1138 000e 1AD4 bmi .L96 +6434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1139 .loc 1 6434 5 is_stmt 1 view .LVU311 +6434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1140 .loc 1 6434 9 is_stmt 0 view .LVU312 + 1141 0010 3200 movs r2, r6 + 1142 0012 2100 movs r1, r4 + 1143 0014 2800 movs r0, r5 + 1144 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1145 .LVL82: +6434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1146 .loc 1 6434 8 view .LVU313 + 1147 001a 0028 cmp r0, #0 + 1148 001c 15D1 bne .L95 +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1149 .loc 1 6440 5 is_stmt 1 view .LVU314 +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1150 .loc 1 6440 11 is_stmt 0 view .LVU315 + 1151 001e FFF7FEFF bl HAL_GetTick + 1152 .LVL83: +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1153 .loc 1 6440 25 view .LVU316 + 1154 0022 801B subs r0, r0, r6 +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1155 .loc 1 6440 8 view .LVU317 + 1156 0024 A042 cmp r0, r4 + 1157 0026 01D8 bhi .L93 +6440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1158 .loc 1 6440 49 discriminator 1 view .LVU318 + 1159 0028 002C cmp r4, #0 + 1160 002a EDD1 bne .L91 + ARM GAS /tmp/ccth6daj.s page 144 + + + 1161 .L93: +6442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1162 .loc 1 6442 7 is_stmt 1 view .LVU319 +6442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1163 .loc 1 6442 23 is_stmt 0 view .LVU320 + 1164 002c 6B6C ldr r3, [r5, #68] + 1165 002e 2022 movs r2, #32 + 1166 0030 1343 orrs r3, r2 + 1167 0032 6B64 str r3, [r5, #68] +6443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1168 .loc 1 6443 7 is_stmt 1 view .LVU321 +6443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1169 .loc 1 6443 19 is_stmt 0 view .LVU322 + 1170 0034 4123 movs r3, #65 + 1171 0036 EA54 strb r2, [r5, r3] +6444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1172 .loc 1 6444 7 is_stmt 1 view .LVU323 +6444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1173 .loc 1 6444 18 is_stmt 0 view .LVU324 + 1174 0038 0023 movs r3, #0 + 1175 003a 2232 adds r2, r2, #34 + 1176 003c AB54 strb r3, [r5, r2] +6447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1177 .loc 1 6447 7 is_stmt 1 view .LVU325 +6447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1178 .loc 1 6447 7 view .LVU326 + 1179 003e 023A subs r2, r2, #2 + 1180 0040 AB54 strb r3, [r5, r2] +6447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1181 .loc 1 6447 7 view .LVU327 +6449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1182 .loc 1 6449 7 view .LVU328 +6449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1183 .loc 1 6449 14 is_stmt 0 view .LVU329 + 1184 0042 0120 movs r0, #1 + 1185 .L92: +6453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1186 .loc 1 6453 1 view .LVU330 + 1187 @ sp needed + 1188 .LVL84: + 1189 .LVL85: + 1190 .LVL86: +6453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1191 .loc 1 6453 1 view .LVU331 + 1192 0044 70BD pop {r4, r5, r6, pc} + 1193 .LVL87: + 1194 .L96: +6452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1195 .loc 1 6452 10 view .LVU332 + 1196 0046 0020 movs r0, #0 + 1197 0048 FCE7 b .L92 + 1198 .L95: +6436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1199 .loc 1 6436 14 view .LVU333 + 1200 004a 0120 movs r0, #1 + 1201 004c FAE7 b .L92 + 1202 .cfi_endproc + ARM GAS /tmp/ccth6daj.s page 145 + + + 1203 .LFE369: + 1205 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 1206 .align 1 + 1207 .syntax unified + 1208 .code 16 + 1209 .thumb_func + 1210 .fpu softvfp + 1212 I2C_WaitOnRXNEFlagUntilTimeout: + 1213 .LVL88: + 1214 .LFB370: +6465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1215 .loc 1 6465 1 is_stmt 1 view -0 + 1216 .cfi_startproc + 1217 @ args = 0, pretend = 0, frame = 0 + 1218 @ frame_needed = 0, uses_anonymous_args = 0 +6465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 1219 .loc 1 6465 1 is_stmt 0 view .LVU335 + 1220 0000 70B5 push {r4, r5, r6, lr} + 1221 .LCFI11: + 1222 .cfi_def_cfa_offset 16 + 1223 .cfi_offset 4, -16 + 1224 .cfi_offset 5, -12 + 1225 .cfi_offset 6, -8 + 1226 .cfi_offset 14, -4 + 1227 0002 0400 movs r4, r0 + 1228 0004 0D00 movs r5, r1 + 1229 0006 1600 movs r6, r2 +6466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1230 .loc 1 6466 3 is_stmt 1 view .LVU336 + 1231 .LVL89: + 1232 .L98: +6466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1233 .loc 1 6466 9 view .LVU337 +6466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1234 .loc 1 6466 10 is_stmt 0 view .LVU338 + 1235 0008 2368 ldr r3, [r4] + 1236 000a 9B69 ldr r3, [r3, #24] +6466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1237 .loc 1 6466 9 view .LVU339 + 1238 000c 5B07 lsls r3, r3, #29 + 1239 000e 33D4 bmi .L105 +6469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1240 .loc 1 6469 5 is_stmt 1 view .LVU340 +6469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1241 .loc 1 6469 9 is_stmt 0 view .LVU341 + 1242 0010 3200 movs r2, r6 + 1243 0012 2900 movs r1, r5 + 1244 0014 2000 movs r0, r4 + 1245 0016 FFF7FEFF bl I2C_IsAcknowledgeFailed + 1246 .LVL90: +6469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1247 .loc 1 6469 8 view .LVU342 + 1248 001a 0028 cmp r0, #0 + 1249 001c 2ED1 bne .L104 +6475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1250 .loc 1 6475 5 is_stmt 1 view .LVU343 +6475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 146 + + + 1251 .loc 1 6475 9 is_stmt 0 view .LVU344 + 1252 001e 2368 ldr r3, [r4] + 1253 0020 9A69 ldr r2, [r3, #24] +6475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1254 .loc 1 6475 8 view .LVU345 + 1255 0022 9206 lsls r2, r2, #26 + 1256 0024 11D4 bmi .L106 +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1257 .loc 1 6505 5 is_stmt 1 view .LVU346 +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1258 .loc 1 6505 11 is_stmt 0 view .LVU347 + 1259 0026 FFF7FEFF bl HAL_GetTick + 1260 .LVL91: +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1261 .loc 1 6505 25 view .LVU348 + 1262 002a 801B subs r0, r0, r6 +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1263 .loc 1 6505 8 view .LVU349 + 1264 002c A842 cmp r0, r5 + 1265 002e 01D8 bhi .L102 +6505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1266 .loc 1 6505 49 discriminator 1 view .LVU350 + 1267 0030 002D cmp r5, #0 + 1268 0032 E9D1 bne .L98 + 1269 .L102: +6507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1270 .loc 1 6507 7 is_stmt 1 view .LVU351 +6507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1271 .loc 1 6507 23 is_stmt 0 view .LVU352 + 1272 0034 636C ldr r3, [r4, #68] + 1273 0036 2022 movs r2, #32 + 1274 0038 1343 orrs r3, r2 + 1275 003a 6364 str r3, [r4, #68] +6508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1276 .loc 1 6508 7 is_stmt 1 view .LVU353 +6508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1277 .loc 1 6508 19 is_stmt 0 view .LVU354 + 1278 003c 4123 movs r3, #65 + 1279 003e E254 strb r2, [r4, r3] +6511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1280 .loc 1 6511 7 is_stmt 1 view .LVU355 +6511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1281 .loc 1 6511 7 view .LVU356 + 1282 0040 013B subs r3, r3, #1 + 1283 0042 0022 movs r2, #0 + 1284 0044 E254 strb r2, [r4, r3] +6511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1285 .loc 1 6511 7 view .LVU357 +6513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1286 .loc 1 6513 7 view .LVU358 +6513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1287 .loc 1 6513 14 is_stmt 0 view .LVU359 + 1288 0046 0120 movs r0, #1 + 1289 .L99: +6517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1290 .loc 1 6517 1 view .LVU360 + 1291 @ sp needed + ARM GAS /tmp/ccth6daj.s page 147 + + + 1292 .LVL92: + 1293 .LVL93: + 1294 .LVL94: +6517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1295 .loc 1 6517 1 view .LVU361 + 1296 0048 70BD pop {r4, r5, r6, pc} + 1297 .LVL95: + 1298 .L106: +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1299 .loc 1 6479 7 is_stmt 1 view .LVU362 +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1300 .loc 1 6479 12 is_stmt 0 view .LVU363 + 1301 004a 9A69 ldr r2, [r3, #24] +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1302 .loc 1 6479 10 view .LVU364 + 1303 004c 5207 lsls r2, r2, #29 + 1304 004e 02D5 bpl .L101 +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1305 .loc 1 6479 68 discriminator 1 view .LVU365 + 1306 0050 228D ldrh r2, [r4, #40] +6479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1307 .loc 1 6479 60 discriminator 1 view .LVU366 + 1308 0052 002A cmp r2, #0 + 1309 0054 F8D1 bne .L99 + 1310 .L101: +6488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1311 .loc 1 6488 9 is_stmt 1 view .LVU367 + 1312 0056 2022 movs r2, #32 + 1313 0058 DA61 str r2, [r3, #28] +6491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1314 .loc 1 6491 9 view .LVU368 + 1315 005a 2168 ldr r1, [r4] + 1316 005c 4B68 ldr r3, [r1, #4] + 1317 005e 0848 ldr r0, .L107 + 1318 0060 0340 ands r3, r0 + 1319 0062 4B60 str r3, [r1, #4] +6493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1320 .loc 1 6493 9 view .LVU369 +6493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1321 .loc 1 6493 25 is_stmt 0 view .LVU370 + 1322 0064 0023 movs r3, #0 + 1323 0066 6364 str r3, [r4, #68] +6494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1324 .loc 1 6494 9 is_stmt 1 view .LVU371 +6494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1325 .loc 1 6494 21 is_stmt 0 view .LVU372 + 1326 0068 4121 movs r1, #65 + 1327 006a 6254 strb r2, [r4, r1] +6495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1328 .loc 1 6495 9 is_stmt 1 view .LVU373 +6495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1329 .loc 1 6495 20 is_stmt 0 view .LVU374 + 1330 006c 2232 adds r2, r2, #34 + 1331 006e A354 strb r3, [r4, r2] +6498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1332 .loc 1 6498 9 is_stmt 1 view .LVU375 +6498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 148 + + + 1333 .loc 1 6498 9 view .LVU376 + 1334 0070 023A subs r2, r2, #2 + 1335 0072 A354 strb r3, [r4, r2] +6498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1336 .loc 1 6498 9 view .LVU377 +6500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1337 .loc 1 6500 9 view .LVU378 +6500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1338 .loc 1 6500 16 is_stmt 0 view .LVU379 + 1339 0074 0120 movs r0, #1 + 1340 0076 E7E7 b .L99 + 1341 .L105: +6516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1342 .loc 1 6516 10 view .LVU380 + 1343 0078 0020 movs r0, #0 + 1344 007a E5E7 b .L99 + 1345 .L104: +6471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1346 .loc 1 6471 14 view .LVU381 + 1347 007c 0120 movs r0, #1 + 1348 007e E3E7 b .L99 + 1349 .L108: + 1350 .align 2 + 1351 .L107: + 1352 0080 00E800FE .word -33495040 + 1353 .cfi_endproc + 1354 .LFE370: + 1356 .section .text.HAL_I2C_MspInit,"ax",%progbits + 1357 .align 1 + 1358 .weak HAL_I2C_MspInit + 1359 .syntax unified + 1360 .code 16 + 1361 .thumb_func + 1362 .fpu softvfp + 1364 HAL_I2C_MspInit: + 1365 .LVL96: + 1366 .LFB299: + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1367 .loc 1 681 1 is_stmt 1 view -0 + 1368 .cfi_startproc + 1369 @ args = 0, pretend = 0, frame = 0 + 1370 @ frame_needed = 0, uses_anonymous_args = 0 + 1371 @ link register save eliminated. + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1372 .loc 1 683 3 view .LVU383 + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1373 .loc 1 688 1 is_stmt 0 view .LVU384 + 1374 @ sp needed + 1375 0000 7047 bx lr + 1376 .cfi_endproc + 1377 .LFE299: + 1379 .section .text.HAL_I2C_Init,"ax",%progbits + 1380 .align 1 + 1381 .global HAL_I2C_Init + 1382 .syntax unified + 1383 .code 16 + 1384 .thumb_func + ARM GAS /tmp/ccth6daj.s page 149 + + + 1385 .fpu softvfp + 1387 HAL_I2C_Init: + 1388 .LVL97: + 1389 .LFB297: + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1390 .loc 1 525 1 is_stmt 1 view -0 + 1391 .cfi_startproc + 1392 @ args = 0, pretend = 0, frame = 0 + 1393 @ frame_needed = 0, uses_anonymous_args = 0 + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1394 .loc 1 525 1 is_stmt 0 view .LVU386 + 1395 0000 10B5 push {r4, lr} + 1396 .LCFI12: + 1397 .cfi_def_cfa_offset 8 + 1398 .cfi_offset 4, -8 + 1399 .cfi_offset 14, -4 + 1400 0002 041E subs r4, r0, #0 + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1401 .loc 1 527 3 is_stmt 1 view .LVU387 + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1402 .loc 1 527 6 is_stmt 0 view .LVU388 + 1403 0004 59D0 beq .L116 + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 1404 .loc 1 533 3 is_stmt 1 view .LVU389 + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 1405 .loc 1 534 3 view .LVU390 + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 1406 .loc 1 535 3 view .LVU391 + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 1407 .loc 1 536 3 view .LVU392 + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 1408 .loc 1 537 3 view .LVU393 + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 1409 .loc 1 538 3 view .LVU394 + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 1410 .loc 1 539 3 view .LVU395 + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1411 .loc 1 540 3 view .LVU396 + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1412 .loc 1 542 3 view .LVU397 + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1413 .loc 1 542 11 is_stmt 0 view .LVU398 + 1414 0006 4123 movs r3, #65 + 1415 0008 C35C ldrb r3, [r0, r3] + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1416 .loc 1 542 6 view .LVU399 + 1417 000a 002B cmp r3, #0 + 1418 000c 43D0 beq .L117 + 1419 .LVL98: + 1420 .L112: + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1421 .loc 1 573 3 is_stmt 1 view .LVU400 + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1422 .loc 1 573 15 is_stmt 0 view .LVU401 + 1423 000e 4123 movs r3, #65 + 1424 0010 2422 movs r2, #36 + 1425 0012 E254 strb r2, [r4, r3] + ARM GAS /tmp/ccth6daj.s page 150 + + + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1426 .loc 1 576 3 is_stmt 1 view .LVU402 + 1427 0014 2268 ldr r2, [r4] + 1428 0016 1368 ldr r3, [r2] + 1429 0018 0121 movs r1, #1 + 1430 001a 8B43 bics r3, r1 + 1431 001c 1360 str r3, [r2] + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1432 .loc 1 580 3 view .LVU403 + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1433 .loc 1 580 7 is_stmt 0 view .LVU404 + 1434 001e 2268 ldr r2, [r4] + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1435 .loc 1 580 47 view .LVU405 + 1436 0020 274B ldr r3, .L120 + 1437 0022 6168 ldr r1, [r4, #4] + 1438 0024 0B40 ands r3, r1 + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1439 .loc 1 580 27 view .LVU406 + 1440 0026 1361 str r3, [r2, #16] + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1441 .loc 1 584 3 is_stmt 1 view .LVU407 + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1442 .loc 1 584 7 is_stmt 0 view .LVU408 + 1443 0028 2268 ldr r2, [r4] + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1444 .loc 1 584 24 view .LVU409 + 1445 002a 9368 ldr r3, [r2, #8] + 1446 002c 2549 ldr r1, .L120+4 + 1447 002e 0B40 ands r3, r1 + 1448 0030 9360 str r3, [r2, #8] + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1449 .loc 1 587 3 is_stmt 1 view .LVU410 + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1450 .loc 1 587 6 is_stmt 0 view .LVU411 + 1451 0032 E368 ldr r3, [r4, #12] + 1452 0034 012B cmp r3, #1 + 1453 0036 34D0 beq .L118 + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1454 .loc 1 593 5 is_stmt 1 view .LVU412 + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1455 .loc 1 593 9 is_stmt 0 view .LVU413 + 1456 0038 2268 ldr r2, [r4] + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1457 .loc 1 593 63 view .LVU414 + 1458 003a 8423 movs r3, #132 + 1459 003c 1B02 lsls r3, r3, #8 + 1460 003e A168 ldr r1, [r4, #8] + 1461 0040 0B43 orrs r3, r1 + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1462 .loc 1 593 26 view .LVU415 + 1463 0042 9360 str r3, [r2, #8] + 1464 .L114: + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1465 .loc 1 598 3 is_stmt 1 view .LVU416 + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1466 .loc 1 598 6 is_stmt 0 view .LVU417 + ARM GAS /tmp/ccth6daj.s page 151 + + + 1467 0044 E368 ldr r3, [r4, #12] + 1468 0046 022B cmp r3, #2 + 1469 0048 32D0 beq .L119 + 1470 .L115: + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1471 .loc 1 603 3 is_stmt 1 view .LVU418 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1472 .loc 1 603 7 is_stmt 0 view .LVU419 + 1473 004a 2268 ldr r2, [r4] + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1474 .loc 1 603 23 view .LVU420 + 1475 004c 5168 ldr r1, [r2, #4] + 1476 004e 1E4B ldr r3, .L120+8 + 1477 0050 0B43 orrs r3, r1 + 1478 0052 5360 str r3, [r2, #4] + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1479 .loc 1 607 3 is_stmt 1 view .LVU421 + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1480 .loc 1 607 7 is_stmt 0 view .LVU422 + 1481 0054 2268 ldr r2, [r4] + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1482 .loc 1 607 24 view .LVU423 + 1483 0056 D368 ldr r3, [r2, #12] + 1484 0058 1A49 ldr r1, .L120+4 + 1485 005a 0B40 ands r3, r1 + 1486 005c D360 str r3, [r2, #12] + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1487 .loc 1 610 3 is_stmt 1 view .LVU424 + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1488 .loc 1 610 54 is_stmt 0 view .LVU425 + 1489 005e 2369 ldr r3, [r4, #16] + 1490 0060 6269 ldr r2, [r4, #20] + 1491 0062 1343 orrs r3, r2 + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1492 .loc 1 611 59 view .LVU426 + 1493 0064 A269 ldr r2, [r4, #24] + 1494 0066 1202 lsls r2, r2, #8 + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1495 .loc 1 610 7 view .LVU427 + 1496 0068 2168 ldr r1, [r4] + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1497 .loc 1 610 79 view .LVU428 + 1498 006a 1343 orrs r3, r2 + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 1499 .loc 1 610 24 view .LVU429 + 1500 006c CB60 str r3, [r1, #12] + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1501 .loc 1 615 3 is_stmt 1 view .LVU430 + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1502 .loc 1 615 7 is_stmt 0 view .LVU431 + 1503 006e 2268 ldr r2, [r4] + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1504 .loc 1 615 53 view .LVU432 + 1505 0070 E369 ldr r3, [r4, #28] + 1506 0072 216A ldr r1, [r4, #32] + 1507 0074 0B43 orrs r3, r1 + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 152 + + + 1508 .loc 1 615 23 view .LVU433 + 1509 0076 1360 str r3, [r2] + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1510 .loc 1 618 3 is_stmt 1 view .LVU434 + 1511 0078 2268 ldr r2, [r4] + 1512 007a 1368 ldr r3, [r2] + 1513 007c 0121 movs r1, #1 + 1514 007e 0B43 orrs r3, r1 + 1515 0080 1360 str r3, [r2] + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1516 .loc 1 620 3 view .LVU435 + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1517 .loc 1 620 19 is_stmt 0 view .LVU436 + 1518 0082 0023 movs r3, #0 + 1519 0084 6364 str r3, [r4, #68] + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1520 .loc 1 621 3 is_stmt 1 view .LVU437 + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1521 .loc 1 621 15 is_stmt 0 view .LVU438 + 1522 0086 4122 movs r2, #65 + 1523 0088 1F31 adds r1, r1, #31 + 1524 008a A154 strb r1, [r4, r2] + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1525 .loc 1 622 3 is_stmt 1 view .LVU439 + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1526 .loc 1 622 23 is_stmt 0 view .LVU440 + 1527 008c 2363 str r3, [r4, #48] + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1528 .loc 1 623 3 is_stmt 1 view .LVU441 + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1529 .loc 1 623 14 is_stmt 0 view .LVU442 + 1530 008e 0132 adds r2, r2, #1 + 1531 0090 A354 strb r3, [r4, r2] + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1532 .loc 1 625 3 is_stmt 1 view .LVU443 + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1533 .loc 1 625 10 is_stmt 0 view .LVU444 + 1534 0092 0020 movs r0, #0 + 1535 .L111: + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1536 .loc 1 626 1 view .LVU445 + 1537 @ sp needed + 1538 .LVL99: + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1539 .loc 1 626 1 view .LVU446 + 1540 0094 10BD pop {r4, pc} + 1541 .LVL100: + 1542 .L117: + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1543 .loc 1 545 5 is_stmt 1 view .LVU447 + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1544 .loc 1 545 16 is_stmt 0 view .LVU448 + 1545 0096 4033 adds r3, r3, #64 + 1546 0098 0022 movs r2, #0 + 1547 009a C254 strb r2, [r0, r3] + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1548 .loc 1 569 5 is_stmt 1 view .LVU449 + ARM GAS /tmp/ccth6daj.s page 153 + + + 1549 009c FFF7FEFF bl HAL_I2C_MspInit + 1550 .LVL101: + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1551 .loc 1 569 5 is_stmt 0 view .LVU450 + 1552 00a0 B5E7 b .L112 + 1553 .L118: + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1554 .loc 1 589 5 is_stmt 1 view .LVU451 + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1555 .loc 1 589 9 is_stmt 0 view .LVU452 + 1556 00a2 2268 ldr r2, [r4] + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1557 .loc 1 589 44 view .LVU453 + 1558 00a4 8023 movs r3, #128 + 1559 00a6 1B02 lsls r3, r3, #8 + 1560 00a8 A168 ldr r1, [r4, #8] + 1561 00aa 0B43 orrs r3, r1 + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1562 .loc 1 589 26 view .LVU454 + 1563 00ac 9360 str r3, [r2, #8] + 1564 00ae C9E7 b .L114 + 1565 .L119: + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1566 .loc 1 600 5 is_stmt 1 view .LVU455 + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1567 .loc 1 600 9 is_stmt 0 view .LVU456 + 1568 00b0 2368 ldr r3, [r4] + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1569 .loc 1 600 25 view .LVU457 + 1570 00b2 8022 movs r2, #128 + 1571 00b4 1201 lsls r2, r2, #4 + 1572 00b6 5A60 str r2, [r3, #4] + 1573 00b8 C7E7 b .L115 + 1574 .LVL102: + 1575 .L116: + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1576 .loc 1 529 12 view .LVU458 + 1577 00ba 0120 movs r0, #1 + 1578 .LVL103: + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1579 .loc 1 529 12 view .LVU459 + 1580 00bc EAE7 b .L111 + 1581 .L121: + 1582 00be C046 .align 2 + 1583 .L120: + 1584 00c0 FFFFFFF0 .word -251658241 + 1585 00c4 FF7FFFFF .word -32769 + 1586 00c8 00800002 .word 33587200 + 1587 .cfi_endproc + 1588 .LFE297: + 1590 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 1591 .align 1 + 1592 .weak HAL_I2C_MspDeInit + 1593 .syntax unified + 1594 .code 16 + 1595 .thumb_func + 1596 .fpu softvfp + ARM GAS /tmp/ccth6daj.s page 154 + + + 1598 HAL_I2C_MspDeInit: + 1599 .LVL104: + 1600 .LFB300: + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 1601 .loc 1 697 1 is_stmt 1 view -0 + 1602 .cfi_startproc + 1603 @ args = 0, pretend = 0, frame = 0 + 1604 @ frame_needed = 0, uses_anonymous_args = 0 + 1605 @ link register save eliminated. + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1606 .loc 1 699 3 view .LVU461 + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1607 .loc 1 704 1 is_stmt 0 view .LVU462 + 1608 @ sp needed + 1609 0000 7047 bx lr + 1610 .cfi_endproc + 1611 .LFE300: + 1613 .section .text.HAL_I2C_DeInit,"ax",%progbits + 1614 .align 1 + 1615 .global HAL_I2C_DeInit + 1616 .syntax unified + 1617 .code 16 + 1618 .thumb_func + 1619 .fpu softvfp + 1621 HAL_I2C_DeInit: + 1622 .LVL105: + 1623 .LFB298: + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1624 .loc 1 635 1 is_stmt 1 view -0 + 1625 .cfi_startproc + 1626 @ args = 0, pretend = 0, frame = 0 + 1627 @ frame_needed = 0, uses_anonymous_args = 0 + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 1628 .loc 1 635 1 is_stmt 0 view .LVU464 + 1629 0000 70B5 push {r4, r5, r6, lr} + 1630 .LCFI13: + 1631 .cfi_def_cfa_offset 16 + 1632 .cfi_offset 4, -16 + 1633 .cfi_offset 5, -12 + 1634 .cfi_offset 6, -8 + 1635 .cfi_offset 14, -4 + 1636 0002 041E subs r4, r0, #0 + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1637 .loc 1 637 3 is_stmt 1 view .LVU465 + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1638 .loc 1 637 6 is_stmt 0 view .LVU466 + 1639 0004 13D0 beq .L125 + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1640 .loc 1 643 3 is_stmt 1 view .LVU467 + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1641 .loc 1 645 3 view .LVU468 + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1642 .loc 1 645 15 is_stmt 0 view .LVU469 + 1643 0006 4125 movs r5, #65 + 1644 0008 2423 movs r3, #36 + 1645 000a 4355 strb r3, [r0, r5] + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 155 + + + 1646 .loc 1 648 3 is_stmt 1 view .LVU470 + 1647 000c 0268 ldr r2, [r0] + 1648 000e 1368 ldr r3, [r2] + 1649 0010 0121 movs r1, #1 + 1650 0012 8B43 bics r3, r1 + 1651 0014 1360 str r3, [r2] + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 1652 .loc 1 660 3 view .LVU471 + 1653 0016 FFF7FEFF bl HAL_I2C_MspDeInit + 1654 .LVL106: + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1655 .loc 1 663 3 view .LVU472 + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 1656 .loc 1 663 19 is_stmt 0 view .LVU473 + 1657 001a 0023 movs r3, #0 + 1658 001c 6364 str r3, [r4, #68] + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1659 .loc 1 664 3 is_stmt 1 view .LVU474 + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 1660 .loc 1 664 15 is_stmt 0 view .LVU475 + 1661 001e 6355 strb r3, [r4, r5] + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1662 .loc 1 665 3 is_stmt 1 view .LVU476 + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1663 .loc 1 665 23 is_stmt 0 view .LVU477 + 1664 0020 2363 str r3, [r4, #48] + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1665 .loc 1 666 3 is_stmt 1 view .LVU478 + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1666 .loc 1 666 14 is_stmt 0 view .LVU479 + 1667 0022 4222 movs r2, #66 + 1668 0024 A354 strb r3, [r4, r2] + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1669 .loc 1 669 3 is_stmt 1 view .LVU480 + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1670 .loc 1 669 3 view .LVU481 + 1671 0026 023A subs r2, r2, #2 + 1672 0028 A354 strb r3, [r4, r2] + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1673 .loc 1 669 3 view .LVU482 + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1674 .loc 1 671 3 view .LVU483 + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1675 .loc 1 671 10 is_stmt 0 view .LVU484 + 1676 002a 0020 movs r0, #0 + 1677 .L124: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1678 .loc 1 672 1 view .LVU485 + 1679 @ sp needed + 1680 .LVL107: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1681 .loc 1 672 1 view .LVU486 + 1682 002c 70BD pop {r4, r5, r6, pc} + 1683 .LVL108: + 1684 .L125: + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1685 .loc 1 639 12 view .LVU487 + ARM GAS /tmp/ccth6daj.s page 156 + + + 1686 002e 0120 movs r0, #1 + 1687 .LVL109: + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1688 .loc 1 639 12 view .LVU488 + 1689 0030 FCE7 b .L124 + 1690 .cfi_endproc + 1691 .LFE298: + 1693 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 1694 .align 1 + 1695 .global HAL_I2C_Master_Transmit + 1696 .syntax unified + 1697 .code 16 + 1698 .thumb_func + 1699 .fpu softvfp + 1701 HAL_I2C_Master_Transmit: + 1702 .LVL110: + 1703 .LFB301: +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 1704 .loc 1 1119 1 is_stmt 1 view -0 + 1705 .cfi_startproc + 1706 @ args = 4, pretend = 0, frame = 8 + 1707 @ frame_needed = 0, uses_anonymous_args = 0 +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 1708 .loc 1 1119 1 is_stmt 0 view .LVU490 + 1709 0000 F0B5 push {r4, r5, r6, r7, lr} + 1710 .LCFI14: + 1711 .cfi_def_cfa_offset 20 + 1712 .cfi_offset 4, -20 + 1713 .cfi_offset 5, -16 + 1714 .cfi_offset 6, -12 + 1715 .cfi_offset 7, -8 + 1716 .cfi_offset 14, -4 + 1717 0002 85B0 sub sp, sp, #20 + 1718 .LCFI15: + 1719 .cfi_def_cfa_offset 40 + 1720 0004 0400 movs r4, r0 + 1721 0006 0F00 movs r7, r1 + 1722 0008 0292 str r2, [sp, #8] + 1723 000a 0393 str r3, [sp, #12] + 1724 000c 0A9D ldr r5, [sp, #40] +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1725 .loc 1 1120 3 is_stmt 1 view .LVU491 +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1726 .loc 1 1122 3 view .LVU492 +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1727 .loc 1 1122 11 is_stmt 0 view .LVU493 + 1728 000e 4123 movs r3, #65 + 1729 .LVL111: +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1730 .loc 1 1122 11 view .LVU494 + 1731 0010 C35C ldrb r3, [r0, r3] +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1732 .loc 1 1122 6 view .LVU495 + 1733 0012 202B cmp r3, #32 + 1734 0014 00D0 beq .LCB1624 + 1735 0016 9BE0 b .L134 @long jump + 1736 .LCB1624: + ARM GAS /tmp/ccth6daj.s page 157 + + +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1737 .loc 1 1125 5 is_stmt 1 view .LVU496 +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1738 .loc 1 1125 5 view .LVU497 + 1739 0018 2033 adds r3, r3, #32 + 1740 001a C35C ldrb r3, [r0, r3] + 1741 001c 012B cmp r3, #1 + 1742 001e 00D1 bne .LCB1630 + 1743 0020 99E0 b .L135 @long jump + 1744 .LCB1630: +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1745 .loc 1 1125 5 discriminator 2 view .LVU498 + 1746 0022 4023 movs r3, #64 + 1747 0024 0122 movs r2, #1 + 1748 .LVL112: +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1749 .loc 1 1125 5 is_stmt 0 discriminator 2 view .LVU499 + 1750 0026 C254 strb r2, [r0, r3] +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1751 .loc 1 1125 5 is_stmt 1 discriminator 2 view .LVU500 +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1752 .loc 1 1128 5 discriminator 2 view .LVU501 +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1753 .loc 1 1128 17 is_stmt 0 discriminator 2 view .LVU502 + 1754 0028 FFF7FEFF bl HAL_GetTick + 1755 .LVL113: +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1756 .loc 1 1128 17 discriminator 2 view .LVU503 + 1757 002c 0600 movs r6, r0 + 1758 .LVL114: +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1759 .loc 1 1130 5 is_stmt 1 discriminator 2 view .LVU504 +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1760 .loc 1 1130 9 is_stmt 0 discriminator 2 view .LVU505 + 1761 002e 8021 movs r1, #128 + 1762 0030 0090 str r0, [sp] + 1763 0032 1923 movs r3, #25 + 1764 0034 0122 movs r2, #1 + 1765 0036 0902 lsls r1, r1, #8 + 1766 0038 2000 movs r0, r4 + 1767 .LVL115: +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1768 .loc 1 1130 9 discriminator 2 view .LVU506 + 1769 003a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1770 .LVL116: +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1771 .loc 1 1130 8 discriminator 2 view .LVU507 + 1772 003e 0028 cmp r0, #0 + 1773 0040 00D0 beq .LCB1654 + 1774 0042 8AE0 b .L136 @long jump + 1775 .LCB1654: +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1776 .loc 1 1135 5 is_stmt 1 view .LVU508 +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1777 .loc 1 1135 21 is_stmt 0 view .LVU509 + 1778 0044 4123 movs r3, #65 + 1779 0046 2122 movs r2, #33 + ARM GAS /tmp/ccth6daj.s page 158 + + + 1780 0048 E254 strb r2, [r4, r3] +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1781 .loc 1 1136 5 is_stmt 1 view .LVU510 +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1782 .loc 1 1136 21 is_stmt 0 view .LVU511 + 1783 004a 0133 adds r3, r3, #1 + 1784 004c 113A subs r2, r2, #17 + 1785 004e E254 strb r2, [r4, r3] +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1786 .loc 1 1137 5 is_stmt 1 view .LVU512 +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1787 .loc 1 1137 21 is_stmt 0 view .LVU513 + 1788 0050 0023 movs r3, #0 + 1789 0052 6364 str r3, [r4, #68] +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 1790 .loc 1 1140 5 is_stmt 1 view .LVU514 +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 1791 .loc 1 1140 21 is_stmt 0 view .LVU515 + 1792 0054 029A ldr r2, [sp, #8] + 1793 0056 6262 str r2, [r4, #36] +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1794 .loc 1 1141 5 is_stmt 1 view .LVU516 +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1795 .loc 1 1141 21 is_stmt 0 view .LVU517 + 1796 0058 039A ldr r2, [sp, #12] + 1797 005a 6285 strh r2, [r4, #42] +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1798 .loc 1 1142 5 is_stmt 1 view .LVU518 +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1799 .loc 1 1142 21 is_stmt 0 view .LVU519 + 1800 005c 6363 str r3, [r4, #52] +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1801 .loc 1 1146 5 is_stmt 1 view .LVU520 +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1802 .loc 1 1146 13 is_stmt 0 view .LVU521 + 1803 005e 638D ldrh r3, [r4, #42] + 1804 0060 9BB2 uxth r3, r3 +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1805 .loc 1 1146 8 view .LVU522 + 1806 0062 FF2B cmp r3, #255 + 1807 0064 0BD9 bls .L128 +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1808 .loc 1 1148 7 is_stmt 1 view .LVU523 +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1809 .loc 1 1148 22 is_stmt 0 view .LVU524 + 1810 0066 FF23 movs r3, #255 + 1811 0068 2385 strh r3, [r4, #40] +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1812 .loc 1 1149 7 is_stmt 1 view .LVU525 + 1813 006a 7F3B subs r3, r3, #127 + 1814 006c 3F4A ldr r2, .L141 + 1815 006e 0092 str r2, [sp] + 1816 0070 5B04 lsls r3, r3, #17 + 1817 0072 FF22 movs r2, #255 + 1818 0074 3900 movs r1, r7 + 1819 0076 2000 movs r0, r4 + 1820 0078 FFF7FEFF bl I2C_TransferConfig + ARM GAS /tmp/ccth6daj.s page 159 + + + 1821 .LVL117: + 1822 007c 18E0 b .L130 + 1823 .L128: +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1824 .loc 1 1154 7 view .LVU526 +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1825 .loc 1 1154 28 is_stmt 0 view .LVU527 + 1826 007e 628D ldrh r2, [r4, #42] + 1827 0080 92B2 uxth r2, r2 +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1828 .loc 1 1154 22 view .LVU528 + 1829 0082 2285 strh r2, [r4, #40] +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 1830 .loc 1 1155 7 is_stmt 1 view .LVU529 + 1831 0084 8023 movs r3, #128 + 1832 0086 D2B2 uxtb r2, r2 + 1833 0088 3849 ldr r1, .L141 + 1834 008a 0091 str r1, [sp] + 1835 008c 9B04 lsls r3, r3, #18 + 1836 008e 3900 movs r1, r7 + 1837 0090 2000 movs r0, r4 + 1838 0092 FFF7FEFF bl I2C_TransferConfig + 1839 .LVL118: + 1840 0096 0BE0 b .L130 + 1841 .L132: +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1842 .loc 1 1191 11 view .LVU530 +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1843 .loc 1 1191 32 is_stmt 0 view .LVU531 + 1844 0098 628D ldrh r2, [r4, #42] + 1845 009a 92B2 uxth r2, r2 +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 1846 .loc 1 1191 26 view .LVU532 + 1847 009c 2285 strh r2, [r4, #40] +1192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 1848 .loc 1 1192 11 is_stmt 1 view .LVU533 + 1849 009e 8023 movs r3, #128 + 1850 00a0 D2B2 uxtb r2, r2 + 1851 00a2 0021 movs r1, #0 + 1852 00a4 0091 str r1, [sp] + 1853 00a6 9B04 lsls r3, r3, #18 + 1854 00a8 3900 movs r1, r7 + 1855 00aa 2000 movs r0, r4 + 1856 00ac FFF7FEFF bl I2C_TransferConfig + 1857 .LVL119: + 1858 .L130: +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1859 .loc 1 1159 11 view .LVU534 +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1860 .loc 1 1159 16 is_stmt 0 view .LVU535 + 1861 00b0 638D ldrh r3, [r4, #42] + 1862 00b2 9BB2 uxth r3, r3 +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1863 .loc 1 1159 11 view .LVU536 + 1864 00b4 002B cmp r3, #0 + 1865 00b6 34D0 beq .L140 +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 160 + + + 1866 .loc 1 1162 7 is_stmt 1 view .LVU537 +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1867 .loc 1 1162 11 is_stmt 0 view .LVU538 + 1868 00b8 3200 movs r2, r6 + 1869 00ba 2900 movs r1, r5 + 1870 00bc 2000 movs r0, r4 + 1871 00be FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1872 .LVL120: +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1873 .loc 1 1162 10 view .LVU539 + 1874 00c2 0028 cmp r0, #0 + 1875 00c4 4BD1 bne .L137 +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1876 .loc 1 1167 7 is_stmt 1 view .LVU540 +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1877 .loc 1 1167 11 is_stmt 0 view .LVU541 + 1878 00c6 2368 ldr r3, [r4] +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1879 .loc 1 1167 30 view .LVU542 + 1880 00c8 626A ldr r2, [r4, #36] + 1881 00ca 1278 ldrb r2, [r2] +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1882 .loc 1 1167 28 view .LVU543 + 1883 00cc 9A62 str r2, [r3, #40] +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1884 .loc 1 1170 7 is_stmt 1 view .LVU544 +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1885 .loc 1 1170 21 is_stmt 0 view .LVU545 + 1886 00ce 636A ldr r3, [r4, #36] + 1887 00d0 0133 adds r3, r3, #1 + 1888 00d2 6362 str r3, [r4, #36] +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 1889 .loc 1 1172 7 is_stmt 1 view .LVU546 +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 1890 .loc 1 1172 11 is_stmt 0 view .LVU547 + 1891 00d4 638D ldrh r3, [r4, #42] +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 1892 .loc 1 1172 22 view .LVU548 + 1893 00d6 013B subs r3, r3, #1 + 1894 00d8 9BB2 uxth r3, r3 + 1895 00da 6385 strh r3, [r4, #42] +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1896 .loc 1 1173 7 is_stmt 1 view .LVU549 +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1897 .loc 1 1173 11 is_stmt 0 view .LVU550 + 1898 00dc 238D ldrh r3, [r4, #40] +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1899 .loc 1 1173 21 view .LVU551 + 1900 00de 013B subs r3, r3, #1 + 1901 00e0 9BB2 uxth r3, r3 + 1902 00e2 2385 strh r3, [r4, #40] +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1903 .loc 1 1175 7 is_stmt 1 view .LVU552 +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1904 .loc 1 1175 16 is_stmt 0 view .LVU553 + 1905 00e4 628D ldrh r2, [r4, #42] + 1906 00e6 92B2 uxth r2, r2 + ARM GAS /tmp/ccth6daj.s page 161 + + +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1907 .loc 1 1175 10 view .LVU554 + 1908 00e8 002A cmp r2, #0 + 1909 00ea E1D0 beq .L130 +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1910 .loc 1 1175 35 discriminator 1 view .LVU555 + 1911 00ec 002B cmp r3, #0 + 1912 00ee DFD1 bne .L130 +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1913 .loc 1 1178 9 is_stmt 1 view .LVU556 +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1914 .loc 1 1178 13 is_stmt 0 view .LVU557 + 1915 00f0 0096 str r6, [sp] + 1916 00f2 2B00 movs r3, r5 + 1917 00f4 0022 movs r2, #0 + 1918 00f6 8021 movs r1, #128 + 1919 00f8 2000 movs r0, r4 + 1920 00fa FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1921 .LVL121: +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1922 .loc 1 1178 12 view .LVU558 + 1923 00fe 0028 cmp r0, #0 + 1924 0100 2FD1 bne .L138 +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1925 .loc 1 1183 9 is_stmt 1 view .LVU559 +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1926 .loc 1 1183 17 is_stmt 0 view .LVU560 + 1927 0102 638D ldrh r3, [r4, #42] + 1928 0104 9BB2 uxth r3, r3 +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1929 .loc 1 1183 12 view .LVU561 + 1930 0106 FF2B cmp r3, #255 + 1931 0108 C6D9 bls .L132 +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1932 .loc 1 1185 11 is_stmt 1 view .LVU562 +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 1933 .loc 1 1185 26 is_stmt 0 view .LVU563 + 1934 010a FF23 movs r3, #255 + 1935 010c 2385 strh r3, [r4, #40] +1186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 1936 .loc 1 1186 11 is_stmt 1 view .LVU564 + 1937 010e 7F3B subs r3, r3, #127 + 1938 0110 0022 movs r2, #0 + 1939 0112 0092 str r2, [sp] + 1940 0114 5B04 lsls r3, r3, #17 + 1941 0116 FF32 adds r2, r2, #255 + 1942 0118 3900 movs r1, r7 + 1943 011a 2000 movs r0, r4 + 1944 011c FFF7FEFF bl I2C_TransferConfig + 1945 .LVL122: + 1946 0120 C6E7 b .L130 + 1947 .L140: +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1948 .loc 1 1200 5 view .LVU565 +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1949 .loc 1 1200 9 is_stmt 0 view .LVU566 + 1950 0122 3200 movs r2, r6 + ARM GAS /tmp/ccth6daj.s page 162 + + + 1951 0124 2900 movs r1, r5 + 1952 0126 2000 movs r0, r4 + 1953 0128 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1954 .LVL123: +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 1955 .loc 1 1200 8 view .LVU567 + 1956 012c 0028 cmp r0, #0 + 1957 012e 1AD1 bne .L139 +1206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1958 .loc 1 1206 5 is_stmt 1 view .LVU568 + 1959 0130 2368 ldr r3, [r4] + 1960 0132 2022 movs r2, #32 + 1961 0134 DA61 str r2, [r3, #28] +1209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1962 .loc 1 1209 5 view .LVU569 + 1963 0136 2168 ldr r1, [r4] + 1964 0138 4B68 ldr r3, [r1, #4] + 1965 013a 0D4D ldr r5, .L141+4 + 1966 013c 2B40 ands r3, r5 + 1967 013e 4B60 str r3, [r1, #4] +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1968 .loc 1 1211 5 view .LVU570 +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1969 .loc 1 1211 17 is_stmt 0 view .LVU571 + 1970 0140 4123 movs r3, #65 + 1971 0142 E254 strb r2, [r4, r3] +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1972 .loc 1 1212 5 is_stmt 1 view .LVU572 +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1973 .loc 1 1212 17 is_stmt 0 view .LVU573 + 1974 0144 0023 movs r3, #0 + 1975 0146 2232 adds r2, r2, #34 + 1976 0148 A354 strb r3, [r4, r2] +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1977 .loc 1 1215 5 is_stmt 1 view .LVU574 +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1978 .loc 1 1215 5 view .LVU575 + 1979 014a 023A subs r2, r2, #2 + 1980 014c A354 strb r3, [r4, r2] +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1981 .loc 1 1215 5 view .LVU576 +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1982 .loc 1 1217 5 view .LVU577 +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1983 .loc 1 1217 12 is_stmt 0 view .LVU578 + 1984 014e 00E0 b .L127 + 1985 .LVL124: + 1986 .L134: +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 1987 .loc 1 1221 12 view .LVU579 + 1988 0150 0220 movs r0, #2 + 1989 .LVL125: + 1990 .L127: +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1991 .loc 1 1223 1 view .LVU580 + 1992 0152 05B0 add sp, sp, #20 + 1993 @ sp needed + ARM GAS /tmp/ccth6daj.s page 163 + + + 1994 .LVL126: +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1995 .loc 1 1223 1 view .LVU581 + 1996 0154 F0BD pop {r4, r5, r6, r7, pc} + 1997 .LVL127: + 1998 .L135: +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 1999 .loc 1 1125 5 view .LVU582 + 2000 0156 0220 movs r0, #2 + 2001 .LVL128: +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2002 .loc 1 1125 5 view .LVU583 + 2003 0158 FBE7 b .L127 + 2004 .LVL129: + 2005 .L136: +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2006 .loc 1 1132 14 view .LVU584 + 2007 015a 0120 movs r0, #1 + 2008 015c F9E7 b .L127 + 2009 .L137: +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2010 .loc 1 1164 16 view .LVU585 + 2011 015e 0120 movs r0, #1 + 2012 0160 F7E7 b .L127 + 2013 .L138: +1180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2014 .loc 1 1180 18 view .LVU586 + 2015 0162 0120 movs r0, #1 + 2016 0164 F5E7 b .L127 + 2017 .L139: +1202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2018 .loc 1 1202 14 view .LVU587 + 2019 0166 0120 movs r0, #1 + 2020 0168 F3E7 b .L127 + 2021 .L142: + 2022 016a C046 .align 2 + 2023 .L141: + 2024 016c 00200080 .word -2147475456 + 2025 0170 00E800FE .word -33495040 + 2026 .cfi_endproc + 2027 .LFE301: + 2029 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 2030 .align 1 + 2031 .global HAL_I2C_Master_Receive + 2032 .syntax unified + 2033 .code 16 + 2034 .thumb_func + 2035 .fpu softvfp + 2037 HAL_I2C_Master_Receive: + 2038 .LVL130: + 2039 .LFB302: +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 2040 .loc 1 1238 1 is_stmt 1 view -0 + 2041 .cfi_startproc + 2042 @ args = 4, pretend = 0, frame = 8 + 2043 @ frame_needed = 0, uses_anonymous_args = 0 +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + ARM GAS /tmp/ccth6daj.s page 164 + + + 2044 .loc 1 1238 1 is_stmt 0 view .LVU589 + 2045 0000 F0B5 push {r4, r5, r6, r7, lr} + 2046 .LCFI16: + 2047 .cfi_def_cfa_offset 20 + 2048 .cfi_offset 4, -20 + 2049 .cfi_offset 5, -16 + 2050 .cfi_offset 6, -12 + 2051 .cfi_offset 7, -8 + 2052 .cfi_offset 14, -4 + 2053 0002 85B0 sub sp, sp, #20 + 2054 .LCFI17: + 2055 .cfi_def_cfa_offset 40 + 2056 0004 0400 movs r4, r0 + 2057 0006 0F00 movs r7, r1 + 2058 0008 0292 str r2, [sp, #8] + 2059 000a 0393 str r3, [sp, #12] + 2060 000c 0A9D ldr r5, [sp, #40] +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2061 .loc 1 1239 3 is_stmt 1 view .LVU590 +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2062 .loc 1 1241 3 view .LVU591 +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2063 .loc 1 1241 11 is_stmt 0 view .LVU592 + 2064 000e 4123 movs r3, #65 + 2065 .LVL131: +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2066 .loc 1 1241 11 view .LVU593 + 2067 0010 C35C ldrb r3, [r0, r3] +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2068 .loc 1 1241 6 view .LVU594 + 2069 0012 202B cmp r3, #32 + 2070 0014 00D0 beq .LCB1945 + 2071 0016 9BE0 b .L151 @long jump + 2072 .LCB1945: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2073 .loc 1 1244 5 is_stmt 1 view .LVU595 +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2074 .loc 1 1244 5 view .LVU596 + 2075 0018 2033 adds r3, r3, #32 + 2076 001a C35C ldrb r3, [r0, r3] + 2077 001c 012B cmp r3, #1 + 2078 001e 00D1 bne .LCB1951 + 2079 0020 99E0 b .L152 @long jump + 2080 .LCB1951: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2081 .loc 1 1244 5 discriminator 2 view .LVU597 + 2082 0022 4023 movs r3, #64 + 2083 0024 0122 movs r2, #1 + 2084 .LVL132: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2085 .loc 1 1244 5 is_stmt 0 discriminator 2 view .LVU598 + 2086 0026 C254 strb r2, [r0, r3] +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2087 .loc 1 1244 5 is_stmt 1 discriminator 2 view .LVU599 +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2088 .loc 1 1247 5 discriminator 2 view .LVU600 +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 165 + + + 2089 .loc 1 1247 17 is_stmt 0 discriminator 2 view .LVU601 + 2090 0028 FFF7FEFF bl HAL_GetTick + 2091 .LVL133: +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2092 .loc 1 1247 17 discriminator 2 view .LVU602 + 2093 002c 0600 movs r6, r0 + 2094 .LVL134: +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2095 .loc 1 1249 5 is_stmt 1 discriminator 2 view .LVU603 +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2096 .loc 1 1249 9 is_stmt 0 discriminator 2 view .LVU604 + 2097 002e 8021 movs r1, #128 + 2098 0030 0090 str r0, [sp] + 2099 0032 1923 movs r3, #25 + 2100 0034 0122 movs r2, #1 + 2101 0036 0902 lsls r1, r1, #8 + 2102 0038 2000 movs r0, r4 + 2103 .LVL135: +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2104 .loc 1 1249 9 discriminator 2 view .LVU605 + 2105 003a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2106 .LVL136: +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2107 .loc 1 1249 8 discriminator 2 view .LVU606 + 2108 003e 0028 cmp r0, #0 + 2109 0040 00D0 beq .LCB1975 + 2110 0042 8AE0 b .L153 @long jump + 2111 .LCB1975: +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2112 .loc 1 1254 5 is_stmt 1 view .LVU607 +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2113 .loc 1 1254 21 is_stmt 0 view .LVU608 + 2114 0044 4123 movs r3, #65 + 2115 0046 2222 movs r2, #34 + 2116 0048 E254 strb r2, [r4, r3] +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2117 .loc 1 1255 5 is_stmt 1 view .LVU609 +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2118 .loc 1 1255 21 is_stmt 0 view .LVU610 + 2119 004a 0133 adds r3, r3, #1 + 2120 004c 123A subs r2, r2, #18 + 2121 004e E254 strb r2, [r4, r3] +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2122 .loc 1 1256 5 is_stmt 1 view .LVU611 +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2123 .loc 1 1256 21 is_stmt 0 view .LVU612 + 2124 0050 0023 movs r3, #0 + 2125 0052 6364 str r3, [r4, #68] +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2126 .loc 1 1259 5 is_stmt 1 view .LVU613 +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2127 .loc 1 1259 21 is_stmt 0 view .LVU614 + 2128 0054 029A ldr r2, [sp, #8] + 2129 0056 6262 str r2, [r4, #36] +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2130 .loc 1 1260 5 is_stmt 1 view .LVU615 +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + ARM GAS /tmp/ccth6daj.s page 166 + + + 2131 .loc 1 1260 21 is_stmt 0 view .LVU616 + 2132 0058 039A ldr r2, [sp, #12] + 2133 005a 6285 strh r2, [r4, #42] +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2134 .loc 1 1261 5 is_stmt 1 view .LVU617 +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2135 .loc 1 1261 21 is_stmt 0 view .LVU618 + 2136 005c 6363 str r3, [r4, #52] +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2137 .loc 1 1265 5 is_stmt 1 view .LVU619 +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2138 .loc 1 1265 13 is_stmt 0 view .LVU620 + 2139 005e 638D ldrh r3, [r4, #42] + 2140 0060 9BB2 uxth r3, r3 +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2141 .loc 1 1265 8 view .LVU621 + 2142 0062 FF2B cmp r3, #255 + 2143 0064 0BD9 bls .L145 +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2144 .loc 1 1267 7 is_stmt 1 view .LVU622 +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2145 .loc 1 1267 22 is_stmt 0 view .LVU623 + 2146 0066 FF23 movs r3, #255 + 2147 0068 2385 strh r3, [r4, #40] +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 2148 .loc 1 1268 7 is_stmt 1 view .LVU624 + 2149 006a 7F3B subs r3, r3, #127 + 2150 006c 3F4A ldr r2, .L158 + 2151 006e 0092 str r2, [sp] + 2152 0070 5B04 lsls r3, r3, #17 + 2153 0072 FF22 movs r2, #255 + 2154 0074 3900 movs r1, r7 + 2155 0076 2000 movs r0, r4 + 2156 0078 FFF7FEFF bl I2C_TransferConfig + 2157 .LVL137: + 2158 007c 18E0 b .L147 + 2159 .L145: +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2160 .loc 1 1273 7 view .LVU625 +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2161 .loc 1 1273 28 is_stmt 0 view .LVU626 + 2162 007e 628D ldrh r2, [r4, #42] + 2163 0080 92B2 uxth r2, r2 +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2164 .loc 1 1273 22 view .LVU627 + 2165 0082 2285 strh r2, [r4, #40] +1274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 2166 .loc 1 1274 7 is_stmt 1 view .LVU628 + 2167 0084 8023 movs r3, #128 + 2168 0086 D2B2 uxtb r2, r2 + 2169 0088 3849 ldr r1, .L158 + 2170 008a 0091 str r1, [sp] + 2171 008c 9B04 lsls r3, r3, #18 + 2172 008e 3900 movs r1, r7 + 2173 0090 2000 movs r0, r4 + 2174 0092 FFF7FEFF bl I2C_TransferConfig + 2175 .LVL138: + ARM GAS /tmp/ccth6daj.s page 167 + + + 2176 0096 0BE0 b .L147 + 2177 .L149: +1311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2178 .loc 1 1311 11 view .LVU629 +1311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2179 .loc 1 1311 32 is_stmt 0 view .LVU630 + 2180 0098 628D ldrh r2, [r4, #42] + 2181 009a 92B2 uxth r2, r2 +1311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2182 .loc 1 1311 26 view .LVU631 + 2183 009c 2285 strh r2, [r4, #40] +1312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2184 .loc 1 1312 11 is_stmt 1 view .LVU632 + 2185 009e 8023 movs r3, #128 + 2186 00a0 D2B2 uxtb r2, r2 + 2187 00a2 0021 movs r1, #0 + 2188 00a4 0091 str r1, [sp] + 2189 00a6 9B04 lsls r3, r3, #18 + 2190 00a8 3900 movs r1, r7 + 2191 00aa 2000 movs r0, r4 + 2192 00ac FFF7FEFF bl I2C_TransferConfig + 2193 .LVL139: + 2194 .L147: +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2195 .loc 1 1278 11 view .LVU633 +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2196 .loc 1 1278 16 is_stmt 0 view .LVU634 + 2197 00b0 638D ldrh r3, [r4, #42] + 2198 00b2 9BB2 uxth r3, r3 +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2199 .loc 1 1278 11 view .LVU635 + 2200 00b4 002B cmp r3, #0 + 2201 00b6 34D0 beq .L157 +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2202 .loc 1 1281 7 is_stmt 1 view .LVU636 +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2203 .loc 1 1281 11 is_stmt 0 view .LVU637 + 2204 00b8 3200 movs r2, r6 + 2205 00ba 2900 movs r1, r5 + 2206 00bc 2000 movs r0, r4 + 2207 00be FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2208 .LVL140: +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2209 .loc 1 1281 10 view .LVU638 + 2210 00c2 0028 cmp r0, #0 + 2211 00c4 4BD1 bne .L154 +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2212 .loc 1 1287 7 is_stmt 1 view .LVU639 +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2213 .loc 1 1287 38 is_stmt 0 view .LVU640 + 2214 00c6 2368 ldr r3, [r4] +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2215 .loc 1 1287 48 view .LVU641 + 2216 00c8 5B6A ldr r3, [r3, #36] +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2217 .loc 1 1287 23 view .LVU642 + 2218 00ca 626A ldr r2, [r4, #36] + ARM GAS /tmp/ccth6daj.s page 168 + + + 2219 00cc 1370 strb r3, [r2] +1290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2220 .loc 1 1290 7 is_stmt 1 view .LVU643 +1290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2221 .loc 1 1290 21 is_stmt 0 view .LVU644 + 2222 00ce 636A ldr r3, [r4, #36] + 2223 00d0 0133 adds r3, r3, #1 + 2224 00d2 6362 str r3, [r4, #36] +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 2225 .loc 1 1292 7 is_stmt 1 view .LVU645 +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 2226 .loc 1 1292 11 is_stmt 0 view .LVU646 + 2227 00d4 238D ldrh r3, [r4, #40] +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 2228 .loc 1 1292 21 view .LVU647 + 2229 00d6 013B subs r3, r3, #1 + 2230 00d8 9BB2 uxth r3, r3 + 2231 00da 2385 strh r3, [r4, #40] +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2232 .loc 1 1293 7 is_stmt 1 view .LVU648 +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2233 .loc 1 1293 11 is_stmt 0 view .LVU649 + 2234 00dc 628D ldrh r2, [r4, #42] +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2235 .loc 1 1293 22 view .LVU650 + 2236 00de 013A subs r2, r2, #1 + 2237 00e0 92B2 uxth r2, r2 + 2238 00e2 6285 strh r2, [r4, #42] +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2239 .loc 1 1295 7 is_stmt 1 view .LVU651 +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2240 .loc 1 1295 16 is_stmt 0 view .LVU652 + 2241 00e4 628D ldrh r2, [r4, #42] + 2242 00e6 92B2 uxth r2, r2 +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2243 .loc 1 1295 10 view .LVU653 + 2244 00e8 002A cmp r2, #0 + 2245 00ea E1D0 beq .L147 +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2246 .loc 1 1295 35 discriminator 1 view .LVU654 + 2247 00ec 002B cmp r3, #0 + 2248 00ee DFD1 bne .L147 +1298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2249 .loc 1 1298 9 is_stmt 1 view .LVU655 +1298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2250 .loc 1 1298 13 is_stmt 0 view .LVU656 + 2251 00f0 0096 str r6, [sp] + 2252 00f2 2B00 movs r3, r5 + 2253 00f4 0022 movs r2, #0 + 2254 00f6 8021 movs r1, #128 + 2255 00f8 2000 movs r0, r4 + 2256 00fa FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2257 .LVL141: +1298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2258 .loc 1 1298 12 view .LVU657 + 2259 00fe 0028 cmp r0, #0 + 2260 0100 2FD1 bne .L155 + ARM GAS /tmp/ccth6daj.s page 169 + + +1303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2261 .loc 1 1303 9 is_stmt 1 view .LVU658 +1303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2262 .loc 1 1303 17 is_stmt 0 view .LVU659 + 2263 0102 638D ldrh r3, [r4, #42] + 2264 0104 9BB2 uxth r3, r3 +1303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2265 .loc 1 1303 12 view .LVU660 + 2266 0106 FF2B cmp r3, #255 + 2267 0108 C6D9 bls .L149 +1305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2268 .loc 1 1305 11 is_stmt 1 view .LVU661 +1305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 2269 .loc 1 1305 26 is_stmt 0 view .LVU662 + 2270 010a FF23 movs r3, #255 + 2271 010c 2385 strh r3, [r4, #40] +1306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 2272 .loc 1 1306 11 is_stmt 1 view .LVU663 + 2273 010e 7F3B subs r3, r3, #127 + 2274 0110 0022 movs r2, #0 + 2275 0112 0092 str r2, [sp] + 2276 0114 5B04 lsls r3, r3, #17 + 2277 0116 FF32 adds r2, r2, #255 + 2278 0118 3900 movs r1, r7 + 2279 011a 2000 movs r0, r4 + 2280 011c FFF7FEFF bl I2C_TransferConfig + 2281 .LVL142: + 2282 0120 C6E7 b .L147 + 2283 .L157: +1320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2284 .loc 1 1320 5 view .LVU664 +1320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2285 .loc 1 1320 9 is_stmt 0 view .LVU665 + 2286 0122 3200 movs r2, r6 + 2287 0124 2900 movs r1, r5 + 2288 0126 2000 movs r0, r4 + 2289 0128 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2290 .LVL143: +1320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2291 .loc 1 1320 8 view .LVU666 + 2292 012c 0028 cmp r0, #0 + 2293 012e 1AD1 bne .L156 +1326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2294 .loc 1 1326 5 is_stmt 1 view .LVU667 + 2295 0130 2368 ldr r3, [r4] + 2296 0132 2022 movs r2, #32 + 2297 0134 DA61 str r2, [r3, #28] +1329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2298 .loc 1 1329 5 view .LVU668 + 2299 0136 2168 ldr r1, [r4] + 2300 0138 4B68 ldr r3, [r1, #4] + 2301 013a 0D4D ldr r5, .L158+4 + 2302 013c 2B40 ands r3, r5 + 2303 013e 4B60 str r3, [r1, #4] +1331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2304 .loc 1 1331 5 view .LVU669 +1331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccth6daj.s page 170 + + + 2305 .loc 1 1331 17 is_stmt 0 view .LVU670 + 2306 0140 4123 movs r3, #65 + 2307 0142 E254 strb r2, [r4, r3] +1332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2308 .loc 1 1332 5 is_stmt 1 view .LVU671 +1332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2309 .loc 1 1332 17 is_stmt 0 view .LVU672 + 2310 0144 0023 movs r3, #0 + 2311 0146 2232 adds r2, r2, #34 + 2312 0148 A354 strb r3, [r4, r2] +1335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2313 .loc 1 1335 5 is_stmt 1 view .LVU673 +1335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2314 .loc 1 1335 5 view .LVU674 + 2315 014a 023A subs r2, r2, #2 + 2316 014c A354 strb r3, [r4, r2] +1335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2317 .loc 1 1335 5 view .LVU675 +1337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2318 .loc 1 1337 5 view .LVU676 +1337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2319 .loc 1 1337 12 is_stmt 0 view .LVU677 + 2320 014e 00E0 b .L144 + 2321 .LVL144: + 2322 .L151: +1341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2323 .loc 1 1341 12 view .LVU678 + 2324 0150 0220 movs r0, #2 + 2325 .LVL145: + 2326 .L144: +1343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2327 .loc 1 1343 1 view .LVU679 + 2328 0152 05B0 add sp, sp, #20 + 2329 @ sp needed + 2330 .LVL146: +1343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2331 .loc 1 1343 1 view .LVU680 + 2332 0154 F0BD pop {r4, r5, r6, r7, pc} + 2333 .LVL147: + 2334 .L152: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2335 .loc 1 1244 5 view .LVU681 + 2336 0156 0220 movs r0, #2 + 2337 .LVL148: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2338 .loc 1 1244 5 view .LVU682 + 2339 0158 FBE7 b .L144 + 2340 .LVL149: + 2341 .L153: +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2342 .loc 1 1251 14 view .LVU683 + 2343 015a 0120 movs r0, #1 + 2344 015c F9E7 b .L144 + 2345 .L154: +1283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2346 .loc 1 1283 16 view .LVU684 + 2347 015e 0120 movs r0, #1 + ARM GAS /tmp/ccth6daj.s page 171 + + + 2348 0160 F7E7 b .L144 + 2349 .L155: +1300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2350 .loc 1 1300 18 view .LVU685 + 2351 0162 0120 movs r0, #1 + 2352 0164 F5E7 b .L144 + 2353 .L156: +1322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2354 .loc 1 1322 14 view .LVU686 + 2355 0166 0120 movs r0, #1 + 2356 0168 F3E7 b .L144 + 2357 .L159: + 2358 016a C046 .align 2 + 2359 .L158: + 2360 016c 00240080 .word -2147474432 + 2361 0170 00E800FE .word -33495040 + 2362 .cfi_endproc + 2363 .LFE302: + 2365 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 2366 .align 1 + 2367 .global HAL_I2C_Slave_Transmit + 2368 .syntax unified + 2369 .code 16 + 2370 .thumb_func + 2371 .fpu softvfp + 2373 HAL_I2C_Slave_Transmit: + 2374 .LVL150: + 2375 .LFB303: +1356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 2376 .loc 1 1356 1 is_stmt 1 view -0 + 2377 .cfi_startproc + 2378 @ args = 0, pretend = 0, frame = 0 + 2379 @ frame_needed = 0, uses_anonymous_args = 0 +1356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 2380 .loc 1 1356 1 is_stmt 0 view .LVU688 + 2381 0000 F0B5 push {r4, r5, r6, r7, lr} + 2382 .LCFI18: + 2383 .cfi_def_cfa_offset 20 + 2384 .cfi_offset 4, -20 + 2385 .cfi_offset 5, -16 + 2386 .cfi_offset 6, -12 + 2387 .cfi_offset 7, -8 + 2388 .cfi_offset 14, -4 + 2389 0002 C646 mov lr, r8 + 2390 0004 00B5 push {lr} + 2391 .LCFI19: + 2392 .cfi_def_cfa_offset 24 + 2393 .cfi_offset 8, -24 + 2394 0006 82B0 sub sp, sp, #8 + 2395 .LCFI20: + 2396 .cfi_def_cfa_offset 32 + 2397 0008 0400 movs r4, r0 + 2398 000a 0D00 movs r5, r1 + 2399 000c 9046 mov r8, r2 + 2400 000e 1E00 movs r6, r3 +1357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2401 .loc 1 1357 3 is_stmt 1 view .LVU689 + ARM GAS /tmp/ccth6daj.s page 172 + + +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2402 .loc 1 1359 3 view .LVU690 +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2403 .loc 1 1359 11 is_stmt 0 view .LVU691 + 2404 0010 4123 movs r3, #65 + 2405 .LVL151: +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2406 .loc 1 1359 11 view .LVU692 + 2407 0012 C35C ldrb r3, [r0, r3] +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2408 .loc 1 1359 6 view .LVU693 + 2409 0014 202B cmp r3, #32 + 2410 0016 00D0 beq .LCB2268 + 2411 0018 B7E0 b .L172 @long jump + 2412 .LCB2268: +1361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2413 .loc 1 1361 5 is_stmt 1 view .LVU694 +1361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2414 .loc 1 1361 8 is_stmt 0 view .LVU695 + 2415 001a 0029 cmp r1, #0 + 2416 001c 4DD0 beq .L162 +1361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2417 .loc 1 1361 25 discriminator 1 view .LVU696 + 2418 001e 002A cmp r2, #0 + 2419 0020 4BD0 beq .L162 +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2420 .loc 1 1367 5 is_stmt 1 view .LVU697 +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2421 .loc 1 1367 5 view .LVU698 + 2422 0022 4023 movs r3, #64 + 2423 0024 C35C ldrb r3, [r0, r3] + 2424 0026 012B cmp r3, #1 + 2425 0028 00D1 bne .LCB2279 + 2426 002a B3E0 b .L173 @long jump + 2427 .LCB2279: +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2428 .loc 1 1367 5 discriminator 2 view .LVU699 + 2429 002c 4023 movs r3, #64 + 2430 002e 0122 movs r2, #1 + 2431 .LVL152: +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2432 .loc 1 1367 5 is_stmt 0 discriminator 2 view .LVU700 + 2433 0030 C254 strb r2, [r0, r3] +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2434 .loc 1 1367 5 is_stmt 1 discriminator 2 view .LVU701 +1370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2435 .loc 1 1370 5 discriminator 2 view .LVU702 +1370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2436 .loc 1 1370 17 is_stmt 0 discriminator 2 view .LVU703 + 2437 0032 FFF7FEFF bl HAL_GetTick + 2438 .LVL153: +1370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2439 .loc 1 1370 17 discriminator 2 view .LVU704 + 2440 0036 0700 movs r7, r0 + 2441 .LVL154: +1372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2442 .loc 1 1372 5 is_stmt 1 discriminator 2 view .LVU705 + ARM GAS /tmp/ccth6daj.s page 173 + + +1372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2443 .loc 1 1372 21 is_stmt 0 discriminator 2 view .LVU706 + 2444 0038 4123 movs r3, #65 + 2445 003a 2122 movs r2, #33 + 2446 003c E254 strb r2, [r4, r3] +1373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2447 .loc 1 1373 5 is_stmt 1 discriminator 2 view .LVU707 +1373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2448 .loc 1 1373 21 is_stmt 0 discriminator 2 view .LVU708 + 2449 003e 0133 adds r3, r3, #1 + 2450 0040 013A subs r2, r2, #1 + 2451 0042 E254 strb r2, [r4, r3] +1374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2452 .loc 1 1374 5 is_stmt 1 discriminator 2 view .LVU709 +1374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2453 .loc 1 1374 21 is_stmt 0 discriminator 2 view .LVU710 + 2454 0044 0023 movs r3, #0 + 2455 0046 6364 str r3, [r4, #68] +1377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2456 .loc 1 1377 5 is_stmt 1 discriminator 2 view .LVU711 +1377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2457 .loc 1 1377 21 is_stmt 0 discriminator 2 view .LVU712 + 2458 0048 6562 str r5, [r4, #36] +1378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2459 .loc 1 1378 5 is_stmt 1 discriminator 2 view .LVU713 +1378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2460 .loc 1 1378 21 is_stmt 0 discriminator 2 view .LVU714 + 2461 004a 4246 mov r2, r8 + 2462 004c 6285 strh r2, [r4, #42] +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2463 .loc 1 1379 5 is_stmt 1 discriminator 2 view .LVU715 +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2464 .loc 1 1379 21 is_stmt 0 discriminator 2 view .LVU716 + 2465 004e 6363 str r3, [r4, #52] +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2466 .loc 1 1382 5 is_stmt 1 discriminator 2 view .LVU717 +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2467 .loc 1 1382 9 is_stmt 0 discriminator 2 view .LVU718 + 2468 0050 2268 ldr r2, [r4] +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2469 .loc 1 1382 25 discriminator 2 view .LVU719 + 2470 0052 5368 ldr r3, [r2, #4] + 2471 0054 5149 ldr r1, .L181 + 2472 0056 0B40 ands r3, r1 + 2473 0058 5360 str r3, [r2, #4] +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2474 .loc 1 1385 5 is_stmt 1 discriminator 2 view .LVU720 +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2475 .loc 1 1385 9 is_stmt 0 discriminator 2 view .LVU721 + 2476 005a 0090 str r0, [sp] + 2477 005c 3300 movs r3, r6 + 2478 005e 0022 movs r2, #0 + 2479 0060 0821 movs r1, #8 + 2480 0062 2000 movs r0, r4 + 2481 .LVL155: +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2482 .loc 1 1385 9 discriminator 2 view .LVU722 + ARM GAS /tmp/ccth6daj.s page 174 + + + 2483 0064 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2484 .LVL156: +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2485 .loc 1 1385 8 discriminator 2 view .LVU723 + 2486 0068 0028 cmp r0, #0 + 2487 006a 2BD1 bne .L175 +1393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2488 .loc 1 1393 5 is_stmt 1 view .LVU724 + 2489 006c 2368 ldr r3, [r4] + 2490 006e 0822 movs r2, #8 + 2491 0070 DA61 str r2, [r3, #28] +1396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2492 .loc 1 1396 5 view .LVU725 +1396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2493 .loc 1 1396 8 is_stmt 0 view .LVU726 + 2494 0072 E368 ldr r3, [r4, #12] + 2495 0074 022B cmp r3, #2 + 2496 0076 2DD0 beq .L176 + 2497 .L165: +1411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2498 .loc 1 1411 5 is_stmt 1 view .LVU727 +1411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2499 .loc 1 1411 9 is_stmt 0 view .LVU728 + 2500 0078 8021 movs r1, #128 + 2501 007a 0097 str r7, [sp] + 2502 007c 3300 movs r3, r6 + 2503 007e 0022 movs r2, #0 + 2504 0080 4902 lsls r1, r1, #9 + 2505 0082 2000 movs r0, r4 + 2506 0084 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2507 .LVL157: +1411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2508 .loc 1 1411 8 view .LVU729 + 2509 0088 0028 cmp r0, #0 + 2510 008a 38D1 bne .L177 + 2511 .LVL158: + 2512 .L167: +1418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2513 .loc 1 1418 11 is_stmt 1 view .LVU730 +1418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2514 .loc 1 1418 16 is_stmt 0 view .LVU731 + 2515 008c 638D ldrh r3, [r4, #42] + 2516 008e 9BB2 uxth r3, r3 +1418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2517 .loc 1 1418 11 view .LVU732 + 2518 0090 002B cmp r3, #0 + 2519 0092 44D0 beq .L178 +1421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2520 .loc 1 1421 7 is_stmt 1 view .LVU733 +1421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2521 .loc 1 1421 11 is_stmt 0 view .LVU734 + 2522 0094 3A00 movs r2, r7 + 2523 0096 3100 movs r1, r6 + 2524 0098 2000 movs r0, r4 + 2525 009a FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 2526 .LVL159: +1421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 175 + + + 2527 .loc 1 1421 10 view .LVU735 + 2528 009e 0028 cmp r0, #0 + 2529 00a0 35D1 bne .L179 +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2530 .loc 1 1429 7 is_stmt 1 view .LVU736 +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2531 .loc 1 1429 11 is_stmt 0 view .LVU737 + 2532 00a2 2368 ldr r3, [r4] +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2533 .loc 1 1429 30 view .LVU738 + 2534 00a4 626A ldr r2, [r4, #36] + 2535 00a6 1278 ldrb r2, [r2] +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2536 .loc 1 1429 28 view .LVU739 + 2537 00a8 9A62 str r2, [r3, #40] +1432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2538 .loc 1 1432 7 is_stmt 1 view .LVU740 +1432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2539 .loc 1 1432 21 is_stmt 0 view .LVU741 + 2540 00aa 636A ldr r3, [r4, #36] + 2541 00ac 0133 adds r3, r3, #1 + 2542 00ae 6362 str r3, [r4, #36] +1434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2543 .loc 1 1434 7 is_stmt 1 view .LVU742 +1434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2544 .loc 1 1434 11 is_stmt 0 view .LVU743 + 2545 00b0 658D ldrh r5, [r4, #42] +1434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2546 .loc 1 1434 22 view .LVU744 + 2547 00b2 013D subs r5, r5, #1 + 2548 00b4 ADB2 uxth r5, r5 + 2549 00b6 6585 strh r5, [r4, #42] + 2550 00b8 E8E7 b .L167 + 2551 .LVL160: + 2552 .L162: +1363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2553 .loc 1 1363 7 is_stmt 1 view .LVU745 +1363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2554 .loc 1 1363 23 is_stmt 0 view .LVU746 + 2555 00ba 8023 movs r3, #128 + 2556 00bc 9B00 lsls r3, r3, #2 + 2557 00be 6364 str r3, [r4, #68] +1364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2558 .loc 1 1364 7 is_stmt 1 view .LVU747 +1364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2559 .loc 1 1364 15 is_stmt 0 view .LVU748 + 2560 00c0 0120 movs r0, #1 + 2561 .LVL161: +1364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2562 .loc 1 1364 15 view .LVU749 + 2563 00c2 63E0 b .L161 + 2564 .LVL162: + 2565 .L175: +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2566 .loc 1 1388 7 is_stmt 1 view .LVU750 +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2567 .loc 1 1388 11 is_stmt 0 view .LVU751 + ARM GAS /tmp/ccth6daj.s page 176 + + + 2568 00c4 2268 ldr r2, [r4] +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2569 .loc 1 1388 27 view .LVU752 + 2570 00c6 5168 ldr r1, [r2, #4] + 2571 00c8 8023 movs r3, #128 + 2572 00ca 1B02 lsls r3, r3, #8 + 2573 00cc 0B43 orrs r3, r1 + 2574 00ce 5360 str r3, [r2, #4] +1389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2575 .loc 1 1389 7 is_stmt 1 view .LVU753 +1389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2576 .loc 1 1389 14 is_stmt 0 view .LVU754 + 2577 00d0 0120 movs r0, #1 + 2578 00d2 5BE0 b .L161 + 2579 .L176: +1399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2580 .loc 1 1399 7 is_stmt 1 view .LVU755 +1399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2581 .loc 1 1399 11 is_stmt 0 view .LVU756 + 2582 00d4 0097 str r7, [sp] + 2583 00d6 3300 movs r3, r6 + 2584 00d8 0022 movs r2, #0 + 2585 00da 0821 movs r1, #8 + 2586 00dc 2000 movs r0, r4 + 2587 00de FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2588 .LVL163: +1399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2589 .loc 1 1399 10 view .LVU757 + 2590 00e2 0028 cmp r0, #0 + 2591 00e4 03D1 bne .L180 +1407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2592 .loc 1 1407 7 is_stmt 1 view .LVU758 + 2593 00e6 2368 ldr r3, [r4] + 2594 00e8 0822 movs r2, #8 + 2595 00ea DA61 str r2, [r3, #28] + 2596 00ec C4E7 b .L165 + 2597 .L180: +1402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2598 .loc 1 1402 9 view .LVU759 +1402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2599 .loc 1 1402 13 is_stmt 0 view .LVU760 + 2600 00ee 2268 ldr r2, [r4] +1402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2601 .loc 1 1402 29 view .LVU761 + 2602 00f0 5168 ldr r1, [r2, #4] + 2603 00f2 8023 movs r3, #128 + 2604 00f4 1B02 lsls r3, r3, #8 + 2605 00f6 0B43 orrs r3, r1 + 2606 00f8 5360 str r3, [r2, #4] +1403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2607 .loc 1 1403 9 is_stmt 1 view .LVU762 +1403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2608 .loc 1 1403 16 is_stmt 0 view .LVU763 + 2609 00fa 0120 movs r0, #1 + 2610 00fc 46E0 b .L161 + 2611 .L177: +1414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccth6daj.s page 177 + + + 2612 .loc 1 1414 7 is_stmt 1 view .LVU764 +1414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2613 .loc 1 1414 11 is_stmt 0 view .LVU765 + 2614 00fe 2268 ldr r2, [r4] +1414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2615 .loc 1 1414 27 view .LVU766 + 2616 0100 5168 ldr r1, [r2, #4] + 2617 0102 8023 movs r3, #128 + 2618 0104 1B02 lsls r3, r3, #8 + 2619 0106 0B43 orrs r3, r1 + 2620 0108 5360 str r3, [r2, #4] +1415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2621 .loc 1 1415 7 is_stmt 1 view .LVU767 +1415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2622 .loc 1 1415 14 is_stmt 0 view .LVU768 + 2623 010a 0120 movs r0, #1 + 2624 010c 3EE0 b .L161 + 2625 .LVL164: + 2626 .L179: +1424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2627 .loc 1 1424 9 is_stmt 1 view .LVU769 +1424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2628 .loc 1 1424 13 is_stmt 0 view .LVU770 + 2629 010e 2268 ldr r2, [r4] +1424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2630 .loc 1 1424 29 view .LVU771 + 2631 0110 5168 ldr r1, [r2, #4] + 2632 0112 8023 movs r3, #128 + 2633 0114 1B02 lsls r3, r3, #8 + 2634 0116 0B43 orrs r3, r1 + 2635 0118 5360 str r3, [r2, #4] +1425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2636 .loc 1 1425 9 is_stmt 1 view .LVU772 +1425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2637 .loc 1 1425 16 is_stmt 0 view .LVU773 + 2638 011a 0120 movs r0, #1 + 2639 011c 36E0 b .L161 + 2640 .L178: +1438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2641 .loc 1 1438 5 is_stmt 1 view .LVU774 +1438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2642 .loc 1 1438 9 is_stmt 0 view .LVU775 + 2643 011e 3A00 movs r2, r7 + 2644 0120 3100 movs r1, r6 + 2645 0122 2000 movs r0, r4 + 2646 0124 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 2647 .LVL165: +1438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2648 .loc 1 1438 8 view .LVU776 + 2649 0128 0028 cmp r0, #0 + 2650 012a 0AD0 beq .L170 +1441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2651 .loc 1 1441 7 is_stmt 1 view .LVU777 +1441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2652 .loc 1 1441 11 is_stmt 0 view .LVU778 + 2653 012c 2268 ldr r2, [r4] +1441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 178 + + + 2654 .loc 1 1441 27 view .LVU779 + 2655 012e 5168 ldr r1, [r2, #4] + 2656 0130 8023 movs r3, #128 + 2657 0132 1B02 lsls r3, r3, #8 + 2658 0134 0B43 orrs r3, r1 + 2659 0136 5360 str r3, [r2, #4] +1443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2660 .loc 1 1443 7 is_stmt 1 view .LVU780 +1443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2661 .loc 1 1443 15 is_stmt 0 view .LVU781 + 2662 0138 636C ldr r3, [r4, #68] +1443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2663 .loc 1 1443 10 view .LVU782 + 2664 013a 042B cmp r3, #4 + 2665 013c 2CD1 bne .L174 +1447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2666 .loc 1 1447 9 is_stmt 1 view .LVU783 +1447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2667 .loc 1 1447 25 is_stmt 0 view .LVU784 + 2668 013e 0023 movs r3, #0 + 2669 0140 6364 str r3, [r4, #68] + 2670 .L170: +1456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2671 .loc 1 1456 5 is_stmt 1 view .LVU785 + 2672 0142 2368 ldr r3, [r4] + 2673 0144 2022 movs r2, #32 + 2674 0146 DA61 str r2, [r3, #28] +1459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2675 .loc 1 1459 5 view .LVU786 +1459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2676 .loc 1 1459 9 is_stmt 0 view .LVU787 + 2677 0148 8021 movs r1, #128 + 2678 014a 0097 str r7, [sp] + 2679 014c 3300 movs r3, r6 + 2680 014e 1F3A subs r2, r2, #31 + 2681 0150 0902 lsls r1, r1, #8 + 2682 0152 2000 movs r0, r4 + 2683 0154 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2684 .LVL166: +1459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2685 .loc 1 1459 8 view .LVU788 + 2686 0158 0028 cmp r0, #0 + 2687 015a 07D0 beq .L171 +1462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2688 .loc 1 1462 7 is_stmt 1 view .LVU789 +1462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2689 .loc 1 1462 11 is_stmt 0 view .LVU790 + 2690 015c 2268 ldr r2, [r4] +1462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2691 .loc 1 1462 27 view .LVU791 + 2692 015e 5168 ldr r1, [r2, #4] + 2693 0160 8023 movs r3, #128 + 2694 0162 1B02 lsls r3, r3, #8 + 2695 0164 0B43 orrs r3, r1 + 2696 0166 5360 str r3, [r2, #4] +1463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2697 .loc 1 1463 7 is_stmt 1 view .LVU792 + ARM GAS /tmp/ccth6daj.s page 179 + + +1463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2698 .loc 1 1463 14 is_stmt 0 view .LVU793 + 2699 0168 0120 movs r0, #1 + 2700 016a 0FE0 b .L161 + 2701 .L171: +1467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2702 .loc 1 1467 5 is_stmt 1 view .LVU794 +1467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2703 .loc 1 1467 9 is_stmt 0 view .LVU795 + 2704 016c 2268 ldr r2, [r4] +1467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2705 .loc 1 1467 25 view .LVU796 + 2706 016e 5168 ldr r1, [r2, #4] + 2707 0170 8023 movs r3, #128 + 2708 0172 1B02 lsls r3, r3, #8 + 2709 0174 0B43 orrs r3, r1 + 2710 0176 5360 str r3, [r2, #4] +1469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2711 .loc 1 1469 5 is_stmt 1 view .LVU797 +1469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2712 .loc 1 1469 17 is_stmt 0 view .LVU798 + 2713 0178 4123 movs r3, #65 + 2714 017a 2022 movs r2, #32 + 2715 017c E254 strb r2, [r4, r3] +1470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2716 .loc 1 1470 5 is_stmt 1 view .LVU799 +1470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2717 .loc 1 1470 17 is_stmt 0 view .LVU800 + 2718 017e 0023 movs r3, #0 + 2719 0180 2232 adds r2, r2, #34 + 2720 0182 A354 strb r3, [r4, r2] +1473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2721 .loc 1 1473 5 is_stmt 1 view .LVU801 +1473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2722 .loc 1 1473 5 view .LVU802 + 2723 0184 023A subs r2, r2, #2 + 2724 0186 A354 strb r3, [r4, r2] +1473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2725 .loc 1 1473 5 view .LVU803 +1475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2726 .loc 1 1475 5 view .LVU804 +1475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2727 .loc 1 1475 12 is_stmt 0 view .LVU805 + 2728 0188 00E0 b .L161 + 2729 .LVL167: + 2730 .L172: +1479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2731 .loc 1 1479 12 view .LVU806 + 2732 018a 0220 movs r0, #2 + 2733 .LVL168: + 2734 .L161: +1481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2735 .loc 1 1481 1 view .LVU807 + 2736 018c 02B0 add sp, sp, #8 + 2737 @ sp needed + 2738 .LVL169: + 2739 .LVL170: + ARM GAS /tmp/ccth6daj.s page 180 + + +1481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2740 .loc 1 1481 1 view .LVU808 + 2741 018e 80BC pop {r7} + 2742 0190 B846 mov r8, r7 + 2743 0192 F0BD pop {r4, r5, r6, r7, pc} + 2744 .LVL171: + 2745 .L173: +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2746 .loc 1 1367 5 view .LVU809 + 2747 0194 0220 movs r0, #2 + 2748 .LVL172: +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2749 .loc 1 1367 5 view .LVU810 + 2750 0196 F9E7 b .L161 + 2751 .LVL173: + 2752 .L174: +1451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2753 .loc 1 1451 16 view .LVU811 + 2754 0198 0120 movs r0, #1 + 2755 019a F7E7 b .L161 + 2756 .L182: + 2757 .align 2 + 2758 .L181: + 2759 019c FF7FFFFF .word -32769 + 2760 .cfi_endproc + 2761 .LFE303: + 2763 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 2764 .align 1 + 2765 .global HAL_I2C_Slave_Receive + 2766 .syntax unified + 2767 .code 16 + 2768 .thumb_func + 2769 .fpu softvfp + 2771 HAL_I2C_Slave_Receive: + 2772 .LVL174: + 2773 .LFB304: +1494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 2774 .loc 1 1494 1 is_stmt 1 view -0 + 2775 .cfi_startproc + 2776 @ args = 0, pretend = 0, frame = 0 + 2777 @ frame_needed = 0, uses_anonymous_args = 0 +1494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 2778 .loc 1 1494 1 is_stmt 0 view .LVU813 + 2779 0000 F0B5 push {r4, r5, r6, r7, lr} + 2780 .LCFI21: + 2781 .cfi_def_cfa_offset 20 + 2782 .cfi_offset 4, -20 + 2783 .cfi_offset 5, -16 + 2784 .cfi_offset 6, -12 + 2785 .cfi_offset 7, -8 + 2786 .cfi_offset 14, -4 + 2787 0002 C646 mov lr, r8 + 2788 0004 00B5 push {lr} + 2789 .LCFI22: + 2790 .cfi_def_cfa_offset 24 + 2791 .cfi_offset 8, -24 + 2792 0006 82B0 sub sp, sp, #8 + ARM GAS /tmp/ccth6daj.s page 181 + + + 2793 .LCFI23: + 2794 .cfi_def_cfa_offset 32 + 2795 0008 0400 movs r4, r0 + 2796 000a 0D00 movs r5, r1 + 2797 000c 9046 mov r8, r2 + 2798 000e 1E00 movs r6, r3 +1495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2799 .loc 1 1495 3 is_stmt 1 view .LVU814 +1497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2800 .loc 1 1497 3 view .LVU815 +1497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2801 .loc 1 1497 11 is_stmt 0 view .LVU816 + 2802 0010 4123 movs r3, #65 + 2803 .LVL175: +1497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2804 .loc 1 1497 11 view .LVU817 + 2805 0012 C35C ldrb r3, [r0, r3] +1497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2806 .loc 1 1497 6 view .LVU818 + 2807 0014 202B cmp r3, #32 + 2808 0016 00D0 beq .LCB2649 + 2809 0018 A9E0 b .L194 @long jump + 2810 .LCB2649: +1499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2811 .loc 1 1499 5 is_stmt 1 view .LVU819 +1499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2812 .loc 1 1499 8 is_stmt 0 view .LVU820 + 2813 001a 0029 cmp r1, #0 + 2814 001c 2ED0 beq .L185 +1499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2815 .loc 1 1499 25 discriminator 1 view .LVU821 + 2816 001e 002A cmp r2, #0 + 2817 0020 2CD0 beq .L185 +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2818 .loc 1 1505 5 is_stmt 1 view .LVU822 +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2819 .loc 1 1505 5 view .LVU823 + 2820 0022 4023 movs r3, #64 + 2821 0024 C35C ldrb r3, [r0, r3] + 2822 0026 012B cmp r3, #1 + 2823 0028 00D1 bne .LCB2660 + 2824 002a A5E0 b .L195 @long jump + 2825 .LCB2660: +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2826 .loc 1 1505 5 discriminator 2 view .LVU824 + 2827 002c 4023 movs r3, #64 + 2828 002e 0122 movs r2, #1 + 2829 .LVL176: +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2830 .loc 1 1505 5 is_stmt 0 discriminator 2 view .LVU825 + 2831 0030 C254 strb r2, [r0, r3] +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2832 .loc 1 1505 5 is_stmt 1 discriminator 2 view .LVU826 +1508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2833 .loc 1 1508 5 discriminator 2 view .LVU827 +1508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2834 .loc 1 1508 17 is_stmt 0 discriminator 2 view .LVU828 + ARM GAS /tmp/ccth6daj.s page 182 + + + 2835 0032 FFF7FEFF bl HAL_GetTick + 2836 .LVL177: +1508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2837 .loc 1 1508 17 discriminator 2 view .LVU829 + 2838 0036 0700 movs r7, r0 + 2839 .LVL178: +1510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2840 .loc 1 1510 5 is_stmt 1 discriminator 2 view .LVU830 +1510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2841 .loc 1 1510 21 is_stmt 0 discriminator 2 view .LVU831 + 2842 0038 4123 movs r3, #65 + 2843 003a 2222 movs r2, #34 + 2844 003c E254 strb r2, [r4, r3] +1511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2845 .loc 1 1511 5 is_stmt 1 discriminator 2 view .LVU832 +1511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2846 .loc 1 1511 21 is_stmt 0 discriminator 2 view .LVU833 + 2847 003e 0133 adds r3, r3, #1 + 2848 0040 023A subs r2, r2, #2 + 2849 0042 E254 strb r2, [r4, r3] +1512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2850 .loc 1 1512 5 is_stmt 1 discriminator 2 view .LVU834 +1512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2851 .loc 1 1512 21 is_stmt 0 discriminator 2 view .LVU835 + 2852 0044 0023 movs r3, #0 + 2853 0046 6364 str r3, [r4, #68] +1515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2854 .loc 1 1515 5 is_stmt 1 discriminator 2 view .LVU836 +1515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 2855 .loc 1 1515 21 is_stmt 0 discriminator 2 view .LVU837 + 2856 0048 6562 str r5, [r4, #36] +1516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2857 .loc 1 1516 5 is_stmt 1 discriminator 2 view .LVU838 +1516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 2858 .loc 1 1516 21 is_stmt 0 discriminator 2 view .LVU839 + 2859 004a 4246 mov r2, r8 + 2860 004c 6285 strh r2, [r4, #42] +1517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2861 .loc 1 1517 5 is_stmt 1 discriminator 2 view .LVU840 +1517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2862 .loc 1 1517 21 is_stmt 0 discriminator 2 view .LVU841 + 2863 004e 6363 str r3, [r4, #52] +1520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2864 .loc 1 1520 5 is_stmt 1 discriminator 2 view .LVU842 +1520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2865 .loc 1 1520 9 is_stmt 0 discriminator 2 view .LVU843 + 2866 0050 2268 ldr r2, [r4] +1520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2867 .loc 1 1520 25 discriminator 2 view .LVU844 + 2868 0052 5368 ldr r3, [r2, #4] + 2869 0054 4949 ldr r1, .L197 + 2870 0056 0B40 ands r3, r1 + 2871 0058 5360 str r3, [r2, #4] +1523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2872 .loc 1 1523 5 is_stmt 1 discriminator 2 view .LVU845 +1523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2873 .loc 1 1523 9 is_stmt 0 discriminator 2 view .LVU846 + ARM GAS /tmp/ccth6daj.s page 183 + + + 2874 005a 0090 str r0, [sp] + 2875 005c 3300 movs r3, r6 + 2876 005e 0022 movs r2, #0 + 2877 0060 0821 movs r1, #8 + 2878 0062 2000 movs r0, r4 + 2879 .LVL179: +1523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2880 .loc 1 1523 9 discriminator 2 view .LVU847 + 2881 0064 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2882 .LVL180: +1523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2883 .loc 1 1523 8 discriminator 2 view .LVU848 + 2884 0068 0028 cmp r0, #0 + 2885 006a 0CD0 beq .L187 +1526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2886 .loc 1 1526 7 is_stmt 1 view .LVU849 +1526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2887 .loc 1 1526 11 is_stmt 0 view .LVU850 + 2888 006c 2268 ldr r2, [r4] +1526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2889 .loc 1 1526 27 view .LVU851 + 2890 006e 5168 ldr r1, [r2, #4] + 2891 0070 8023 movs r3, #128 + 2892 0072 1B02 lsls r3, r3, #8 + 2893 0074 0B43 orrs r3, r1 + 2894 0076 5360 str r3, [r2, #4] +1527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2895 .loc 1 1527 7 is_stmt 1 view .LVU852 +1527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2896 .loc 1 1527 14 is_stmt 0 view .LVU853 + 2897 0078 0120 movs r0, #1 + 2898 007a 79E0 b .L184 + 2899 .LVL181: + 2900 .L185: +1501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2901 .loc 1 1501 7 is_stmt 1 view .LVU854 +1501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2902 .loc 1 1501 23 is_stmt 0 view .LVU855 + 2903 007c 8023 movs r3, #128 + 2904 007e 9B00 lsls r3, r3, #2 + 2905 0080 6364 str r3, [r4, #68] +1502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2906 .loc 1 1502 7 is_stmt 1 view .LVU856 +1502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2907 .loc 1 1502 15 is_stmt 0 view .LVU857 + 2908 0082 0120 movs r0, #1 + 2909 .LVL182: +1502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2910 .loc 1 1502 15 view .LVU858 + 2911 0084 74E0 b .L184 + 2912 .LVL183: + 2913 .L187: +1531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2914 .loc 1 1531 5 is_stmt 1 view .LVU859 + 2915 0086 2368 ldr r3, [r4] + 2916 0088 0822 movs r2, #8 + 2917 008a DA61 str r2, [r3, #28] + ARM GAS /tmp/ccth6daj.s page 184 + + +1534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2918 .loc 1 1534 5 view .LVU860 +1534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2919 .loc 1 1534 9 is_stmt 0 view .LVU861 + 2920 008c 8021 movs r1, #128 + 2921 008e 0097 str r7, [sp] + 2922 0090 3300 movs r3, r6 + 2923 0092 073A subs r2, r2, #7 + 2924 0094 4902 lsls r1, r1, #9 + 2925 0096 2000 movs r0, r4 + 2926 0098 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 2927 .LVL184: +1534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2928 .loc 1 1534 8 view .LVU862 + 2929 009c 0028 cmp r0, #0 + 2930 009e 12D0 beq .L188 +1537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2931 .loc 1 1537 7 is_stmt 1 view .LVU863 +1537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2932 .loc 1 1537 11 is_stmt 0 view .LVU864 + 2933 00a0 2268 ldr r2, [r4] +1537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 2934 .loc 1 1537 27 view .LVU865 + 2935 00a2 5168 ldr r1, [r2, #4] + 2936 00a4 8023 movs r3, #128 + 2937 00a6 1B02 lsls r3, r3, #8 + 2938 00a8 0B43 orrs r3, r1 + 2939 00aa 5360 str r3, [r2, #4] +1538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2940 .loc 1 1538 7 is_stmt 1 view .LVU866 +1538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2941 .loc 1 1538 14 is_stmt 0 view .LVU867 + 2942 00ac 0120 movs r0, #1 + 2943 00ae 5FE0 b .L184 + 2944 .LVL185: + 2945 .L189: +1565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2946 .loc 1 1565 7 is_stmt 1 view .LVU868 +1565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2947 .loc 1 1565 38 is_stmt 0 view .LVU869 + 2948 00b0 2368 ldr r3, [r4] +1565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2949 .loc 1 1565 48 view .LVU870 + 2950 00b2 5B6A ldr r3, [r3, #36] +1565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2951 .loc 1 1565 23 view .LVU871 + 2952 00b4 626A ldr r2, [r4, #36] + 2953 00b6 1370 strb r3, [r2] +1568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2954 .loc 1 1568 7 is_stmt 1 view .LVU872 +1568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2955 .loc 1 1568 21 is_stmt 0 view .LVU873 + 2956 00b8 636A ldr r3, [r4, #36] + 2957 00ba 0133 adds r3, r3, #1 + 2958 00bc 6362 str r3, [r4, #36] +1570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2959 .loc 1 1570 7 is_stmt 1 view .LVU874 + ARM GAS /tmp/ccth6daj.s page 185 + + +1570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2960 .loc 1 1570 11 is_stmt 0 view .LVU875 + 2961 00be 658D ldrh r5, [r4, #42] +1570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 2962 .loc 1 1570 22 view .LVU876 + 2963 00c0 013D subs r5, r5, #1 + 2964 00c2 ADB2 uxth r5, r5 + 2965 00c4 6585 strh r5, [r4, #42] + 2966 .L188: +1541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2967 .loc 1 1541 11 is_stmt 1 view .LVU877 +1541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2968 .loc 1 1541 16 is_stmt 0 view .LVU878 + 2969 00c6 638D ldrh r3, [r4, #42] + 2970 00c8 9BB2 uxth r3, r3 +1541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2971 .loc 1 1541 11 view .LVU879 + 2972 00ca 002B cmp r3, #0 + 2973 00cc 1CD0 beq .L196 +1544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2974 .loc 1 1544 7 is_stmt 1 view .LVU880 +1544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2975 .loc 1 1544 11 is_stmt 0 view .LVU881 + 2976 00ce 3A00 movs r2, r7 + 2977 00d0 3100 movs r1, r6 + 2978 00d2 2000 movs r0, r4 + 2979 00d4 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 2980 .LVL186: +1544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2981 .loc 1 1544 10 view .LVU882 + 2982 00d8 0028 cmp r0, #0 + 2983 00da E9D0 beq .L189 +1547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2984 .loc 1 1547 9 is_stmt 1 view .LVU883 +1547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2985 .loc 1 1547 13 is_stmt 0 view .LVU884 + 2986 00dc 2268 ldr r2, [r4] +1547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 2987 .loc 1 1547 29 view .LVU885 + 2988 00de 5168 ldr r1, [r2, #4] + 2989 00e0 8023 movs r3, #128 + 2990 00e2 1B02 lsls r3, r3, #8 + 2991 00e4 0B43 orrs r3, r1 + 2992 00e6 5360 str r3, [r2, #4] +1550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2993 .loc 1 1550 9 is_stmt 1 view .LVU886 +1550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2994 .loc 1 1550 13 is_stmt 0 view .LVU887 + 2995 00e8 2368 ldr r3, [r4] + 2996 00ea 9A69 ldr r2, [r3, #24] +1550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 2997 .loc 1 1550 12 view .LVU888 + 2998 00ec 5207 lsls r2, r2, #29 + 2999 00ee 09D5 bpl .L190 +1553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3000 .loc 1 1553 11 is_stmt 1 view .LVU889 +1553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 186 + + + 3001 .loc 1 1553 52 is_stmt 0 view .LVU890 + 3002 00f0 5B6A ldr r3, [r3, #36] +1553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3003 .loc 1 1553 27 view .LVU891 + 3004 00f2 626A ldr r2, [r4, #36] + 3005 00f4 1370 strb r3, [r2] +1556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3006 .loc 1 1556 11 is_stmt 1 view .LVU892 +1556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3007 .loc 1 1556 25 is_stmt 0 view .LVU893 + 3008 00f6 636A ldr r3, [r4, #36] + 3009 00f8 0133 adds r3, r3, #1 + 3010 00fa 6362 str r3, [r4, #36] +1558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3011 .loc 1 1558 11 is_stmt 1 view .LVU894 +1558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3012 .loc 1 1558 15 is_stmt 0 view .LVU895 + 3013 00fc 638D ldrh r3, [r4, #42] +1558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3014 .loc 1 1558 26 view .LVU896 + 3015 00fe 013B subs r3, r3, #1 + 3016 0100 9BB2 uxth r3, r3 + 3017 0102 6385 strh r3, [r4, #42] + 3018 .L190: +1561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3019 .loc 1 1561 9 is_stmt 1 view .LVU897 +1561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3020 .loc 1 1561 16 is_stmt 0 view .LVU898 + 3021 0104 0120 movs r0, #1 + 3022 0106 33E0 b .L184 + 3023 .L196: +1574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3024 .loc 1 1574 5 is_stmt 1 view .LVU899 +1574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3025 .loc 1 1574 9 is_stmt 0 view .LVU900 + 3026 0108 3A00 movs r2, r7 + 3027 010a 3100 movs r1, r6 + 3028 010c 2000 movs r0, r4 + 3029 010e FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 3030 .LVL187: +1574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3031 .loc 1 1574 8 view .LVU901 + 3032 0112 0028 cmp r0, #0 + 3033 0114 07D0 beq .L192 +1577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3034 .loc 1 1577 7 is_stmt 1 view .LVU902 +1577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3035 .loc 1 1577 11 is_stmt 0 view .LVU903 + 3036 0116 2268 ldr r2, [r4] +1577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3037 .loc 1 1577 27 view .LVU904 + 3038 0118 5168 ldr r1, [r2, #4] + 3039 011a 8023 movs r3, #128 + 3040 011c 1B02 lsls r3, r3, #8 + 3041 011e 0B43 orrs r3, r1 + 3042 0120 5360 str r3, [r2, #4] +1578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 187 + + + 3043 .loc 1 1578 7 is_stmt 1 view .LVU905 +1578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3044 .loc 1 1578 14 is_stmt 0 view .LVU906 + 3045 0122 0120 movs r0, #1 + 3046 0124 24E0 b .L184 + 3047 .L192: +1582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3048 .loc 1 1582 5 is_stmt 1 view .LVU907 + 3049 0126 2368 ldr r3, [r4] + 3050 0128 2022 movs r2, #32 + 3051 012a DA61 str r2, [r3, #28] +1585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3052 .loc 1 1585 5 view .LVU908 +1585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3053 .loc 1 1585 9 is_stmt 0 view .LVU909 + 3054 012c 8021 movs r1, #128 + 3055 012e 0097 str r7, [sp] + 3056 0130 3300 movs r3, r6 + 3057 0132 1F3A subs r2, r2, #31 + 3058 0134 0902 lsls r1, r1, #8 + 3059 0136 2000 movs r0, r4 + 3060 0138 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3061 .LVL188: +1585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3062 .loc 1 1585 8 view .LVU910 + 3063 013c 0028 cmp r0, #0 + 3064 013e 07D0 beq .L193 +1588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3065 .loc 1 1588 7 is_stmt 1 view .LVU911 +1588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3066 .loc 1 1588 11 is_stmt 0 view .LVU912 + 3067 0140 2268 ldr r2, [r4] +1588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 3068 .loc 1 1588 27 view .LVU913 + 3069 0142 5168 ldr r1, [r2, #4] + 3070 0144 8023 movs r3, #128 + 3071 0146 1B02 lsls r3, r3, #8 + 3072 0148 0B43 orrs r3, r1 + 3073 014a 5360 str r3, [r2, #4] +1589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3074 .loc 1 1589 7 is_stmt 1 view .LVU914 +1589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3075 .loc 1 1589 14 is_stmt 0 view .LVU915 + 3076 014c 0120 movs r0, #1 + 3077 014e 0FE0 b .L184 + 3078 .L193: +1593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3079 .loc 1 1593 5 is_stmt 1 view .LVU916 +1593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3080 .loc 1 1593 9 is_stmt 0 view .LVU917 + 3081 0150 2268 ldr r2, [r4] +1593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3082 .loc 1 1593 25 view .LVU918 + 3083 0152 5168 ldr r1, [r2, #4] + 3084 0154 8023 movs r3, #128 + 3085 0156 1B02 lsls r3, r3, #8 + 3086 0158 0B43 orrs r3, r1 + ARM GAS /tmp/ccth6daj.s page 188 + + + 3087 015a 5360 str r3, [r2, #4] +1595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3088 .loc 1 1595 5 is_stmt 1 view .LVU919 +1595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3089 .loc 1 1595 17 is_stmt 0 view .LVU920 + 3090 015c 4123 movs r3, #65 + 3091 015e 2022 movs r2, #32 + 3092 0160 E254 strb r2, [r4, r3] +1596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3093 .loc 1 1596 5 is_stmt 1 view .LVU921 +1596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3094 .loc 1 1596 17 is_stmt 0 view .LVU922 + 3095 0162 0023 movs r3, #0 + 3096 0164 2232 adds r2, r2, #34 + 3097 0166 A354 strb r3, [r4, r2] +1599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3098 .loc 1 1599 5 is_stmt 1 view .LVU923 +1599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3099 .loc 1 1599 5 view .LVU924 + 3100 0168 023A subs r2, r2, #2 + 3101 016a A354 strb r3, [r4, r2] +1599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3102 .loc 1 1599 5 view .LVU925 +1601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3103 .loc 1 1601 5 view .LVU926 +1601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3104 .loc 1 1601 12 is_stmt 0 view .LVU927 + 3105 016c 00E0 b .L184 + 3106 .LVL189: + 3107 .L194: +1605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3108 .loc 1 1605 12 view .LVU928 + 3109 016e 0220 movs r0, #2 + 3110 .LVL190: + 3111 .L184: +1607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3112 .loc 1 1607 1 view .LVU929 + 3113 0170 02B0 add sp, sp, #8 + 3114 @ sp needed + 3115 .LVL191: + 3116 .LVL192: +1607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3117 .loc 1 1607 1 view .LVU930 + 3118 0172 80BC pop {r7} + 3119 0174 B846 mov r8, r7 + 3120 0176 F0BD pop {r4, r5, r6, r7, pc} + 3121 .LVL193: + 3122 .L195: +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3123 .loc 1 1505 5 view .LVU931 + 3124 0178 0220 movs r0, #2 + 3125 .LVL194: +1505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3126 .loc 1 1505 5 view .LVU932 + 3127 017a F9E7 b .L184 + 3128 .L198: + 3129 .align 2 + ARM GAS /tmp/ccth6daj.s page 189 + + + 3130 .L197: + 3131 017c FF7FFFFF .word -32769 + 3132 .cfi_endproc + 3133 .LFE304: + 3135 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 3136 .align 1 + 3137 .global HAL_I2C_Master_Transmit_IT + 3138 .syntax unified + 3139 .code 16 + 3140 .thumb_func + 3141 .fpu softvfp + 3143 HAL_I2C_Master_Transmit_IT: + 3144 .LVL195: + 3145 .LFB305: +1621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3146 .loc 1 1621 1 is_stmt 1 view -0 + 3147 .cfi_startproc + 3148 @ args = 0, pretend = 0, frame = 0 + 3149 @ frame_needed = 0, uses_anonymous_args = 0 +1621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3150 .loc 1 1621 1 is_stmt 0 view .LVU934 + 3151 0000 30B5 push {r4, r5, lr} + 3152 .LCFI24: + 3153 .cfi_def_cfa_offset 12 + 3154 .cfi_offset 4, -12 + 3155 .cfi_offset 5, -8 + 3156 .cfi_offset 14, -4 + 3157 0002 83B0 sub sp, sp, #12 + 3158 .LCFI25: + 3159 .cfi_def_cfa_offset 24 + 3160 0004 0400 movs r4, r0 +1622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3161 .loc 1 1622 3 is_stmt 1 view .LVU935 +1624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3162 .loc 1 1624 3 view .LVU936 +1624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3163 .loc 1 1624 11 is_stmt 0 view .LVU937 + 3164 0006 4120 movs r0, #65 + 3165 .LVL196: +1624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3166 .loc 1 1624 11 view .LVU938 + 3167 0008 205C ldrb r0, [r4, r0] +1624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3168 .loc 1 1624 6 view .LVU939 + 3169 000a 2028 cmp r0, #32 + 3170 000c 36D1 bne .L203 +1626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3171 .loc 1 1626 5 is_stmt 1 view .LVU940 +1626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3172 .loc 1 1626 9 is_stmt 0 view .LVU941 + 3173 000e 2068 ldr r0, [r4] + 3174 0010 8069 ldr r0, [r0, #24] +1626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3175 .loc 1 1626 8 view .LVU942 + 3176 0012 0004 lsls r0, r0, #16 + 3177 0014 34D4 bmi .L204 +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 190 + + + 3178 .loc 1 1632 5 is_stmt 1 view .LVU943 +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3179 .loc 1 1632 5 view .LVU944 + 3180 0016 4020 movs r0, #64 + 3181 0018 205C ldrb r0, [r4, r0] + 3182 001a 0128 cmp r0, #1 + 3183 001c 32D0 beq .L205 +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3184 .loc 1 1632 5 discriminator 2 view .LVU945 + 3185 001e 4020 movs r0, #64 + 3186 0020 0125 movs r5, #1 + 3187 0022 2554 strb r5, [r4, r0] +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3188 .loc 1 1632 5 discriminator 2 view .LVU946 +1634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3189 .loc 1 1634 5 discriminator 2 view .LVU947 +1634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3190 .loc 1 1634 23 is_stmt 0 discriminator 2 view .LVU948 + 3191 0024 0130 adds r0, r0, #1 + 3192 0026 2035 adds r5, r5, #32 + 3193 0028 2554 strb r5, [r4, r0] +1635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3194 .loc 1 1635 5 is_stmt 1 discriminator 2 view .LVU949 +1635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3195 .loc 1 1635 23 is_stmt 0 discriminator 2 view .LVU950 + 3196 002a 0130 adds r0, r0, #1 + 3197 002c 113D subs r5, r5, #17 + 3198 002e 2554 strb r5, [r4, r0] +1636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3199 .loc 1 1636 5 is_stmt 1 discriminator 2 view .LVU951 +1636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3200 .loc 1 1636 23 is_stmt 0 discriminator 2 view .LVU952 + 3201 0030 0020 movs r0, #0 + 3202 0032 6064 str r0, [r4, #68] +1639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3203 .loc 1 1639 5 is_stmt 1 discriminator 2 view .LVU953 +1639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3204 .loc 1 1639 23 is_stmt 0 discriminator 2 view .LVU954 + 3205 0034 6262 str r2, [r4, #36] +1640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3206 .loc 1 1640 5 is_stmt 1 discriminator 2 view .LVU955 +1640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3207 .loc 1 1640 23 is_stmt 0 discriminator 2 view .LVU956 + 3208 0036 6385 strh r3, [r4, #42] +1641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3209 .loc 1 1641 5 is_stmt 1 discriminator 2 view .LVU957 +1641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3210 .loc 1 1641 23 is_stmt 0 discriminator 2 view .LVU958 + 3211 0038 134B ldr r3, .L206 + 3212 .LVL197: +1641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3213 .loc 1 1641 23 discriminator 2 view .LVU959 + 3214 003a E362 str r3, [r4, #44] + 3215 .LVL198: +1642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3216 .loc 1 1642 5 is_stmt 1 discriminator 2 view .LVU960 +1642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 191 + + + 3217 .loc 1 1642 23 is_stmt 0 discriminator 2 view .LVU961 + 3218 003c 134B ldr r3, .L206+4 + 3219 003e 6363 str r3, [r4, #52] +1644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3220 .loc 1 1644 5 is_stmt 1 discriminator 2 view .LVU962 +1644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3221 .loc 1 1644 13 is_stmt 0 discriminator 2 view .LVU963 + 3222 0040 638D ldrh r3, [r4, #42] + 3223 0042 9BB2 uxth r3, r3 +1644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3224 .loc 1 1644 8 discriminator 2 view .LVU964 + 3225 0044 FF2B cmp r3, #255 + 3226 0046 14D9 bls .L201 +1646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3227 .loc 1 1646 7 is_stmt 1 view .LVU965 +1646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3228 .loc 1 1646 22 is_stmt 0 view .LVU966 + 3229 0048 FF23 movs r3, #255 + 3230 004a 2385 strh r3, [r4, #40] +1647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3231 .loc 1 1647 7 is_stmt 1 view .LVU967 + 3232 .LVL199: +1647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3233 .loc 1 1647 16 is_stmt 0 view .LVU968 + 3234 004c 8023 movs r3, #128 + 3235 004e 5B04 lsls r3, r3, #17 + 3236 .LVL200: + 3237 .L202: +1657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3238 .loc 1 1657 5 is_stmt 1 view .LVU969 +1657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3239 .loc 1 1657 55 is_stmt 0 view .LVU970 + 3240 0050 228D ldrh r2, [r4, #40] + 3241 .LVL201: +1657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3242 .loc 1 1657 5 view .LVU971 + 3243 0052 D2B2 uxtb r2, r2 + 3244 0054 0E48 ldr r0, .L206+8 + 3245 0056 0090 str r0, [sp] + 3246 .LVL202: +1657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3247 .loc 1 1657 5 view .LVU972 + 3248 0058 2000 movs r0, r4 + 3249 005a FFF7FEFF bl I2C_TransferConfig + 3250 .LVL203: +1660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3251 .loc 1 1660 5 is_stmt 1 view .LVU973 +1660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3252 .loc 1 1660 5 view .LVU974 + 3253 005e 4023 movs r3, #64 + 3254 0060 0022 movs r2, #0 + 3255 0062 E254 strb r2, [r4, r3] +1660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3256 .loc 1 1660 5 view .LVU975 +1670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3257 .loc 1 1670 5 view .LVU976 + 3258 0064 0121 movs r1, #1 + ARM GAS /tmp/ccth6daj.s page 192 + + + 3259 0066 2000 movs r0, r4 + 3260 0068 FFF7FEFF bl I2C_Enable_IRQ + 3261 .LVL204: +1672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3262 .loc 1 1672 5 view .LVU977 +1672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3263 .loc 1 1672 12 is_stmt 0 view .LVU978 + 3264 006c 0020 movs r0, #0 + 3265 .L200: +1678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3266 .loc 1 1678 1 view .LVU979 + 3267 006e 03B0 add sp, sp, #12 + 3268 @ sp needed + 3269 .LVL205: +1678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3270 .loc 1 1678 1 view .LVU980 + 3271 0070 30BD pop {r4, r5, pc} + 3272 .LVL206: + 3273 .L201: +1651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3274 .loc 1 1651 7 is_stmt 1 view .LVU981 +1651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3275 .loc 1 1651 28 is_stmt 0 view .LVU982 + 3276 0072 638D ldrh r3, [r4, #42] +1651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3277 .loc 1 1651 22 view .LVU983 + 3278 0074 2385 strh r3, [r4, #40] +1652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3279 .loc 1 1652 7 is_stmt 1 view .LVU984 + 3280 .LVL207: +1652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3281 .loc 1 1652 16 is_stmt 0 view .LVU985 + 3282 0076 8023 movs r3, #128 + 3283 0078 9B04 lsls r3, r3, #18 + 3284 007a E9E7 b .L202 + 3285 .LVL208: + 3286 .L203: +1676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3287 .loc 1 1676 12 view .LVU986 + 3288 007c 0220 movs r0, #2 + 3289 007e F6E7 b .L200 + 3290 .L204: +1628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3291 .loc 1 1628 14 view .LVU987 + 3292 0080 0220 movs r0, #2 + 3293 0082 F4E7 b .L200 + 3294 .L205: +1632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3295 .loc 1 1632 5 view .LVU988 + 3296 0084 0220 movs r0, #2 + 3297 0086 F2E7 b .L200 + 3298 .L207: + 3299 .align 2 + 3300 .L206: + 3301 0088 0000FFFF .word -65536 + 3302 008c 00000000 .word I2C_Master_ISR_IT + 3303 0090 00200080 .word -2147475456 + ARM GAS /tmp/ccth6daj.s page 193 + + + 3304 .cfi_endproc + 3305 .LFE305: + 3307 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 3308 .align 1 + 3309 .global HAL_I2C_Master_Receive_IT + 3310 .syntax unified + 3311 .code 16 + 3312 .thumb_func + 3313 .fpu softvfp + 3315 HAL_I2C_Master_Receive_IT: + 3316 .LVL209: + 3317 .LFB306: +1692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3318 .loc 1 1692 1 is_stmt 1 view -0 + 3319 .cfi_startproc + 3320 @ args = 0, pretend = 0, frame = 0 + 3321 @ frame_needed = 0, uses_anonymous_args = 0 +1692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3322 .loc 1 1692 1 is_stmt 0 view .LVU990 + 3323 0000 30B5 push {r4, r5, lr} + 3324 .LCFI26: + 3325 .cfi_def_cfa_offset 12 + 3326 .cfi_offset 4, -12 + 3327 .cfi_offset 5, -8 + 3328 .cfi_offset 14, -4 + 3329 0002 83B0 sub sp, sp, #12 + 3330 .LCFI27: + 3331 .cfi_def_cfa_offset 24 + 3332 0004 0400 movs r4, r0 +1693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3333 .loc 1 1693 3 is_stmt 1 view .LVU991 +1695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3334 .loc 1 1695 3 view .LVU992 +1695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3335 .loc 1 1695 11 is_stmt 0 view .LVU993 + 3336 0006 4120 movs r0, #65 + 3337 .LVL210: +1695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3338 .loc 1 1695 11 view .LVU994 + 3339 0008 205C ldrb r0, [r4, r0] +1695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3340 .loc 1 1695 6 view .LVU995 + 3341 000a 2028 cmp r0, #32 + 3342 000c 36D1 bne .L212 +1697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3343 .loc 1 1697 5 is_stmt 1 view .LVU996 +1697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3344 .loc 1 1697 9 is_stmt 0 view .LVU997 + 3345 000e 2068 ldr r0, [r4] + 3346 0010 8069 ldr r0, [r0, #24] +1697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3347 .loc 1 1697 8 view .LVU998 + 3348 0012 0004 lsls r0, r0, #16 + 3349 0014 34D4 bmi .L213 +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3350 .loc 1 1703 5 is_stmt 1 view .LVU999 +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 194 + + + 3351 .loc 1 1703 5 view .LVU1000 + 3352 0016 4020 movs r0, #64 + 3353 0018 205C ldrb r0, [r4, r0] + 3354 001a 0128 cmp r0, #1 + 3355 001c 32D0 beq .L214 +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3356 .loc 1 1703 5 discriminator 2 view .LVU1001 + 3357 001e 4020 movs r0, #64 + 3358 0020 0125 movs r5, #1 + 3359 0022 2554 strb r5, [r4, r0] +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3360 .loc 1 1703 5 discriminator 2 view .LVU1002 +1705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3361 .loc 1 1705 5 discriminator 2 view .LVU1003 +1705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3362 .loc 1 1705 23 is_stmt 0 discriminator 2 view .LVU1004 + 3363 0024 0130 adds r0, r0, #1 + 3364 0026 2135 adds r5, r5, #33 + 3365 0028 2554 strb r5, [r4, r0] +1706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3366 .loc 1 1706 5 is_stmt 1 discriminator 2 view .LVU1005 +1706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3367 .loc 1 1706 23 is_stmt 0 discriminator 2 view .LVU1006 + 3368 002a 0130 adds r0, r0, #1 + 3369 002c 123D subs r5, r5, #18 + 3370 002e 2554 strb r5, [r4, r0] +1707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3371 .loc 1 1707 5 is_stmt 1 discriminator 2 view .LVU1007 +1707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3372 .loc 1 1707 23 is_stmt 0 discriminator 2 view .LVU1008 + 3373 0030 0020 movs r0, #0 + 3374 0032 6064 str r0, [r4, #68] +1710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3375 .loc 1 1710 5 is_stmt 1 discriminator 2 view .LVU1009 +1710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3376 .loc 1 1710 23 is_stmt 0 discriminator 2 view .LVU1010 + 3377 0034 6262 str r2, [r4, #36] +1711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3378 .loc 1 1711 5 is_stmt 1 discriminator 2 view .LVU1011 +1711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3379 .loc 1 1711 23 is_stmt 0 discriminator 2 view .LVU1012 + 3380 0036 6385 strh r3, [r4, #42] +1712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3381 .loc 1 1712 5 is_stmt 1 discriminator 2 view .LVU1013 +1712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3382 .loc 1 1712 23 is_stmt 0 discriminator 2 view .LVU1014 + 3383 0038 134B ldr r3, .L215 + 3384 .LVL211: +1712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3385 .loc 1 1712 23 discriminator 2 view .LVU1015 + 3386 003a E362 str r3, [r4, #44] + 3387 .LVL212: +1713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3388 .loc 1 1713 5 is_stmt 1 discriminator 2 view .LVU1016 +1713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3389 .loc 1 1713 23 is_stmt 0 discriminator 2 view .LVU1017 + 3390 003c 134B ldr r3, .L215+4 + ARM GAS /tmp/ccth6daj.s page 195 + + + 3391 003e 6363 str r3, [r4, #52] +1715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3392 .loc 1 1715 5 is_stmt 1 discriminator 2 view .LVU1018 +1715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3393 .loc 1 1715 13 is_stmt 0 discriminator 2 view .LVU1019 + 3394 0040 638D ldrh r3, [r4, #42] + 3395 0042 9BB2 uxth r3, r3 +1715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3396 .loc 1 1715 8 discriminator 2 view .LVU1020 + 3397 0044 FF2B cmp r3, #255 + 3398 0046 14D9 bls .L210 +1717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3399 .loc 1 1717 7 is_stmt 1 view .LVU1021 +1717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3400 .loc 1 1717 22 is_stmt 0 view .LVU1022 + 3401 0048 FF23 movs r3, #255 + 3402 004a 2385 strh r3, [r4, #40] +1718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3403 .loc 1 1718 7 is_stmt 1 view .LVU1023 + 3404 .LVL213: +1718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3405 .loc 1 1718 16 is_stmt 0 view .LVU1024 + 3406 004c 8023 movs r3, #128 + 3407 004e 5B04 lsls r3, r3, #17 + 3408 .LVL214: + 3409 .L211: +1728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3410 .loc 1 1728 5 is_stmt 1 view .LVU1025 +1728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3411 .loc 1 1728 55 is_stmt 0 view .LVU1026 + 3412 0050 228D ldrh r2, [r4, #40] + 3413 .LVL215: +1728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3414 .loc 1 1728 5 view .LVU1027 + 3415 0052 D2B2 uxtb r2, r2 + 3416 0054 0E48 ldr r0, .L215+8 + 3417 0056 0090 str r0, [sp] + 3418 .LVL216: +1728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3419 .loc 1 1728 5 view .LVU1028 + 3420 0058 2000 movs r0, r4 + 3421 005a FFF7FEFF bl I2C_TransferConfig + 3422 .LVL217: +1731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3423 .loc 1 1731 5 is_stmt 1 view .LVU1029 +1731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3424 .loc 1 1731 5 view .LVU1030 + 3425 005e 4023 movs r3, #64 + 3426 0060 0022 movs r2, #0 + 3427 0062 E254 strb r2, [r4, r3] +1731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3428 .loc 1 1731 5 view .LVU1031 +1741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3429 .loc 1 1741 5 view .LVU1032 + 3430 0064 0221 movs r1, #2 + 3431 0066 2000 movs r0, r4 + 3432 0068 FFF7FEFF bl I2C_Enable_IRQ + ARM GAS /tmp/ccth6daj.s page 196 + + + 3433 .LVL218: +1743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3434 .loc 1 1743 5 view .LVU1033 +1743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3435 .loc 1 1743 12 is_stmt 0 view .LVU1034 + 3436 006c 0020 movs r0, #0 + 3437 .L209: +1749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3438 .loc 1 1749 1 view .LVU1035 + 3439 006e 03B0 add sp, sp, #12 + 3440 @ sp needed + 3441 .LVL219: +1749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3442 .loc 1 1749 1 view .LVU1036 + 3443 0070 30BD pop {r4, r5, pc} + 3444 .LVL220: + 3445 .L210: +1722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3446 .loc 1 1722 7 is_stmt 1 view .LVU1037 +1722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3447 .loc 1 1722 28 is_stmt 0 view .LVU1038 + 3448 0072 638D ldrh r3, [r4, #42] +1722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3449 .loc 1 1722 22 view .LVU1039 + 3450 0074 2385 strh r3, [r4, #40] +1723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3451 .loc 1 1723 7 is_stmt 1 view .LVU1040 + 3452 .LVL221: +1723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3453 .loc 1 1723 16 is_stmt 0 view .LVU1041 + 3454 0076 8023 movs r3, #128 + 3455 0078 9B04 lsls r3, r3, #18 + 3456 007a E9E7 b .L211 + 3457 .LVL222: + 3458 .L212: +1747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3459 .loc 1 1747 12 view .LVU1042 + 3460 007c 0220 movs r0, #2 + 3461 007e F6E7 b .L209 + 3462 .L213: +1699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3463 .loc 1 1699 14 view .LVU1043 + 3464 0080 0220 movs r0, #2 + 3465 0082 F4E7 b .L209 + 3466 .L214: +1703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3467 .loc 1 1703 5 view .LVU1044 + 3468 0084 0220 movs r0, #2 + 3469 0086 F2E7 b .L209 + 3470 .L216: + 3471 .align 2 + 3472 .L215: + 3473 0088 0000FFFF .word -65536 + 3474 008c 00000000 .word I2C_Master_ISR_IT + 3475 0090 00240080 .word -2147474432 + 3476 .cfi_endproc + 3477 .LFE306: + ARM GAS /tmp/ccth6daj.s page 197 + + + 3479 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 3480 .align 1 + 3481 .global HAL_I2C_Slave_Transmit_IT + 3482 .syntax unified + 3483 .code 16 + 3484 .thumb_func + 3485 .fpu softvfp + 3487 HAL_I2C_Slave_Transmit_IT: + 3488 .LVL223: + 3489 .LFB307: +1760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3490 .loc 1 1760 1 is_stmt 1 view -0 + 3491 .cfi_startproc + 3492 @ args = 0, pretend = 0, frame = 0 + 3493 @ frame_needed = 0, uses_anonymous_args = 0 +1760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3494 .loc 1 1760 1 is_stmt 0 view .LVU1046 + 3495 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3496 .LCFI28: + 3497 .cfi_def_cfa_offset 24 + 3498 .cfi_offset 3, -24 + 3499 .cfi_offset 4, -20 + 3500 .cfi_offset 5, -16 + 3501 .cfi_offset 6, -12 + 3502 .cfi_offset 7, -8 + 3503 .cfi_offset 14, -4 +1761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3504 .loc 1 1761 3 is_stmt 1 view .LVU1047 +1761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3505 .loc 1 1761 11 is_stmt 0 view .LVU1048 + 3506 0002 4123 movs r3, #65 + 3507 0004 C35C ldrb r3, [r0, r3] +1761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3508 .loc 1 1761 6 view .LVU1049 + 3509 0006 202B cmp r3, #32 + 3510 0008 21D1 bne .L219 +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3511 .loc 1 1764 5 is_stmt 1 view .LVU1050 +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3512 .loc 1 1764 5 view .LVU1051 + 3513 000a 2033 adds r3, r3, #32 + 3514 000c C35C ldrb r3, [r0, r3] + 3515 000e 012B cmp r3, #1 + 3516 0010 1FD0 beq .L220 +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3517 .loc 1 1764 5 discriminator 2 view .LVU1052 + 3518 0012 4024 movs r4, #64 + 3519 0014 0123 movs r3, #1 + 3520 0016 0355 strb r3, [r0, r4] +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3521 .loc 1 1764 5 discriminator 2 view .LVU1053 +1766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3522 .loc 1 1766 5 discriminator 2 view .LVU1054 +1766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3523 .loc 1 1766 23 is_stmt 0 discriminator 2 view .LVU1055 + 3524 0018 4033 adds r3, r3, #64 + 3525 001a 2125 movs r5, #33 + ARM GAS /tmp/ccth6daj.s page 198 + + + 3526 001c C554 strb r5, [r0, r3] +1767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3527 .loc 1 1767 5 is_stmt 1 discriminator 2 view .LVU1056 +1767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3528 .loc 1 1767 23 is_stmt 0 discriminator 2 view .LVU1057 + 3529 001e 0133 adds r3, r3, #1 + 3530 0020 013D subs r5, r5, #1 + 3531 0022 C554 strb r5, [r0, r3] +1768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3532 .loc 1 1768 5 is_stmt 1 discriminator 2 view .LVU1058 +1768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3533 .loc 1 1768 23 is_stmt 0 discriminator 2 view .LVU1059 + 3534 0024 0025 movs r5, #0 + 3535 0026 4564 str r5, [r0, #68] +1771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3536 .loc 1 1771 5 is_stmt 1 discriminator 2 view .LVU1060 +1771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3537 .loc 1 1771 9 is_stmt 0 discriminator 2 view .LVU1061 + 3538 0028 0668 ldr r6, [r0] +1771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3539 .loc 1 1771 25 discriminator 2 view .LVU1062 + 3540 002a 7368 ldr r3, [r6, #4] + 3541 002c 0A4F ldr r7, .L221 + 3542 002e 3B40 ands r3, r7 + 3543 0030 7360 str r3, [r6, #4] +1774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3544 .loc 1 1774 5 is_stmt 1 discriminator 2 view .LVU1063 +1774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3545 .loc 1 1774 23 is_stmt 0 discriminator 2 view .LVU1064 + 3546 0032 4162 str r1, [r0, #36] +1775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3547 .loc 1 1775 5 is_stmt 1 discriminator 2 view .LVU1065 +1775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3548 .loc 1 1775 23 is_stmt 0 discriminator 2 view .LVU1066 + 3549 0034 4285 strh r2, [r0, #42] +1776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3550 .loc 1 1776 5 is_stmt 1 discriminator 2 view .LVU1067 +1776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3551 .loc 1 1776 29 is_stmt 0 discriminator 2 view .LVU1068 + 3552 0036 438D ldrh r3, [r0, #42] +1776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3553 .loc 1 1776 23 discriminator 2 view .LVU1069 + 3554 0038 0385 strh r3, [r0, #40] +1777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3555 .loc 1 1777 5 is_stmt 1 discriminator 2 view .LVU1070 +1777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3556 .loc 1 1777 23 is_stmt 0 discriminator 2 view .LVU1071 + 3557 003a 084B ldr r3, .L221+4 + 3558 003c C362 str r3, [r0, #44] +1778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3559 .loc 1 1778 5 is_stmt 1 discriminator 2 view .LVU1072 +1778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3560 .loc 1 1778 23 is_stmt 0 discriminator 2 view .LVU1073 + 3561 003e 084B ldr r3, .L221+8 + 3562 0040 4363 str r3, [r0, #52] +1781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3563 .loc 1 1781 5 is_stmt 1 discriminator 2 view .LVU1074 + ARM GAS /tmp/ccth6daj.s page 199 + + +1781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3564 .loc 1 1781 5 discriminator 2 view .LVU1075 + 3565 0042 0555 strb r5, [r0, r4] +1781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3566 .loc 1 1781 5 discriminator 2 view .LVU1076 +1791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3567 .loc 1 1791 5 discriminator 2 view .LVU1077 + 3568 0044 0749 ldr r1, .L221+12 + 3569 .LVL224: +1791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3570 .loc 1 1791 5 is_stmt 0 discriminator 2 view .LVU1078 + 3571 0046 FFF7FEFF bl I2C_Enable_IRQ + 3572 .LVL225: +1793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3573 .loc 1 1793 5 is_stmt 1 discriminator 2 view .LVU1079 +1793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3574 .loc 1 1793 12 is_stmt 0 discriminator 2 view .LVU1080 + 3575 004a 0020 movs r0, #0 + 3576 .L218: +1799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3577 .loc 1 1799 1 view .LVU1081 + 3578 @ sp needed + 3579 004c F8BD pop {r3, r4, r5, r6, r7, pc} + 3580 .LVL226: + 3581 .L219: +1797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3582 .loc 1 1797 12 view .LVU1082 + 3583 004e 0220 movs r0, #2 + 3584 .LVL227: +1797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3585 .loc 1 1797 12 view .LVU1083 + 3586 0050 FCE7 b .L218 + 3587 .LVL228: + 3588 .L220: +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3589 .loc 1 1764 5 view .LVU1084 + 3590 0052 0220 movs r0, #2 + 3591 .LVL229: +1764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3592 .loc 1 1764 5 view .LVU1085 + 3593 0054 FAE7 b .L218 + 3594 .L222: + 3595 0056 C046 .align 2 + 3596 .L221: + 3597 0058 FF7FFFFF .word -32769 + 3598 005c 0000FFFF .word -65536 + 3599 0060 00000000 .word I2C_Slave_ISR_IT + 3600 0064 01800000 .word 32769 + 3601 .cfi_endproc + 3602 .LFE307: + 3604 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 3605 .align 1 + 3606 .global HAL_I2C_Slave_Receive_IT + 3607 .syntax unified + 3608 .code 16 + 3609 .thumb_func + 3610 .fpu softvfp + ARM GAS /tmp/ccth6daj.s page 200 + + + 3612 HAL_I2C_Slave_Receive_IT: + 3613 .LVL230: + 3614 .LFB308: +1810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3615 .loc 1 1810 1 is_stmt 1 view -0 + 3616 .cfi_startproc + 3617 @ args = 0, pretend = 0, frame = 0 + 3618 @ frame_needed = 0, uses_anonymous_args = 0 +1810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3619 .loc 1 1810 1 is_stmt 0 view .LVU1087 + 3620 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 3621 .LCFI29: + 3622 .cfi_def_cfa_offset 24 + 3623 .cfi_offset 3, -24 + 3624 .cfi_offset 4, -20 + 3625 .cfi_offset 5, -16 + 3626 .cfi_offset 6, -12 + 3627 .cfi_offset 7, -8 + 3628 .cfi_offset 14, -4 +1811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3629 .loc 1 1811 3 is_stmt 1 view .LVU1088 +1811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3630 .loc 1 1811 11 is_stmt 0 view .LVU1089 + 3631 0002 4123 movs r3, #65 + 3632 0004 C35C ldrb r3, [r0, r3] +1811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3633 .loc 1 1811 6 view .LVU1090 + 3634 0006 202B cmp r3, #32 + 3635 0008 21D1 bne .L225 +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3636 .loc 1 1814 5 is_stmt 1 view .LVU1091 +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3637 .loc 1 1814 5 view .LVU1092 + 3638 000a 2033 adds r3, r3, #32 + 3639 000c C35C ldrb r3, [r0, r3] + 3640 000e 012B cmp r3, #1 + 3641 0010 1FD0 beq .L226 +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3642 .loc 1 1814 5 discriminator 2 view .LVU1093 + 3643 0012 4024 movs r4, #64 + 3644 0014 0123 movs r3, #1 + 3645 0016 0355 strb r3, [r0, r4] +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3646 .loc 1 1814 5 discriminator 2 view .LVU1094 +1816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3647 .loc 1 1816 5 discriminator 2 view .LVU1095 +1816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3648 .loc 1 1816 23 is_stmt 0 discriminator 2 view .LVU1096 + 3649 0018 4033 adds r3, r3, #64 + 3650 001a 2225 movs r5, #34 + 3651 001c C554 strb r5, [r0, r3] +1817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3652 .loc 1 1817 5 is_stmt 1 discriminator 2 view .LVU1097 +1817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3653 .loc 1 1817 23 is_stmt 0 discriminator 2 view .LVU1098 + 3654 001e 0133 adds r3, r3, #1 + 3655 0020 023D subs r5, r5, #2 + ARM GAS /tmp/ccth6daj.s page 201 + + + 3656 0022 C554 strb r5, [r0, r3] +1818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3657 .loc 1 1818 5 is_stmt 1 discriminator 2 view .LVU1099 +1818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3658 .loc 1 1818 23 is_stmt 0 discriminator 2 view .LVU1100 + 3659 0024 0025 movs r5, #0 + 3660 0026 4564 str r5, [r0, #68] +1821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3661 .loc 1 1821 5 is_stmt 1 discriminator 2 view .LVU1101 +1821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3662 .loc 1 1821 9 is_stmt 0 discriminator 2 view .LVU1102 + 3663 0028 0668 ldr r6, [r0] +1821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3664 .loc 1 1821 25 discriminator 2 view .LVU1103 + 3665 002a 7368 ldr r3, [r6, #4] + 3666 002c 0A4F ldr r7, .L227 + 3667 002e 3B40 ands r3, r7 + 3668 0030 7360 str r3, [r6, #4] +1824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3669 .loc 1 1824 5 is_stmt 1 discriminator 2 view .LVU1104 +1824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3670 .loc 1 1824 23 is_stmt 0 discriminator 2 view .LVU1105 + 3671 0032 4162 str r1, [r0, #36] +1825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3672 .loc 1 1825 5 is_stmt 1 discriminator 2 view .LVU1106 +1825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3673 .loc 1 1825 23 is_stmt 0 discriminator 2 view .LVU1107 + 3674 0034 4285 strh r2, [r0, #42] +1826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3675 .loc 1 1826 5 is_stmt 1 discriminator 2 view .LVU1108 +1826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3676 .loc 1 1826 29 is_stmt 0 discriminator 2 view .LVU1109 + 3677 0036 438D ldrh r3, [r0, #42] +1826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3678 .loc 1 1826 23 discriminator 2 view .LVU1110 + 3679 0038 0385 strh r3, [r0, #40] +1827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3680 .loc 1 1827 5 is_stmt 1 discriminator 2 view .LVU1111 +1827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 3681 .loc 1 1827 23 is_stmt 0 discriminator 2 view .LVU1112 + 3682 003a 084B ldr r3, .L227+4 + 3683 003c C362 str r3, [r0, #44] +1828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3684 .loc 1 1828 5 is_stmt 1 discriminator 2 view .LVU1113 +1828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3685 .loc 1 1828 23 is_stmt 0 discriminator 2 view .LVU1114 + 3686 003e 084B ldr r3, .L227+8 + 3687 0040 4363 str r3, [r0, #52] +1831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3688 .loc 1 1831 5 is_stmt 1 discriminator 2 view .LVU1115 +1831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3689 .loc 1 1831 5 discriminator 2 view .LVU1116 + 3690 0042 0555 strb r5, [r0, r4] +1831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3691 .loc 1 1831 5 discriminator 2 view .LVU1117 +1841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3692 .loc 1 1841 5 discriminator 2 view .LVU1118 + ARM GAS /tmp/ccth6daj.s page 202 + + + 3693 0044 0749 ldr r1, .L227+12 + 3694 .LVL231: +1841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3695 .loc 1 1841 5 is_stmt 0 discriminator 2 view .LVU1119 + 3696 0046 FFF7FEFF bl I2C_Enable_IRQ + 3697 .LVL232: +1843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3698 .loc 1 1843 5 is_stmt 1 discriminator 2 view .LVU1120 +1843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3699 .loc 1 1843 12 is_stmt 0 discriminator 2 view .LVU1121 + 3700 004a 0020 movs r0, #0 + 3701 .L224: +1849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3702 .loc 1 1849 1 view .LVU1122 + 3703 @ sp needed + 3704 004c F8BD pop {r3, r4, r5, r6, r7, pc} + 3705 .LVL233: + 3706 .L225: +1847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3707 .loc 1 1847 12 view .LVU1123 + 3708 004e 0220 movs r0, #2 + 3709 .LVL234: +1847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3710 .loc 1 1847 12 view .LVU1124 + 3711 0050 FCE7 b .L224 + 3712 .LVL235: + 3713 .L226: +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3714 .loc 1 1814 5 view .LVU1125 + 3715 0052 0220 movs r0, #2 + 3716 .LVL236: +1814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3717 .loc 1 1814 5 view .LVU1126 + 3718 0054 FAE7 b .L224 + 3719 .L228: + 3720 0056 C046 .align 2 + 3721 .L227: + 3722 0058 FF7FFFFF .word -32769 + 3723 005c 0000FFFF .word -65536 + 3724 0060 00000000 .word I2C_Slave_ISR_IT + 3725 0064 02800000 .word 32770 + 3726 .cfi_endproc + 3727 .LFE308: + 3729 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 3730 .align 1 + 3731 .global HAL_I2C_Master_Transmit_DMA + 3732 .syntax unified + 3733 .code 16 + 3734 .thumb_func + 3735 .fpu softvfp + 3737 HAL_I2C_Master_Transmit_DMA: + 3738 .LVL237: + 3739 .LFB309: +1863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3740 .loc 1 1863 1 is_stmt 1 view -0 + 3741 .cfi_startproc + 3742 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccth6daj.s page 203 + + + 3743 @ frame_needed = 0, uses_anonymous_args = 0 +1863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 3744 .loc 1 1863 1 is_stmt 0 view .LVU1128 + 3745 0000 70B5 push {r4, r5, r6, lr} + 3746 .LCFI30: + 3747 .cfi_def_cfa_offset 16 + 3748 .cfi_offset 4, -16 + 3749 .cfi_offset 5, -12 + 3750 .cfi_offset 6, -8 + 3751 .cfi_offset 14, -4 + 3752 0002 82B0 sub sp, sp, #8 + 3753 .LCFI31: + 3754 .cfi_def_cfa_offset 24 + 3755 0004 0400 movs r4, r0 + 3756 0006 0D00 movs r5, r1 + 3757 0008 1000 movs r0, r2 + 3758 .LVL238: +1864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 3759 .loc 1 1864 3 is_stmt 1 view .LVU1129 +1865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3760 .loc 1 1865 3 view .LVU1130 +1867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3761 .loc 1 1867 3 view .LVU1131 +1867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3762 .loc 1 1867 11 is_stmt 0 view .LVU1132 + 3763 000a 4122 movs r2, #65 + 3764 .LVL239: +1867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3765 .loc 1 1867 11 view .LVU1133 + 3766 000c A25C ldrb r2, [r4, r2] +1867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3767 .loc 1 1867 6 view .LVU1134 + 3768 000e 202A cmp r2, #32 + 3769 0010 00D0 beq .LCB3548 + 3770 0012 8CE0 b .L238 @long jump + 3771 .LCB3548: +1869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3772 .loc 1 1869 5 is_stmt 1 view .LVU1135 +1869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3773 .loc 1 1869 9 is_stmt 0 view .LVU1136 + 3774 0014 2268 ldr r2, [r4] + 3775 0016 9269 ldr r2, [r2, #24] +1869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3776 .loc 1 1869 8 view .LVU1137 + 3777 0018 1204 lsls r2, r2, #16 + 3778 001a 00D5 bpl .LCB3555 + 3779 001c 8AE0 b .L239 @long jump + 3780 .LCB3555: +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3781 .loc 1 1875 5 is_stmt 1 view .LVU1138 +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3782 .loc 1 1875 5 view .LVU1139 + 3783 001e 4022 movs r2, #64 + 3784 0020 A25C ldrb r2, [r4, r2] + 3785 0022 012A cmp r2, #1 + 3786 0024 00D1 bne .LCB3561 + 3787 0026 87E0 b .L240 @long jump + ARM GAS /tmp/ccth6daj.s page 204 + + + 3788 .LCB3561: +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3789 .loc 1 1875 5 discriminator 2 view .LVU1140 + 3790 0028 4022 movs r2, #64 + 3791 002a 0121 movs r1, #1 + 3792 .LVL240: +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3793 .loc 1 1875 5 is_stmt 0 discriminator 2 view .LVU1141 + 3794 002c A154 strb r1, [r4, r2] +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3795 .loc 1 1875 5 is_stmt 1 discriminator 2 view .LVU1142 +1877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3796 .loc 1 1877 5 discriminator 2 view .LVU1143 +1877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 3797 .loc 1 1877 23 is_stmt 0 discriminator 2 view .LVU1144 + 3798 002e 0132 adds r2, r2, #1 + 3799 0030 2031 adds r1, r1, #32 + 3800 0032 A154 strb r1, [r4, r2] +1878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3801 .loc 1 1878 5 is_stmt 1 discriminator 2 view .LVU1145 +1878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3802 .loc 1 1878 23 is_stmt 0 discriminator 2 view .LVU1146 + 3803 0034 0132 adds r2, r2, #1 + 3804 0036 1139 subs r1, r1, #17 + 3805 0038 A154 strb r1, [r4, r2] +1879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3806 .loc 1 1879 5 is_stmt 1 discriminator 2 view .LVU1147 +1879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3807 .loc 1 1879 23 is_stmt 0 discriminator 2 view .LVU1148 + 3808 003a 0022 movs r2, #0 + 3809 003c 6264 str r2, [r4, #68] +1882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3810 .loc 1 1882 5 is_stmt 1 discriminator 2 view .LVU1149 +1882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 3811 .loc 1 1882 23 is_stmt 0 discriminator 2 view .LVU1150 + 3812 003e 6062 str r0, [r4, #36] +1883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3813 .loc 1 1883 5 is_stmt 1 discriminator 2 view .LVU1151 +1883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3814 .loc 1 1883 23 is_stmt 0 discriminator 2 view .LVU1152 + 3815 0040 6385 strh r3, [r4, #42] +1884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3816 .loc 1 1884 5 is_stmt 1 discriminator 2 view .LVU1153 +1884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3817 .loc 1 1884 23 is_stmt 0 discriminator 2 view .LVU1154 + 3818 0042 3E4B ldr r3, .L243 + 3819 .LVL241: +1884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 3820 .loc 1 1884 23 discriminator 2 view .LVU1155 + 3821 0044 E362 str r3, [r4, #44] + 3822 .LVL242: +1885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3823 .loc 1 1885 5 is_stmt 1 discriminator 2 view .LVU1156 +1885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3824 .loc 1 1885 23 is_stmt 0 discriminator 2 view .LVU1157 + 3825 0046 3E4B ldr r3, .L243+4 + 3826 0048 6363 str r3, [r4, #52] + ARM GAS /tmp/ccth6daj.s page 205 + + +1887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3827 .loc 1 1887 5 is_stmt 1 discriminator 2 view .LVU1158 +1887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3828 .loc 1 1887 13 is_stmt 0 discriminator 2 view .LVU1159 + 3829 004a 638D ldrh r3, [r4, #42] + 3830 004c 9BB2 uxth r3, r3 +1887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3831 .loc 1 1887 8 discriminator 2 view .LVU1160 + 3832 004e FF2B cmp r3, #255 + 3833 0050 2AD9 bls .L231 +1889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3834 .loc 1 1889 7 is_stmt 1 view .LVU1161 +1889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 3835 .loc 1 1889 22 is_stmt 0 view .LVU1162 + 3836 0052 FF23 movs r3, #255 + 3837 0054 2385 strh r3, [r4, #40] +1890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3838 .loc 1 1890 7 is_stmt 1 view .LVU1163 + 3839 .LVL243: +1890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3840 .loc 1 1890 16 is_stmt 0 view .LVU1164 + 3841 0056 8026 movs r6, #128 + 3842 0058 7604 lsls r6, r6, #17 + 3843 .LVL244: + 3844 .L232: +1898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3845 .loc 1 1898 5 is_stmt 1 view .LVU1165 +1898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3846 .loc 1 1898 13 is_stmt 0 view .LVU1166 + 3847 005a 228D ldrh r2, [r4, #40] +1898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3848 .loc 1 1898 8 view .LVU1167 + 3849 005c 002A cmp r2, #0 + 3850 005e 52D0 beq .L233 +1900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3851 .loc 1 1900 7 is_stmt 1 view .LVU1168 +1900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3852 .loc 1 1900 15 is_stmt 0 view .LVU1169 + 3853 0060 A36B ldr r3, [r4, #56] +1900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3854 .loc 1 1900 10 view .LVU1170 + 3855 0062 002B cmp r3, #0 + 3856 0064 25D0 beq .L234 +1903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3857 .loc 1 1903 9 is_stmt 1 view .LVU1171 +1903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3858 .loc 1 1903 40 is_stmt 0 view .LVU1172 + 3859 0066 374A ldr r2, .L243+8 + 3860 0068 DA62 str r2, [r3, #44] +1906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3861 .loc 1 1906 9 is_stmt 1 view .LVU1173 +1906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3862 .loc 1 1906 13 is_stmt 0 view .LVU1174 + 3863 006a A36B ldr r3, [r4, #56] +1906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3864 .loc 1 1906 41 view .LVU1175 + 3865 006c 364A ldr r2, .L243+12 + ARM GAS /tmp/ccth6daj.s page 206 + + + 3866 006e 5A63 str r2, [r3, #52] +1909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3867 .loc 1 1909 9 is_stmt 1 view .LVU1176 +1909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3868 .loc 1 1909 13 is_stmt 0 view .LVU1177 + 3869 0070 A26B ldr r2, [r4, #56] +1909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3870 .loc 1 1909 44 view .LVU1178 + 3871 0072 0023 movs r3, #0 + 3872 0074 1363 str r3, [r2, #48] +1910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3873 .loc 1 1910 9 is_stmt 1 view .LVU1179 +1910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3874 .loc 1 1910 13 is_stmt 0 view .LVU1180 + 3875 0076 A26B ldr r2, [r4, #56] +1910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3876 .loc 1 1910 41 view .LVU1181 + 3877 0078 9363 str r3, [r2, #56] +1913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 3878 .loc 1 1913 9 is_stmt 1 view .LVU1182 +1913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 3879 .loc 1 1913 83 is_stmt 0 view .LVU1183 + 3880 007a 2268 ldr r2, [r4] + 3881 007c 2832 adds r2, r2, #40 +1914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3882 .loc 1 1914 46 view .LVU1184 + 3883 007e 238D ldrh r3, [r4, #40] +1913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 3884 .loc 1 1913 25 view .LVU1185 + 3885 0080 0100 movs r1, r0 + 3886 0082 A06B ldr r0, [r4, #56] + 3887 .LVL245: +1913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 3888 .loc 1 1913 25 view .LVU1186 + 3889 0084 FFF7FEFF bl HAL_DMA_Start_IT + 3890 .LVL246: +1931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3891 .loc 1 1931 7 is_stmt 1 view .LVU1187 +1931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 3892 .loc 1 1931 10 is_stmt 0 view .LVU1188 + 3893 0088 0028 cmp r0, #0 + 3894 008a 20D0 beq .L242 +1955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3895 .loc 1 1955 9 is_stmt 1 view .LVU1189 +1955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3896 .loc 1 1955 25 is_stmt 0 view .LVU1190 + 3897 008c 4123 movs r3, #65 + 3898 008e 2022 movs r2, #32 + 3899 0090 E254 strb r2, [r4, r3] +1956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3900 .loc 1 1956 9 is_stmt 1 view .LVU1191 +1956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3901 .loc 1 1956 25 is_stmt 0 view .LVU1192 + 3902 0092 0022 movs r2, #0 + 3903 0094 0133 adds r3, r3, #1 + 3904 0096 E254 strb r2, [r4, r3] +1959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 207 + + + 3905 .loc 1 1959 9 is_stmt 1 view .LVU1193 +1959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3906 .loc 1 1959 25 is_stmt 0 view .LVU1194 + 3907 0098 636C ldr r3, [r4, #68] + 3908 009a 1021 movs r1, #16 + 3909 009c 0B43 orrs r3, r1 + 3910 009e 6364 str r3, [r4, #68] +1962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3911 .loc 1 1962 9 is_stmt 1 view .LVU1195 +1962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3912 .loc 1 1962 9 view .LVU1196 + 3913 00a0 4023 movs r3, #64 + 3914 00a2 E254 strb r2, [r4, r3] +1962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3915 .loc 1 1962 9 view .LVU1197 +1964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3916 .loc 1 1964 9 view .LVU1198 +1964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3917 .loc 1 1964 16 is_stmt 0 view .LVU1199 + 3918 00a4 0120 movs r0, #1 + 3919 .LVL247: +1964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3920 .loc 1 1964 16 view .LVU1200 + 3921 00a6 43E0 b .L230 + 3922 .LVL248: + 3923 .L231: +1894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3924 .loc 1 1894 7 is_stmt 1 view .LVU1201 +1894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3925 .loc 1 1894 28 is_stmt 0 view .LVU1202 + 3926 00a8 638D ldrh r3, [r4, #42] +1894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 3927 .loc 1 1894 22 view .LVU1203 + 3928 00aa 2385 strh r3, [r4, #40] +1895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3929 .loc 1 1895 7 is_stmt 1 view .LVU1204 + 3930 .LVL249: +1895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3931 .loc 1 1895 16 is_stmt 0 view .LVU1205 + 3932 00ac 8026 movs r6, #128 + 3933 00ae B604 lsls r6, r6, #18 + 3934 00b0 D3E7 b .L232 + 3935 .LVL250: + 3936 .L234: +1919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3937 .loc 1 1919 9 is_stmt 1 view .LVU1206 +1919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3938 .loc 1 1919 25 is_stmt 0 view .LVU1207 + 3939 00b2 4123 movs r3, #65 + 3940 00b4 2022 movs r2, #32 + 3941 00b6 E254 strb r2, [r4, r3] +1920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3942 .loc 1 1920 9 is_stmt 1 view .LVU1208 +1920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3943 .loc 1 1920 25 is_stmt 0 view .LVU1209 + 3944 00b8 0022 movs r2, #0 + 3945 00ba 0133 adds r3, r3, #1 + ARM GAS /tmp/ccth6daj.s page 208 + + + 3946 00bc E254 strb r2, [r4, r3] +1923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3947 .loc 1 1923 9 is_stmt 1 view .LVU1210 +1923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3948 .loc 1 1923 25 is_stmt 0 view .LVU1211 + 3949 00be 636C ldr r3, [r4, #68] + 3950 00c0 8021 movs r1, #128 + 3951 00c2 0B43 orrs r3, r1 + 3952 00c4 6364 str r3, [r4, #68] +1926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3953 .loc 1 1926 9 is_stmt 1 view .LVU1212 +1926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3954 .loc 1 1926 9 view .LVU1213 + 3955 00c6 4023 movs r3, #64 + 3956 00c8 E254 strb r2, [r4, r3] +1926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3957 .loc 1 1926 9 view .LVU1214 +1928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3958 .loc 1 1928 9 view .LVU1215 +1928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3959 .loc 1 1928 16 is_stmt 0 view .LVU1216 + 3960 00ca 0120 movs r0, #1 + 3961 .LVL251: +1928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 3962 .loc 1 1928 16 view .LVU1217 + 3963 00cc 30E0 b .L230 + 3964 .LVL252: + 3965 .L242: +1935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3966 .loc 1 1935 9 is_stmt 1 view .LVU1218 +1935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3967 .loc 1 1935 59 is_stmt 0 view .LVU1219 + 3968 00ce 228D ldrh r2, [r4, #40] +1935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3969 .loc 1 1935 9 view .LVU1220 + 3970 00d0 D2B2 uxtb r2, r2 + 3971 00d2 1E4B ldr r3, .L243+16 + 3972 00d4 0093 str r3, [sp] + 3973 00d6 3300 movs r3, r6 + 3974 00d8 2900 movs r1, r5 + 3975 00da 2000 movs r0, r4 + 3976 .LVL253: +1935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3977 .loc 1 1935 9 view .LVU1221 + 3978 00dc FFF7FEFF bl I2C_TransferConfig + 3979 .LVL254: +1938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3980 .loc 1 1938 9 is_stmt 1 view .LVU1222 +1938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3981 .loc 1 1938 25 is_stmt 0 view .LVU1223 + 3982 00e0 638D ldrh r3, [r4, #42] +1938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3983 .loc 1 1938 32 view .LVU1224 + 3984 00e2 228D ldrh r2, [r4, #40] +1938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3985 .loc 1 1938 25 view .LVU1225 + 3986 00e4 9B1A subs r3, r3, r2 + ARM GAS /tmp/ccth6daj.s page 209 + + + 3987 00e6 9BB2 uxth r3, r3 + 3988 00e8 6385 strh r3, [r4, #42] +1941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3989 .loc 1 1941 9 is_stmt 1 view .LVU1226 +1941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3990 .loc 1 1941 9 view .LVU1227 + 3991 00ea 4023 movs r3, #64 + 3992 00ec 0022 movs r2, #0 + 3993 00ee E254 strb r2, [r4, r3] +1941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3994 .loc 1 1941 9 view .LVU1228 +1947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 3995 .loc 1 1947 9 view .LVU1229 + 3996 00f0 1021 movs r1, #16 + 3997 00f2 2000 movs r0, r4 + 3998 00f4 FFF7FEFF bl I2C_Enable_IRQ + 3999 .LVL255: +1950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4000 .loc 1 1950 9 view .LVU1230 +1950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4001 .loc 1 1950 13 is_stmt 0 view .LVU1231 + 4002 00f8 2268 ldr r2, [r4] +1950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4003 .loc 1 1950 29 view .LVU1232 + 4004 00fa 1168 ldr r1, [r2] + 4005 00fc 8023 movs r3, #128 + 4006 00fe DB01 lsls r3, r3, #7 + 4007 0100 0B43 orrs r3, r1 + 4008 0102 1360 str r3, [r2] + 4009 0104 11E0 b .L237 + 4010 .LVL256: + 4011 .L233: +1970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4012 .loc 1 1970 7 is_stmt 1 view .LVU1233 +1970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4013 .loc 1 1970 21 is_stmt 0 view .LVU1234 + 4014 0106 124B ldr r3, .L243+20 + 4015 0108 6363 str r3, [r4, #52] +1974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 4016 .loc 1 1974 7 is_stmt 1 view .LVU1235 + 4017 010a 8023 movs r3, #128 + 4018 010c D2B2 uxtb r2, r2 + 4019 010e 0F49 ldr r1, .L243+16 + 4020 0110 0091 str r1, [sp] + 4021 0112 9B04 lsls r3, r3, #18 + 4022 0114 2900 movs r1, r5 + 4023 0116 2000 movs r0, r4 + 4024 .LVL257: +1974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 4025 .loc 1 1974 7 is_stmt 0 view .LVU1236 + 4026 0118 FFF7FEFF bl I2C_TransferConfig + 4027 .LVL258: +1978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4028 .loc 1 1978 7 is_stmt 1 view .LVU1237 +1978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4029 .loc 1 1978 7 view .LVU1238 + 4030 011c 4023 movs r3, #64 + ARM GAS /tmp/ccth6daj.s page 210 + + + 4031 011e 0022 movs r2, #0 + 4032 0120 E254 strb r2, [r4, r3] +1978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4033 .loc 1 1978 7 view .LVU1239 +1987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4034 .loc 1 1987 7 view .LVU1240 + 4035 0122 0121 movs r1, #1 + 4036 0124 2000 movs r0, r4 + 4037 0126 FFF7FEFF bl I2C_Enable_IRQ + 4038 .LVL259: + 4039 .L237: +1990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4040 .loc 1 1990 5 view .LVU1241 +1990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4041 .loc 1 1990 12 is_stmt 0 view .LVU1242 + 4042 012a 0020 movs r0, #0 + 4043 012c 00E0 b .L230 + 4044 .LVL260: + 4045 .L238: +1994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4046 .loc 1 1994 12 view .LVU1243 + 4047 012e 0220 movs r0, #2 + 4048 .LVL261: + 4049 .L230: +1996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4050 .loc 1 1996 1 view .LVU1244 + 4051 0130 02B0 add sp, sp, #8 + 4052 @ sp needed + 4053 .LVL262: +1996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4054 .loc 1 1996 1 view .LVU1245 + 4055 0132 70BD pop {r4, r5, r6, pc} + 4056 .LVL263: + 4057 .L239: +1871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4058 .loc 1 1871 14 view .LVU1246 + 4059 0134 0220 movs r0, #2 + 4060 .LVL264: +1871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4061 .loc 1 1871 14 view .LVU1247 + 4062 0136 FBE7 b .L230 + 4063 .LVL265: + 4064 .L240: +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4065 .loc 1 1875 5 view .LVU1248 + 4066 0138 0220 movs r0, #2 + 4067 .LVL266: +1875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4068 .loc 1 1875 5 view .LVU1249 + 4069 013a F9E7 b .L230 + 4070 .L244: + 4071 .align 2 + 4072 .L243: + 4073 013c 0000FFFF .word -65536 + 4074 0140 00000000 .word I2C_Master_ISR_DMA + 4075 0144 00000000 .word I2C_DMAMasterTransmitCplt + 4076 0148 00000000 .word I2C_DMAError + ARM GAS /tmp/ccth6daj.s page 211 + + + 4077 014c 00200080 .word -2147475456 + 4078 0150 00000000 .word I2C_Master_ISR_IT + 4079 .cfi_endproc + 4080 .LFE309: + 4082 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 4083 .align 1 + 4084 .global HAL_I2C_Master_Receive_DMA + 4085 .syntax unified + 4086 .code 16 + 4087 .thumb_func + 4088 .fpu softvfp + 4090 HAL_I2C_Master_Receive_DMA: + 4091 .LVL267: + 4092 .LFB310: +2010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 4093 .loc 1 2010 1 is_stmt 1 view -0 + 4094 .cfi_startproc + 4095 @ args = 0, pretend = 0, frame = 0 + 4096 @ frame_needed = 0, uses_anonymous_args = 0 +2010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 4097 .loc 1 2010 1 is_stmt 0 view .LVU1251 + 4098 0000 70B5 push {r4, r5, r6, lr} + 4099 .LCFI32: + 4100 .cfi_def_cfa_offset 16 + 4101 .cfi_offset 4, -16 + 4102 .cfi_offset 5, -12 + 4103 .cfi_offset 6, -8 + 4104 .cfi_offset 14, -4 + 4105 0002 82B0 sub sp, sp, #8 + 4106 .LCFI33: + 4107 .cfi_def_cfa_offset 24 + 4108 0004 0400 movs r4, r0 + 4109 0006 0D00 movs r5, r1 +2011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4110 .loc 1 2011 3 is_stmt 1 view .LVU1252 +2012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4111 .loc 1 2012 3 view .LVU1253 +2014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4112 .loc 1 2014 3 view .LVU1254 +2014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4113 .loc 1 2014 11 is_stmt 0 view .LVU1255 + 4114 0008 4121 movs r1, #65 + 4115 .LVL268: +2014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4116 .loc 1 2014 11 view .LVU1256 + 4117 000a 415C ldrb r1, [r0, r1] +2014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4118 .loc 1 2014 6 view .LVU1257 + 4119 000c 2029 cmp r1, #32 + 4120 000e 00D0 beq .LCB3869 + 4121 0010 8BE0 b .L254 @long jump + 4122 .LCB3869: +2016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4123 .loc 1 2016 5 is_stmt 1 view .LVU1258 +2016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4124 .loc 1 2016 9 is_stmt 0 view .LVU1259 + 4125 0012 0168 ldr r1, [r0] + ARM GAS /tmp/ccth6daj.s page 212 + + + 4126 0014 8969 ldr r1, [r1, #24] +2016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4127 .loc 1 2016 8 view .LVU1260 + 4128 0016 0904 lsls r1, r1, #16 + 4129 0018 00D5 bpl .LCB3876 + 4130 001a 89E0 b .L255 @long jump + 4131 .LCB3876: +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4132 .loc 1 2022 5 is_stmt 1 view .LVU1261 +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4133 .loc 1 2022 5 view .LVU1262 + 4134 001c 4021 movs r1, #64 + 4135 001e 415C ldrb r1, [r0, r1] + 4136 0020 0129 cmp r1, #1 + 4137 0022 00D1 bne .LCB3882 + 4138 0024 86E0 b .L256 @long jump + 4139 .LCB3882: +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4140 .loc 1 2022 5 discriminator 2 view .LVU1263 + 4141 0026 4021 movs r1, #64 + 4142 0028 0120 movs r0, #1 + 4143 .LVL269: +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4144 .loc 1 2022 5 is_stmt 0 discriminator 2 view .LVU1264 + 4145 002a 6054 strb r0, [r4, r1] +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4146 .loc 1 2022 5 is_stmt 1 discriminator 2 view .LVU1265 +2024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4147 .loc 1 2024 5 discriminator 2 view .LVU1266 +2024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 4148 .loc 1 2024 23 is_stmt 0 discriminator 2 view .LVU1267 + 4149 002c 0131 adds r1, r1, #1 + 4150 002e 2130 adds r0, r0, #33 + 4151 0030 6054 strb r0, [r4, r1] +2025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4152 .loc 1 2025 5 is_stmt 1 discriminator 2 view .LVU1268 +2025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4153 .loc 1 2025 23 is_stmt 0 discriminator 2 view .LVU1269 + 4154 0032 0131 adds r1, r1, #1 + 4155 0034 1238 subs r0, r0, #18 + 4156 0036 6054 strb r0, [r4, r1] +2026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4157 .loc 1 2026 5 is_stmt 1 discriminator 2 view .LVU1270 +2026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4158 .loc 1 2026 23 is_stmt 0 discriminator 2 view .LVU1271 + 4159 0038 0021 movs r1, #0 + 4160 003a 6164 str r1, [r4, #68] +2029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4161 .loc 1 2029 5 is_stmt 1 discriminator 2 view .LVU1272 +2029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4162 .loc 1 2029 23 is_stmt 0 discriminator 2 view .LVU1273 + 4163 003c 6262 str r2, [r4, #36] +2030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4164 .loc 1 2030 5 is_stmt 1 discriminator 2 view .LVU1274 +2030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4165 .loc 1 2030 23 is_stmt 0 discriminator 2 view .LVU1275 + 4166 003e 6385 strh r3, [r4, #42] + ARM GAS /tmp/ccth6daj.s page 213 + + +2031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4167 .loc 1 2031 5 is_stmt 1 discriminator 2 view .LVU1276 +2031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4168 .loc 1 2031 23 is_stmt 0 discriminator 2 view .LVU1277 + 4169 0040 3D4B ldr r3, .L259 + 4170 .LVL270: +2031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 4171 .loc 1 2031 23 discriminator 2 view .LVU1278 + 4172 0042 E362 str r3, [r4, #44] + 4173 .LVL271: +2032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4174 .loc 1 2032 5 is_stmt 1 discriminator 2 view .LVU1279 +2032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4175 .loc 1 2032 23 is_stmt 0 discriminator 2 view .LVU1280 + 4176 0044 3D4B ldr r3, .L259+4 + 4177 0046 6363 str r3, [r4, #52] +2034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4178 .loc 1 2034 5 is_stmt 1 discriminator 2 view .LVU1281 +2034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4179 .loc 1 2034 13 is_stmt 0 discriminator 2 view .LVU1282 + 4180 0048 638D ldrh r3, [r4, #42] + 4181 004a 9BB2 uxth r3, r3 +2034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4182 .loc 1 2034 8 discriminator 2 view .LVU1283 + 4183 004c FF2B cmp r3, #255 + 4184 004e 29D9 bls .L247 +2036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4185 .loc 1 2036 7 is_stmt 1 view .LVU1284 +2036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 4186 .loc 1 2036 22 is_stmt 0 view .LVU1285 + 4187 0050 FF23 movs r3, #255 + 4188 0052 2385 strh r3, [r4, #40] +2037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4189 .loc 1 2037 7 is_stmt 1 view .LVU1286 + 4190 .LVL272: +2037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4191 .loc 1 2037 16 is_stmt 0 view .LVU1287 + 4192 0054 8026 movs r6, #128 + 4193 0056 7604 lsls r6, r6, #17 + 4194 .LVL273: + 4195 .L248: +2045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4196 .loc 1 2045 5 is_stmt 1 view .LVU1288 +2045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4197 .loc 1 2045 13 is_stmt 0 view .LVU1289 + 4198 0058 218D ldrh r1, [r4, #40] +2045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4199 .loc 1 2045 8 view .LVU1290 + 4200 005a 0029 cmp r1, #0 + 4201 005c 51D0 beq .L249 +2047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4202 .loc 1 2047 7 is_stmt 1 view .LVU1291 +2047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4203 .loc 1 2047 15 is_stmt 0 view .LVU1292 + 4204 005e E36B ldr r3, [r4, #60] +2047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4205 .loc 1 2047 10 view .LVU1293 + ARM GAS /tmp/ccth6daj.s page 214 + + + 4206 0060 002B cmp r3, #0 + 4207 0062 24D0 beq .L250 +2050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4208 .loc 1 2050 9 is_stmt 1 view .LVU1294 +2050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4209 .loc 1 2050 40 is_stmt 0 view .LVU1295 + 4210 0064 3649 ldr r1, .L259+8 + 4211 0066 D962 str r1, [r3, #44] +2053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4212 .loc 1 2053 9 is_stmt 1 view .LVU1296 +2053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4213 .loc 1 2053 13 is_stmt 0 view .LVU1297 + 4214 0068 E36B ldr r3, [r4, #60] +2053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4215 .loc 1 2053 41 view .LVU1298 + 4216 006a 3649 ldr r1, .L259+12 + 4217 006c 5963 str r1, [r3, #52] +2056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4218 .loc 1 2056 9 is_stmt 1 view .LVU1299 +2056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4219 .loc 1 2056 13 is_stmt 0 view .LVU1300 + 4220 006e E16B ldr r1, [r4, #60] +2056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4221 .loc 1 2056 44 view .LVU1301 + 4222 0070 0023 movs r3, #0 + 4223 0072 0B63 str r3, [r1, #48] +2057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4224 .loc 1 2057 9 is_stmt 1 view .LVU1302 +2057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4225 .loc 1 2057 13 is_stmt 0 view .LVU1303 + 4226 0074 E16B ldr r1, [r4, #60] +2057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4227 .loc 1 2057 41 view .LVU1304 + 4228 0076 8B63 str r3, [r1, #56] +2060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4229 .loc 1 2060 9 is_stmt 1 view .LVU1305 +2060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4230 .loc 1 2060 66 is_stmt 0 view .LVU1306 + 4231 0078 2168 ldr r1, [r4] + 4232 007a 2431 adds r1, r1, #36 +2061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4233 .loc 1 2061 46 view .LVU1307 + 4234 007c 238D ldrh r3, [r4, #40] +2060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4235 .loc 1 2060 25 view .LVU1308 + 4236 007e E06B ldr r0, [r4, #60] + 4237 0080 FFF7FEFF bl HAL_DMA_Start_IT + 4238 .LVL274: +2078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4239 .loc 1 2078 7 is_stmt 1 view .LVU1309 +2078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4240 .loc 1 2078 10 is_stmt 0 view .LVU1310 + 4241 0084 0028 cmp r0, #0 + 4242 0086 20D0 beq .L258 +2102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4243 .loc 1 2102 9 is_stmt 1 view .LVU1311 +2102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccth6daj.s page 215 + + + 4244 .loc 1 2102 25 is_stmt 0 view .LVU1312 + 4245 0088 4123 movs r3, #65 + 4246 008a 2022 movs r2, #32 + 4247 008c E254 strb r2, [r4, r3] +2103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4248 .loc 1 2103 9 is_stmt 1 view .LVU1313 +2103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4249 .loc 1 2103 25 is_stmt 0 view .LVU1314 + 4250 008e 0022 movs r2, #0 + 4251 0090 0133 adds r3, r3, #1 + 4252 0092 E254 strb r2, [r4, r3] +2106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4253 .loc 1 2106 9 is_stmt 1 view .LVU1315 +2106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4254 .loc 1 2106 25 is_stmt 0 view .LVU1316 + 4255 0094 636C ldr r3, [r4, #68] + 4256 0096 1021 movs r1, #16 + 4257 0098 0B43 orrs r3, r1 + 4258 009a 6364 str r3, [r4, #68] +2109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4259 .loc 1 2109 9 is_stmt 1 view .LVU1317 +2109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4260 .loc 1 2109 9 view .LVU1318 + 4261 009c 4023 movs r3, #64 + 4262 009e E254 strb r2, [r4, r3] +2109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4263 .loc 1 2109 9 view .LVU1319 +2111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4264 .loc 1 2111 9 view .LVU1320 +2111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4265 .loc 1 2111 16 is_stmt 0 view .LVU1321 + 4266 00a0 0120 movs r0, #1 + 4267 .LVL275: +2111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4268 .loc 1 2111 16 view .LVU1322 + 4269 00a2 43E0 b .L246 + 4270 .LVL276: + 4271 .L247: +2041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4272 .loc 1 2041 7 is_stmt 1 view .LVU1323 +2041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4273 .loc 1 2041 28 is_stmt 0 view .LVU1324 + 4274 00a4 638D ldrh r3, [r4, #42] +2041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 4275 .loc 1 2041 22 view .LVU1325 + 4276 00a6 2385 strh r3, [r4, #40] +2042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4277 .loc 1 2042 7 is_stmt 1 view .LVU1326 + 4278 .LVL277: +2042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4279 .loc 1 2042 16 is_stmt 0 view .LVU1327 + 4280 00a8 8026 movs r6, #128 + 4281 00aa B604 lsls r6, r6, #18 + 4282 00ac D4E7 b .L248 + 4283 .LVL278: + 4284 .L250: +2066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccth6daj.s page 216 + + + 4285 .loc 1 2066 9 is_stmt 1 view .LVU1328 +2066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4286 .loc 1 2066 25 is_stmt 0 view .LVU1329 + 4287 00ae 4123 movs r3, #65 + 4288 00b0 2022 movs r2, #32 + 4289 .LVL279: +2066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4290 .loc 1 2066 25 view .LVU1330 + 4291 00b2 E254 strb r2, [r4, r3] + 4292 .LVL280: +2067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4293 .loc 1 2067 9 is_stmt 1 view .LVU1331 +2067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4294 .loc 1 2067 25 is_stmt 0 view .LVU1332 + 4295 00b4 0022 movs r2, #0 + 4296 00b6 0133 adds r3, r3, #1 + 4297 00b8 E254 strb r2, [r4, r3] +2070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4298 .loc 1 2070 9 is_stmt 1 view .LVU1333 +2070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4299 .loc 1 2070 25 is_stmt 0 view .LVU1334 + 4300 00ba 636C ldr r3, [r4, #68] + 4301 00bc 8021 movs r1, #128 + 4302 00be 0B43 orrs r3, r1 + 4303 00c0 6364 str r3, [r4, #68] +2073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4304 .loc 1 2073 9 is_stmt 1 view .LVU1335 +2073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4305 .loc 1 2073 9 view .LVU1336 + 4306 00c2 4023 movs r3, #64 + 4307 00c4 E254 strb r2, [r4, r3] +2073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4308 .loc 1 2073 9 view .LVU1337 +2075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4309 .loc 1 2075 9 view .LVU1338 +2075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4310 .loc 1 2075 16 is_stmt 0 view .LVU1339 + 4311 00c6 0120 movs r0, #1 + 4312 00c8 30E0 b .L246 + 4313 .LVL281: + 4314 .L258: +2082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4315 .loc 1 2082 9 is_stmt 1 view .LVU1340 +2082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4316 .loc 1 2082 59 is_stmt 0 view .LVU1341 + 4317 00ca 228D ldrh r2, [r4, #40] +2082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4318 .loc 1 2082 9 view .LVU1342 + 4319 00cc D2B2 uxtb r2, r2 + 4320 00ce 1E4B ldr r3, .L259+16 + 4321 00d0 0093 str r3, [sp] + 4322 00d2 3300 movs r3, r6 + 4323 00d4 2900 movs r1, r5 + 4324 00d6 2000 movs r0, r4 + 4325 .LVL282: +2082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4326 .loc 1 2082 9 view .LVU1343 + ARM GAS /tmp/ccth6daj.s page 217 + + + 4327 00d8 FFF7FEFF bl I2C_TransferConfig + 4328 .LVL283: +2085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4329 .loc 1 2085 9 is_stmt 1 view .LVU1344 +2085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4330 .loc 1 2085 25 is_stmt 0 view .LVU1345 + 4331 00dc 638D ldrh r3, [r4, #42] +2085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4332 .loc 1 2085 32 view .LVU1346 + 4333 00de 228D ldrh r2, [r4, #40] +2085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4334 .loc 1 2085 25 view .LVU1347 + 4335 00e0 9B1A subs r3, r3, r2 + 4336 00e2 9BB2 uxth r3, r3 + 4337 00e4 6385 strh r3, [r4, #42] +2088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4338 .loc 1 2088 9 is_stmt 1 view .LVU1348 +2088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4339 .loc 1 2088 9 view .LVU1349 + 4340 00e6 4023 movs r3, #64 + 4341 00e8 0022 movs r2, #0 + 4342 00ea E254 strb r2, [r4, r3] +2088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4343 .loc 1 2088 9 view .LVU1350 +2094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4344 .loc 1 2094 9 view .LVU1351 + 4345 00ec 1021 movs r1, #16 + 4346 00ee 2000 movs r0, r4 + 4347 00f0 FFF7FEFF bl I2C_Enable_IRQ + 4348 .LVL284: +2097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4349 .loc 1 2097 9 view .LVU1352 +2097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4350 .loc 1 2097 13 is_stmt 0 view .LVU1353 + 4351 00f4 2268 ldr r2, [r4] +2097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4352 .loc 1 2097 29 view .LVU1354 + 4353 00f6 1168 ldr r1, [r2] + 4354 00f8 8023 movs r3, #128 + 4355 00fa 1B02 lsls r3, r3, #8 + 4356 00fc 0B43 orrs r3, r1 + 4357 00fe 1360 str r3, [r2] + 4358 0100 11E0 b .L253 + 4359 .LVL285: + 4360 .L249: +2117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4361 .loc 1 2117 7 is_stmt 1 view .LVU1355 +2117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4362 .loc 1 2117 21 is_stmt 0 view .LVU1356 + 4363 0102 124B ldr r3, .L259+20 + 4364 0104 6363 str r3, [r4, #52] +2121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 4365 .loc 1 2121 7 is_stmt 1 view .LVU1357 + 4366 0106 8023 movs r3, #128 + 4367 0108 CAB2 uxtb r2, r1 + 4368 .LVL286: +2121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + ARM GAS /tmp/ccth6daj.s page 218 + + + 4369 .loc 1 2121 7 is_stmt 0 view .LVU1358 + 4370 010a 0F49 ldr r1, .L259+16 + 4371 010c 0091 str r1, [sp] + 4372 .LVL287: +2121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 4373 .loc 1 2121 7 view .LVU1359 + 4374 010e 9B04 lsls r3, r3, #18 + 4375 0110 2900 movs r1, r5 + 4376 0112 2000 movs r0, r4 + 4377 0114 FFF7FEFF bl I2C_TransferConfig + 4378 .LVL288: +2125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4379 .loc 1 2125 7 is_stmt 1 view .LVU1360 +2125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4380 .loc 1 2125 7 view .LVU1361 + 4381 0118 4023 movs r3, #64 + 4382 011a 0022 movs r2, #0 + 4383 011c E254 strb r2, [r4, r3] +2125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4384 .loc 1 2125 7 view .LVU1362 +2134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4385 .loc 1 2134 7 view .LVU1363 + 4386 011e 0121 movs r1, #1 + 4387 0120 2000 movs r0, r4 + 4388 0122 FFF7FEFF bl I2C_Enable_IRQ + 4389 .LVL289: + 4390 .L253: +2137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4391 .loc 1 2137 5 view .LVU1364 +2137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4392 .loc 1 2137 12 is_stmt 0 view .LVU1365 + 4393 0126 0020 movs r0, #0 + 4394 0128 00E0 b .L246 + 4395 .LVL290: + 4396 .L254: +2141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4397 .loc 1 2141 12 view .LVU1366 + 4398 012a 0220 movs r0, #2 + 4399 .LVL291: + 4400 .L246: +2143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4401 .loc 1 2143 1 view .LVU1367 + 4402 012c 02B0 add sp, sp, #8 + 4403 @ sp needed + 4404 .LVL292: +2143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4405 .loc 1 2143 1 view .LVU1368 + 4406 012e 70BD pop {r4, r5, r6, pc} + 4407 .LVL293: + 4408 .L255: +2018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4409 .loc 1 2018 14 view .LVU1369 + 4410 0130 0220 movs r0, #2 + 4411 .LVL294: +2018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4412 .loc 1 2018 14 view .LVU1370 + 4413 0132 FBE7 b .L246 + ARM GAS /tmp/ccth6daj.s page 219 + + + 4414 .LVL295: + 4415 .L256: +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4416 .loc 1 2022 5 view .LVU1371 + 4417 0134 0220 movs r0, #2 + 4418 .LVL296: +2022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4419 .loc 1 2022 5 view .LVU1372 + 4420 0136 F9E7 b .L246 + 4421 .L260: + 4422 .align 2 + 4423 .L259: + 4424 0138 0000FFFF .word -65536 + 4425 013c 00000000 .word I2C_Master_ISR_DMA + 4426 0140 00000000 .word I2C_DMAMasterReceiveCplt + 4427 0144 00000000 .word I2C_DMAError + 4428 0148 00240080 .word -2147474432 + 4429 014c 00000000 .word I2C_Master_ISR_IT + 4430 .cfi_endproc + 4431 .LFE310: + 4433 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 4434 .align 1 + 4435 .global HAL_I2C_Slave_Transmit_DMA + 4436 .syntax unified + 4437 .code 16 + 4438 .thumb_func + 4439 .fpu softvfp + 4441 HAL_I2C_Slave_Transmit_DMA: + 4442 .LVL297: + 4443 .LFB311: +2154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4444 .loc 1 2154 1 is_stmt 1 view -0 + 4445 .cfi_startproc + 4446 @ args = 0, pretend = 0, frame = 0 + 4447 @ frame_needed = 0, uses_anonymous_args = 0 +2154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4448 .loc 1 2154 1 is_stmt 0 view .LVU1374 + 4449 0000 70B5 push {r4, r5, r6, lr} + 4450 .LCFI34: + 4451 .cfi_def_cfa_offset 16 + 4452 .cfi_offset 4, -16 + 4453 .cfi_offset 5, -12 + 4454 .cfi_offset 6, -8 + 4455 .cfi_offset 14, -4 + 4456 0002 0400 movs r4, r0 +2155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4457 .loc 1 2155 3 is_stmt 1 view .LVU1375 +2157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4458 .loc 1 2157 3 view .LVU1376 +2157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4459 .loc 1 2157 11 is_stmt 0 view .LVU1377 + 4460 0004 4123 movs r3, #65 + 4461 0006 C35C ldrb r3, [r0, r3] +2157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4462 .loc 1 2157 6 view .LVU1378 + 4463 0008 202B cmp r3, #32 + 4464 000a 64D1 bne .L268 + ARM GAS /tmp/ccth6daj.s page 220 + + +2159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4465 .loc 1 2159 5 is_stmt 1 view .LVU1379 +2159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4466 .loc 1 2159 8 is_stmt 0 view .LVU1380 + 4467 000c 0029 cmp r1, #0 + 4468 000e 3BD0 beq .L263 +2159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4469 .loc 1 2159 25 discriminator 1 view .LVU1381 + 4470 0010 002A cmp r2, #0 + 4471 0012 39D0 beq .L263 +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4472 .loc 1 2165 5 is_stmt 1 view .LVU1382 +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4473 .loc 1 2165 5 view .LVU1383 + 4474 0014 4023 movs r3, #64 + 4475 0016 C35C ldrb r3, [r0, r3] + 4476 0018 012B cmp r3, #1 + 4477 001a 5FD0 beq .L269 +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4478 .loc 1 2165 5 discriminator 2 view .LVU1384 + 4479 001c 4023 movs r3, #64 + 4480 001e 0120 movs r0, #1 + 4481 .LVL298: +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4482 .loc 1 2165 5 is_stmt 0 discriminator 2 view .LVU1385 + 4483 0020 E054 strb r0, [r4, r3] +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4484 .loc 1 2165 5 is_stmt 1 discriminator 2 view .LVU1386 +2167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4485 .loc 1 2167 5 discriminator 2 view .LVU1387 +2167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4486 .loc 1 2167 23 is_stmt 0 discriminator 2 view .LVU1388 + 4487 0022 0133 adds r3, r3, #1 + 4488 0024 2030 adds r0, r0, #32 + 4489 0026 E054 strb r0, [r4, r3] +2168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4490 .loc 1 2168 5 is_stmt 1 discriminator 2 view .LVU1389 +2168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4491 .loc 1 2168 23 is_stmt 0 discriminator 2 view .LVU1390 + 4492 0028 0133 adds r3, r3, #1 + 4493 002a 0138 subs r0, r0, #1 + 4494 002c E054 strb r0, [r4, r3] +2169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4495 .loc 1 2169 5 is_stmt 1 discriminator 2 view .LVU1391 +2169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4496 .loc 1 2169 23 is_stmt 0 discriminator 2 view .LVU1392 + 4497 002e 0023 movs r3, #0 + 4498 0030 6364 str r3, [r4, #68] +2172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4499 .loc 1 2172 5 is_stmt 1 discriminator 2 view .LVU1393 +2172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4500 .loc 1 2172 23 is_stmt 0 discriminator 2 view .LVU1394 + 4501 0032 6162 str r1, [r4, #36] +2173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4502 .loc 1 2173 5 is_stmt 1 discriminator 2 view .LVU1395 +2173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4503 .loc 1 2173 23 is_stmt 0 discriminator 2 view .LVU1396 + ARM GAS /tmp/ccth6daj.s page 221 + + + 4504 0034 6285 strh r2, [r4, #42] +2174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4505 .loc 1 2174 5 is_stmt 1 discriminator 2 view .LVU1397 +2174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4506 .loc 1 2174 29 is_stmt 0 discriminator 2 view .LVU1398 + 4507 0036 638D ldrh r3, [r4, #42] +2174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4508 .loc 1 2174 23 discriminator 2 view .LVU1399 + 4509 0038 2385 strh r3, [r4, #40] +2175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4510 .loc 1 2175 5 is_stmt 1 discriminator 2 view .LVU1400 +2175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4511 .loc 1 2175 23 is_stmt 0 discriminator 2 view .LVU1401 + 4512 003a 294B ldr r3, .L272 + 4513 003c E362 str r3, [r4, #44] +2176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4514 .loc 1 2176 5 is_stmt 1 discriminator 2 view .LVU1402 +2176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4515 .loc 1 2176 23 is_stmt 0 discriminator 2 view .LVU1403 + 4516 003e 294B ldr r3, .L272+4 + 4517 0040 6363 str r3, [r4, #52] +2178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4518 .loc 1 2178 5 is_stmt 1 discriminator 2 view .LVU1404 +2178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4519 .loc 1 2178 13 is_stmt 0 discriminator 2 view .LVU1405 + 4520 0042 A36B ldr r3, [r4, #56] +2178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4521 .loc 1 2178 8 discriminator 2 view .LVU1406 + 4522 0044 002B cmp r3, #0 + 4523 0046 24D0 beq .L265 +2181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4524 .loc 1 2181 7 is_stmt 1 view .LVU1407 +2181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4525 .loc 1 2181 38 is_stmt 0 view .LVU1408 + 4526 0048 274A ldr r2, .L272+8 + 4527 .LVL299: +2181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4528 .loc 1 2181 38 view .LVU1409 + 4529 004a DA62 str r2, [r3, #44] +2184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4530 .loc 1 2184 7 is_stmt 1 view .LVU1410 +2184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4531 .loc 1 2184 11 is_stmt 0 view .LVU1411 + 4532 004c A36B ldr r3, [r4, #56] +2184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4533 .loc 1 2184 39 view .LVU1412 + 4534 004e 274A ldr r2, .L272+12 + 4535 0050 5A63 str r2, [r3, #52] +2187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4536 .loc 1 2187 7 is_stmt 1 view .LVU1413 +2187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4537 .loc 1 2187 11 is_stmt 0 view .LVU1414 + 4538 0052 A26B ldr r2, [r4, #56] +2187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 4539 .loc 1 2187 42 view .LVU1415 + 4540 0054 0023 movs r3, #0 + 4541 0056 1363 str r3, [r2, #48] + ARM GAS /tmp/ccth6daj.s page 222 + + +2188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4542 .loc 1 2188 7 is_stmt 1 view .LVU1416 +2188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4543 .loc 1 2188 11 is_stmt 0 view .LVU1417 + 4544 0058 A26B ldr r2, [r4, #56] +2188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4545 .loc 1 2188 39 view .LVU1418 + 4546 005a 9363 str r3, [r2, #56] +2191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4547 .loc 1 2191 7 is_stmt 1 view .LVU1419 +2191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4548 .loc 1 2191 81 is_stmt 0 view .LVU1420 + 4549 005c 2268 ldr r2, [r4] + 4550 005e 2832 adds r2, r2, #40 +2192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4551 .loc 1 2192 44 view .LVU1421 + 4552 0060 238D ldrh r3, [r4, #40] +2191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4553 .loc 1 2191 23 view .LVU1422 + 4554 0062 A06B ldr r0, [r4, #56] + 4555 0064 FFF7FEFF bl HAL_DMA_Start_IT + 4556 .LVL300: +2191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4557 .loc 1 2191 23 view .LVU1423 + 4558 0068 051E subs r5, r0, #0 + 4559 .LVL301: +2209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4560 .loc 1 2209 5 is_stmt 1 view .LVU1424 +2209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4561 .loc 1 2209 8 is_stmt 0 view .LVU1425 + 4562 006a 20D0 beq .L271 +2229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4563 .loc 1 2229 7 is_stmt 1 view .LVU1426 +2229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4564 .loc 1 2229 23 is_stmt 0 view .LVU1427 + 4565 006c 4123 movs r3, #65 + 4566 006e 2822 movs r2, #40 + 4567 0070 E254 strb r2, [r4, r3] +2230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4568 .loc 1 2230 7 is_stmt 1 view .LVU1428 +2230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4569 .loc 1 2230 23 is_stmt 0 view .LVU1429 + 4570 0072 0022 movs r2, #0 + 4571 0074 0133 adds r3, r3, #1 + 4572 0076 E254 strb r2, [r4, r3] +2233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4573 .loc 1 2233 7 is_stmt 1 view .LVU1430 +2233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4574 .loc 1 2233 23 is_stmt 0 view .LVU1431 + 4575 0078 636C ldr r3, [r4, #68] + 4576 007a 1021 movs r1, #16 + 4577 007c 0B43 orrs r3, r1 + 4578 007e 6364 str r3, [r4, #68] +2236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4579 .loc 1 2236 7 is_stmt 1 view .LVU1432 +2236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4580 .loc 1 2236 7 view .LVU1433 + ARM GAS /tmp/ccth6daj.s page 223 + + + 4581 0080 4023 movs r3, #64 + 4582 0082 E254 strb r2, [r4, r3] +2236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4583 .loc 1 2236 7 view .LVU1434 +2238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4584 .loc 1 2238 7 view .LVU1435 +2238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4585 .loc 1 2238 14 is_stmt 0 view .LVU1436 + 4586 0084 0125 movs r5, #1 + 4587 0086 27E0 b .L262 + 4588 .LVL302: + 4589 .L263: +2161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 4590 .loc 1 2161 7 is_stmt 1 view .LVU1437 +2161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 4591 .loc 1 2161 23 is_stmt 0 view .LVU1438 + 4592 0088 8023 movs r3, #128 + 4593 008a 9B00 lsls r3, r3, #2 + 4594 008c 6364 str r3, [r4, #68] +2162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4595 .loc 1 2162 7 is_stmt 1 view .LVU1439 +2162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4596 .loc 1 2162 15 is_stmt 0 view .LVU1440 + 4597 008e 0125 movs r5, #1 + 4598 0090 22E0 b .L262 + 4599 .LVL303: + 4600 .L265: +2197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4601 .loc 1 2197 7 is_stmt 1 view .LVU1441 +2197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4602 .loc 1 2197 23 is_stmt 0 view .LVU1442 + 4603 0092 4123 movs r3, #65 + 4604 0094 2822 movs r2, #40 + 4605 .LVL304: +2197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4606 .loc 1 2197 23 view .LVU1443 + 4607 0096 E254 strb r2, [r4, r3] +2198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4608 .loc 1 2198 7 is_stmt 1 view .LVU1444 +2198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4609 .loc 1 2198 23 is_stmt 0 view .LVU1445 + 4610 0098 0022 movs r2, #0 + 4611 009a 0133 adds r3, r3, #1 + 4612 009c E254 strb r2, [r4, r3] +2201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4613 .loc 1 2201 7 is_stmt 1 view .LVU1446 +2201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4614 .loc 1 2201 23 is_stmt 0 view .LVU1447 + 4615 009e 636C ldr r3, [r4, #68] + 4616 00a0 8021 movs r1, #128 + 4617 .LVL305: +2201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4618 .loc 1 2201 23 view .LVU1448 + 4619 00a2 0B43 orrs r3, r1 + 4620 00a4 6364 str r3, [r4, #68] +2204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4621 .loc 1 2204 7 is_stmt 1 view .LVU1449 + ARM GAS /tmp/ccth6daj.s page 224 + + +2204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4622 .loc 1 2204 7 view .LVU1450 + 4623 00a6 4023 movs r3, #64 + 4624 00a8 E254 strb r2, [r4, r3] +2204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4625 .loc 1 2204 7 view .LVU1451 +2206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4626 .loc 1 2206 7 view .LVU1452 +2206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4627 .loc 1 2206 14 is_stmt 0 view .LVU1453 + 4628 00aa 0125 movs r5, #1 + 4629 00ac 14E0 b .L262 + 4630 .LVL306: + 4631 .L271: +2212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4632 .loc 1 2212 7 is_stmt 1 view .LVU1454 +2212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4633 .loc 1 2212 11 is_stmt 0 view .LVU1455 + 4634 00ae 2268 ldr r2, [r4] +2212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4635 .loc 1 2212 27 view .LVU1456 + 4636 00b0 5368 ldr r3, [r2, #4] + 4637 00b2 0F49 ldr r1, .L272+16 + 4638 00b4 0B40 ands r3, r1 + 4639 00b6 5360 str r3, [r2, #4] +2215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4640 .loc 1 2215 7 is_stmt 1 view .LVU1457 +2215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4641 .loc 1 2215 7 view .LVU1458 + 4642 00b8 4023 movs r3, #64 + 4643 00ba 0022 movs r2, #0 + 4644 00bc E254 strb r2, [r4, r3] +2215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4645 .loc 1 2215 7 view .LVU1459 +2221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4646 .loc 1 2221 7 view .LVU1460 + 4647 00be 8021 movs r1, #128 + 4648 00c0 0902 lsls r1, r1, #8 + 4649 00c2 2000 movs r0, r4 + 4650 .LVL307: +2221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4651 .loc 1 2221 7 is_stmt 0 view .LVU1461 + 4652 00c4 FFF7FEFF bl I2C_Enable_IRQ + 4653 .LVL308: +2224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4654 .loc 1 2224 7 is_stmt 1 view .LVU1462 +2224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4655 .loc 1 2224 11 is_stmt 0 view .LVU1463 + 4656 00c8 2268 ldr r2, [r4] +2224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4657 .loc 1 2224 27 view .LVU1464 + 4658 00ca 1168 ldr r1, [r2] + 4659 00cc 8023 movs r3, #128 + 4660 00ce DB01 lsls r3, r3, #7 + 4661 00d0 0B43 orrs r3, r1 + 4662 00d2 1360 str r3, [r2] +2241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 225 + + + 4663 .loc 1 2241 5 is_stmt 1 view .LVU1465 +2241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4664 .loc 1 2241 12 is_stmt 0 view .LVU1466 + 4665 00d4 00E0 b .L262 + 4666 .LVL309: + 4667 .L268: +2245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4668 .loc 1 2245 12 view .LVU1467 + 4669 00d6 0225 movs r5, #2 + 4670 .LVL310: + 4671 .L262: +2247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4672 .loc 1 2247 1 view .LVU1468 + 4673 00d8 2800 movs r0, r5 + 4674 @ sp needed + 4675 .LVL311: +2247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4676 .loc 1 2247 1 view .LVU1469 + 4677 00da 70BD pop {r4, r5, r6, pc} + 4678 .LVL312: + 4679 .L269: +2165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4680 .loc 1 2165 5 view .LVU1470 + 4681 00dc 0225 movs r5, #2 + 4682 00de FBE7 b .L262 + 4683 .L273: + 4684 .align 2 + 4685 .L272: + 4686 00e0 0000FFFF .word -65536 + 4687 00e4 00000000 .word I2C_Slave_ISR_DMA + 4688 00e8 00000000 .word I2C_DMASlaveTransmitCplt + 4689 00ec 00000000 .word I2C_DMAError + 4690 00f0 FF7FFFFF .word -32769 + 4691 .cfi_endproc + 4692 .LFE311: + 4694 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 4695 .align 1 + 4696 .global HAL_I2C_Slave_Receive_DMA + 4697 .syntax unified + 4698 .code 16 + 4699 .thumb_func + 4700 .fpu softvfp + 4702 HAL_I2C_Slave_Receive_DMA: + 4703 .LVL313: + 4704 .LFB312: +2258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4705 .loc 1 2258 1 is_stmt 1 view -0 + 4706 .cfi_startproc + 4707 @ args = 0, pretend = 0, frame = 0 + 4708 @ frame_needed = 0, uses_anonymous_args = 0 +2258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 4709 .loc 1 2258 1 is_stmt 0 view .LVU1472 + 4710 0000 70B5 push {r4, r5, r6, lr} + 4711 .LCFI35: + 4712 .cfi_def_cfa_offset 16 + 4713 .cfi_offset 4, -16 + 4714 .cfi_offset 5, -12 + ARM GAS /tmp/ccth6daj.s page 226 + + + 4715 .cfi_offset 6, -8 + 4716 .cfi_offset 14, -4 + 4717 0002 0400 movs r4, r0 +2259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4718 .loc 1 2259 3 is_stmt 1 view .LVU1473 +2261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4719 .loc 1 2261 3 view .LVU1474 +2261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4720 .loc 1 2261 11 is_stmt 0 view .LVU1475 + 4721 0004 4123 movs r3, #65 + 4722 0006 C35C ldrb r3, [r0, r3] +2261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4723 .loc 1 2261 6 view .LVU1476 + 4724 0008 202B cmp r3, #32 + 4725 000a 65D1 bne .L281 +2263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4726 .loc 1 2263 5 is_stmt 1 view .LVU1477 +2263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4727 .loc 1 2263 8 is_stmt 0 view .LVU1478 + 4728 000c 0029 cmp r1, #0 + 4729 000e 3DD0 beq .L276 +2263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4730 .loc 1 2263 25 discriminator 1 view .LVU1479 + 4731 0010 002A cmp r2, #0 + 4732 0012 3BD0 beq .L276 +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4733 .loc 1 2269 5 is_stmt 1 view .LVU1480 +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4734 .loc 1 2269 5 view .LVU1481 + 4735 0014 4023 movs r3, #64 + 4736 0016 C35C ldrb r3, [r0, r3] + 4737 0018 012B cmp r3, #1 + 4738 001a 60D0 beq .L282 +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4739 .loc 1 2269 5 discriminator 2 view .LVU1482 + 4740 001c 4023 movs r3, #64 + 4741 001e 0120 movs r0, #1 + 4742 .LVL314: +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4743 .loc 1 2269 5 is_stmt 0 discriminator 2 view .LVU1483 + 4744 0020 E054 strb r0, [r4, r3] +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4745 .loc 1 2269 5 is_stmt 1 discriminator 2 view .LVU1484 +2271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4746 .loc 1 2271 5 discriminator 2 view .LVU1485 +2271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 4747 .loc 1 2271 23 is_stmt 0 discriminator 2 view .LVU1486 + 4748 0022 0133 adds r3, r3, #1 + 4749 0024 2130 adds r0, r0, #33 + 4750 0026 E054 strb r0, [r4, r3] +2272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4751 .loc 1 2272 5 is_stmt 1 discriminator 2 view .LVU1487 +2272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4752 .loc 1 2272 23 is_stmt 0 discriminator 2 view .LVU1488 + 4753 0028 0133 adds r3, r3, #1 + 4754 002a 0238 subs r0, r0, #2 + 4755 002c E054 strb r0, [r4, r3] + ARM GAS /tmp/ccth6daj.s page 227 + + +2273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4756 .loc 1 2273 5 is_stmt 1 discriminator 2 view .LVU1489 +2273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4757 .loc 1 2273 23 is_stmt 0 discriminator 2 view .LVU1490 + 4758 002e 0023 movs r3, #0 + 4759 0030 6364 str r3, [r4, #68] +2276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4760 .loc 1 2276 5 is_stmt 1 discriminator 2 view .LVU1491 +2276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 4761 .loc 1 2276 23 is_stmt 0 discriminator 2 view .LVU1492 + 4762 0032 6162 str r1, [r4, #36] +2277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4763 .loc 1 2277 5 is_stmt 1 discriminator 2 view .LVU1493 +2277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4764 .loc 1 2277 23 is_stmt 0 discriminator 2 view .LVU1494 + 4765 0034 6285 strh r2, [r4, #42] +2278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4766 .loc 1 2278 5 is_stmt 1 discriminator 2 view .LVU1495 +2278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4767 .loc 1 2278 29 is_stmt 0 discriminator 2 view .LVU1496 + 4768 0036 638D ldrh r3, [r4, #42] +2278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4769 .loc 1 2278 23 discriminator 2 view .LVU1497 + 4770 0038 2385 strh r3, [r4, #40] +2279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4771 .loc 1 2279 5 is_stmt 1 discriminator 2 view .LVU1498 +2279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 4772 .loc 1 2279 23 is_stmt 0 discriminator 2 view .LVU1499 + 4773 003a 2A4B ldr r3, .L285 + 4774 003c E362 str r3, [r4, #44] +2280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4775 .loc 1 2280 5 is_stmt 1 discriminator 2 view .LVU1500 +2280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4776 .loc 1 2280 23 is_stmt 0 discriminator 2 view .LVU1501 + 4777 003e 2A4B ldr r3, .L285+4 + 4778 0040 6363 str r3, [r4, #52] +2282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4779 .loc 1 2282 5 is_stmt 1 discriminator 2 view .LVU1502 +2282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4780 .loc 1 2282 13 is_stmt 0 discriminator 2 view .LVU1503 + 4781 0042 E36B ldr r3, [r4, #60] +2282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4782 .loc 1 2282 8 discriminator 2 view .LVU1504 + 4783 0044 002B cmp r3, #0 + 4784 0046 26D0 beq .L278 +2285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4785 .loc 1 2285 7 is_stmt 1 view .LVU1505 +2285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4786 .loc 1 2285 38 is_stmt 0 view .LVU1506 + 4787 0048 284A ldr r2, .L285+8 + 4788 .LVL315: +2285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4789 .loc 1 2285 38 view .LVU1507 + 4790 004a DA62 str r2, [r3, #44] +2288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4791 .loc 1 2288 7 is_stmt 1 view .LVU1508 +2288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 228 + + + 4792 .loc 1 2288 11 is_stmt 0 view .LVU1509 + 4793 004c E36B ldr r3, [r4, #60] +2288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4794 .loc 1 2288 39 view .LVU1510 + 4795 004e 284A ldr r2, .L285+12 + 4796 0050 5A63 str r2, [r3, #52] +2291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4797 .loc 1 2291 7 is_stmt 1 view .LVU1511 +2291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4798 .loc 1 2291 11 is_stmt 0 view .LVU1512 + 4799 0052 E26B ldr r2, [r4, #60] +2291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 4800 .loc 1 2291 42 view .LVU1513 + 4801 0054 0023 movs r3, #0 + 4802 0056 1363 str r3, [r2, #48] +2292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4803 .loc 1 2292 7 is_stmt 1 view .LVU1514 +2292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4804 .loc 1 2292 11 is_stmt 0 view .LVU1515 + 4805 0058 E26B ldr r2, [r4, #60] +2292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4806 .loc 1 2292 39 view .LVU1516 + 4807 005a 9363 str r3, [r2, #56] +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4808 .loc 1 2295 7 is_stmt 1 view .LVU1517 +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4809 .loc 1 2295 64 is_stmt 0 view .LVU1518 + 4810 005c 2068 ldr r0, [r4] + 4811 005e 2430 adds r0, r0, #36 +2296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4812 .loc 1 2296 44 view .LVU1519 + 4813 0060 238D ldrh r3, [r4, #40] +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4814 .loc 1 2295 23 view .LVU1520 + 4815 0062 0A00 movs r2, r1 + 4816 0064 0100 movs r1, r0 + 4817 .LVL316: +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4818 .loc 1 2295 23 view .LVU1521 + 4819 0066 E06B ldr r0, [r4, #60] + 4820 0068 FFF7FEFF bl HAL_DMA_Start_IT + 4821 .LVL317: +2295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 4822 .loc 1 2295 23 view .LVU1522 + 4823 006c 051E subs r5, r0, #0 + 4824 .LVL318: +2313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4825 .loc 1 2313 5 is_stmt 1 view .LVU1523 +2313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4826 .loc 1 2313 8 is_stmt 0 view .LVU1524 + 4827 006e 20D0 beq .L284 +2333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4828 .loc 1 2333 7 is_stmt 1 view .LVU1525 +2333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4829 .loc 1 2333 23 is_stmt 0 view .LVU1526 + 4830 0070 4123 movs r3, #65 + 4831 0072 2822 movs r2, #40 + ARM GAS /tmp/ccth6daj.s page 229 + + + 4832 0074 E254 strb r2, [r4, r3] +2334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4833 .loc 1 2334 7 is_stmt 1 view .LVU1527 +2334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4834 .loc 1 2334 23 is_stmt 0 view .LVU1528 + 4835 0076 0022 movs r2, #0 + 4836 0078 0133 adds r3, r3, #1 + 4837 007a E254 strb r2, [r4, r3] +2337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4838 .loc 1 2337 7 is_stmt 1 view .LVU1529 +2337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4839 .loc 1 2337 23 is_stmt 0 view .LVU1530 + 4840 007c 636C ldr r3, [r4, #68] + 4841 007e 1021 movs r1, #16 + 4842 0080 0B43 orrs r3, r1 + 4843 0082 6364 str r3, [r4, #68] +2340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4844 .loc 1 2340 7 is_stmt 1 view .LVU1531 +2340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4845 .loc 1 2340 7 view .LVU1532 + 4846 0084 4023 movs r3, #64 + 4847 0086 E254 strb r2, [r4, r3] +2340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4848 .loc 1 2340 7 view .LVU1533 +2342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4849 .loc 1 2342 7 view .LVU1534 +2342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4850 .loc 1 2342 14 is_stmt 0 view .LVU1535 + 4851 0088 0125 movs r5, #1 + 4852 008a 26E0 b .L275 + 4853 .LVL319: + 4854 .L276: +2265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 4855 .loc 1 2265 7 is_stmt 1 view .LVU1536 +2265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 4856 .loc 1 2265 23 is_stmt 0 view .LVU1537 + 4857 008c 8023 movs r3, #128 + 4858 008e 9B00 lsls r3, r3, #2 + 4859 0090 6364 str r3, [r4, #68] +2266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4860 .loc 1 2266 7 is_stmt 1 view .LVU1538 +2266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4861 .loc 1 2266 15 is_stmt 0 view .LVU1539 + 4862 0092 0125 movs r5, #1 + 4863 0094 21E0 b .L275 + 4864 .LVL320: + 4865 .L278: +2301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4866 .loc 1 2301 7 is_stmt 1 view .LVU1540 +2301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4867 .loc 1 2301 23 is_stmt 0 view .LVU1541 + 4868 0096 4123 movs r3, #65 + 4869 0098 2822 movs r2, #40 + 4870 .LVL321: +2301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4871 .loc 1 2301 23 view .LVU1542 + 4872 009a E254 strb r2, [r4, r3] + ARM GAS /tmp/ccth6daj.s page 230 + + +2302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4873 .loc 1 2302 7 is_stmt 1 view .LVU1543 +2302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4874 .loc 1 2302 23 is_stmt 0 view .LVU1544 + 4875 009c 0022 movs r2, #0 + 4876 009e 0133 adds r3, r3, #1 + 4877 00a0 E254 strb r2, [r4, r3] +2305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4878 .loc 1 2305 7 is_stmt 1 view .LVU1545 +2305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4879 .loc 1 2305 23 is_stmt 0 view .LVU1546 + 4880 00a2 636C ldr r3, [r4, #68] + 4881 00a4 8021 movs r1, #128 + 4882 .LVL322: +2305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4883 .loc 1 2305 23 view .LVU1547 + 4884 00a6 0B43 orrs r3, r1 + 4885 00a8 6364 str r3, [r4, #68] +2308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4886 .loc 1 2308 7 is_stmt 1 view .LVU1548 +2308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4887 .loc 1 2308 7 view .LVU1549 + 4888 00aa 4023 movs r3, #64 + 4889 00ac E254 strb r2, [r4, r3] +2308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4890 .loc 1 2308 7 view .LVU1550 +2310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4891 .loc 1 2310 7 view .LVU1551 +2310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4892 .loc 1 2310 14 is_stmt 0 view .LVU1552 + 4893 00ae 0125 movs r5, #1 + 4894 00b0 13E0 b .L275 + 4895 .LVL323: + 4896 .L284: +2316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4897 .loc 1 2316 7 is_stmt 1 view .LVU1553 +2316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4898 .loc 1 2316 11 is_stmt 0 view .LVU1554 + 4899 00b2 2268 ldr r2, [r4] +2316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4900 .loc 1 2316 27 view .LVU1555 + 4901 00b4 5368 ldr r3, [r2, #4] + 4902 00b6 0F49 ldr r1, .L285+16 + 4903 00b8 0B40 ands r3, r1 + 4904 00ba 5360 str r3, [r2, #4] +2319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4905 .loc 1 2319 7 is_stmt 1 view .LVU1556 +2319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4906 .loc 1 2319 7 view .LVU1557 + 4907 00bc 4023 movs r3, #64 + 4908 00be 0022 movs r2, #0 + 4909 00c0 E254 strb r2, [r4, r3] +2319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4910 .loc 1 2319 7 view .LVU1558 +2325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4911 .loc 1 2325 7 view .LVU1559 + 4912 00c2 8026 movs r6, #128 + ARM GAS /tmp/ccth6daj.s page 231 + + + 4913 00c4 3602 lsls r6, r6, #8 + 4914 00c6 3100 movs r1, r6 + 4915 00c8 2000 movs r0, r4 + 4916 .LVL324: +2325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4917 .loc 1 2325 7 is_stmt 0 view .LVU1560 + 4918 00ca FFF7FEFF bl I2C_Enable_IRQ + 4919 .LVL325: +2328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4920 .loc 1 2328 7 is_stmt 1 view .LVU1561 +2328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4921 .loc 1 2328 11 is_stmt 0 view .LVU1562 + 4922 00ce 2368 ldr r3, [r4] +2328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4923 .loc 1 2328 27 view .LVU1563 + 4924 00d0 1A68 ldr r2, [r3] + 4925 00d2 1643 orrs r6, r2 + 4926 00d4 1E60 str r6, [r3] +2345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4927 .loc 1 2345 5 is_stmt 1 view .LVU1564 +2345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4928 .loc 1 2345 12 is_stmt 0 view .LVU1565 + 4929 00d6 00E0 b .L275 + 4930 .LVL326: + 4931 .L281: +2349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 4932 .loc 1 2349 12 view .LVU1566 + 4933 00d8 0225 movs r5, #2 + 4934 .LVL327: + 4935 .L275: +2351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 4936 .loc 1 2351 1 view .LVU1567 + 4937 00da 2800 movs r0, r5 + 4938 @ sp needed + 4939 .LVL328: +2351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 4940 .loc 1 2351 1 view .LVU1568 + 4941 00dc 70BD pop {r4, r5, r6, pc} + 4942 .LVL329: + 4943 .L282: +2269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4944 .loc 1 2269 5 view .LVU1569 + 4945 00de 0225 movs r5, #2 + 4946 00e0 FBE7 b .L275 + 4947 .L286: + 4948 00e2 C046 .align 2 + 4949 .L285: + 4950 00e4 0000FFFF .word -65536 + 4951 00e8 00000000 .word I2C_Slave_ISR_DMA + 4952 00ec 00000000 .word I2C_DMASlaveReceiveCplt + 4953 00f0 00000000 .word I2C_DMAError + 4954 00f4 FF7FFFFF .word -32769 + 4955 .cfi_endproc + 4956 .LFE312: + 4958 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 4959 .align 1 + 4960 .global HAL_I2C_Mem_Write + ARM GAS /tmp/ccth6daj.s page 232 + + + 4961 .syntax unified + 4962 .code 16 + 4963 .thumb_func + 4964 .fpu softvfp + 4966 HAL_I2C_Mem_Write: + 4967 .LVL330: + 4968 .LFB313: +2367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 4969 .loc 1 2367 1 is_stmt 1 view -0 + 4970 .cfi_startproc + 4971 @ args = 12, pretend = 0, frame = 16 + 4972 @ frame_needed = 0, uses_anonymous_args = 0 +2367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 4973 .loc 1 2367 1 is_stmt 0 view .LVU1571 + 4974 0000 F0B5 push {r4, r5, r6, r7, lr} + 4975 .LCFI36: + 4976 .cfi_def_cfa_offset 20 + 4977 .cfi_offset 4, -20 + 4978 .cfi_offset 5, -16 + 4979 .cfi_offset 6, -12 + 4980 .cfi_offset 7, -8 + 4981 .cfi_offset 14, -4 + 4982 0002 87B0 sub sp, sp, #28 + 4983 .LCFI37: + 4984 .cfi_def_cfa_offset 48 + 4985 0004 0400 movs r4, r0 + 4986 0006 0391 str r1, [sp, #12] + 4987 0008 0492 str r2, [sp, #16] + 4988 000a 0593 str r3, [sp, #20] + 4989 000c 0CAB add r3, sp, #48 + 4990 .LVL331: +2367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 4991 .loc 1 2367 1 view .LVU1572 + 4992 000e 20CB ldmia r3!, {r5} + 4993 .LVL332: +2367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 4994 .loc 1 2367 1 view .LVU1573 + 4995 0010 1F88 ldrh r7, [r3] +2368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4996 .loc 1 2368 3 is_stmt 1 view .LVU1574 +2371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 4997 .loc 1 2371 3 view .LVU1575 +2373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4998 .loc 1 2373 3 view .LVU1576 +2373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 4999 .loc 1 2373 11 is_stmt 0 view .LVU1577 + 5000 0012 4123 movs r3, #65 + 5001 .LVL333: +2373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5002 .loc 1 2373 11 view .LVU1578 + 5003 0014 C35C ldrb r3, [r0, r3] +2373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5004 .loc 1 2373 6 view .LVU1579 + 5005 0016 202B cmp r3, #32 + 5006 0018 00D0 beq .LCB4677 + 5007 001a B3E0 b .L297 @long jump + 5008 .LCB4677: + ARM GAS /tmp/ccth6daj.s page 233 + + +2375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5009 .loc 1 2375 5 is_stmt 1 view .LVU1580 +2375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5010 .loc 1 2375 8 is_stmt 0 view .LVU1581 + 5011 001c 002D cmp r5, #0 + 5012 001e 18D0 beq .L289 +2375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5013 .loc 1 2375 25 discriminator 1 view .LVU1582 + 5014 0020 002F cmp r7, #0 + 5015 0022 16D0 beq .L289 +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5016 .loc 1 2382 5 is_stmt 1 view .LVU1583 +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5017 .loc 1 2382 5 view .LVU1584 + 5018 0024 4023 movs r3, #64 + 5019 0026 C35C ldrb r3, [r0, r3] + 5020 0028 012B cmp r3, #1 + 5021 002a 00D1 bne .LCB4688 + 5022 002c ADE0 b .L298 @long jump + 5023 .LCB4688: +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5024 .loc 1 2382 5 discriminator 2 view .LVU1585 + 5025 002e 4023 movs r3, #64 + 5026 0030 0122 movs r2, #1 + 5027 .LVL334: +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5028 .loc 1 2382 5 is_stmt 0 discriminator 2 view .LVU1586 + 5029 0032 C254 strb r2, [r0, r3] +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5030 .loc 1 2382 5 is_stmt 1 discriminator 2 view .LVU1587 +2385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5031 .loc 1 2385 5 discriminator 2 view .LVU1588 +2385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5032 .loc 1 2385 17 is_stmt 0 discriminator 2 view .LVU1589 + 5033 0034 FFF7FEFF bl HAL_GetTick + 5034 .LVL335: +2385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5035 .loc 1 2385 17 discriminator 2 view .LVU1590 + 5036 0038 0600 movs r6, r0 + 5037 .LVL336: +2387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5038 .loc 1 2387 5 is_stmt 1 discriminator 2 view .LVU1591 +2387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5039 .loc 1 2387 9 is_stmt 0 discriminator 2 view .LVU1592 + 5040 003a 8021 movs r1, #128 + 5041 003c 0090 str r0, [sp] + 5042 003e 1923 movs r3, #25 + 5043 0040 0122 movs r2, #1 + 5044 0042 0902 lsls r1, r1, #8 + 5045 0044 2000 movs r0, r4 + 5046 .LVL337: +2387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5047 .loc 1 2387 9 discriminator 2 view .LVU1593 + 5048 0046 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5049 .LVL338: +2387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5050 .loc 1 2387 8 discriminator 2 view .LVU1594 + ARM GAS /tmp/ccth6daj.s page 234 + + + 5051 004a 0028 cmp r0, #0 + 5052 004c 06D0 beq .L303 +2389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5053 .loc 1 2389 14 view .LVU1595 + 5054 004e 0120 movs r0, #1 + 5055 0050 99E0 b .L288 + 5056 .LVL339: + 5057 .L289: +2377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5058 .loc 1 2377 7 is_stmt 1 view .LVU1596 +2377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5059 .loc 1 2377 23 is_stmt 0 view .LVU1597 + 5060 0052 8023 movs r3, #128 + 5061 0054 9B00 lsls r3, r3, #2 + 5062 0056 6364 str r3, [r4, #68] +2378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5063 .loc 1 2378 7 is_stmt 1 view .LVU1598 +2378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5064 .loc 1 2378 15 is_stmt 0 view .LVU1599 + 5065 0058 0120 movs r0, #1 + 5066 .LVL340: +2378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5067 .loc 1 2378 15 view .LVU1600 + 5068 005a 94E0 b .L288 + 5069 .LVL341: + 5070 .L303: +2392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5071 .loc 1 2392 5 is_stmt 1 view .LVU1601 +2392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5072 .loc 1 2392 21 is_stmt 0 view .LVU1602 + 5073 005c 4123 movs r3, #65 + 5074 005e 2122 movs r2, #33 + 5075 0060 E254 strb r2, [r4, r3] +2393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5076 .loc 1 2393 5 is_stmt 1 view .LVU1603 +2393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5077 .loc 1 2393 21 is_stmt 0 view .LVU1604 + 5078 0062 0133 adds r3, r3, #1 + 5079 0064 1F32 adds r2, r2, #31 + 5080 0066 E254 strb r2, [r4, r3] +2394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5081 .loc 1 2394 5 is_stmt 1 view .LVU1605 +2394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5082 .loc 1 2394 21 is_stmt 0 view .LVU1606 + 5083 0068 0023 movs r3, #0 + 5084 006a 6364 str r3, [r4, #68] +2397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5085 .loc 1 2397 5 is_stmt 1 view .LVU1607 +2397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5086 .loc 1 2397 21 is_stmt 0 view .LVU1608 + 5087 006c 6562 str r5, [r4, #36] +2398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5088 .loc 1 2398 5 is_stmt 1 view .LVU1609 +2398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5089 .loc 1 2398 21 is_stmt 0 view .LVU1610 + 5090 006e 6785 strh r7, [r4, #42] +2399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 235 + + + 5091 .loc 1 2399 5 is_stmt 1 view .LVU1611 +2399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5092 .loc 1 2399 21 is_stmt 0 view .LVU1612 + 5093 0070 6363 str r3, [r4, #52] +2402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5094 .loc 1 2402 5 is_stmt 1 view .LVU1613 +2402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5095 .loc 1 2402 9 is_stmt 0 view .LVU1614 + 5096 0072 0196 str r6, [sp, #4] + 5097 0074 0E9B ldr r3, [sp, #56] + 5098 0076 0093 str r3, [sp] + 5099 0078 059B ldr r3, [sp, #20] + 5100 007a 049A ldr r2, [sp, #16] + 5101 007c 0399 ldr r1, [sp, #12] + 5102 007e 2000 movs r0, r4 + 5103 0080 FFF7FEFF bl I2C_RequestMemoryWrite + 5104 .LVL342: +2402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5105 .loc 1 2402 8 view .LVU1615 + 5106 0084 0028 cmp r0, #0 + 5107 0086 0FD1 bne .L304 +2410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5108 .loc 1 2410 5 is_stmt 1 view .LVU1616 +2410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5109 .loc 1 2410 13 is_stmt 0 view .LVU1617 + 5110 0088 638D ldrh r3, [r4, #42] + 5111 008a 9BB2 uxth r3, r3 +2410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5112 .loc 1 2410 8 view .LVU1618 + 5113 008c FF2B cmp r3, #255 + 5114 008e 10D9 bls .L292 +2412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 5115 .loc 1 2412 7 is_stmt 1 view .LVU1619 +2412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 5116 .loc 1 2412 22 is_stmt 0 view .LVU1620 + 5117 0090 FF23 movs r3, #255 + 5118 0092 2385 strh r3, [r4, #40] +2413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5119 .loc 1 2413 7 is_stmt 1 view .LVU1621 + 5120 0094 7F3B subs r3, r3, #127 + 5121 0096 0022 movs r2, #0 + 5122 0098 0092 str r2, [sp] + 5123 009a 5B04 lsls r3, r3, #17 + 5124 009c FF32 adds r2, r2, #255 + 5125 009e 0399 ldr r1, [sp, #12] + 5126 00a0 2000 movs r0, r4 + 5127 00a2 FFF7FEFF bl I2C_TransferConfig + 5128 .LVL343: + 5129 00a6 21E0 b .L296 + 5130 .L304: +2405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5131 .loc 1 2405 7 view .LVU1622 +2405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5132 .loc 1 2405 7 view .LVU1623 + 5133 00a8 4023 movs r3, #64 + 5134 00aa 0022 movs r2, #0 + 5135 00ac E254 strb r2, [r4, r3] + ARM GAS /tmp/ccth6daj.s page 236 + + +2405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5136 .loc 1 2405 7 view .LVU1624 +2406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5137 .loc 1 2406 7 view .LVU1625 +2406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5138 .loc 1 2406 14 is_stmt 0 view .LVU1626 + 5139 00ae 0120 movs r0, #1 + 5140 00b0 69E0 b .L288 + 5141 .L292: +2417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5142 .loc 1 2417 7 is_stmt 1 view .LVU1627 +2417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5143 .loc 1 2417 28 is_stmt 0 view .LVU1628 + 5144 00b2 628D ldrh r2, [r4, #42] + 5145 00b4 92B2 uxth r2, r2 +2417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 5146 .loc 1 2417 22 view .LVU1629 + 5147 00b6 2285 strh r2, [r4, #40] +2418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5148 .loc 1 2418 7 is_stmt 1 view .LVU1630 + 5149 00b8 8023 movs r3, #128 + 5150 00ba D2B2 uxtb r2, r2 + 5151 00bc 0021 movs r1, #0 + 5152 00be 0091 str r1, [sp] + 5153 00c0 9B04 lsls r3, r3, #18 + 5154 00c2 0399 ldr r1, [sp, #12] + 5155 00c4 2000 movs r0, r4 + 5156 00c6 FFF7FEFF bl I2C_TransferConfig + 5157 .LVL344: + 5158 00ca 0FE0 b .L296 + 5159 .L295: +2454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5160 .loc 1 2454 11 view .LVU1631 +2454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5161 .loc 1 2454 32 is_stmt 0 view .LVU1632 + 5162 00cc 628D ldrh r2, [r4, #42] + 5163 00ce 92B2 uxth r2, r2 +2454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5164 .loc 1 2454 26 view .LVU1633 + 5165 00d0 2285 strh r2, [r4, #40] +2455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5166 .loc 1 2455 11 is_stmt 1 view .LVU1634 + 5167 00d2 8023 movs r3, #128 + 5168 00d4 D2B2 uxtb r2, r2 + 5169 00d6 0021 movs r1, #0 + 5170 00d8 0091 str r1, [sp] + 5171 00da 9B04 lsls r3, r3, #18 + 5172 00dc 0399 ldr r1, [sp, #12] + 5173 00de 2000 movs r0, r4 + 5174 00e0 FFF7FEFF bl I2C_TransferConfig + 5175 .LVL345: + 5176 .L294: +2460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5177 .loc 1 2460 13 view .LVU1635 +2460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5178 .loc 1 2460 18 is_stmt 0 view .LVU1636 + 5179 00e4 638D ldrh r3, [r4, #42] + ARM GAS /tmp/ccth6daj.s page 237 + + + 5180 00e6 9BB2 uxth r3, r3 +2460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5181 .loc 1 2460 5 view .LVU1637 + 5182 00e8 002B cmp r3, #0 + 5183 00ea 34D0 beq .L305 + 5184 .L296: +2421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5185 .loc 1 2421 5 is_stmt 1 view .LVU1638 +2424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5186 .loc 1 2424 7 view .LVU1639 +2424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5187 .loc 1 2424 11 is_stmt 0 view .LVU1640 + 5188 00ec 3200 movs r2, r6 + 5189 00ee 0E99 ldr r1, [sp, #56] + 5190 00f0 2000 movs r0, r4 + 5191 00f2 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 5192 .LVL346: +2424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5193 .loc 1 2424 10 view .LVU1641 + 5194 00f6 0028 cmp r0, #0 + 5195 00f8 49D1 bne .L300 +2430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5196 .loc 1 2430 7 is_stmt 1 view .LVU1642 +2430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5197 .loc 1 2430 11 is_stmt 0 view .LVU1643 + 5198 00fa 2368 ldr r3, [r4] +2430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5199 .loc 1 2430 30 view .LVU1644 + 5200 00fc 626A ldr r2, [r4, #36] + 5201 00fe 1278 ldrb r2, [r2] +2430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5202 .loc 1 2430 28 view .LVU1645 + 5203 0100 9A62 str r2, [r3, #40] +2433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5204 .loc 1 2433 7 is_stmt 1 view .LVU1646 +2433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5205 .loc 1 2433 21 is_stmt 0 view .LVU1647 + 5206 0102 636A ldr r3, [r4, #36] + 5207 0104 0133 adds r3, r3, #1 + 5208 0106 6362 str r3, [r4, #36] +2435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 5209 .loc 1 2435 7 is_stmt 1 view .LVU1648 +2435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 5210 .loc 1 2435 11 is_stmt 0 view .LVU1649 + 5211 0108 638D ldrh r3, [r4, #42] +2435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 5212 .loc 1 2435 22 view .LVU1650 + 5213 010a 013B subs r3, r3, #1 + 5214 010c 9BB2 uxth r3, r3 + 5215 010e 6385 strh r3, [r4, #42] +2436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5216 .loc 1 2436 7 is_stmt 1 view .LVU1651 +2436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5217 .loc 1 2436 11 is_stmt 0 view .LVU1652 + 5218 0110 238D ldrh r3, [r4, #40] +2436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5219 .loc 1 2436 21 view .LVU1653 + ARM GAS /tmp/ccth6daj.s page 238 + + + 5220 0112 013B subs r3, r3, #1 + 5221 0114 9BB2 uxth r3, r3 + 5222 0116 2385 strh r3, [r4, #40] +2438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5223 .loc 1 2438 7 is_stmt 1 view .LVU1654 +2438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5224 .loc 1 2438 16 is_stmt 0 view .LVU1655 + 5225 0118 628D ldrh r2, [r4, #42] + 5226 011a 92B2 uxth r2, r2 +2438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5227 .loc 1 2438 10 view .LVU1656 + 5228 011c 002A cmp r2, #0 + 5229 011e E1D0 beq .L294 +2438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5230 .loc 1 2438 35 discriminator 1 view .LVU1657 + 5231 0120 002B cmp r3, #0 + 5232 0122 DFD1 bne .L294 +2441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5233 .loc 1 2441 9 is_stmt 1 view .LVU1658 +2441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5234 .loc 1 2441 13 is_stmt 0 view .LVU1659 + 5235 0124 0096 str r6, [sp] + 5236 0126 0E9B ldr r3, [sp, #56] + 5237 0128 0022 movs r2, #0 + 5238 012a 8021 movs r1, #128 + 5239 012c 2000 movs r0, r4 + 5240 012e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5241 .LVL347: +2441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5242 .loc 1 2441 12 view .LVU1660 + 5243 0132 0028 cmp r0, #0 + 5244 0134 2DD1 bne .L301 +2446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5245 .loc 1 2446 9 is_stmt 1 view .LVU1661 +2446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5246 .loc 1 2446 17 is_stmt 0 view .LVU1662 + 5247 0136 638D ldrh r3, [r4, #42] + 5248 0138 9BB2 uxth r3, r3 +2446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5249 .loc 1 2446 12 view .LVU1663 + 5250 013a FF2B cmp r3, #255 + 5251 013c C6D9 bls .L295 +2448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5252 .loc 1 2448 11 is_stmt 1 view .LVU1664 +2448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5253 .loc 1 2448 26 is_stmt 0 view .LVU1665 + 5254 013e FF23 movs r3, #255 + 5255 0140 2385 strh r3, [r4, #40] +2449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5256 .loc 1 2449 11 is_stmt 1 view .LVU1666 + 5257 0142 7F3B subs r3, r3, #127 + 5258 0144 0022 movs r2, #0 + 5259 0146 0092 str r2, [sp] + 5260 0148 5B04 lsls r3, r3, #17 + 5261 014a FF32 adds r2, r2, #255 + 5262 014c 0399 ldr r1, [sp, #12] + 5263 014e 2000 movs r0, r4 + ARM GAS /tmp/ccth6daj.s page 239 + + + 5264 0150 FFF7FEFF bl I2C_TransferConfig + 5265 .LVL348: + 5266 0154 C6E7 b .L294 + 5267 .L305: +2464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5268 .loc 1 2464 5 view .LVU1667 +2464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5269 .loc 1 2464 9 is_stmt 0 view .LVU1668 + 5270 0156 3200 movs r2, r6 + 5271 0158 0E99 ldr r1, [sp, #56] + 5272 015a 2000 movs r0, r4 + 5273 015c FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5274 .LVL349: +2464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5275 .loc 1 2464 8 view .LVU1669 + 5276 0160 0028 cmp r0, #0 + 5277 0162 18D1 bne .L302 +2470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5278 .loc 1 2470 5 is_stmt 1 view .LVU1670 + 5279 0164 2368 ldr r3, [r4] + 5280 0166 2022 movs r2, #32 + 5281 0168 DA61 str r2, [r3, #28] +2473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5282 .loc 1 2473 5 view .LVU1671 + 5283 016a 2168 ldr r1, [r4] + 5284 016c 4B68 ldr r3, [r1, #4] + 5285 016e 0B4D ldr r5, .L306 + 5286 0170 2B40 ands r3, r5 + 5287 0172 4B60 str r3, [r1, #4] +2475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5288 .loc 1 2475 5 view .LVU1672 +2475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5289 .loc 1 2475 17 is_stmt 0 view .LVU1673 + 5290 0174 4123 movs r3, #65 + 5291 0176 E254 strb r2, [r4, r3] +2476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5292 .loc 1 2476 5 is_stmt 1 view .LVU1674 +2476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5293 .loc 1 2476 17 is_stmt 0 view .LVU1675 + 5294 0178 0023 movs r3, #0 + 5295 017a 2232 adds r2, r2, #34 + 5296 017c A354 strb r3, [r4, r2] +2479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5297 .loc 1 2479 5 is_stmt 1 view .LVU1676 +2479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5298 .loc 1 2479 5 view .LVU1677 + 5299 017e 023A subs r2, r2, #2 + 5300 0180 A354 strb r3, [r4, r2] +2479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5301 .loc 1 2479 5 view .LVU1678 +2481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5302 .loc 1 2481 5 view .LVU1679 +2481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5303 .loc 1 2481 12 is_stmt 0 view .LVU1680 + 5304 0182 00E0 b .L288 + 5305 .LVL350: + 5306 .L297: + ARM GAS /tmp/ccth6daj.s page 240 + + +2485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5307 .loc 1 2485 12 view .LVU1681 + 5308 0184 0220 movs r0, #2 + 5309 .LVL351: + 5310 .L288: +2487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5311 .loc 1 2487 1 view .LVU1682 + 5312 0186 07B0 add sp, sp, #28 + 5313 @ sp needed + 5314 .LVL352: +2487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5315 .loc 1 2487 1 view .LVU1683 + 5316 0188 F0BD pop {r4, r5, r6, r7, pc} + 5317 .LVL353: + 5318 .L298: +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5319 .loc 1 2382 5 view .LVU1684 + 5320 018a 0220 movs r0, #2 + 5321 .LVL354: +2382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5322 .loc 1 2382 5 view .LVU1685 + 5323 018c FBE7 b .L288 + 5324 .LVL355: + 5325 .L300: +2426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5326 .loc 1 2426 16 view .LVU1686 + 5327 018e 0120 movs r0, #1 + 5328 0190 F9E7 b .L288 + 5329 .L301: +2443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5330 .loc 1 2443 18 view .LVU1687 + 5331 0192 0120 movs r0, #1 + 5332 0194 F7E7 b .L288 + 5333 .L302: +2466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5334 .loc 1 2466 14 view .LVU1688 + 5335 0196 0120 movs r0, #1 + 5336 0198 F5E7 b .L288 + 5337 .L307: + 5338 019a C046 .align 2 + 5339 .L306: + 5340 019c 00E800FE .word -33495040 + 5341 .cfi_endproc + 5342 .LFE313: + 5344 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 5345 .align 1 + 5346 .global HAL_I2C_Mem_Read + 5347 .syntax unified + 5348 .code 16 + 5349 .thumb_func + 5350 .fpu softvfp + 5352 HAL_I2C_Mem_Read: + 5353 .LVL356: + 5354 .LFB314: +2504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5355 .loc 1 2504 1 is_stmt 1 view -0 + 5356 .cfi_startproc + ARM GAS /tmp/ccth6daj.s page 241 + + + 5357 @ args = 12, pretend = 0, frame = 16 + 5358 @ frame_needed = 0, uses_anonymous_args = 0 +2504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5359 .loc 1 2504 1 is_stmt 0 view .LVU1690 + 5360 0000 F0B5 push {r4, r5, r6, r7, lr} + 5361 .LCFI38: + 5362 .cfi_def_cfa_offset 20 + 5363 .cfi_offset 4, -20 + 5364 .cfi_offset 5, -16 + 5365 .cfi_offset 6, -12 + 5366 .cfi_offset 7, -8 + 5367 .cfi_offset 14, -4 + 5368 0002 87B0 sub sp, sp, #28 + 5369 .LCFI39: + 5370 .cfi_def_cfa_offset 48 + 5371 0004 0400 movs r4, r0 + 5372 0006 0391 str r1, [sp, #12] + 5373 0008 0492 str r2, [sp, #16] + 5374 000a 0593 str r3, [sp, #20] + 5375 000c 0CAB add r3, sp, #48 + 5376 .LVL357: +2504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5377 .loc 1 2504 1 view .LVU1691 + 5378 000e 20CB ldmia r3!, {r5} + 5379 .LVL358: +2504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5380 .loc 1 2504 1 view .LVU1692 + 5381 0010 1F88 ldrh r7, [r3] +2505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5382 .loc 1 2505 3 is_stmt 1 view .LVU1693 +2508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5383 .loc 1 2508 3 view .LVU1694 +2510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5384 .loc 1 2510 3 view .LVU1695 +2510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5385 .loc 1 2510 11 is_stmt 0 view .LVU1696 + 5386 0012 4123 movs r3, #65 + 5387 .LVL359: +2510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5388 .loc 1 2510 11 view .LVU1697 + 5389 0014 C35C ldrb r3, [r0, r3] +2510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5390 .loc 1 2510 6 view .LVU1698 + 5391 0016 202B cmp r3, #32 + 5392 0018 00D0 beq .LCB5071 + 5393 001a B5E0 b .L318 @long jump + 5394 .LCB5071: +2512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5395 .loc 1 2512 5 is_stmt 1 view .LVU1699 +2512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5396 .loc 1 2512 8 is_stmt 0 view .LVU1700 + 5397 001c 002D cmp r5, #0 + 5398 001e 18D0 beq .L310 +2512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5399 .loc 1 2512 25 discriminator 1 view .LVU1701 + 5400 0020 002F cmp r7, #0 + 5401 0022 16D0 beq .L310 + ARM GAS /tmp/ccth6daj.s page 242 + + +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5402 .loc 1 2519 5 is_stmt 1 view .LVU1702 +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5403 .loc 1 2519 5 view .LVU1703 + 5404 0024 4023 movs r3, #64 + 5405 0026 C35C ldrb r3, [r0, r3] + 5406 0028 012B cmp r3, #1 + 5407 002a 00D1 bne .LCB5082 + 5408 002c AFE0 b .L319 @long jump + 5409 .LCB5082: +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5410 .loc 1 2519 5 discriminator 2 view .LVU1704 + 5411 002e 4023 movs r3, #64 + 5412 0030 0122 movs r2, #1 + 5413 .LVL360: +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5414 .loc 1 2519 5 is_stmt 0 discriminator 2 view .LVU1705 + 5415 0032 C254 strb r2, [r0, r3] +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5416 .loc 1 2519 5 is_stmt 1 discriminator 2 view .LVU1706 +2522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5417 .loc 1 2522 5 discriminator 2 view .LVU1707 +2522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5418 .loc 1 2522 17 is_stmt 0 discriminator 2 view .LVU1708 + 5419 0034 FFF7FEFF bl HAL_GetTick + 5420 .LVL361: +2522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5421 .loc 1 2522 17 discriminator 2 view .LVU1709 + 5422 0038 0600 movs r6, r0 + 5423 .LVL362: +2524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5424 .loc 1 2524 5 is_stmt 1 discriminator 2 view .LVU1710 +2524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5425 .loc 1 2524 9 is_stmt 0 discriminator 2 view .LVU1711 + 5426 003a 8021 movs r1, #128 + 5427 003c 0090 str r0, [sp] + 5428 003e 1923 movs r3, #25 + 5429 0040 0122 movs r2, #1 + 5430 0042 0902 lsls r1, r1, #8 + 5431 0044 2000 movs r0, r4 + 5432 .LVL363: +2524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5433 .loc 1 2524 9 discriminator 2 view .LVU1712 + 5434 0046 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5435 .LVL364: +2524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5436 .loc 1 2524 8 discriminator 2 view .LVU1713 + 5437 004a 0028 cmp r0, #0 + 5438 004c 06D0 beq .L324 +2526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5439 .loc 1 2526 14 view .LVU1714 + 5440 004e 0120 movs r0, #1 + 5441 0050 9BE0 b .L309 + 5442 .LVL365: + 5443 .L310: +2514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5444 .loc 1 2514 7 is_stmt 1 view .LVU1715 + ARM GAS /tmp/ccth6daj.s page 243 + + +2514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5445 .loc 1 2514 23 is_stmt 0 view .LVU1716 + 5446 0052 8023 movs r3, #128 + 5447 0054 9B00 lsls r3, r3, #2 + 5448 0056 6364 str r3, [r4, #68] +2515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5449 .loc 1 2515 7 is_stmt 1 view .LVU1717 +2515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5450 .loc 1 2515 15 is_stmt 0 view .LVU1718 + 5451 0058 0120 movs r0, #1 + 5452 .LVL366: +2515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5453 .loc 1 2515 15 view .LVU1719 + 5454 005a 96E0 b .L309 + 5455 .LVL367: + 5456 .L324: +2529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5457 .loc 1 2529 5 is_stmt 1 view .LVU1720 +2529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5458 .loc 1 2529 21 is_stmt 0 view .LVU1721 + 5459 005c 4123 movs r3, #65 + 5460 005e 2222 movs r2, #34 + 5461 0060 E254 strb r2, [r4, r3] +2530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5462 .loc 1 2530 5 is_stmt 1 view .LVU1722 +2530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5463 .loc 1 2530 21 is_stmt 0 view .LVU1723 + 5464 0062 0133 adds r3, r3, #1 + 5465 0064 1E32 adds r2, r2, #30 + 5466 0066 E254 strb r2, [r4, r3] +2531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5467 .loc 1 2531 5 is_stmt 1 view .LVU1724 +2531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5468 .loc 1 2531 21 is_stmt 0 view .LVU1725 + 5469 0068 0023 movs r3, #0 + 5470 006a 6364 str r3, [r4, #68] +2534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5471 .loc 1 2534 5 is_stmt 1 view .LVU1726 +2534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5472 .loc 1 2534 21 is_stmt 0 view .LVU1727 + 5473 006c 6562 str r5, [r4, #36] +2535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5474 .loc 1 2535 5 is_stmt 1 view .LVU1728 +2535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 5475 .loc 1 2535 21 is_stmt 0 view .LVU1729 + 5476 006e 6785 strh r7, [r4, #42] +2536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5477 .loc 1 2536 5 is_stmt 1 view .LVU1730 +2536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5478 .loc 1 2536 21 is_stmt 0 view .LVU1731 + 5479 0070 6363 str r3, [r4, #52] +2539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5480 .loc 1 2539 5 is_stmt 1 view .LVU1732 +2539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5481 .loc 1 2539 9 is_stmt 0 view .LVU1733 + 5482 0072 0196 str r6, [sp, #4] + 5483 0074 0E9B ldr r3, [sp, #56] + ARM GAS /tmp/ccth6daj.s page 244 + + + 5484 0076 0093 str r3, [sp] + 5485 0078 059B ldr r3, [sp, #20] + 5486 007a 049A ldr r2, [sp, #16] + 5487 007c 0399 ldr r1, [sp, #12] + 5488 007e 2000 movs r0, r4 + 5489 0080 FFF7FEFF bl I2C_RequestMemoryRead + 5490 .LVL368: +2539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5491 .loc 1 2539 8 view .LVU1734 + 5492 0084 0028 cmp r0, #0 + 5493 0086 0FD1 bne .L325 +2548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5494 .loc 1 2548 5 is_stmt 1 view .LVU1735 +2548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5495 .loc 1 2548 13 is_stmt 0 view .LVU1736 + 5496 0088 638D ldrh r3, [r4, #42] + 5497 008a 9BB2 uxth r3, r3 +2548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5498 .loc 1 2548 8 view .LVU1737 + 5499 008c FF2B cmp r3, #255 + 5500 008e 10D9 bls .L313 +2550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5501 .loc 1 2550 7 is_stmt 1 view .LVU1738 +2550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 5502 .loc 1 2550 22 is_stmt 0 view .LVU1739 + 5503 0090 FF23 movs r3, #255 + 5504 0092 2385 strh r3, [r4, #40] +2551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5505 .loc 1 2551 7 is_stmt 1 view .LVU1740 + 5506 0094 7F3B subs r3, r3, #127 + 5507 0096 424A ldr r2, .L327 + 5508 0098 0092 str r2, [sp] + 5509 009a 5B04 lsls r3, r3, #17 + 5510 009c FF22 movs r2, #255 + 5511 009e 0399 ldr r1, [sp, #12] + 5512 00a0 2000 movs r0, r4 + 5513 00a2 FFF7FEFF bl I2C_TransferConfig + 5514 .LVL369: + 5515 00a6 21E0 b .L317 + 5516 .L325: +2542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5517 .loc 1 2542 7 view .LVU1741 +2542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5518 .loc 1 2542 7 view .LVU1742 + 5519 00a8 4023 movs r3, #64 + 5520 00aa 0022 movs r2, #0 + 5521 00ac E254 strb r2, [r4, r3] +2542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5522 .loc 1 2542 7 view .LVU1743 +2543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5523 .loc 1 2543 7 view .LVU1744 +2543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5524 .loc 1 2543 14 is_stmt 0 view .LVU1745 + 5525 00ae 0120 movs r0, #1 + 5526 00b0 6BE0 b .L309 + 5527 .L313: +2556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + ARM GAS /tmp/ccth6daj.s page 245 + + + 5528 .loc 1 2556 7 is_stmt 1 view .LVU1746 +2556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5529 .loc 1 2556 28 is_stmt 0 view .LVU1747 + 5530 00b2 628D ldrh r2, [r4, #42] + 5531 00b4 92B2 uxth r2, r2 +2556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5532 .loc 1 2556 22 view .LVU1748 + 5533 00b6 2285 strh r2, [r4, #40] +2557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 5534 .loc 1 2557 7 is_stmt 1 view .LVU1749 + 5535 00b8 8023 movs r3, #128 + 5536 00ba D2B2 uxtb r2, r2 + 5537 00bc 3849 ldr r1, .L327 + 5538 00be 0091 str r1, [sp] + 5539 00c0 9B04 lsls r3, r3, #18 + 5540 00c2 0399 ldr r1, [sp, #12] + 5541 00c4 2000 movs r0, r4 + 5542 00c6 FFF7FEFF bl I2C_TransferConfig + 5543 .LVL370: + 5544 00ca 0FE0 b .L317 + 5545 .L316: +2594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5546 .loc 1 2594 11 view .LVU1750 +2594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5547 .loc 1 2594 32 is_stmt 0 view .LVU1751 + 5548 00cc 628D ldrh r2, [r4, #42] + 5549 00ce 92B2 uxth r2, r2 +2594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 5550 .loc 1 2594 26 view .LVU1752 + 5551 00d0 2285 strh r2, [r4, #40] +2595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5552 .loc 1 2595 11 is_stmt 1 view .LVU1753 + 5553 00d2 8023 movs r3, #128 + 5554 00d4 D2B2 uxtb r2, r2 + 5555 00d6 0021 movs r1, #0 + 5556 00d8 0091 str r1, [sp] + 5557 00da 9B04 lsls r3, r3, #18 + 5558 00dc 0399 ldr r1, [sp, #12] + 5559 00de 2000 movs r0, r4 + 5560 00e0 FFF7FEFF bl I2C_TransferConfig + 5561 .LVL371: + 5562 .L315: +2599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5563 .loc 1 2599 13 view .LVU1754 +2599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5564 .loc 1 2599 18 is_stmt 0 view .LVU1755 + 5565 00e4 638D ldrh r3, [r4, #42] + 5566 00e6 9BB2 uxth r3, r3 +2599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5567 .loc 1 2599 5 view .LVU1756 + 5568 00e8 002B cmp r3, #0 + 5569 00ea 36D0 beq .L326 + 5570 .L317: +2561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5571 .loc 1 2561 5 is_stmt 1 view .LVU1757 +2564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5572 .loc 1 2564 7 view .LVU1758 + ARM GAS /tmp/ccth6daj.s page 246 + + +2564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5573 .loc 1 2564 11 is_stmt 0 view .LVU1759 + 5574 00ec 0096 str r6, [sp] + 5575 00ee 0E9B ldr r3, [sp, #56] + 5576 00f0 0022 movs r2, #0 + 5577 00f2 0421 movs r1, #4 + 5578 00f4 2000 movs r0, r4 + 5579 00f6 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5580 .LVL372: +2564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5581 .loc 1 2564 10 view .LVU1760 + 5582 00fa 0028 cmp r0, #0 + 5583 00fc 49D1 bne .L321 +2570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5584 .loc 1 2570 7 is_stmt 1 view .LVU1761 +2570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5585 .loc 1 2570 38 is_stmt 0 view .LVU1762 + 5586 00fe 2368 ldr r3, [r4] +2570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5587 .loc 1 2570 48 view .LVU1763 + 5588 0100 5B6A ldr r3, [r3, #36] +2570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5589 .loc 1 2570 23 view .LVU1764 + 5590 0102 626A ldr r2, [r4, #36] + 5591 0104 1370 strb r3, [r2] +2573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5592 .loc 1 2573 7 is_stmt 1 view .LVU1765 +2573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5593 .loc 1 2573 21 is_stmt 0 view .LVU1766 + 5594 0106 636A ldr r3, [r4, #36] + 5595 0108 0133 adds r3, r3, #1 + 5596 010a 6362 str r3, [r4, #36] +2575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 5597 .loc 1 2575 7 is_stmt 1 view .LVU1767 +2575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 5598 .loc 1 2575 11 is_stmt 0 view .LVU1768 + 5599 010c 238D ldrh r3, [r4, #40] +2575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 5600 .loc 1 2575 21 view .LVU1769 + 5601 010e 013B subs r3, r3, #1 + 5602 0110 9BB2 uxth r3, r3 + 5603 0112 2385 strh r3, [r4, #40] +2576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5604 .loc 1 2576 7 is_stmt 1 view .LVU1770 +2576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5605 .loc 1 2576 11 is_stmt 0 view .LVU1771 + 5606 0114 628D ldrh r2, [r4, #42] +2576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5607 .loc 1 2576 22 view .LVU1772 + 5608 0116 013A subs r2, r2, #1 + 5609 0118 92B2 uxth r2, r2 + 5610 011a 6285 strh r2, [r4, #42] +2578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5611 .loc 1 2578 7 is_stmt 1 view .LVU1773 +2578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5612 .loc 1 2578 16 is_stmt 0 view .LVU1774 + 5613 011c 628D ldrh r2, [r4, #42] + ARM GAS /tmp/ccth6daj.s page 247 + + + 5614 011e 92B2 uxth r2, r2 +2578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5615 .loc 1 2578 10 view .LVU1775 + 5616 0120 002A cmp r2, #0 + 5617 0122 DFD0 beq .L315 +2578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5618 .loc 1 2578 35 discriminator 1 view .LVU1776 + 5619 0124 002B cmp r3, #0 + 5620 0126 DDD1 bne .L315 +2581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5621 .loc 1 2581 9 is_stmt 1 view .LVU1777 +2581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5622 .loc 1 2581 13 is_stmt 0 view .LVU1778 + 5623 0128 0096 str r6, [sp] + 5624 012a 0E9B ldr r3, [sp, #56] + 5625 012c 0022 movs r2, #0 + 5626 012e 8021 movs r1, #128 + 5627 0130 2000 movs r0, r4 + 5628 0132 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5629 .LVL373: +2581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5630 .loc 1 2581 12 view .LVU1779 + 5631 0136 0028 cmp r0, #0 + 5632 0138 2DD1 bne .L322 +2586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5633 .loc 1 2586 9 is_stmt 1 view .LVU1780 +2586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5634 .loc 1 2586 17 is_stmt 0 view .LVU1781 + 5635 013a 638D ldrh r3, [r4, #42] + 5636 013c 9BB2 uxth r3, r3 +2586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5637 .loc 1 2586 12 view .LVU1782 + 5638 013e FF2B cmp r3, #255 + 5639 0140 C4D9 bls .L316 +2588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5640 .loc 1 2588 11 is_stmt 1 view .LVU1783 +2588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 5641 .loc 1 2588 26 is_stmt 0 view .LVU1784 + 5642 0142 FF23 movs r3, #255 + 5643 0144 2385 strh r3, [r4, #40] +2589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_NO_STARTSTOP); + 5644 .loc 1 2589 11 is_stmt 1 view .LVU1785 + 5645 0146 7F3B subs r3, r3, #127 + 5646 0148 0022 movs r2, #0 + 5647 014a 0092 str r2, [sp] + 5648 014c 5B04 lsls r3, r3, #17 + 5649 014e FF32 adds r2, r2, #255 + 5650 0150 0399 ldr r1, [sp, #12] + 5651 0152 2000 movs r0, r4 + 5652 0154 FFF7FEFF bl I2C_TransferConfig + 5653 .LVL374: + 5654 0158 C4E7 b .L315 + 5655 .L326: +2603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5656 .loc 1 2603 5 view .LVU1786 +2603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5657 .loc 1 2603 9 is_stmt 0 view .LVU1787 + ARM GAS /tmp/ccth6daj.s page 248 + + + 5658 015a 3200 movs r2, r6 + 5659 015c 0E99 ldr r1, [sp, #56] + 5660 015e 2000 movs r0, r4 + 5661 0160 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 5662 .LVL375: +2603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5663 .loc 1 2603 8 view .LVU1788 + 5664 0164 0028 cmp r0, #0 + 5665 0166 18D1 bne .L323 +2609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5666 .loc 1 2609 5 is_stmt 1 view .LVU1789 + 5667 0168 2368 ldr r3, [r4] + 5668 016a 2022 movs r2, #32 + 5669 016c DA61 str r2, [r3, #28] +2612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5670 .loc 1 2612 5 view .LVU1790 + 5671 016e 2168 ldr r1, [r4] + 5672 0170 4B68 ldr r3, [r1, #4] + 5673 0172 0C4D ldr r5, .L327+4 + 5674 0174 2B40 ands r3, r5 + 5675 0176 4B60 str r3, [r1, #4] +2614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5676 .loc 1 2614 5 view .LVU1791 +2614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5677 .loc 1 2614 17 is_stmt 0 view .LVU1792 + 5678 0178 4123 movs r3, #65 + 5679 017a E254 strb r2, [r4, r3] +2615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5680 .loc 1 2615 5 is_stmt 1 view .LVU1793 +2615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5681 .loc 1 2615 17 is_stmt 0 view .LVU1794 + 5682 017c 0023 movs r3, #0 + 5683 017e 2232 adds r2, r2, #34 + 5684 0180 A354 strb r3, [r4, r2] +2618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5685 .loc 1 2618 5 is_stmt 1 view .LVU1795 +2618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5686 .loc 1 2618 5 view .LVU1796 + 5687 0182 023A subs r2, r2, #2 + 5688 0184 A354 strb r3, [r4, r2] +2618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5689 .loc 1 2618 5 view .LVU1797 +2620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5690 .loc 1 2620 5 view .LVU1798 +2620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5691 .loc 1 2620 12 is_stmt 0 view .LVU1799 + 5692 0186 00E0 b .L309 + 5693 .LVL376: + 5694 .L318: +2624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5695 .loc 1 2624 12 view .LVU1800 + 5696 0188 0220 movs r0, #2 + 5697 .LVL377: + 5698 .L309: +2626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 5699 .loc 1 2626 1 view .LVU1801 + 5700 018a 07B0 add sp, sp, #28 + ARM GAS /tmp/ccth6daj.s page 249 + + + 5701 @ sp needed + 5702 .LVL378: +2626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 5703 .loc 1 2626 1 view .LVU1802 + 5704 018c F0BD pop {r4, r5, r6, r7, pc} + 5705 .LVL379: + 5706 .L319: +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5707 .loc 1 2519 5 view .LVU1803 + 5708 018e 0220 movs r0, #2 + 5709 .LVL380: +2519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5710 .loc 1 2519 5 view .LVU1804 + 5711 0190 FBE7 b .L309 + 5712 .LVL381: + 5713 .L321: +2566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5714 .loc 1 2566 16 view .LVU1805 + 5715 0192 0120 movs r0, #1 + 5716 0194 F9E7 b .L309 + 5717 .L322: +2583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5718 .loc 1 2583 18 view .LVU1806 + 5719 0196 0120 movs r0, #1 + 5720 0198 F7E7 b .L309 + 5721 .L323: +2605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5722 .loc 1 2605 14 view .LVU1807 + 5723 019a 0120 movs r0, #1 + 5724 019c F5E7 b .L309 + 5725 .L328: + 5726 019e C046 .align 2 + 5727 .L327: + 5728 01a0 00240080 .word -2147474432 + 5729 01a4 00E800FE .word -33495040 + 5730 .cfi_endproc + 5731 .LFE314: + 5733 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 5734 .align 1 + 5735 .global HAL_I2C_Mem_Write_IT + 5736 .syntax unified + 5737 .code 16 + 5738 .thumb_func + 5739 .fpu softvfp + 5741 HAL_I2C_Mem_Write_IT: + 5742 .LVL382: + 5743 .LFB315: +2641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5744 .loc 1 2641 1 is_stmt 1 view -0 + 5745 .cfi_startproc + 5746 @ args = 8, pretend = 0, frame = 8 + 5747 @ frame_needed = 0, uses_anonymous_args = 0 +2641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5748 .loc 1 2641 1 is_stmt 0 view .LVU1809 + 5749 0000 F0B5 push {r4, r5, r6, r7, lr} + 5750 .LCFI40: + 5751 .cfi_def_cfa_offset 20 + ARM GAS /tmp/ccth6daj.s page 250 + + + 5752 .cfi_offset 4, -20 + 5753 .cfi_offset 5, -16 + 5754 .cfi_offset 6, -12 + 5755 .cfi_offset 7, -8 + 5756 .cfi_offset 14, -4 + 5757 0002 D646 mov lr, r10 + 5758 0004 4746 mov r7, r8 + 5759 0006 80B5 push {r7, lr} + 5760 .LCFI41: + 5761 .cfi_def_cfa_offset 28 + 5762 .cfi_offset 8, -28 + 5763 .cfi_offset 10, -24 + 5764 0008 85B0 sub sp, sp, #20 + 5765 .LCFI42: + 5766 .cfi_def_cfa_offset 48 + 5767 000a 0400 movs r4, r0 + 5768 000c 0D00 movs r5, r1 + 5769 000e 0292 str r2, [sp, #8] + 5770 0010 0393 str r3, [sp, #12] + 5771 0012 0CAB add r3, sp, #48 + 5772 .LVL383: +2641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5773 .loc 1 2641 1 view .LVU1810 + 5774 0014 80CB ldmia r3!, {r7} + 5775 .LVL384: +2641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5776 .loc 1 2641 1 view .LVU1811 + 5777 0016 1E88 ldrh r6, [r3] +2642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 5778 .loc 1 2642 3 is_stmt 1 view .LVU1812 +2643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5779 .loc 1 2643 3 view .LVU1813 +2646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5780 .loc 1 2646 3 view .LVU1814 +2648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5781 .loc 1 2648 3 view .LVU1815 +2648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5782 .loc 1 2648 11 is_stmt 0 view .LVU1816 + 5783 0018 4123 movs r3, #65 + 5784 .LVL385: +2648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5785 .loc 1 2648 11 view .LVU1817 + 5786 001a C35C ldrb r3, [r0, r3] +2648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5787 .loc 1 2648 6 view .LVU1818 + 5788 001c 202B cmp r3, #32 + 5789 001e 54D1 bne .L336 +2650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5790 .loc 1 2650 5 is_stmt 1 view .LVU1819 +2650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5791 .loc 1 2650 8 is_stmt 0 view .LVU1820 + 5792 0020 002F cmp r7, #0 + 5793 0022 37D0 beq .L331 +2650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5794 .loc 1 2650 25 discriminator 1 view .LVU1821 + 5795 0024 002E cmp r6, #0 + 5796 0026 35D0 beq .L331 + ARM GAS /tmp/ccth6daj.s page 251 + + +2656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5797 .loc 1 2656 5 is_stmt 1 view .LVU1822 +2656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5798 .loc 1 2656 9 is_stmt 0 view .LVU1823 + 5799 0028 0368 ldr r3, [r0] + 5800 002a 9B69 ldr r3, [r3, #24] +2656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5801 .loc 1 2656 8 view .LVU1824 + 5802 002c 1B04 lsls r3, r3, #16 + 5803 002e 53D4 bmi .L337 +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5804 .loc 1 2662 5 is_stmt 1 view .LVU1825 +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5805 .loc 1 2662 5 view .LVU1826 + 5806 0030 4023 movs r3, #64 + 5807 0032 C35C ldrb r3, [r0, r3] + 5808 0034 012B cmp r3, #1 + 5809 0036 51D0 beq .L338 +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5810 .loc 1 2662 5 discriminator 2 view .LVU1827 + 5811 0038 4023 movs r3, #64 + 5812 003a 9A46 mov r10, r3 + 5813 003c 3F3B subs r3, r3, #63 + 5814 003e 5246 mov r2, r10 + 5815 .LVL386: +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5816 .loc 1 2662 5 is_stmt 0 discriminator 2 view .LVU1828 + 5817 0040 8354 strb r3, [r0, r2] +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5818 .loc 1 2662 5 is_stmt 1 discriminator 2 view .LVU1829 +2665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5819 .loc 1 2665 5 discriminator 2 view .LVU1830 +2665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5820 .loc 1 2665 17 is_stmt 0 discriminator 2 view .LVU1831 + 5821 0042 FFF7FEFF bl HAL_GetTick + 5822 .LVL387: +2667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5823 .loc 1 2667 5 is_stmt 1 discriminator 2 view .LVU1832 +2667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5824 .loc 1 2667 23 is_stmt 0 discriminator 2 view .LVU1833 + 5825 0046 4123 movs r3, #65 + 5826 0048 2122 movs r2, #33 + 5827 004a E254 strb r2, [r4, r3] +2668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5828 .loc 1 2668 5 is_stmt 1 discriminator 2 view .LVU1834 +2668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5829 .loc 1 2668 23 is_stmt 0 discriminator 2 view .LVU1835 + 5830 004c 0133 adds r3, r3, #1 + 5831 004e 5246 mov r2, r10 + 5832 0050 E254 strb r2, [r4, r3] +2669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5833 .loc 1 2669 5 is_stmt 1 discriminator 2 view .LVU1836 +2669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5834 .loc 1 2669 23 is_stmt 0 discriminator 2 view .LVU1837 + 5835 0052 0023 movs r3, #0 + 5836 0054 6364 str r3, [r4, #68] +2672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + ARM GAS /tmp/ccth6daj.s page 252 + + + 5837 .loc 1 2672 5 is_stmt 1 discriminator 2 view .LVU1838 +2672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 5838 .loc 1 2672 23 is_stmt 0 discriminator 2 view .LVU1839 + 5839 0056 6762 str r7, [r4, #36] +2673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5840 .loc 1 2673 5 is_stmt 1 discriminator 2 view .LVU1840 +2673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5841 .loc 1 2673 23 is_stmt 0 discriminator 2 view .LVU1841 + 5842 0058 6685 strh r6, [r4, #42] +2674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5843 .loc 1 2674 5 is_stmt 1 discriminator 2 view .LVU1842 +2674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5844 .loc 1 2674 23 is_stmt 0 discriminator 2 view .LVU1843 + 5845 005a 214B ldr r3, .L339 + 5846 005c E362 str r3, [r4, #44] +2675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5847 .loc 1 2675 5 is_stmt 1 discriminator 2 view .LVU1844 +2675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5848 .loc 1 2675 23 is_stmt 0 discriminator 2 view .LVU1845 + 5849 005e 214B ldr r3, .L339+4 + 5850 0060 6363 str r3, [r4, #52] +2677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5851 .loc 1 2677 5 is_stmt 1 discriminator 2 view .LVU1846 +2677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5852 .loc 1 2677 13 is_stmt 0 discriminator 2 view .LVU1847 + 5853 0062 638D ldrh r3, [r4, #42] + 5854 0064 9BB2 uxth r3, r3 +2677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 5855 .loc 1 2677 8 discriminator 2 view .LVU1848 + 5856 0066 FF2B cmp r3, #255 + 5857 0068 19D9 bls .L333 +2679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5858 .loc 1 2679 7 is_stmt 1 view .LVU1849 +2679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5859 .loc 1 2679 22 is_stmt 0 view .LVU1850 + 5860 006a FF23 movs r3, #255 + 5861 006c 2385 strh r3, [r4, #40] +2680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5862 .loc 1 2680 7 is_stmt 1 view .LVU1851 + 5863 .LVL388: +2680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5864 .loc 1 2680 16 is_stmt 0 view .LVU1852 + 5865 006e 8023 movs r3, #128 + 5866 0070 5B04 lsls r3, r3, #17 + 5867 0072 9846 mov r8, r3 + 5868 .LVL389: + 5869 .L334: +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 5870 .loc 1 2689 5 is_stmt 1 view .LVU1853 +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 5871 .loc 1 2689 9 is_stmt 0 view .LVU1854 + 5872 0074 0190 str r0, [sp, #4] + 5873 0076 1923 movs r3, #25 + 5874 0078 0093 str r3, [sp] + 5875 007a 039B ldr r3, [sp, #12] + 5876 007c 029A ldr r2, [sp, #8] + 5877 007e 2900 movs r1, r5 + ARM GAS /tmp/ccth6daj.s page 253 + + + 5878 0080 2000 movs r0, r4 + 5879 .LVL390: +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 5880 .loc 1 2689 9 view .LVU1855 + 5881 0082 FFF7FEFF bl I2C_RequestMemoryWrite + 5882 .LVL391: +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 5883 .loc 1 2689 9 view .LVU1856 + 5884 0086 061E subs r6, r0, #0 +2689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 5885 .loc 1 2689 8 view .LVU1857 + 5886 0088 0FD0 beq .L335 +2693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5887 .loc 1 2693 7 is_stmt 1 view .LVU1858 +2693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5888 .loc 1 2693 7 view .LVU1859 + 5889 008a 4023 movs r3, #64 + 5890 008c 0022 movs r2, #0 + 5891 008e E254 strb r2, [r4, r3] +2693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5892 .loc 1 2693 7 view .LVU1860 +2694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5893 .loc 1 2694 7 view .LVU1861 +2694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5894 .loc 1 2694 14 is_stmt 0 view .LVU1862 + 5895 0090 0126 movs r6, #1 + 5896 0092 1BE0 b .L330 + 5897 .LVL392: + 5898 .L331: +2652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5899 .loc 1 2652 7 is_stmt 1 view .LVU1863 +2652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 5900 .loc 1 2652 23 is_stmt 0 view .LVU1864 + 5901 0094 8023 movs r3, #128 + 5902 0096 9B00 lsls r3, r3, #2 + 5903 0098 6364 str r3, [r4, #68] +2653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5904 .loc 1 2653 7 is_stmt 1 view .LVU1865 +2653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5905 .loc 1 2653 15 is_stmt 0 view .LVU1866 + 5906 009a 0126 movs r6, #1 + 5907 009c 16E0 b .L330 + 5908 .LVL393: + 5909 .L333: +2684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5910 .loc 1 2684 7 is_stmt 1 view .LVU1867 +2684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5911 .loc 1 2684 28 is_stmt 0 view .LVU1868 + 5912 009e 638D ldrh r3, [r4, #42] +2684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 5913 .loc 1 2684 22 view .LVU1869 + 5914 00a0 2385 strh r3, [r4, #40] +2685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5915 .loc 1 2685 7 is_stmt 1 view .LVU1870 + 5916 .LVL394: +2685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5917 .loc 1 2685 16 is_stmt 0 view .LVU1871 + ARM GAS /tmp/ccth6daj.s page 254 + + + 5918 00a2 8023 movs r3, #128 + 5919 00a4 9B04 lsls r3, r3, #18 + 5920 00a6 9846 mov r8, r3 + 5921 00a8 E4E7 b .L334 + 5922 .LVL395: + 5923 .L335: +2698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5924 .loc 1 2698 5 is_stmt 1 view .LVU1872 +2698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5925 .loc 1 2698 55 is_stmt 0 view .LVU1873 + 5926 00aa 228D ldrh r2, [r4, #40] +2698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5927 .loc 1 2698 5 view .LVU1874 + 5928 00ac D2B2 uxtb r2, r2 + 5929 00ae 0027 movs r7, #0 + 5930 00b0 0097 str r7, [sp] + 5931 00b2 4346 mov r3, r8 + 5932 00b4 2900 movs r1, r5 + 5933 00b6 2000 movs r0, r4 + 5934 00b8 FFF7FEFF bl I2C_TransferConfig + 5935 .LVL396: +2701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5936 .loc 1 2701 5 is_stmt 1 view .LVU1875 +2701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5937 .loc 1 2701 5 view .LVU1876 + 5938 00bc 4023 movs r3, #64 + 5939 00be E754 strb r7, [r4, r3] +2701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5940 .loc 1 2701 5 view .LVU1877 +2711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5941 .loc 1 2711 5 view .LVU1878 + 5942 00c0 0121 movs r1, #1 + 5943 00c2 2000 movs r0, r4 + 5944 00c4 FFF7FEFF bl I2C_Enable_IRQ + 5945 .LVL397: +2713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5946 .loc 1 2713 5 view .LVU1879 +2713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5947 .loc 1 2713 12 is_stmt 0 view .LVU1880 + 5948 00c8 00E0 b .L330 + 5949 .LVL398: + 5950 .L336: +2717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5951 .loc 1 2717 12 view .LVU1881 + 5952 00ca 0226 movs r6, #2 + 5953 .LVL399: + 5954 .L330: +2719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5955 .loc 1 2719 1 view .LVU1882 + 5956 00cc 3000 movs r0, r6 + 5957 00ce 05B0 add sp, sp, #20 + 5958 @ sp needed + 5959 .LVL400: +2719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5960 .loc 1 2719 1 view .LVU1883 + 5961 00d0 C0BC pop {r6, r7} + 5962 00d2 BA46 mov r10, r7 + ARM GAS /tmp/ccth6daj.s page 255 + + + 5963 00d4 B046 mov r8, r6 + 5964 00d6 F0BD pop {r4, r5, r6, r7, pc} + 5965 .LVL401: + 5966 .L337: +2658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 5967 .loc 1 2658 14 view .LVU1884 + 5968 00d8 0226 movs r6, #2 + 5969 00da F7E7 b .L330 + 5970 .L338: +2662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 5971 .loc 1 2662 5 view .LVU1885 + 5972 00dc 0226 movs r6, #2 + 5973 00de F5E7 b .L330 + 5974 .L340: + 5975 .align 2 + 5976 .L339: + 5977 00e0 0000FFFF .word -65536 + 5978 00e4 00000000 .word I2C_Master_ISR_IT + 5979 .cfi_endproc + 5980 .LFE315: + 5982 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 5983 .align 1 + 5984 .global HAL_I2C_Mem_Read_IT + 5985 .syntax unified + 5986 .code 16 + 5987 .thumb_func + 5988 .fpu softvfp + 5990 HAL_I2C_Mem_Read_IT: + 5991 .LVL402: + 5992 .LFB316: +2735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5993 .loc 1 2735 1 is_stmt 1 view -0 + 5994 .cfi_startproc + 5995 @ args = 8, pretend = 0, frame = 8 + 5996 @ frame_needed = 0, uses_anonymous_args = 0 +2735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 5997 .loc 1 2735 1 is_stmt 0 view .LVU1887 + 5998 0000 F0B5 push {r4, r5, r6, r7, lr} + 5999 .LCFI43: + 6000 .cfi_def_cfa_offset 20 + 6001 .cfi_offset 4, -20 + 6002 .cfi_offset 5, -16 + 6003 .cfi_offset 6, -12 + 6004 .cfi_offset 7, -8 + 6005 .cfi_offset 14, -4 + 6006 0002 D646 mov lr, r10 + 6007 0004 4746 mov r7, r8 + 6008 0006 80B5 push {r7, lr} + 6009 .LCFI44: + 6010 .cfi_def_cfa_offset 28 + 6011 .cfi_offset 8, -28 + 6012 .cfi_offset 10, -24 + 6013 0008 85B0 sub sp, sp, #20 + 6014 .LCFI45: + 6015 .cfi_def_cfa_offset 48 + 6016 000a 0400 movs r4, r0 + 6017 000c 0D00 movs r5, r1 + ARM GAS /tmp/ccth6daj.s page 256 + + + 6018 000e 0292 str r2, [sp, #8] + 6019 0010 0393 str r3, [sp, #12] + 6020 0012 0CAB add r3, sp, #48 + 6021 .LVL403: +2735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6022 .loc 1 2735 1 view .LVU1888 + 6023 0014 80CB ldmia r3!, {r7} + 6024 .LVL404: +2735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6025 .loc 1 2735 1 view .LVU1889 + 6026 0016 1E88 ldrh r6, [r3] +2736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 6027 .loc 1 2736 3 is_stmt 1 view .LVU1890 +2737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6028 .loc 1 2737 3 view .LVU1891 +2740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6029 .loc 1 2740 3 view .LVU1892 +2742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6030 .loc 1 2742 3 view .LVU1893 +2742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6031 .loc 1 2742 11 is_stmt 0 view .LVU1894 + 6032 0018 4123 movs r3, #65 + 6033 .LVL405: +2742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6034 .loc 1 2742 11 view .LVU1895 + 6035 001a C35C ldrb r3, [r0, r3] +2742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6036 .loc 1 2742 6 view .LVU1896 + 6037 001c 202B cmp r3, #32 + 6038 001e 55D1 bne .L348 +2744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6039 .loc 1 2744 5 is_stmt 1 view .LVU1897 +2744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6040 .loc 1 2744 8 is_stmt 0 view .LVU1898 + 6041 0020 002F cmp r7, #0 + 6042 0022 37D0 beq .L343 +2744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6043 .loc 1 2744 25 discriminator 1 view .LVU1899 + 6044 0024 002E cmp r6, #0 + 6045 0026 35D0 beq .L343 +2750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6046 .loc 1 2750 5 is_stmt 1 view .LVU1900 +2750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6047 .loc 1 2750 9 is_stmt 0 view .LVU1901 + 6048 0028 0368 ldr r3, [r0] + 6049 002a 9B69 ldr r3, [r3, #24] +2750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6050 .loc 1 2750 8 view .LVU1902 + 6051 002c 1B04 lsls r3, r3, #16 + 6052 002e 54D4 bmi .L349 +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6053 .loc 1 2756 5 is_stmt 1 view .LVU1903 +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6054 .loc 1 2756 5 view .LVU1904 + 6055 0030 4023 movs r3, #64 + 6056 0032 C35C ldrb r3, [r0, r3] + 6057 0034 012B cmp r3, #1 + ARM GAS /tmp/ccth6daj.s page 257 + + + 6058 0036 52D0 beq .L350 +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6059 .loc 1 2756 5 discriminator 2 view .LVU1905 + 6060 0038 4023 movs r3, #64 + 6061 003a 9A46 mov r10, r3 + 6062 003c 3F3B subs r3, r3, #63 + 6063 003e 5246 mov r2, r10 + 6064 .LVL406: +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6065 .loc 1 2756 5 is_stmt 0 discriminator 2 view .LVU1906 + 6066 0040 8354 strb r3, [r0, r2] +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6067 .loc 1 2756 5 is_stmt 1 discriminator 2 view .LVU1907 +2759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6068 .loc 1 2759 5 discriminator 2 view .LVU1908 +2759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6069 .loc 1 2759 17 is_stmt 0 discriminator 2 view .LVU1909 + 6070 0042 FFF7FEFF bl HAL_GetTick + 6071 .LVL407: +2761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6072 .loc 1 2761 5 is_stmt 1 discriminator 2 view .LVU1910 +2761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6073 .loc 1 2761 23 is_stmt 0 discriminator 2 view .LVU1911 + 6074 0046 4123 movs r3, #65 + 6075 0048 2222 movs r2, #34 + 6076 004a E254 strb r2, [r4, r3] +2762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6077 .loc 1 2762 5 is_stmt 1 discriminator 2 view .LVU1912 +2762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6078 .loc 1 2762 23 is_stmt 0 discriminator 2 view .LVU1913 + 6079 004c 0133 adds r3, r3, #1 + 6080 004e 5246 mov r2, r10 + 6081 0050 E254 strb r2, [r4, r3] +2763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6082 .loc 1 2763 5 is_stmt 1 discriminator 2 view .LVU1914 +2763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6083 .loc 1 2763 23 is_stmt 0 discriminator 2 view .LVU1915 + 6084 0052 0023 movs r3, #0 + 6085 0054 6364 str r3, [r4, #68] +2766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6086 .loc 1 2766 5 is_stmt 1 discriminator 2 view .LVU1916 +2766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6087 .loc 1 2766 23 is_stmt 0 discriminator 2 view .LVU1917 + 6088 0056 6762 str r7, [r4, #36] +2767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6089 .loc 1 2767 5 is_stmt 1 discriminator 2 view .LVU1918 +2767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6090 .loc 1 2767 23 is_stmt 0 discriminator 2 view .LVU1919 + 6091 0058 6685 strh r6, [r4, #42] +2768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6092 .loc 1 2768 5 is_stmt 1 discriminator 2 view .LVU1920 +2768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6093 .loc 1 2768 23 is_stmt 0 discriminator 2 view .LVU1921 + 6094 005a 224B ldr r3, .L351 + 6095 005c E362 str r3, [r4, #44] +2769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6096 .loc 1 2769 5 is_stmt 1 discriminator 2 view .LVU1922 + ARM GAS /tmp/ccth6daj.s page 258 + + +2769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6097 .loc 1 2769 23 is_stmt 0 discriminator 2 view .LVU1923 + 6098 005e 224B ldr r3, .L351+4 + 6099 0060 6363 str r3, [r4, #52] +2771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6100 .loc 1 2771 5 is_stmt 1 discriminator 2 view .LVU1924 +2771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6101 .loc 1 2771 13 is_stmt 0 discriminator 2 view .LVU1925 + 6102 0062 638D ldrh r3, [r4, #42] + 6103 0064 9BB2 uxth r3, r3 +2771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6104 .loc 1 2771 8 discriminator 2 view .LVU1926 + 6105 0066 FF2B cmp r3, #255 + 6106 0068 19D9 bls .L345 +2773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6107 .loc 1 2773 7 is_stmt 1 view .LVU1927 +2773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6108 .loc 1 2773 22 is_stmt 0 view .LVU1928 + 6109 006a FF23 movs r3, #255 + 6110 006c 2385 strh r3, [r4, #40] +2774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6111 .loc 1 2774 7 is_stmt 1 view .LVU1929 + 6112 .LVL408: +2774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6113 .loc 1 2774 16 is_stmt 0 view .LVU1930 + 6114 006e 8023 movs r3, #128 + 6115 0070 5B04 lsls r3, r3, #17 + 6116 0072 9846 mov r8, r3 + 6117 .LVL409: + 6118 .L346: +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6119 .loc 1 2783 5 is_stmt 1 view .LVU1931 +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6120 .loc 1 2783 9 is_stmt 0 view .LVU1932 + 6121 0074 0190 str r0, [sp, #4] + 6122 0076 1923 movs r3, #25 + 6123 0078 0093 str r3, [sp] + 6124 007a 039B ldr r3, [sp, #12] + 6125 007c 029A ldr r2, [sp, #8] + 6126 007e 2900 movs r1, r5 + 6127 0080 2000 movs r0, r4 + 6128 .LVL410: +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6129 .loc 1 2783 9 view .LVU1933 + 6130 0082 FFF7FEFF bl I2C_RequestMemoryRead + 6131 .LVL411: +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6132 .loc 1 2783 9 view .LVU1934 + 6133 0086 061E subs r6, r0, #0 +2783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6134 .loc 1 2783 8 view .LVU1935 + 6135 0088 0FD0 beq .L347 +2786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6136 .loc 1 2786 7 is_stmt 1 view .LVU1936 +2786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6137 .loc 1 2786 7 view .LVU1937 + 6138 008a 4023 movs r3, #64 + ARM GAS /tmp/ccth6daj.s page 259 + + + 6139 008c 0022 movs r2, #0 + 6140 008e E254 strb r2, [r4, r3] +2786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6141 .loc 1 2786 7 view .LVU1938 +2787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6142 .loc 1 2787 7 view .LVU1939 +2787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6143 .loc 1 2787 14 is_stmt 0 view .LVU1940 + 6144 0090 0126 movs r6, #1 + 6145 0092 1CE0 b .L342 + 6146 .LVL412: + 6147 .L343: +2746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6148 .loc 1 2746 7 is_stmt 1 view .LVU1941 +2746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6149 .loc 1 2746 23 is_stmt 0 view .LVU1942 + 6150 0094 8023 movs r3, #128 + 6151 0096 9B00 lsls r3, r3, #2 + 6152 0098 6364 str r3, [r4, #68] +2747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6153 .loc 1 2747 7 is_stmt 1 view .LVU1943 +2747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6154 .loc 1 2747 15 is_stmt 0 view .LVU1944 + 6155 009a 0126 movs r6, #1 + 6156 009c 17E0 b .L342 + 6157 .LVL413: + 6158 .L345: +2778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6159 .loc 1 2778 7 is_stmt 1 view .LVU1945 +2778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6160 .loc 1 2778 28 is_stmt 0 view .LVU1946 + 6161 009e 638D ldrh r3, [r4, #42] +2778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6162 .loc 1 2778 22 view .LVU1947 + 6163 00a0 2385 strh r3, [r4, #40] +2779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6164 .loc 1 2779 7 is_stmt 1 view .LVU1948 + 6165 .LVL414: +2779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6166 .loc 1 2779 16 is_stmt 0 view .LVU1949 + 6167 00a2 8023 movs r3, #128 + 6168 00a4 9B04 lsls r3, r3, #18 + 6169 00a6 9846 mov r8, r3 + 6170 00a8 E4E7 b .L346 + 6171 .LVL415: + 6172 .L347: +2791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6173 .loc 1 2791 5 is_stmt 1 view .LVU1950 +2791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6174 .loc 1 2791 55 is_stmt 0 view .LVU1951 + 6175 00aa 228D ldrh r2, [r4, #40] +2791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6176 .loc 1 2791 5 view .LVU1952 + 6177 00ac D2B2 uxtb r2, r2 + 6178 00ae 0F4B ldr r3, .L351+8 + 6179 00b0 0093 str r3, [sp] + 6180 00b2 4346 mov r3, r8 + ARM GAS /tmp/ccth6daj.s page 260 + + + 6181 00b4 2900 movs r1, r5 + 6182 00b6 2000 movs r0, r4 + 6183 00b8 FFF7FEFF bl I2C_TransferConfig + 6184 .LVL416: +2794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6185 .loc 1 2794 5 is_stmt 1 view .LVU1953 +2794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6186 .loc 1 2794 5 view .LVU1954 + 6187 00bc 4023 movs r3, #64 + 6188 00be 0022 movs r2, #0 + 6189 00c0 E254 strb r2, [r4, r3] +2794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6190 .loc 1 2794 5 view .LVU1955 +2804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6191 .loc 1 2804 5 view .LVU1956 + 6192 00c2 0221 movs r1, #2 + 6193 00c4 2000 movs r0, r4 + 6194 00c6 FFF7FEFF bl I2C_Enable_IRQ + 6195 .LVL417: +2806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6196 .loc 1 2806 5 view .LVU1957 +2806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6197 .loc 1 2806 12 is_stmt 0 view .LVU1958 + 6198 00ca 00E0 b .L342 + 6199 .LVL418: + 6200 .L348: +2810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6201 .loc 1 2810 12 view .LVU1959 + 6202 00cc 0226 movs r6, #2 + 6203 .LVL419: + 6204 .L342: +2812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 6205 .loc 1 2812 1 view .LVU1960 + 6206 00ce 3000 movs r0, r6 + 6207 00d0 05B0 add sp, sp, #20 + 6208 @ sp needed + 6209 .LVL420: +2812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /** + 6210 .loc 1 2812 1 view .LVU1961 + 6211 00d2 C0BC pop {r6, r7} + 6212 00d4 BA46 mov r10, r7 + 6213 00d6 B046 mov r8, r6 + 6214 00d8 F0BD pop {r4, r5, r6, r7, pc} + 6215 .LVL421: + 6216 .L349: +2752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6217 .loc 1 2752 14 view .LVU1962 + 6218 00da 0226 movs r6, #2 + 6219 00dc F7E7 b .L342 + 6220 .L350: +2756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6221 .loc 1 2756 5 view .LVU1963 + 6222 00de 0226 movs r6, #2 + 6223 00e0 F5E7 b .L342 + 6224 .L352: + 6225 00e2 C046 .align 2 + 6226 .L351: + ARM GAS /tmp/ccth6daj.s page 261 + + + 6227 00e4 0000FFFF .word -65536 + 6228 00e8 00000000 .word I2C_Master_ISR_IT + 6229 00ec 00240080 .word -2147474432 + 6230 .cfi_endproc + 6231 .LFE316: + 6233 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 6234 .align 1 + 6235 .global HAL_I2C_Mem_Write_DMA + 6236 .syntax unified + 6237 .code 16 + 6238 .thumb_func + 6239 .fpu softvfp + 6241 HAL_I2C_Mem_Write_DMA: + 6242 .LVL422: + 6243 .LFB317: +2827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6244 .loc 1 2827 1 is_stmt 1 view -0 + 6245 .cfi_startproc + 6246 @ args = 8, pretend = 0, frame = 16 + 6247 @ frame_needed = 0, uses_anonymous_args = 0 +2827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6248 .loc 1 2827 1 is_stmt 0 view .LVU1965 + 6249 0000 F0B5 push {r4, r5, r6, r7, lr} + 6250 .LCFI46: + 6251 .cfi_def_cfa_offset 20 + 6252 .cfi_offset 4, -20 + 6253 .cfi_offset 5, -16 + 6254 .cfi_offset 6, -12 + 6255 .cfi_offset 7, -8 + 6256 .cfi_offset 14, -4 + 6257 0002 CE46 mov lr, r9 + 6258 0004 00B5 push {lr} + 6259 .LCFI47: + 6260 .cfi_def_cfa_offset 24 + 6261 .cfi_offset 9, -24 + 6262 0006 86B0 sub sp, sp, #24 + 6263 .LCFI48: + 6264 .cfi_def_cfa_offset 48 + 6265 0008 0400 movs r4, r0 + 6266 000a 0391 str r1, [sp, #12] + 6267 000c 0492 str r2, [sp, #16] + 6268 000e 0593 str r3, [sp, #20] + 6269 0010 0CAB add r3, sp, #48 + 6270 .LVL423: +2827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6271 .loc 1 2827 1 view .LVU1966 + 6272 0012 40CB ldmia r3!, {r6} + 6273 .LVL424: +2827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6274 .loc 1 2827 1 view .LVU1967 + 6275 0014 1F88 ldrh r7, [r3] +2828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 6276 .loc 1 2828 3 is_stmt 1 view .LVU1968 +2829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6277 .loc 1 2829 3 view .LVU1969 +2830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6278 .loc 1 2830 3 view .LVU1970 + ARM GAS /tmp/ccth6daj.s page 262 + + +2833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6279 .loc 1 2833 3 view .LVU1971 +2835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6280 .loc 1 2835 3 view .LVU1972 +2835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6281 .loc 1 2835 11 is_stmt 0 view .LVU1973 + 6282 0016 4123 movs r3, #65 + 6283 .LVL425: +2835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6284 .loc 1 2835 11 view .LVU1974 + 6285 0018 C35C ldrb r3, [r0, r3] +2835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6286 .loc 1 2835 6 view .LVU1975 + 6287 001a 202B cmp r3, #32 + 6288 001c 00D0 beq .LCB5997 + 6289 001e 90E0 b .L363 @long jump + 6290 .LCB5997: +2837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6291 .loc 1 2837 5 is_stmt 1 view .LVU1976 +2837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6292 .loc 1 2837 8 is_stmt 0 view .LVU1977 + 6293 0020 002E cmp r6, #0 + 6294 0022 55D0 beq .L355 +2837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6295 .loc 1 2837 25 discriminator 1 view .LVU1978 + 6296 0024 002F cmp r7, #0 + 6297 0026 53D0 beq .L355 +2843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6298 .loc 1 2843 5 is_stmt 1 view .LVU1979 +2843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6299 .loc 1 2843 9 is_stmt 0 view .LVU1980 + 6300 0028 0368 ldr r3, [r0] + 6301 002a 9B69 ldr r3, [r3, #24] +2843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6302 .loc 1 2843 8 view .LVU1981 + 6303 002c 1B04 lsls r3, r3, #16 + 6304 002e 00D5 bpl .LCB6009 + 6305 0030 8DE0 b .L364 @long jump + 6306 .LCB6009: +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6307 .loc 1 2849 5 is_stmt 1 view .LVU1982 +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6308 .loc 1 2849 5 view .LVU1983 + 6309 0032 4023 movs r3, #64 + 6310 0034 C35C ldrb r3, [r0, r3] + 6311 0036 012B cmp r3, #1 + 6312 0038 00D1 bne .LCB6015 + 6313 003a 8AE0 b .L365 @long jump + 6314 .LCB6015: +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6315 .loc 1 2849 5 discriminator 2 view .LVU1984 + 6316 003c 4025 movs r5, #64 + 6317 003e 0123 movs r3, #1 + 6318 0040 4355 strb r3, [r0, r5] +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6319 .loc 1 2849 5 discriminator 2 view .LVU1985 +2852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 263 + + + 6320 .loc 1 2852 5 discriminator 2 view .LVU1986 +2852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6321 .loc 1 2852 17 is_stmt 0 discriminator 2 view .LVU1987 + 6322 0042 FFF7FEFF bl HAL_GetTick + 6323 .LVL426: +2854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6324 .loc 1 2854 5 is_stmt 1 discriminator 2 view .LVU1988 +2854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6325 .loc 1 2854 23 is_stmt 0 discriminator 2 view .LVU1989 + 6326 0046 4123 movs r3, #65 + 6327 0048 2122 movs r2, #33 + 6328 004a E254 strb r2, [r4, r3] +2855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6329 .loc 1 2855 5 is_stmt 1 discriminator 2 view .LVU1990 +2855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6330 .loc 1 2855 23 is_stmt 0 discriminator 2 view .LVU1991 + 6331 004c 0133 adds r3, r3, #1 + 6332 004e E554 strb r5, [r4, r3] +2856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6333 .loc 1 2856 5 is_stmt 1 discriminator 2 view .LVU1992 +2856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6334 .loc 1 2856 23 is_stmt 0 discriminator 2 view .LVU1993 + 6335 0050 0023 movs r3, #0 + 6336 0052 6364 str r3, [r4, #68] +2859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6337 .loc 1 2859 5 is_stmt 1 discriminator 2 view .LVU1994 +2859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6338 .loc 1 2859 23 is_stmt 0 discriminator 2 view .LVU1995 + 6339 0054 6662 str r6, [r4, #36] +2860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6340 .loc 1 2860 5 is_stmt 1 discriminator 2 view .LVU1996 +2860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6341 .loc 1 2860 23 is_stmt 0 discriminator 2 view .LVU1997 + 6342 0056 6785 strh r7, [r4, #42] +2861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6343 .loc 1 2861 5 is_stmt 1 discriminator 2 view .LVU1998 +2861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6344 .loc 1 2861 23 is_stmt 0 discriminator 2 view .LVU1999 + 6345 0058 3F4B ldr r3, .L369 + 6346 005a E362 str r3, [r4, #44] +2862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6347 .loc 1 2862 5 is_stmt 1 discriminator 2 view .LVU2000 +2862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6348 .loc 1 2862 23 is_stmt 0 discriminator 2 view .LVU2001 + 6349 005c 3F4B ldr r3, .L369+4 + 6350 005e 6363 str r3, [r4, #52] +2864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6351 .loc 1 2864 5 is_stmt 1 discriminator 2 view .LVU2002 +2864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6352 .loc 1 2864 13 is_stmt 0 discriminator 2 view .LVU2003 + 6353 0060 638D ldrh r3, [r4, #42] + 6354 0062 9BB2 uxth r3, r3 +2864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6355 .loc 1 2864 8 discriminator 2 view .LVU2004 + 6356 0064 FF2B cmp r3, #255 + 6357 0066 38D9 bls .L357 +2866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + ARM GAS /tmp/ccth6daj.s page 264 + + + 6358 .loc 1 2866 7 is_stmt 1 view .LVU2005 +2866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6359 .loc 1 2866 22 is_stmt 0 view .LVU2006 + 6360 0068 FF23 movs r3, #255 + 6361 006a 2385 strh r3, [r4, #40] +2867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6362 .loc 1 2867 7 is_stmt 1 view .LVU2007 + 6363 .LVL427: +2867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6364 .loc 1 2867 16 is_stmt 0 view .LVU2008 + 6365 006c 8023 movs r3, #128 + 6366 006e 5B04 lsls r3, r3, #17 + 6367 0070 9946 mov r9, r3 + 6368 .LVL428: + 6369 .L358: +2876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 6370 .loc 1 2876 5 is_stmt 1 view .LVU2009 +2876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 6371 .loc 1 2876 9 is_stmt 0 view .LVU2010 + 6372 0072 0190 str r0, [sp, #4] + 6373 0074 1923 movs r3, #25 + 6374 0076 0093 str r3, [sp] + 6375 0078 059B ldr r3, [sp, #20] + 6376 007a 049A ldr r2, [sp, #16] + 6377 007c 0399 ldr r1, [sp, #12] + 6378 007e 2000 movs r0, r4 + 6379 .LVL429: +2876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 6380 .loc 1 2876 9 view .LVU2011 + 6381 0080 FFF7FEFF bl I2C_RequestMemoryWrite + 6382 .LVL430: +2876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** != HAL_OK) + 6383 .loc 1 2876 8 view .LVU2012 + 6384 0084 0028 cmp r0, #0 + 6385 0086 2ED1 bne .L367 +2885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6386 .loc 1 2885 5 is_stmt 1 view .LVU2013 +2885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6387 .loc 1 2885 13 is_stmt 0 view .LVU2014 + 6388 0088 A36B ldr r3, [r4, #56] +2885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6389 .loc 1 2885 8 view .LVU2015 + 6390 008a 002B cmp r3, #0 + 6391 008c 30D0 beq .L360 +2888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6392 .loc 1 2888 7 is_stmt 1 view .LVU2016 +2888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6393 .loc 1 2888 38 is_stmt 0 view .LVU2017 + 6394 008e 344A ldr r2, .L369+8 + 6395 0090 DA62 str r2, [r3, #44] +2891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6396 .loc 1 2891 7 is_stmt 1 view .LVU2018 +2891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6397 .loc 1 2891 11 is_stmt 0 view .LVU2019 + 6398 0092 A36B ldr r3, [r4, #56] +2891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6399 .loc 1 2891 39 view .LVU2020 + ARM GAS /tmp/ccth6daj.s page 265 + + + 6400 0094 334A ldr r2, .L369+12 + 6401 0096 5A63 str r2, [r3, #52] +2894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6402 .loc 1 2894 7 is_stmt 1 view .LVU2021 +2894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6403 .loc 1 2894 11 is_stmt 0 view .LVU2022 + 6404 0098 A26B ldr r2, [r4, #56] +2894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6405 .loc 1 2894 42 view .LVU2023 + 6406 009a 0023 movs r3, #0 + 6407 009c 1363 str r3, [r2, #48] +2895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6408 .loc 1 2895 7 is_stmt 1 view .LVU2024 +2895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6409 .loc 1 2895 11 is_stmt 0 view .LVU2025 + 6410 009e A26B ldr r2, [r4, #56] +2895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6411 .loc 1 2895 39 view .LVU2026 + 6412 00a0 9363 str r3, [r2, #56] +2898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6413 .loc 1 2898 7 is_stmt 1 view .LVU2027 +2898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6414 .loc 1 2898 81 is_stmt 0 view .LVU2028 + 6415 00a2 2268 ldr r2, [r4] + 6416 00a4 2832 adds r2, r2, #40 +2899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6417 .loc 1 2899 44 view .LVU2029 + 6418 00a6 238D ldrh r3, [r4, #40] +2898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6419 .loc 1 2898 23 view .LVU2030 + 6420 00a8 3100 movs r1, r6 + 6421 00aa A06B ldr r0, [r4, #56] + 6422 00ac FFF7FEFF bl HAL_DMA_Start_IT + 6423 .LVL431: + 6424 00b0 061E subs r6, r0, #0 + 6425 .LVL432: +2916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6426 .loc 1 2916 5 is_stmt 1 view .LVU2031 +2916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6427 .loc 1 2916 8 is_stmt 0 view .LVU2032 + 6428 00b2 2BD0 beq .L368 +2940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6429 .loc 1 2940 7 is_stmt 1 view .LVU2033 +2940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6430 .loc 1 2940 23 is_stmt 0 view .LVU2034 + 6431 00b4 4123 movs r3, #65 + 6432 00b6 2022 movs r2, #32 + 6433 00b8 E254 strb r2, [r4, r3] +2941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6434 .loc 1 2941 7 is_stmt 1 view .LVU2035 +2941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6435 .loc 1 2941 23 is_stmt 0 view .LVU2036 + 6436 00ba 0022 movs r2, #0 + 6437 00bc 0133 adds r3, r3, #1 + 6438 00be E254 strb r2, [r4, r3] +2944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6439 .loc 1 2944 7 is_stmt 1 view .LVU2037 + ARM GAS /tmp/ccth6daj.s page 266 + + +2944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6440 .loc 1 2944 23 is_stmt 0 view .LVU2038 + 6441 00c0 636C ldr r3, [r4, #68] + 6442 00c2 1021 movs r1, #16 + 6443 00c4 0B43 orrs r3, r1 + 6444 00c6 6364 str r3, [r4, #68] +2947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6445 .loc 1 2947 7 is_stmt 1 view .LVU2039 +2947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6446 .loc 1 2947 7 view .LVU2040 + 6447 00c8 4023 movs r3, #64 + 6448 00ca E254 strb r2, [r4, r3] +2947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6449 .loc 1 2947 7 view .LVU2041 +2949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6450 .loc 1 2949 7 view .LVU2042 +2949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6451 .loc 1 2949 14 is_stmt 0 view .LVU2043 + 6452 00cc 0126 movs r6, #1 + 6453 00ce 39E0 b .L354 + 6454 .LVL433: + 6455 .L355: +2839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6456 .loc 1 2839 7 is_stmt 1 view .LVU2044 +2839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6457 .loc 1 2839 23 is_stmt 0 view .LVU2045 + 6458 00d0 8023 movs r3, #128 + 6459 00d2 9B00 lsls r3, r3, #2 + 6460 00d4 6364 str r3, [r4, #68] +2840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6461 .loc 1 2840 7 is_stmt 1 view .LVU2046 +2840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6462 .loc 1 2840 15 is_stmt 0 view .LVU2047 + 6463 00d6 0126 movs r6, #1 + 6464 00d8 34E0 b .L354 + 6465 .LVL434: + 6466 .L357: +2871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6467 .loc 1 2871 7 is_stmt 1 view .LVU2048 +2871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6468 .loc 1 2871 28 is_stmt 0 view .LVU2049 + 6469 00da 638D ldrh r3, [r4, #42] +2871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6470 .loc 1 2871 22 view .LVU2050 + 6471 00dc 2385 strh r3, [r4, #40] +2872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6472 .loc 1 2872 7 is_stmt 1 view .LVU2051 + 6473 .LVL435: +2872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6474 .loc 1 2872 16 is_stmt 0 view .LVU2052 + 6475 00de 8023 movs r3, #128 + 6476 00e0 9B04 lsls r3, r3, #18 + 6477 00e2 9946 mov r9, r3 + 6478 00e4 C5E7 b .L358 + 6479 .LVL436: + 6480 .L367: +2880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccth6daj.s page 267 + + + 6481 .loc 1 2880 7 is_stmt 1 view .LVU2053 +2880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6482 .loc 1 2880 7 view .LVU2054 + 6483 00e6 4023 movs r3, #64 + 6484 00e8 0022 movs r2, #0 + 6485 00ea E254 strb r2, [r4, r3] +2880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6486 .loc 1 2880 7 view .LVU2055 +2881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6487 .loc 1 2881 7 view .LVU2056 +2881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6488 .loc 1 2881 14 is_stmt 0 view .LVU2057 + 6489 00ec 0126 movs r6, #1 + 6490 00ee 29E0 b .L354 + 6491 .L360: +2904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6492 .loc 1 2904 7 is_stmt 1 view .LVU2058 +2904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6493 .loc 1 2904 23 is_stmt 0 view .LVU2059 + 6494 00f0 4123 movs r3, #65 + 6495 00f2 2022 movs r2, #32 + 6496 00f4 E254 strb r2, [r4, r3] +2905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6497 .loc 1 2905 7 is_stmt 1 view .LVU2060 +2905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6498 .loc 1 2905 23 is_stmt 0 view .LVU2061 + 6499 00f6 0022 movs r2, #0 + 6500 00f8 0133 adds r3, r3, #1 + 6501 00fa E254 strb r2, [r4, r3] +2908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6502 .loc 1 2908 7 is_stmt 1 view .LVU2062 +2908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6503 .loc 1 2908 23 is_stmt 0 view .LVU2063 + 6504 00fc 636C ldr r3, [r4, #68] + 6505 00fe 8021 movs r1, #128 + 6506 0100 0B43 orrs r3, r1 + 6507 0102 6364 str r3, [r4, #68] +2911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6508 .loc 1 2911 7 is_stmt 1 view .LVU2064 +2911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6509 .loc 1 2911 7 view .LVU2065 + 6510 0104 4023 movs r3, #64 + 6511 0106 E254 strb r2, [r4, r3] +2911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6512 .loc 1 2911 7 view .LVU2066 +2913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6513 .loc 1 2913 7 view .LVU2067 +2913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6514 .loc 1 2913 14 is_stmt 0 view .LVU2068 + 6515 0108 0126 movs r6, #1 + 6516 010a 1BE0 b .L354 + 6517 .LVL437: + 6518 .L368: +2920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6519 .loc 1 2920 7 is_stmt 1 view .LVU2069 +2920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6520 .loc 1 2920 57 is_stmt 0 view .LVU2070 + ARM GAS /tmp/ccth6daj.s page 268 + + + 6521 010c 228D ldrh r2, [r4, #40] +2920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6522 .loc 1 2920 7 view .LVU2071 + 6523 010e D2B2 uxtb r2, r2 + 6524 0110 0027 movs r7, #0 + 6525 0112 0097 str r7, [sp] + 6526 0114 4B46 mov r3, r9 + 6527 0116 0399 ldr r1, [sp, #12] + 6528 0118 2000 movs r0, r4 + 6529 .LVL438: +2920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6530 .loc 1 2920 7 view .LVU2072 + 6531 011a FFF7FEFF bl I2C_TransferConfig + 6532 .LVL439: +2923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6533 .loc 1 2923 7 is_stmt 1 view .LVU2073 +2923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6534 .loc 1 2923 23 is_stmt 0 view .LVU2074 + 6535 011e 638D ldrh r3, [r4, #42] +2923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6536 .loc 1 2923 30 view .LVU2075 + 6537 0120 228D ldrh r2, [r4, #40] +2923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6538 .loc 1 2923 23 view .LVU2076 + 6539 0122 9B1A subs r3, r3, r2 + 6540 0124 9BB2 uxth r3, r3 + 6541 0126 6385 strh r3, [r4, #42] +2926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6542 .loc 1 2926 7 is_stmt 1 view .LVU2077 +2926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6543 .loc 1 2926 7 view .LVU2078 + 6544 0128 4023 movs r3, #64 + 6545 012a E754 strb r7, [r4, r3] +2926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6546 .loc 1 2926 7 view .LVU2079 +2932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6547 .loc 1 2932 7 view .LVU2080 + 6548 012c 1021 movs r1, #16 + 6549 012e 2000 movs r0, r4 + 6550 0130 FFF7FEFF bl I2C_Enable_IRQ + 6551 .LVL440: +2935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6552 .loc 1 2935 7 view .LVU2081 +2935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6553 .loc 1 2935 11 is_stmt 0 view .LVU2082 + 6554 0134 2268 ldr r2, [r4] +2935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6555 .loc 1 2935 27 view .LVU2083 + 6556 0136 1168 ldr r1, [r2] + 6557 0138 8023 movs r3, #128 + 6558 013a DB01 lsls r3, r3, #7 + 6559 013c 0B43 orrs r3, r1 + 6560 013e 1360 str r3, [r2] +2952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6561 .loc 1 2952 5 is_stmt 1 view .LVU2084 +2952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6562 .loc 1 2952 12 is_stmt 0 view .LVU2085 + ARM GAS /tmp/ccth6daj.s page 269 + + + 6563 0140 00E0 b .L354 + 6564 .LVL441: + 6565 .L363: +2956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6566 .loc 1 2956 12 view .LVU2086 + 6567 0142 0226 movs r6, #2 + 6568 .LVL442: + 6569 .L354: +2958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6570 .loc 1 2958 1 view .LVU2087 + 6571 0144 3000 movs r0, r6 + 6572 0146 06B0 add sp, sp, #24 + 6573 @ sp needed + 6574 .LVL443: +2958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6575 .loc 1 2958 1 view .LVU2088 + 6576 0148 80BC pop {r7} + 6577 014a B946 mov r9, r7 + 6578 014c F0BD pop {r4, r5, r6, r7, pc} + 6579 .LVL444: + 6580 .L364: +2845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6581 .loc 1 2845 14 view .LVU2089 + 6582 014e 0226 movs r6, #2 + 6583 0150 F8E7 b .L354 + 6584 .L365: +2849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6585 .loc 1 2849 5 view .LVU2090 + 6586 0152 0226 movs r6, #2 + 6587 0154 F6E7 b .L354 + 6588 .L370: + 6589 0156 C046 .align 2 + 6590 .L369: + 6591 0158 0000FFFF .word -65536 + 6592 015c 00000000 .word I2C_Master_ISR_DMA + 6593 0160 00000000 .word I2C_DMAMasterTransmitCplt + 6594 0164 00000000 .word I2C_DMAError + 6595 .cfi_endproc + 6596 .LFE317: + 6598 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 6599 .align 1 + 6600 .global HAL_I2C_Mem_Read_DMA + 6601 .syntax unified + 6602 .code 16 + 6603 .thumb_func + 6604 .fpu softvfp + 6606 HAL_I2C_Mem_Read_DMA: + 6607 .LVL445: + 6608 .LFB318: +2974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6609 .loc 1 2974 1 is_stmt 1 view -0 + 6610 .cfi_startproc + 6611 @ args = 8, pretend = 0, frame = 16 + 6612 @ frame_needed = 0, uses_anonymous_args = 0 +2974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6613 .loc 1 2974 1 is_stmt 0 view .LVU2092 + 6614 0000 F0B5 push {r4, r5, r6, r7, lr} + ARM GAS /tmp/ccth6daj.s page 270 + + + 6615 .LCFI49: + 6616 .cfi_def_cfa_offset 20 + 6617 .cfi_offset 4, -20 + 6618 .cfi_offset 5, -16 + 6619 .cfi_offset 6, -12 + 6620 .cfi_offset 7, -8 + 6621 .cfi_offset 14, -4 + 6622 0002 CE46 mov lr, r9 + 6623 0004 00B5 push {lr} + 6624 .LCFI50: + 6625 .cfi_def_cfa_offset 24 + 6626 .cfi_offset 9, -24 + 6627 0006 86B0 sub sp, sp, #24 + 6628 .LCFI51: + 6629 .cfi_def_cfa_offset 48 + 6630 0008 0400 movs r4, r0 + 6631 000a 0391 str r1, [sp, #12] + 6632 000c 0492 str r2, [sp, #16] + 6633 000e 0593 str r3, [sp, #20] + 6634 0010 0CAB add r3, sp, #48 + 6635 .LVL446: +2974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6636 .loc 1 2974 1 view .LVU2093 + 6637 0012 40CB ldmia r3!, {r6} + 6638 .LVL447: +2974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6639 .loc 1 2974 1 view .LVU2094 + 6640 0014 1F88 ldrh r7, [r3] +2975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 6641 .loc 1 2975 3 is_stmt 1 view .LVU2095 +2976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 6642 .loc 1 2976 3 view .LVU2096 +2977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6643 .loc 1 2977 3 view .LVU2097 +2980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6644 .loc 1 2980 3 view .LVU2098 +2982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6645 .loc 1 2982 3 view .LVU2099 +2982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6646 .loc 1 2982 11 is_stmt 0 view .LVU2100 + 6647 0016 4123 movs r3, #65 + 6648 .LVL448: +2982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6649 .loc 1 2982 11 view .LVU2101 + 6650 0018 C35C ldrb r3, [r0, r3] +2982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6651 .loc 1 2982 6 view .LVU2102 + 6652 001a 202B cmp r3, #32 + 6653 001c 00D0 beq .LCB6356 + 6654 001e 91E0 b .L381 @long jump + 6655 .LCB6356: +2984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6656 .loc 1 2984 5 is_stmt 1 view .LVU2103 +2984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6657 .loc 1 2984 8 is_stmt 0 view .LVU2104 + 6658 0020 002E cmp r6, #0 + 6659 0022 55D0 beq .L373 + ARM GAS /tmp/ccth6daj.s page 271 + + +2984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6660 .loc 1 2984 25 discriminator 1 view .LVU2105 + 6661 0024 002F cmp r7, #0 + 6662 0026 53D0 beq .L373 +2990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6663 .loc 1 2990 5 is_stmt 1 view .LVU2106 +2990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6664 .loc 1 2990 9 is_stmt 0 view .LVU2107 + 6665 0028 0368 ldr r3, [r0] + 6666 002a 9B69 ldr r3, [r3, #24] +2990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6667 .loc 1 2990 8 view .LVU2108 + 6668 002c 1B04 lsls r3, r3, #16 + 6669 002e 00D5 bpl .LCB6368 + 6670 0030 8EE0 b .L382 @long jump + 6671 .LCB6368: +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6672 .loc 1 2996 5 is_stmt 1 view .LVU2109 +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6673 .loc 1 2996 5 view .LVU2110 + 6674 0032 4023 movs r3, #64 + 6675 0034 C35C ldrb r3, [r0, r3] + 6676 0036 012B cmp r3, #1 + 6677 0038 00D1 bne .LCB6374 + 6678 003a 8BE0 b .L383 @long jump + 6679 .LCB6374: +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6680 .loc 1 2996 5 discriminator 2 view .LVU2111 + 6681 003c 4025 movs r5, #64 + 6682 003e 0123 movs r3, #1 + 6683 0040 4355 strb r3, [r0, r5] +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6684 .loc 1 2996 5 discriminator 2 view .LVU2112 +2999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6685 .loc 1 2999 5 discriminator 2 view .LVU2113 +2999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6686 .loc 1 2999 17 is_stmt 0 discriminator 2 view .LVU2114 + 6687 0042 FFF7FEFF bl HAL_GetTick + 6688 .LVL449: +3001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6689 .loc 1 3001 5 is_stmt 1 discriminator 2 view .LVU2115 +3001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 6690 .loc 1 3001 23 is_stmt 0 discriminator 2 view .LVU2116 + 6691 0046 4123 movs r3, #65 + 6692 0048 2222 movs r2, #34 + 6693 004a E254 strb r2, [r4, r3] +3002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6694 .loc 1 3002 5 is_stmt 1 discriminator 2 view .LVU2117 +3002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6695 .loc 1 3002 23 is_stmt 0 discriminator 2 view .LVU2118 + 6696 004c 0133 adds r3, r3, #1 + 6697 004e E554 strb r5, [r4, r3] +3003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6698 .loc 1 3003 5 is_stmt 1 discriminator 2 view .LVU2119 +3003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6699 .loc 1 3003 23 is_stmt 0 discriminator 2 view .LVU2120 + 6700 0050 0023 movs r3, #0 + ARM GAS /tmp/ccth6daj.s page 272 + + + 6701 0052 6364 str r3, [r4, #68] +3006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6702 .loc 1 3006 5 is_stmt 1 discriminator 2 view .LVU2121 +3006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 6703 .loc 1 3006 23 is_stmt 0 discriminator 2 view .LVU2122 + 6704 0054 6662 str r6, [r4, #36] +3007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6705 .loc 1 3007 5 is_stmt 1 discriminator 2 view .LVU2123 +3007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 6706 .loc 1 3007 23 is_stmt 0 discriminator 2 view .LVU2124 + 6707 0056 6785 strh r7, [r4, #42] +3008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6708 .loc 1 3008 5 is_stmt 1 discriminator 2 view .LVU2125 +3008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6709 .loc 1 3008 23 is_stmt 0 discriminator 2 view .LVU2126 + 6710 0058 3F4B ldr r3, .L387 + 6711 005a E362 str r3, [r4, #44] +3009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6712 .loc 1 3009 5 is_stmt 1 discriminator 2 view .LVU2127 +3009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6713 .loc 1 3009 23 is_stmt 0 discriminator 2 view .LVU2128 + 6714 005c 3F4B ldr r3, .L387+4 + 6715 005e 6363 str r3, [r4, #52] +3011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6716 .loc 1 3011 5 is_stmt 1 discriminator 2 view .LVU2129 +3011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6717 .loc 1 3011 13 is_stmt 0 discriminator 2 view .LVU2130 + 6718 0060 638D ldrh r3, [r4, #42] + 6719 0062 9BB2 uxth r3, r3 +3011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6720 .loc 1 3011 8 discriminator 2 view .LVU2131 + 6721 0064 FF2B cmp r3, #255 + 6722 0066 38D9 bls .L375 +3013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6723 .loc 1 3013 7 is_stmt 1 view .LVU2132 +3013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6724 .loc 1 3013 22 is_stmt 0 view .LVU2133 + 6725 0068 FF23 movs r3, #255 + 6726 006a 2385 strh r3, [r4, #40] +3014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6727 .loc 1 3014 7 is_stmt 1 view .LVU2134 + 6728 .LVL450: +3014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6729 .loc 1 3014 16 is_stmt 0 view .LVU2135 + 6730 006c 8023 movs r3, #128 + 6731 006e 5B04 lsls r3, r3, #17 + 6732 0070 9946 mov r9, r3 + 6733 .LVL451: + 6734 .L376: +3023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6735 .loc 1 3023 5 is_stmt 1 view .LVU2136 +3023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6736 .loc 1 3023 9 is_stmt 0 view .LVU2137 + 6737 0072 0190 str r0, [sp, #4] + 6738 0074 1923 movs r3, #25 + 6739 0076 0093 str r3, [sp] + 6740 0078 059B ldr r3, [sp, #20] + ARM GAS /tmp/ccth6daj.s page 273 + + + 6741 007a 049A ldr r2, [sp, #16] + 6742 007c 0399 ldr r1, [sp, #12] + 6743 007e 2000 movs r0, r4 + 6744 .LVL452: +3023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6745 .loc 1 3023 9 view .LVU2138 + 6746 0080 FFF7FEFF bl I2C_RequestMemoryRead + 6747 .LVL453: +3023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6748 .loc 1 3023 8 view .LVU2139 + 6749 0084 0028 cmp r0, #0 + 6750 0086 2ED1 bne .L385 +3030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6751 .loc 1 3030 5 is_stmt 1 view .LVU2140 +3030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6752 .loc 1 3030 13 is_stmt 0 view .LVU2141 + 6753 0088 E36B ldr r3, [r4, #60] +3030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6754 .loc 1 3030 8 view .LVU2142 + 6755 008a 002B cmp r3, #0 + 6756 008c 30D0 beq .L378 +3033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6757 .loc 1 3033 7 is_stmt 1 view .LVU2143 +3033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6758 .loc 1 3033 38 is_stmt 0 view .LVU2144 + 6759 008e 344A ldr r2, .L387+8 + 6760 0090 DA62 str r2, [r3, #44] +3036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6761 .loc 1 3036 7 is_stmt 1 view .LVU2145 +3036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6762 .loc 1 3036 11 is_stmt 0 view .LVU2146 + 6763 0092 E36B ldr r3, [r4, #60] +3036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6764 .loc 1 3036 39 view .LVU2147 + 6765 0094 334A ldr r2, .L387+12 + 6766 0096 5A63 str r2, [r3, #52] +3039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6767 .loc 1 3039 7 is_stmt 1 view .LVU2148 +3039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6768 .loc 1 3039 11 is_stmt 0 view .LVU2149 + 6769 0098 E26B ldr r2, [r4, #60] +3039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 6770 .loc 1 3039 42 view .LVU2150 + 6771 009a 0023 movs r3, #0 + 6772 009c 1363 str r3, [r2, #48] +3040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6773 .loc 1 3040 7 is_stmt 1 view .LVU2151 +3040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6774 .loc 1 3040 11 is_stmt 0 view .LVU2152 + 6775 009e E26B ldr r2, [r4, #60] +3040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6776 .loc 1 3040 39 view .LVU2153 + 6777 00a0 9363 str r3, [r2, #56] +3043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6778 .loc 1 3043 7 is_stmt 1 view .LVU2154 +3043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6779 .loc 1 3043 64 is_stmt 0 view .LVU2155 + ARM GAS /tmp/ccth6daj.s page 274 + + + 6780 00a2 2168 ldr r1, [r4] + 6781 00a4 2431 adds r1, r1, #36 +3044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6782 .loc 1 3044 44 view .LVU2156 + 6783 00a6 238D ldrh r3, [r4, #40] +3043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 6784 .loc 1 3043 23 view .LVU2157 + 6785 00a8 3200 movs r2, r6 + 6786 00aa E06B ldr r0, [r4, #60] + 6787 00ac FFF7FEFF bl HAL_DMA_Start_IT + 6788 .LVL454: + 6789 00b0 061E subs r6, r0, #0 + 6790 .LVL455: +3061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6791 .loc 1 3061 5 is_stmt 1 view .LVU2158 +3061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 6792 .loc 1 3061 8 is_stmt 0 view .LVU2159 + 6793 00b2 2BD0 beq .L386 +3084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6794 .loc 1 3084 7 is_stmt 1 view .LVU2160 +3084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6795 .loc 1 3084 23 is_stmt 0 view .LVU2161 + 6796 00b4 4123 movs r3, #65 + 6797 00b6 2022 movs r2, #32 + 6798 00b8 E254 strb r2, [r4, r3] +3085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6799 .loc 1 3085 7 is_stmt 1 view .LVU2162 +3085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6800 .loc 1 3085 23 is_stmt 0 view .LVU2163 + 6801 00ba 0022 movs r2, #0 + 6802 00bc 0133 adds r3, r3, #1 + 6803 00be E254 strb r2, [r4, r3] +3088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6804 .loc 1 3088 7 is_stmt 1 view .LVU2164 +3088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6805 .loc 1 3088 23 is_stmt 0 view .LVU2165 + 6806 00c0 636C ldr r3, [r4, #68] + 6807 00c2 1021 movs r1, #16 + 6808 00c4 0B43 orrs r3, r1 + 6809 00c6 6364 str r3, [r4, #68] +3091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6810 .loc 1 3091 7 is_stmt 1 view .LVU2166 +3091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6811 .loc 1 3091 7 view .LVU2167 + 6812 00c8 4023 movs r3, #64 + 6813 00ca E254 strb r2, [r4, r3] +3091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6814 .loc 1 3091 7 view .LVU2168 +3093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6815 .loc 1 3093 7 view .LVU2169 +3093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6816 .loc 1 3093 14 is_stmt 0 view .LVU2170 + 6817 00cc 0126 movs r6, #1 + 6818 00ce 3AE0 b .L372 + 6819 .LVL456: + 6820 .L373: +2986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/ccth6daj.s page 275 + + + 6821 .loc 1 2986 7 is_stmt 1 view .LVU2171 +2986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6822 .loc 1 2986 23 is_stmt 0 view .LVU2172 + 6823 00d0 8023 movs r3, #128 + 6824 00d2 9B00 lsls r3, r3, #2 + 6825 00d4 6364 str r3, [r4, #68] +2987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6826 .loc 1 2987 7 is_stmt 1 view .LVU2173 +2987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6827 .loc 1 2987 15 is_stmt 0 view .LVU2174 + 6828 00d6 0126 movs r6, #1 + 6829 00d8 35E0 b .L372 + 6830 .LVL457: + 6831 .L375: +3018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6832 .loc 1 3018 7 is_stmt 1 view .LVU2175 +3018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6833 .loc 1 3018 28 is_stmt 0 view .LVU2176 + 6834 00da 638D ldrh r3, [r4, #42] +3018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 6835 .loc 1 3018 22 view .LVU2177 + 6836 00dc 2385 strh r3, [r4, #40] +3019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6837 .loc 1 3019 7 is_stmt 1 view .LVU2178 + 6838 .LVL458: +3019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6839 .loc 1 3019 16 is_stmt 0 view .LVU2179 + 6840 00de 8023 movs r3, #128 + 6841 00e0 9B04 lsls r3, r3, #18 + 6842 00e2 9946 mov r9, r3 + 6843 00e4 C5E7 b .L376 + 6844 .LVL459: + 6845 .L385: +3026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6846 .loc 1 3026 7 is_stmt 1 view .LVU2180 +3026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6847 .loc 1 3026 7 view .LVU2181 + 6848 00e6 4023 movs r3, #64 + 6849 00e8 0022 movs r2, #0 + 6850 00ea E254 strb r2, [r4, r3] +3026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 6851 .loc 1 3026 7 view .LVU2182 +3027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6852 .loc 1 3027 7 view .LVU2183 +3027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6853 .loc 1 3027 14 is_stmt 0 view .LVU2184 + 6854 00ec 0126 movs r6, #1 + 6855 00ee 2AE0 b .L372 + 6856 .L378: +3049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6857 .loc 1 3049 7 is_stmt 1 view .LVU2185 +3049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6858 .loc 1 3049 23 is_stmt 0 view .LVU2186 + 6859 00f0 4123 movs r3, #65 + 6860 00f2 2022 movs r2, #32 + 6861 00f4 E254 strb r2, [r4, r3] +3050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 276 + + + 6862 .loc 1 3050 7 is_stmt 1 view .LVU2187 +3050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6863 .loc 1 3050 23 is_stmt 0 view .LVU2188 + 6864 00f6 0022 movs r2, #0 + 6865 00f8 0133 adds r3, r3, #1 + 6866 00fa E254 strb r2, [r4, r3] +3053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6867 .loc 1 3053 7 is_stmt 1 view .LVU2189 +3053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6868 .loc 1 3053 23 is_stmt 0 view .LVU2190 + 6869 00fc 636C ldr r3, [r4, #68] + 6870 00fe 8021 movs r1, #128 + 6871 0100 0B43 orrs r3, r1 + 6872 0102 6364 str r3, [r4, #68] +3056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6873 .loc 1 3056 7 is_stmt 1 view .LVU2191 +3056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6874 .loc 1 3056 7 view .LVU2192 + 6875 0104 4023 movs r3, #64 + 6876 0106 E254 strb r2, [r4, r3] +3056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6877 .loc 1 3056 7 view .LVU2193 +3058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6878 .loc 1 3058 7 view .LVU2194 +3058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6879 .loc 1 3058 14 is_stmt 0 view .LVU2195 + 6880 0108 0126 movs r6, #1 + 6881 010a 1CE0 b .L372 + 6882 .LVL460: + 6883 .L386: +3064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6884 .loc 1 3064 7 is_stmt 1 view .LVU2196 +3064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6885 .loc 1 3064 57 is_stmt 0 view .LVU2197 + 6886 010c 228D ldrh r2, [r4, #40] +3064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6887 .loc 1 3064 7 view .LVU2198 + 6888 010e D2B2 uxtb r2, r2 + 6889 0110 154B ldr r3, .L387+16 + 6890 0112 0093 str r3, [sp] + 6891 0114 4B46 mov r3, r9 + 6892 0116 0399 ldr r1, [sp, #12] + 6893 0118 2000 movs r0, r4 + 6894 .LVL461: +3064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6895 .loc 1 3064 7 view .LVU2199 + 6896 011a FFF7FEFF bl I2C_TransferConfig + 6897 .LVL462: +3067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6898 .loc 1 3067 7 is_stmt 1 view .LVU2200 +3067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6899 .loc 1 3067 23 is_stmt 0 view .LVU2201 + 6900 011e 638D ldrh r3, [r4, #42] +3067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6901 .loc 1 3067 30 view .LVU2202 + 6902 0120 228D ldrh r2, [r4, #40] +3067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 277 + + + 6903 .loc 1 3067 23 view .LVU2203 + 6904 0122 9B1A subs r3, r3, r2 + 6905 0124 9BB2 uxth r3, r3 + 6906 0126 6385 strh r3, [r4, #42] +3070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6907 .loc 1 3070 7 is_stmt 1 view .LVU2204 +3070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6908 .loc 1 3070 7 view .LVU2205 + 6909 0128 4023 movs r3, #64 + 6910 012a 0022 movs r2, #0 + 6911 012c E254 strb r2, [r4, r3] +3070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6912 .loc 1 3070 7 view .LVU2206 +3076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6913 .loc 1 3076 7 view .LVU2207 + 6914 012e 1021 movs r1, #16 + 6915 0130 2000 movs r0, r4 + 6916 0132 FFF7FEFF bl I2C_Enable_IRQ + 6917 .LVL463: +3079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6918 .loc 1 3079 7 view .LVU2208 +3079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6919 .loc 1 3079 11 is_stmt 0 view .LVU2209 + 6920 0136 2268 ldr r2, [r4] +3079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6921 .loc 1 3079 27 view .LVU2210 + 6922 0138 1168 ldr r1, [r2] + 6923 013a 8023 movs r3, #128 + 6924 013c 1B02 lsls r3, r3, #8 + 6925 013e 0B43 orrs r3, r1 + 6926 0140 1360 str r3, [r2] +3096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6927 .loc 1 3096 5 is_stmt 1 view .LVU2211 +3096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6928 .loc 1 3096 12 is_stmt 0 view .LVU2212 + 6929 0142 00E0 b .L372 + 6930 .LVL464: + 6931 .L381: +3100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 6932 .loc 1 3100 12 view .LVU2213 + 6933 0144 0226 movs r6, #2 + 6934 .LVL465: + 6935 .L372: +3102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6936 .loc 1 3102 1 view .LVU2214 + 6937 0146 3000 movs r0, r6 + 6938 0148 06B0 add sp, sp, #24 + 6939 @ sp needed + 6940 .LVL466: +3102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6941 .loc 1 3102 1 view .LVU2215 + 6942 014a 80BC pop {r7} + 6943 014c B946 mov r9, r7 + 6944 014e F0BD pop {r4, r5, r6, r7, pc} + 6945 .LVL467: + 6946 .L382: +2992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 278 + + + 6947 .loc 1 2992 14 view .LVU2216 + 6948 0150 0226 movs r6, #2 + 6949 0152 F8E7 b .L372 + 6950 .L383: +2996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 6951 .loc 1 2996 5 view .LVU2217 + 6952 0154 0226 movs r6, #2 + 6953 0156 F6E7 b .L372 + 6954 .L388: + 6955 .align 2 + 6956 .L387: + 6957 0158 0000FFFF .word -65536 + 6958 015c 00000000 .word I2C_Master_ISR_DMA + 6959 0160 00000000 .word I2C_DMAMasterReceiveCplt + 6960 0164 00000000 .word I2C_DMAError + 6961 0168 00240080 .word -2147474432 + 6962 .cfi_endproc + 6963 .LFE318: + 6965 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 6966 .align 1 + 6967 .global HAL_I2C_IsDeviceReady + 6968 .syntax unified + 6969 .code 16 + 6970 .thumb_func + 6971 .fpu softvfp + 6973 HAL_I2C_IsDeviceReady: + 6974 .LVL468: + 6975 .LFB319: +3117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6976 .loc 1 3117 1 is_stmt 1 view -0 + 6977 .cfi_startproc + 6978 @ args = 0, pretend = 0, frame = 8 + 6979 @ frame_needed = 0, uses_anonymous_args = 0 +3117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tickstart; + 6980 .loc 1 3117 1 is_stmt 0 view .LVU2219 + 6981 0000 F0B5 push {r4, r5, r6, r7, lr} + 6982 .LCFI52: + 6983 .cfi_def_cfa_offset 20 + 6984 .cfi_offset 4, -20 + 6985 .cfi_offset 5, -16 + 6986 .cfi_offset 6, -12 + 6987 .cfi_offset 7, -8 + 6988 .cfi_offset 14, -4 + 6989 0002 CE46 mov lr, r9 + 6990 0004 4746 mov r7, r8 + 6991 0006 80B5 push {r7, lr} + 6992 .LCFI53: + 6993 .cfi_def_cfa_offset 28 + 6994 .cfi_offset 8, -28 + 6995 .cfi_offset 9, -24 + 6996 0008 85B0 sub sp, sp, #20 + 6997 .LCFI54: + 6998 .cfi_def_cfa_offset 48 + 6999 000a 0600 movs r6, r0 + 7000 000c 8946 mov r9, r1 + 7001 000e 9046 mov r8, r2 + 7002 0010 1D00 movs r5, r3 + ARM GAS /tmp/ccth6daj.s page 279 + + +3118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7003 .loc 1 3118 3 is_stmt 1 view .LVU2220 +3120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7004 .loc 1 3120 3 view .LVU2221 +3120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7005 .loc 1 3120 17 is_stmt 0 view .LVU2222 + 7006 0012 0023 movs r3, #0 + 7007 .LVL469: +3120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7008 .loc 1 3120 17 view .LVU2223 + 7009 0014 0393 str r3, [sp, #12] +3122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** FlagStatus tmp2; + 7010 .loc 1 3122 3 is_stmt 1 view .LVU2224 +3123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7011 .loc 1 3123 3 view .LVU2225 +3125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7012 .loc 1 3125 3 view .LVU2226 +3125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7013 .loc 1 3125 11 is_stmt 0 view .LVU2227 + 7014 0016 4133 adds r3, r3, #65 + 7015 0018 C35C ldrb r3, [r0, r3] +3125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7016 .loc 1 3125 6 view .LVU2228 + 7017 001a 202B cmp r3, #32 + 7018 001c 00D0 beq .LCB6710 + 7019 001e A6E0 b .L400 @long jump + 7020 .LCB6710: +3127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7021 .loc 1 3127 5 is_stmt 1 view .LVU2229 +3127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7022 .loc 1 3127 9 is_stmt 0 view .LVU2230 + 7023 0020 0368 ldr r3, [r0] + 7024 0022 9B69 ldr r3, [r3, #24] +3127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7025 .loc 1 3127 8 view .LVU2231 + 7026 0024 1B04 lsls r3, r3, #16 + 7027 0026 00D5 bpl .LCB6717 + 7028 0028 A3E0 b .L401 @long jump + 7029 .LCB6717: +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7030 .loc 1 3133 5 is_stmt 1 view .LVU2232 +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7031 .loc 1 3133 5 view .LVU2233 + 7032 002a 4023 movs r3, #64 + 7033 002c C35C ldrb r3, [r0, r3] + 7034 002e 012B cmp r3, #1 + 7035 0030 00D1 bne .LCB6723 + 7036 0032 A0E0 b .L402 @long jump + 7037 .LCB6723: +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7038 .loc 1 3133 5 discriminator 2 view .LVU2234 + 7039 0034 4023 movs r3, #64 + 7040 0036 0122 movs r2, #1 + 7041 .LVL470: +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7042 .loc 1 3133 5 is_stmt 0 discriminator 2 view .LVU2235 + 7043 0038 C254 strb r2, [r0, r3] + ARM GAS /tmp/ccth6daj.s page 280 + + +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7044 .loc 1 3133 5 is_stmt 1 discriminator 2 view .LVU2236 +3135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7045 .loc 1 3135 5 discriminator 2 view .LVU2237 +3135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7046 .loc 1 3135 17 is_stmt 0 discriminator 2 view .LVU2238 + 7047 003a 0133 adds r3, r3, #1 + 7048 003c 2332 adds r2, r2, #35 + 7049 003e C254 strb r2, [r0, r3] +3136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7050 .loc 1 3136 5 is_stmt 1 discriminator 2 view .LVU2239 +3136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7051 .loc 1 3136 21 is_stmt 0 discriminator 2 view .LVU2240 + 7052 0040 0023 movs r3, #0 + 7053 0042 4364 str r3, [r0, #68] + 7054 .LVL471: + 7055 .L399: +3138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7056 .loc 1 3138 5 is_stmt 1 view .LVU2241 +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7057 .loc 1 3141 7 view .LVU2242 +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7058 .loc 1 3141 29 is_stmt 0 view .LVU2243 + 7059 0044 F368 ldr r3, [r6, #12] + 7060 0046 012B cmp r3, #1 + 7061 0048 18D0 beq .L406 +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7062 .loc 1 3141 29 discriminator 2 view .LVU2244 + 7063 004a 4B46 mov r3, r9 + 7064 004c 9A05 lsls r2, r3, #22 + 7065 004e 920D lsrs r2, r2, #22 + 7066 0050 A023 movs r3, #160 + 7067 0052 9B01 lsls r3, r3, #6 + 7068 0054 1343 orrs r3, r2 + 7069 .L392: +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7070 .loc 1 3141 11 discriminator 4 view .LVU2245 + 7071 0056 3268 ldr r2, [r6] +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7072 .loc 1 3141 27 discriminator 4 view .LVU2246 + 7073 0058 5360 str r3, [r2, #4] +3145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7074 .loc 1 3145 7 is_stmt 1 discriminator 4 view .LVU2247 +3145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7075 .loc 1 3145 19 is_stmt 0 discriminator 4 view .LVU2248 + 7076 005a FFF7FEFF bl HAL_GetTick + 7077 .LVL472: + 7078 005e 0700 movs r7, r0 + 7079 .LVL473: +3147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7080 .loc 1 3147 7 is_stmt 1 discriminator 4 view .LVU2249 +3147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7081 .loc 1 3147 14 is_stmt 0 discriminator 4 view .LVU2250 + 7082 0060 3368 ldr r3, [r6] + 7083 0062 9A69 ldr r2, [r3, #24] + 7084 0064 2024 movs r4, #32 + 7085 0066 1440 ands r4, r2 + ARM GAS /tmp/ccth6daj.s page 281 + + + 7086 0068 621E subs r2, r4, #1 + 7087 006a 9441 sbcs r4, r4, r2 + 7088 006c E2B2 uxtb r2, r4 + 7089 .LVL474: +3148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7090 .loc 1 3148 7 is_stmt 1 discriminator 4 view .LVU2251 +3148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7091 .loc 1 3148 14 is_stmt 0 discriminator 4 view .LVU2252 + 7092 006e 9C69 ldr r4, [r3, #24] + 7093 0070 1023 movs r3, #16 + 7094 0072 2340 ands r3, r4 + 7095 0074 591E subs r1, r3, #1 + 7096 0076 8B41 sbcs r3, r3, r1 + 7097 0078 DCB2 uxtb r4, r3 + 7098 .LVL475: +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7099 .loc 1 3150 7 is_stmt 1 discriminator 4 view .LVU2253 +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7100 .loc 1 3150 13 is_stmt 0 discriminator 4 view .LVU2254 + 7101 007a 12E0 b .L393 + 7102 .LVL476: + 7103 .L406: +3141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7104 .loc 1 3141 29 discriminator 1 view .LVU2255 + 7105 007c 4B46 mov r3, r9 + 7106 007e 9A05 lsls r2, r3, #22 + 7107 0080 920D lsrs r2, r2, #22 + 7108 0082 414B ldr r3, .L410 + 7109 0084 1343 orrs r3, r2 + 7110 0086 E6E7 b .L392 + 7111 .LVL477: + 7112 .L394: +3169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7113 .loc 1 3169 9 is_stmt 1 view .LVU2256 +3169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 7114 .loc 1 3169 16 is_stmt 0 view .LVU2257 + 7115 0088 3368 ldr r3, [r6] + 7116 008a 9A69 ldr r2, [r3, #24] + 7117 008c 2024 movs r4, #32 + 7118 008e 1440 ands r4, r2 + 7119 0090 621E subs r2, r4, #1 + 7120 0092 9441 sbcs r4, r4, r2 + 7121 0094 E2B2 uxtb r2, r4 + 7122 .LVL478: +3170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7123 .loc 1 3170 9 is_stmt 1 view .LVU2258 +3170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7124 .loc 1 3170 16 is_stmt 0 view .LVU2259 + 7125 0096 9B69 ldr r3, [r3, #24] + 7126 0098 1024 movs r4, #16 + 7127 009a 1C40 ands r4, r3 + 7128 009c 631E subs r3, r4, #1 + 7129 009e 9C41 sbcs r4, r4, r3 + 7130 00a0 E4B2 uxtb r4, r4 + 7131 .LVL479: + 7132 .L393: +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 282 + + + 7133 .loc 1 3150 13 is_stmt 1 view .LVU2260 +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7134 .loc 1 3150 30 is_stmt 0 view .LVU2261 + 7135 00a2 1443 orrs r4, r2 + 7136 .LVL480: +3150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7137 .loc 1 3150 13 view .LVU2262 + 7138 00a4 17D1 bne .L407 +3152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7139 .loc 1 3152 9 is_stmt 1 view .LVU2263 +3152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7140 .loc 1 3152 12 is_stmt 0 view .LVU2264 + 7141 00a6 6B1C adds r3, r5, #1 + 7142 00a8 EED0 beq .L394 +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7143 .loc 1 3154 11 is_stmt 1 view .LVU2265 +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7144 .loc 1 3154 17 is_stmt 0 view .LVU2266 + 7145 00aa FFF7FEFF bl HAL_GetTick + 7146 .LVL481: +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7147 .loc 1 3154 31 view .LVU2267 + 7148 00ae C01B subs r0, r0, r7 +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7149 .loc 1 3154 14 view .LVU2268 + 7150 00b0 A842 cmp r0, r5 + 7151 00b2 01D8 bhi .L395 +3154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7152 .loc 1 3154 55 discriminator 1 view .LVU2269 + 7153 00b4 002D cmp r5, #0 + 7154 00b6 E7D1 bne .L394 + 7155 .L395: +3157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7156 .loc 1 3157 13 is_stmt 1 view .LVU2270 +3157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7157 .loc 1 3157 25 is_stmt 0 view .LVU2271 + 7158 00b8 2022 movs r2, #32 + 7159 00ba 4123 movs r3, #65 + 7160 00bc F254 strb r2, [r6, r3] +3160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7161 .loc 1 3160 13 is_stmt 1 view .LVU2272 +3160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7162 .loc 1 3160 29 is_stmt 0 view .LVU2273 + 7163 00be 736C ldr r3, [r6, #68] + 7164 00c0 1343 orrs r3, r2 + 7165 00c2 7364 str r3, [r6, #68] +3163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7166 .loc 1 3163 13 is_stmt 1 view .LVU2274 +3163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7167 .loc 1 3163 13 view .LVU2275 + 7168 00c4 4023 movs r3, #64 + 7169 00c6 0022 movs r2, #0 + 7170 00c8 F254 strb r2, [r6, r3] +3163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7171 .loc 1 3163 13 view .LVU2276 +3165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7172 .loc 1 3165 13 view .LVU2277 + ARM GAS /tmp/ccth6daj.s page 283 + + +3165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7173 .loc 1 3165 20 is_stmt 0 view .LVU2278 + 7174 00ca 0120 movs r0, #1 + 7175 .LVL482: + 7176 .L390: +3243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7177 .loc 1 3243 1 view .LVU2279 + 7178 00cc 05B0 add sp, sp, #20 + 7179 @ sp needed + 7180 .LVL483: + 7181 .LVL484: + 7182 .LVL485: +3243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7183 .loc 1 3243 1 view .LVU2280 + 7184 00ce C0BC pop {r6, r7} + 7185 00d0 B946 mov r9, r7 + 7186 00d2 B046 mov r8, r6 + 7187 00d4 F0BD pop {r4, r5, r6, r7, pc} + 7188 .LVL486: + 7189 .L407: +3174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7190 .loc 1 3174 7 is_stmt 1 view .LVU2281 +3174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7191 .loc 1 3174 11 is_stmt 0 view .LVU2282 + 7192 00d6 3368 ldr r3, [r6] + 7193 00d8 9B69 ldr r3, [r3, #24] +3174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7194 .loc 1 3174 10 view .LVU2283 + 7195 00da DB06 lsls r3, r3, #27 + 7196 00dc 22D5 bpl .L408 +3196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7197 .loc 1 3196 9 is_stmt 1 view .LVU2284 +3196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7198 .loc 1 3196 13 is_stmt 0 view .LVU2285 + 7199 00de 0097 str r7, [sp] + 7200 00e0 2B00 movs r3, r5 + 7201 00e2 0022 movs r2, #0 + 7202 .LVL487: +3196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7203 .loc 1 3196 13 view .LVU2286 + 7204 00e4 2021 movs r1, #32 + 7205 00e6 3000 movs r0, r6 + 7206 00e8 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 7207 .LVL488: +3196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7208 .loc 1 3196 12 view .LVU2287 + 7209 00ec 0028 cmp r0, #0 + 7210 00ee 46D1 bne .L404 +3202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7211 .loc 1 3202 9 is_stmt 1 view .LVU2288 + 7212 00f0 3368 ldr r3, [r6] + 7213 00f2 1022 movs r2, #16 + 7214 00f4 DA61 str r2, [r3, #28] +3205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7215 .loc 1 3205 9 view .LVU2289 + 7216 00f6 3368 ldr r3, [r6] + 7217 00f8 1032 adds r2, r2, #16 + ARM GAS /tmp/ccth6daj.s page 284 + + + 7218 00fa DA61 str r2, [r3, #28] +3209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7219 .loc 1 3209 7 view .LVU2290 +3209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7220 .loc 1 3209 22 is_stmt 0 view .LVU2291 + 7221 00fc 039B ldr r3, [sp, #12] +3209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7222 .loc 1 3209 10 view .LVU2292 + 7223 00fe 4345 cmp r3, r8 + 7224 0100 22D0 beq .L409 + 7225 .L398: +3225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 7226 .loc 1 3225 7 is_stmt 1 view .LVU2293 +3225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 7227 .loc 1 3225 17 is_stmt 0 view .LVU2294 + 7228 0102 039B ldr r3, [sp, #12] + 7229 0104 0133 adds r3, r3, #1 + 7230 0106 0393 str r3, [sp, #12] +3226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7231 .loc 1 3226 13 is_stmt 1 view .LVU2295 +3226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7232 .loc 1 3226 25 is_stmt 0 view .LVU2296 + 7233 0108 039B ldr r3, [sp, #12] +3226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7234 .loc 1 3226 5 view .LVU2297 + 7235 010a 4345 cmp r3, r8 + 7236 010c 9AD3 bcc .L399 +3229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7237 .loc 1 3229 5 is_stmt 1 view .LVU2298 +3229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7238 .loc 1 3229 17 is_stmt 0 view .LVU2299 + 7239 010e 2022 movs r2, #32 + 7240 0110 4123 movs r3, #65 + 7241 0112 F254 strb r2, [r6, r3] +3232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7242 .loc 1 3232 5 is_stmt 1 view .LVU2300 +3232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7243 .loc 1 3232 21 is_stmt 0 view .LVU2301 + 7244 0114 736C ldr r3, [r6, #68] + 7245 0116 1343 orrs r3, r2 + 7246 0118 7364 str r3, [r6, #68] +3235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7247 .loc 1 3235 5 is_stmt 1 view .LVU2302 +3235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7248 .loc 1 3235 5 view .LVU2303 + 7249 011a 4023 movs r3, #64 + 7250 011c 0022 movs r2, #0 + 7251 011e F254 strb r2, [r6, r3] +3235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7252 .loc 1 3235 5 view .LVU2304 +3237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7253 .loc 1 3237 5 view .LVU2305 +3237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7254 .loc 1 3237 12 is_stmt 0 view .LVU2306 + 7255 0120 0120 movs r0, #1 + 7256 0122 D3E7 b .L390 + 7257 .LVL489: + ARM GAS /tmp/ccth6daj.s page 285 + + + 7258 .L408: +3177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7259 .loc 1 3177 9 is_stmt 1 view .LVU2307 +3177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7260 .loc 1 3177 13 is_stmt 0 view .LVU2308 + 7261 0124 0097 str r7, [sp] + 7262 0126 2B00 movs r3, r5 + 7263 0128 0022 movs r2, #0 + 7264 .LVL490: +3177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7265 .loc 1 3177 13 view .LVU2309 + 7266 012a 2021 movs r1, #32 + 7267 012c 3000 movs r0, r6 + 7268 012e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 7269 .LVL491: +3177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7270 .loc 1 3177 12 view .LVU2310 + 7271 0132 0028 cmp r0, #0 + 7272 0134 21D1 bne .L403 +3183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7273 .loc 1 3183 9 is_stmt 1 view .LVU2311 + 7274 0136 3268 ldr r2, [r6] + 7275 0138 2023 movs r3, #32 + 7276 013a D361 str r3, [r2, #28] +3186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7277 .loc 1 3186 9 view .LVU2312 +3186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7278 .loc 1 3186 21 is_stmt 0 view .LVU2313 + 7279 013c 4122 movs r2, #65 + 7280 013e B354 strb r3, [r6, r2] +3189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7281 .loc 1 3189 9 is_stmt 1 view .LVU2314 +3189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7282 .loc 1 3189 9 view .LVU2315 + 7283 0140 2033 adds r3, r3, #32 + 7284 0142 0022 movs r2, #0 + 7285 0144 F254 strb r2, [r6, r3] +3189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7286 .loc 1 3189 9 view .LVU2316 +3191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7287 .loc 1 3191 9 view .LVU2317 +3191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7288 .loc 1 3191 16 is_stmt 0 view .LVU2318 + 7289 0146 C1E7 b .L390 + 7290 .L409: +3212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7291 .loc 1 3212 9 is_stmt 1 view .LVU2319 +3212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7292 .loc 1 3212 13 is_stmt 0 view .LVU2320 + 7293 0148 3268 ldr r2, [r6] +3212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7294 .loc 1 3212 29 view .LVU2321 + 7295 014a 5168 ldr r1, [r2, #4] + 7296 014c 8023 movs r3, #128 + 7297 014e DB01 lsls r3, r3, #7 + 7298 0150 0B43 orrs r3, r1 + 7299 0152 5360 str r3, [r2, #4] + ARM GAS /tmp/ccth6daj.s page 286 + + +3215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7300 .loc 1 3215 9 is_stmt 1 view .LVU2322 +3215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7301 .loc 1 3215 13 is_stmt 0 view .LVU2323 + 7302 0154 0097 str r7, [sp] + 7303 0156 2B00 movs r3, r5 + 7304 0158 0022 movs r2, #0 + 7305 015a 2021 movs r1, #32 + 7306 015c 3000 movs r0, r6 + 7307 015e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 7308 .LVL492: +3215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7309 .loc 1 3215 12 view .LVU2324 + 7310 0162 0028 cmp r0, #0 + 7311 0164 0DD1 bne .L405 +3221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7312 .loc 1 3221 9 is_stmt 1 view .LVU2325 + 7313 0166 3368 ldr r3, [r6] + 7314 0168 2022 movs r2, #32 + 7315 016a DA61 str r2, [r3, #28] + 7316 016c C9E7 b .L398 + 7317 .LVL493: + 7318 .L400: +3241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7319 .loc 1 3241 12 is_stmt 0 view .LVU2326 + 7320 016e 0220 movs r0, #2 + 7321 .LVL494: +3241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7322 .loc 1 3241 12 view .LVU2327 + 7323 0170 ACE7 b .L390 + 7324 .LVL495: + 7325 .L401: +3129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7326 .loc 1 3129 14 view .LVU2328 + 7327 0172 0220 movs r0, #2 + 7328 .LVL496: +3129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7329 .loc 1 3129 14 view .LVU2329 + 7330 0174 AAE7 b .L390 + 7331 .LVL497: + 7332 .L402: +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7333 .loc 1 3133 5 view .LVU2330 + 7334 0176 0220 movs r0, #2 + 7335 .LVL498: +3133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7336 .loc 1 3133 5 view .LVU2331 + 7337 0178 A8E7 b .L390 + 7338 .LVL499: + 7339 .L403: +3179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7340 .loc 1 3179 18 view .LVU2332 + 7341 017a 0120 movs r0, #1 + 7342 017c A6E7 b .L390 + 7343 .L404: +3198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7344 .loc 1 3198 18 view .LVU2333 + ARM GAS /tmp/ccth6daj.s page 287 + + + 7345 017e 0120 movs r0, #1 + 7346 0180 A4E7 b .L390 + 7347 .L405: +3217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7348 .loc 1 3217 18 view .LVU2334 + 7349 0182 0120 movs r0, #1 + 7350 0184 A2E7 b .L390 + 7351 .L411: + 7352 0186 C046 .align 2 + 7353 .L410: + 7354 0188 00200002 .word 33562624 + 7355 .cfi_endproc + 7356 .LFE319: + 7358 .section .text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits + 7359 .align 1 + 7360 .global HAL_I2C_Master_Seq_Transmit_IT + 7361 .syntax unified + 7362 .code 16 + 7363 .thumb_func + 7364 .fpu softvfp + 7366 HAL_I2C_Master_Seq_Transmit_IT: + 7367 .LVL500: + 7368 .LFB320: +3259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7369 .loc 1 3259 1 is_stmt 1 view -0 + 7370 .cfi_startproc + 7371 @ args = 4, pretend = 0, frame = 0 + 7372 @ frame_needed = 0, uses_anonymous_args = 0 +3259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7373 .loc 1 3259 1 is_stmt 0 view .LVU2336 + 7374 0000 70B5 push {r4, r5, r6, lr} + 7375 .LCFI55: + 7376 .cfi_def_cfa_offset 16 + 7377 .cfi_offset 4, -16 + 7378 .cfi_offset 5, -12 + 7379 .cfi_offset 6, -8 + 7380 .cfi_offset 14, -4 + 7381 0002 82B0 sub sp, sp, #8 + 7382 .LCFI56: + 7383 .cfi_def_cfa_offset 24 + 7384 0004 0400 movs r4, r0 + 7385 0006 0D00 movs r5, r1 +3260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 7386 .loc 1 3260 3 is_stmt 1 view .LVU2337 +3261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7387 .loc 1 3261 3 view .LVU2338 + 7388 .LVL501: +3264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7389 .loc 1 3264 3 view .LVU2339 +3266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7390 .loc 1 3266 3 view .LVU2340 +3266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7391 .loc 1 3266 11 is_stmt 0 view .LVU2341 + 7392 0008 4121 movs r1, #65 + 7393 .LVL502: +3266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7394 .loc 1 3266 11 view .LVU2342 + ARM GAS /tmp/ccth6daj.s page 288 + + + 7395 000a 415C ldrb r1, [r0, r1] +3266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7396 .loc 1 3266 6 view .LVU2343 + 7397 000c 2029 cmp r1, #32 + 7398 000e 4AD1 bne .L418 +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7399 .loc 1 3269 5 is_stmt 1 view .LVU2344 +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7400 .loc 1 3269 5 view .LVU2345 + 7401 0010 2031 adds r1, r1, #32 + 7402 0012 415C ldrb r1, [r0, r1] + 7403 0014 0129 cmp r1, #1 + 7404 0016 48D0 beq .L419 +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7405 .loc 1 3269 5 discriminator 2 view .LVU2346 + 7406 0018 4021 movs r1, #64 + 7407 001a 0120 movs r0, #1 + 7408 .LVL503: +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7409 .loc 1 3269 5 is_stmt 0 discriminator 2 view .LVU2347 + 7410 001c 6054 strb r0, [r4, r1] +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7411 .loc 1 3269 5 is_stmt 1 discriminator 2 view .LVU2348 +3271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7412 .loc 1 3271 5 discriminator 2 view .LVU2349 +3271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7413 .loc 1 3271 21 is_stmt 0 discriminator 2 view .LVU2350 + 7414 001e 0131 adds r1, r1, #1 + 7415 0020 2030 adds r0, r0, #32 + 7416 0022 6054 strb r0, [r4, r1] +3272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7417 .loc 1 3272 5 is_stmt 1 discriminator 2 view .LVU2351 +3272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7418 .loc 1 3272 21 is_stmt 0 discriminator 2 view .LVU2352 + 7419 0024 0131 adds r1, r1, #1 + 7420 0026 1138 subs r0, r0, #17 + 7421 0028 6054 strb r0, [r4, r1] +3273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7422 .loc 1 3273 5 is_stmt 1 discriminator 2 view .LVU2353 +3273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7423 .loc 1 3273 21 is_stmt 0 discriminator 2 view .LVU2354 + 7424 002a 0021 movs r1, #0 + 7425 002c 6164 str r1, [r4, #68] +3276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7426 .loc 1 3276 5 is_stmt 1 discriminator 2 view .LVU2355 +3276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7427 .loc 1 3276 23 is_stmt 0 discriminator 2 view .LVU2356 + 7428 002e 6262 str r2, [r4, #36] +3277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7429 .loc 1 3277 5 is_stmt 1 discriminator 2 view .LVU2357 +3277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7430 .loc 1 3277 23 is_stmt 0 discriminator 2 view .LVU2358 + 7431 0030 6385 strh r3, [r4, #42] +3278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7432 .loc 1 3278 5 is_stmt 1 discriminator 2 view .LVU2359 +3278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7433 .loc 1 3278 23 is_stmt 0 discriminator 2 view .LVU2360 + ARM GAS /tmp/ccth6daj.s page 289 + + + 7434 0032 069B ldr r3, [sp, #24] + 7435 .LVL504: +3278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 7436 .loc 1 3278 23 discriminator 2 view .LVU2361 + 7437 0034 E362 str r3, [r4, #44] + 7438 .LVL505: +3279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7439 .loc 1 3279 5 is_stmt 1 discriminator 2 view .LVU2362 +3279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7440 .loc 1 3279 23 is_stmt 0 discriminator 2 view .LVU2363 + 7441 0036 1E4B ldr r3, .L422 + 7442 0038 6363 str r3, [r4, #52] +3282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7443 .loc 1 3282 5 is_stmt 1 discriminator 2 view .LVU2364 +3282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7444 .loc 1 3282 13 is_stmt 0 discriminator 2 view .LVU2365 + 7445 003a 638D ldrh r3, [r4, #42] + 7446 003c 9BB2 uxth r3, r3 +3282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7447 .loc 1 3282 8 discriminator 2 view .LVU2366 + 7448 003e FF2B cmp r3, #255 + 7449 0040 10D9 bls .L414 +3284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7450 .loc 1 3284 7 is_stmt 1 view .LVU2367 +3284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7451 .loc 1 3284 22 is_stmt 0 view .LVU2368 + 7452 0042 FF23 movs r3, #255 + 7453 0044 2385 strh r3, [r4, #40] +3285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7454 .loc 1 3285 7 is_stmt 1 view .LVU2369 + 7455 .LVL506: +3285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7456 .loc 1 3285 16 is_stmt 0 view .LVU2370 + 7457 0046 8026 movs r6, #128 + 7458 0048 7604 lsls r6, r6, #17 + 7459 .LVL507: + 7460 .L415: +3296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7461 .loc 1 3296 5 is_stmt 1 view .LVU2371 +3296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7462 .loc 1 3296 14 is_stmt 0 view .LVU2372 + 7463 004a 236B ldr r3, [r4, #48] +3296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7464 .loc 1 3296 8 view .LVU2373 + 7465 004c 112B cmp r3, #17 + 7466 004e 0DD1 bne .L416 +3297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7467 .loc 1 3297 8 view .LVU2374 + 7468 0050 069B ldr r3, [sp, #24] + 7469 0052 AA2B cmp r3, #170 + 7470 0054 0AD0 beq .L416 +3297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7471 .loc 1 3297 8 discriminator 2 view .LVU2375 + 7472 0056 AA23 movs r3, #170 + 7473 0058 1B02 lsls r3, r3, #8 + 7474 005a 069A ldr r2, [sp, #24] + 7475 .LVL508: + ARM GAS /tmp/ccth6daj.s page 290 + + +3297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7476 .loc 1 3297 8 discriminator 2 view .LVU2376 + 7477 005c 9A42 cmp r2, r3 + 7478 005e 05D0 beq .L416 +3299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7479 .loc 1 3299 19 view .LVU2377 + 7480 0060 0023 movs r3, #0 + 7481 0062 0CE0 b .L417 + 7482 .LVL509: + 7483 .L414: +3289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7484 .loc 1 3289 7 is_stmt 1 view .LVU2378 +3289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7485 .loc 1 3289 28 is_stmt 0 view .LVU2379 + 7486 0064 638D ldrh r3, [r4, #42] +3289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7487 .loc 1 3289 22 view .LVU2380 + 7488 0066 2385 strh r3, [r4, #40] +3290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7489 .loc 1 3290 7 is_stmt 1 view .LVU2381 +3290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7490 .loc 1 3290 16 is_stmt 0 view .LVU2382 + 7491 0068 E66A ldr r6, [r4, #44] + 7492 .LVL510: +3290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7493 .loc 1 3290 16 view .LVU2383 + 7494 006a EEE7 b .L415 + 7495 .LVL511: + 7496 .L416: +3304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7497 .loc 1 3304 7 is_stmt 1 view .LVU2384 + 7498 006c 2000 movs r0, r4 + 7499 006e FFF7FEFF bl I2C_ConvertOtherXferOptions + 7500 .LVL512: +3307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7501 .loc 1 3307 7 view .LVU2385 +3307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7502 .loc 1 3307 15 is_stmt 0 view .LVU2386 + 7503 0072 638D ldrh r3, [r4, #42] + 7504 0074 9BB2 uxth r3, r3 +3307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7505 .loc 1 3307 10 view .LVU2387 + 7506 0076 FF2B cmp r3, #255 + 7507 0078 13D8 bhi .L421 +3309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7508 .loc 1 3309 9 is_stmt 1 view .LVU2388 +3309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7509 .loc 1 3309 18 is_stmt 0 view .LVU2389 + 7510 007a E66A ldr r6, [r4, #44] + 7511 .LVL513: +3261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7512 .loc 1 3261 12 view .LVU2390 + 7513 007c 0D4B ldr r3, .L422+4 + 7514 .L417: + 7515 .LVL514: +3314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7516 .loc 1 3314 5 is_stmt 1 view .LVU2391 + ARM GAS /tmp/ccth6daj.s page 291 + + +3314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7517 .loc 1 3314 55 is_stmt 0 view .LVU2392 + 7518 007e 228D ldrh r2, [r4, #40] +3314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7519 .loc 1 3314 5 view .LVU2393 + 7520 0080 D2B2 uxtb r2, r2 + 7521 0082 0093 str r3, [sp] + 7522 0084 3300 movs r3, r6 + 7523 .LVL515: +3314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7524 .loc 1 3314 5 view .LVU2394 + 7525 0086 2900 movs r1, r5 + 7526 0088 2000 movs r0, r4 + 7527 008a FFF7FEFF bl I2C_TransferConfig + 7528 .LVL516: +3317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7529 .loc 1 3317 5 is_stmt 1 view .LVU2395 +3317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7530 .loc 1 3317 5 view .LVU2396 + 7531 008e 4023 movs r3, #64 + 7532 0090 0022 movs r2, #0 + 7533 0092 E254 strb r2, [r4, r3] +3317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7534 .loc 1 3317 5 view .LVU2397 +3322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7535 .loc 1 3322 5 view .LVU2398 + 7536 0094 0121 movs r1, #1 + 7537 0096 2000 movs r0, r4 + 7538 0098 FFF7FEFF bl I2C_Enable_IRQ + 7539 .LVL517: +3324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7540 .loc 1 3324 5 view .LVU2399 +3324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7541 .loc 1 3324 12 is_stmt 0 view .LVU2400 + 7542 009c 0020 movs r0, #0 + 7543 .LVL518: + 7544 .L413: +3330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7545 .loc 1 3330 1 view .LVU2401 + 7546 009e 02B0 add sp, sp, #8 + 7547 @ sp needed + 7548 .LVL519: +3330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7549 .loc 1 3330 1 view .LVU2402 + 7550 00a0 70BD pop {r4, r5, r6, pc} + 7551 .LVL520: + 7552 .L421: +3261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7553 .loc 1 3261 12 view .LVU2403 + 7554 00a2 044B ldr r3, .L422+4 + 7555 00a4 EBE7 b .L417 + 7556 .LVL521: + 7557 .L418: +3328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7558 .loc 1 3328 12 view .LVU2404 + 7559 00a6 0220 movs r0, #2 + 7560 .LVL522: + ARM GAS /tmp/ccth6daj.s page 292 + + +3328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7561 .loc 1 3328 12 view .LVU2405 + 7562 00a8 F9E7 b .L413 + 7563 .LVL523: + 7564 .L419: +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7565 .loc 1 3269 5 view .LVU2406 + 7566 00aa 0220 movs r0, #2 + 7567 .LVL524: +3269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7568 .loc 1 3269 5 view .LVU2407 + 7569 00ac F7E7 b .L413 + 7570 .L423: + 7571 00ae C046 .align 2 + 7572 .L422: + 7573 00b0 00000000 .word I2C_Master_ISR_IT + 7574 00b4 00200080 .word -2147475456 + 7575 .cfi_endproc + 7576 .LFE320: + 7578 .section .text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits + 7579 .align 1 + 7580 .global HAL_I2C_Master_Seq_Transmit_DMA + 7581 .syntax unified + 7582 .code 16 + 7583 .thumb_func + 7584 .fpu softvfp + 7586 HAL_I2C_Master_Seq_Transmit_DMA: + 7587 .LVL525: + 7588 .LFB321: +3346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7589 .loc 1 3346 1 is_stmt 1 view -0 + 7590 .cfi_startproc + 7591 @ args = 4, pretend = 0, frame = 8 + 7592 @ frame_needed = 0, uses_anonymous_args = 0 +3346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7593 .loc 1 3346 1 is_stmt 0 view .LVU2409 + 7594 0000 F0B5 push {r4, r5, r6, r7, lr} + 7595 .LCFI57: + 7596 .cfi_def_cfa_offset 20 + 7597 .cfi_offset 4, -20 + 7598 .cfi_offset 5, -16 + 7599 .cfi_offset 6, -12 + 7600 .cfi_offset 7, -8 + 7601 .cfi_offset 14, -4 + 7602 0002 85B0 sub sp, sp, #20 + 7603 .LCFI58: + 7604 .cfi_def_cfa_offset 40 + 7605 0004 0400 movs r4, r0 + 7606 0006 0391 str r1, [sp, #12] + 7607 0008 1500 movs r5, r2 +3347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 7608 .loc 1 3347 3 is_stmt 1 view .LVU2410 +3348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7609 .loc 1 3348 3 view .LVU2411 + 7610 .LVL526: +3349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7611 .loc 1 3349 3 view .LVU2412 + ARM GAS /tmp/ccth6daj.s page 293 + + +3352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7612 .loc 1 3352 3 view .LVU2413 +3354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7613 .loc 1 3354 3 view .LVU2414 +3354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7614 .loc 1 3354 11 is_stmt 0 view .LVU2415 + 7615 000a 4122 movs r2, #65 + 7616 .LVL527: +3354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7617 .loc 1 3354 11 view .LVU2416 + 7618 000c 825C ldrb r2, [r0, r2] +3354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7619 .loc 1 3354 6 view .LVU2417 + 7620 000e 202A cmp r2, #32 + 7621 0010 00D0 beq .LCB7313 + 7622 0012 9DE0 b .L435 @long jump + 7623 .LCB7313: +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7624 .loc 1 3357 5 is_stmt 1 view .LVU2418 +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7625 .loc 1 3357 5 view .LVU2419 + 7626 0014 2032 adds r2, r2, #32 + 7627 0016 825C ldrb r2, [r0, r2] + 7628 0018 012A cmp r2, #1 + 7629 001a 00D1 bne .LCB7319 + 7630 001c 9BE0 b .L436 @long jump + 7631 .LCB7319: +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7632 .loc 1 3357 5 discriminator 2 view .LVU2420 + 7633 001e 4022 movs r2, #64 + 7634 0020 0121 movs r1, #1 + 7635 .LVL528: +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7636 .loc 1 3357 5 is_stmt 0 discriminator 2 view .LVU2421 + 7637 0022 8154 strb r1, [r0, r2] +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7638 .loc 1 3357 5 is_stmt 1 discriminator 2 view .LVU2422 +3359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7639 .loc 1 3359 5 discriminator 2 view .LVU2423 +3359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 7640 .loc 1 3359 21 is_stmt 0 discriminator 2 view .LVU2424 + 7641 0024 0132 adds r2, r2, #1 + 7642 0026 2031 adds r1, r1, #32 + 7643 0028 8154 strb r1, [r0, r2] +3360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7644 .loc 1 3360 5 is_stmt 1 discriminator 2 view .LVU2425 +3360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7645 .loc 1 3360 21 is_stmt 0 discriminator 2 view .LVU2426 + 7646 002a 0132 adds r2, r2, #1 + 7647 002c 1139 subs r1, r1, #17 + 7648 002e 8154 strb r1, [r0, r2] +3361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7649 .loc 1 3361 5 is_stmt 1 discriminator 2 view .LVU2427 +3361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7650 .loc 1 3361 21 is_stmt 0 discriminator 2 view .LVU2428 + 7651 0030 0022 movs r2, #0 + 7652 0032 4264 str r2, [r0, #68] + ARM GAS /tmp/ccth6daj.s page 294 + + +3364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7653 .loc 1 3364 5 is_stmt 1 discriminator 2 view .LVU2429 +3364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 7654 .loc 1 3364 23 is_stmt 0 discriminator 2 view .LVU2430 + 7655 0034 4562 str r5, [r0, #36] +3365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7656 .loc 1 3365 5 is_stmt 1 discriminator 2 view .LVU2431 +3365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7657 .loc 1 3365 23 is_stmt 0 discriminator 2 view .LVU2432 + 7658 0036 4385 strh r3, [r0, #42] +3366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7659 .loc 1 3366 5 is_stmt 1 discriminator 2 view .LVU2433 +3366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7660 .loc 1 3366 23 is_stmt 0 discriminator 2 view .LVU2434 + 7661 0038 0A9B ldr r3, [sp, #40] + 7662 .LVL529: +3366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 7663 .loc 1 3366 23 discriminator 2 view .LVU2435 + 7664 003a C362 str r3, [r0, #44] + 7665 .LVL530: +3367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7666 .loc 1 3367 5 is_stmt 1 discriminator 2 view .LVU2436 +3367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7667 .loc 1 3367 23 is_stmt 0 discriminator 2 view .LVU2437 + 7668 003c 474B ldr r3, .L441 + 7669 003e 4363 str r3, [r0, #52] +3370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7670 .loc 1 3370 5 is_stmt 1 discriminator 2 view .LVU2438 +3370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7671 .loc 1 3370 13 is_stmt 0 discriminator 2 view .LVU2439 + 7672 0040 438D ldrh r3, [r0, #42] + 7673 0042 9BB2 uxth r3, r3 +3370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7674 .loc 1 3370 8 discriminator 2 view .LVU2440 + 7675 0044 FF2B cmp r3, #255 + 7676 0046 10D9 bls .L426 +3372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7677 .loc 1 3372 7 is_stmt 1 view .LVU2441 +3372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 7678 .loc 1 3372 22 is_stmt 0 view .LVU2442 + 7679 0048 FF23 movs r3, #255 + 7680 004a 0385 strh r3, [r0, #40] +3373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7681 .loc 1 3373 7 is_stmt 1 view .LVU2443 + 7682 .LVL531: +3373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7683 .loc 1 3373 16 is_stmt 0 view .LVU2444 + 7684 004c 8027 movs r7, #128 + 7685 004e 7F04 lsls r7, r7, #17 + 7686 .LVL532: + 7687 .L427: +3384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7688 .loc 1 3384 5 is_stmt 1 view .LVU2445 +3384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 7689 .loc 1 3384 14 is_stmt 0 view .LVU2446 + 7690 0050 236B ldr r3, [r4, #48] +3384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + ARM GAS /tmp/ccth6daj.s page 295 + + + 7691 .loc 1 3384 8 view .LVU2447 + 7692 0052 112B cmp r3, #17 + 7693 0054 0DD1 bne .L428 +3385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7694 .loc 1 3385 8 view .LVU2448 + 7695 0056 0A9B ldr r3, [sp, #40] + 7696 0058 AA2B cmp r3, #170 + 7697 005a 0AD0 beq .L428 +3385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7698 .loc 1 3385 8 discriminator 2 view .LVU2449 + 7699 005c AA23 movs r3, #170 + 7700 005e 1B02 lsls r3, r3, #8 + 7701 0060 0A9A ldr r2, [sp, #40] + 7702 0062 9A42 cmp r2, r3 + 7703 0064 05D0 beq .L428 +3387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7704 .loc 1 3387 19 view .LVU2450 + 7705 0066 0026 movs r6, #0 + 7706 0068 0CE0 b .L429 + 7707 .LVL533: + 7708 .L426: +3377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7709 .loc 1 3377 7 is_stmt 1 view .LVU2451 +3377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7710 .loc 1 3377 28 is_stmt 0 view .LVU2452 + 7711 006a 438D ldrh r3, [r0, #42] +3377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 7712 .loc 1 3377 22 view .LVU2453 + 7713 006c 0385 strh r3, [r0, #40] +3378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7714 .loc 1 3378 7 is_stmt 1 view .LVU2454 +3378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7715 .loc 1 3378 16 is_stmt 0 view .LVU2455 + 7716 006e C76A ldr r7, [r0, #44] + 7717 .LVL534: +3378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7718 .loc 1 3378 16 view .LVU2456 + 7719 0070 EEE7 b .L427 + 7720 .L428: +3392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7721 .loc 1 3392 7 is_stmt 1 view .LVU2457 + 7722 0072 2000 movs r0, r4 + 7723 .LVL535: +3392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7724 .loc 1 3392 7 is_stmt 0 view .LVU2458 + 7725 0074 FFF7FEFF bl I2C_ConvertOtherXferOptions + 7726 .LVL536: +3395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7727 .loc 1 3395 7 is_stmt 1 view .LVU2459 +3395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7728 .loc 1 3395 15 is_stmt 0 view .LVU2460 + 7729 0078 638D ldrh r3, [r4, #42] + 7730 007a 9BB2 uxth r3, r3 +3395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7731 .loc 1 3395 10 view .LVU2461 + 7732 007c FF2B cmp r3, #255 + 7733 007e 28D8 bhi .L438 + ARM GAS /tmp/ccth6daj.s page 296 + + +3397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7734 .loc 1 3397 9 is_stmt 1 view .LVU2462 +3397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7735 .loc 1 3397 18 is_stmt 0 view .LVU2463 + 7736 0080 E76A ldr r7, [r4, #44] + 7737 .LVL537: +3348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7738 .loc 1 3348 12 view .LVU2464 + 7739 0082 374E ldr r6, .L441+4 + 7740 .L429: + 7741 .LVL538: +3401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7742 .loc 1 3401 5 is_stmt 1 view .LVU2465 +3401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7743 .loc 1 3401 13 is_stmt 0 view .LVU2466 + 7744 0084 228D ldrh r2, [r4, #40] +3401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7745 .loc 1 3401 8 view .LVU2467 + 7746 0086 002A cmp r2, #0 + 7747 0088 4ED0 beq .L430 +3403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7748 .loc 1 3403 7 is_stmt 1 view .LVU2468 +3403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7749 .loc 1 3403 15 is_stmt 0 view .LVU2469 + 7750 008a A36B ldr r3, [r4, #56] +3403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7751 .loc 1 3403 10 view .LVU2470 + 7752 008c 002B cmp r3, #0 + 7753 008e 22D0 beq .L431 +3406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7754 .loc 1 3406 9 is_stmt 1 view .LVU2471 +3406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7755 .loc 1 3406 40 is_stmt 0 view .LVU2472 + 7756 0090 344A ldr r2, .L441+8 + 7757 0092 DA62 str r2, [r3, #44] +3409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7758 .loc 1 3409 9 is_stmt 1 view .LVU2473 +3409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7759 .loc 1 3409 13 is_stmt 0 view .LVU2474 + 7760 0094 A36B ldr r3, [r4, #56] +3409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7761 .loc 1 3409 41 view .LVU2475 + 7762 0096 344A ldr r2, .L441+12 + 7763 0098 5A63 str r2, [r3, #52] +3412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7764 .loc 1 3412 9 is_stmt 1 view .LVU2476 +3412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7765 .loc 1 3412 13 is_stmt 0 view .LVU2477 + 7766 009a A26B ldr r2, [r4, #56] +3412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7767 .loc 1 3412 44 view .LVU2478 + 7768 009c 0023 movs r3, #0 + 7769 009e 1363 str r3, [r2, #48] +3413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7770 .loc 1 3413 9 is_stmt 1 view .LVU2479 +3413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7771 .loc 1 3413 13 is_stmt 0 view .LVU2480 + ARM GAS /tmp/ccth6daj.s page 297 + + + 7772 00a0 A26B ldr r2, [r4, #56] +3413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7773 .loc 1 3413 41 view .LVU2481 + 7774 00a2 9363 str r3, [r2, #56] +3416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 7775 .loc 1 3416 9 is_stmt 1 view .LVU2482 +3416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 7776 .loc 1 3416 83 is_stmt 0 view .LVU2483 + 7777 00a4 2268 ldr r2, [r4] + 7778 00a6 2832 adds r2, r2, #40 +3417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7779 .loc 1 3417 46 view .LVU2484 + 7780 00a8 238D ldrh r3, [r4, #40] +3416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 7781 .loc 1 3416 25 view .LVU2485 + 7782 00aa 2900 movs r1, r5 + 7783 00ac A06B ldr r0, [r4, #56] + 7784 00ae FFF7FEFF bl HAL_DMA_Start_IT + 7785 .LVL539: +3434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7786 .loc 1 3434 7 is_stmt 1 view .LVU2486 +3434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7787 .loc 1 3434 10 is_stmt 0 view .LVU2487 + 7788 00b2 0028 cmp r0, #0 + 7789 00b4 1DD0 beq .L440 +3457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7790 .loc 1 3457 9 is_stmt 1 view .LVU2488 +3457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7791 .loc 1 3457 25 is_stmt 0 view .LVU2489 + 7792 00b6 4123 movs r3, #65 + 7793 00b8 2022 movs r2, #32 + 7794 00ba E254 strb r2, [r4, r3] +3458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7795 .loc 1 3458 9 is_stmt 1 view .LVU2490 +3458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7796 .loc 1 3458 25 is_stmt 0 view .LVU2491 + 7797 00bc 0022 movs r2, #0 + 7798 00be 0133 adds r3, r3, #1 + 7799 00c0 E254 strb r2, [r4, r3] +3461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7800 .loc 1 3461 9 is_stmt 1 view .LVU2492 +3461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7801 .loc 1 3461 25 is_stmt 0 view .LVU2493 + 7802 00c2 636C ldr r3, [r4, #68] + 7803 00c4 1021 movs r1, #16 + 7804 00c6 0B43 orrs r3, r1 + 7805 00c8 6364 str r3, [r4, #68] +3464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7806 .loc 1 3464 9 is_stmt 1 view .LVU2494 +3464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7807 .loc 1 3464 9 view .LVU2495 + 7808 00ca 4023 movs r3, #64 + 7809 00cc E254 strb r2, [r4, r3] +3464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7810 .loc 1 3464 9 view .LVU2496 +3466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7811 .loc 1 3466 9 view .LVU2497 + ARM GAS /tmp/ccth6daj.s page 298 + + +3466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7812 .loc 1 3466 16 is_stmt 0 view .LVU2498 + 7813 00ce 0120 movs r0, #1 + 7814 .LVL540: +3466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7815 .loc 1 3466 16 view .LVU2499 + 7816 00d0 3FE0 b .L425 + 7817 .LVL541: + 7818 .L438: +3348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 7819 .loc 1 3348 12 view .LVU2500 + 7820 00d2 234E ldr r6, .L441+4 + 7821 00d4 D6E7 b .L429 + 7822 .LVL542: + 7823 .L431: +3422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7824 .loc 1 3422 9 is_stmt 1 view .LVU2501 +3422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7825 .loc 1 3422 25 is_stmt 0 view .LVU2502 + 7826 00d6 4123 movs r3, #65 + 7827 00d8 2022 movs r2, #32 + 7828 00da E254 strb r2, [r4, r3] +3423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7829 .loc 1 3423 9 is_stmt 1 view .LVU2503 +3423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7830 .loc 1 3423 25 is_stmt 0 view .LVU2504 + 7831 00dc 0022 movs r2, #0 + 7832 00de 0133 adds r3, r3, #1 + 7833 00e0 E254 strb r2, [r4, r3] +3426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7834 .loc 1 3426 9 is_stmt 1 view .LVU2505 +3426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7835 .loc 1 3426 25 is_stmt 0 view .LVU2506 + 7836 00e2 636C ldr r3, [r4, #68] + 7837 00e4 8021 movs r1, #128 + 7838 00e6 0B43 orrs r3, r1 + 7839 00e8 6364 str r3, [r4, #68] +3429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7840 .loc 1 3429 9 is_stmt 1 view .LVU2507 +3429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7841 .loc 1 3429 9 view .LVU2508 + 7842 00ea 4023 movs r3, #64 + 7843 00ec E254 strb r2, [r4, r3] +3429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7844 .loc 1 3429 9 view .LVU2509 +3431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7845 .loc 1 3431 9 view .LVU2510 +3431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7846 .loc 1 3431 16 is_stmt 0 view .LVU2511 + 7847 00ee 0120 movs r0, #1 + 7848 00f0 2FE0 b .L425 + 7849 .LVL543: + 7850 .L440: +3437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7851 .loc 1 3437 9 is_stmt 1 view .LVU2512 +3437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7852 .loc 1 3437 59 is_stmt 0 view .LVU2513 + ARM GAS /tmp/ccth6daj.s page 299 + + + 7853 00f2 228D ldrh r2, [r4, #40] +3437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7854 .loc 1 3437 9 view .LVU2514 + 7855 00f4 D2B2 uxtb r2, r2 + 7856 00f6 0096 str r6, [sp] + 7857 00f8 3B00 movs r3, r7 + 7858 00fa 0399 ldr r1, [sp, #12] + 7859 00fc 2000 movs r0, r4 + 7860 .LVL544: +3437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7861 .loc 1 3437 9 view .LVU2515 + 7862 00fe FFF7FEFF bl I2C_TransferConfig + 7863 .LVL545: +3440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7864 .loc 1 3440 9 is_stmt 1 view .LVU2516 +3440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7865 .loc 1 3440 25 is_stmt 0 view .LVU2517 + 7866 0102 638D ldrh r3, [r4, #42] +3440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7867 .loc 1 3440 32 view .LVU2518 + 7868 0104 228D ldrh r2, [r4, #40] +3440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7869 .loc 1 3440 25 view .LVU2519 + 7870 0106 9B1A subs r3, r3, r2 + 7871 0108 9BB2 uxth r3, r3 + 7872 010a 6385 strh r3, [r4, #42] +3443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7873 .loc 1 3443 9 is_stmt 1 view .LVU2520 +3443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7874 .loc 1 3443 9 view .LVU2521 + 7875 010c 4023 movs r3, #64 + 7876 010e 0022 movs r2, #0 + 7877 0110 E254 strb r2, [r4, r3] +3443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7878 .loc 1 3443 9 view .LVU2522 +3449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7879 .loc 1 3449 9 view .LVU2523 + 7880 0112 1021 movs r1, #16 + 7881 0114 2000 movs r0, r4 + 7882 0116 FFF7FEFF bl I2C_Enable_IRQ + 7883 .LVL546: +3452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7884 .loc 1 3452 9 view .LVU2524 +3452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7885 .loc 1 3452 13 is_stmt 0 view .LVU2525 + 7886 011a 2268 ldr r2, [r4] +3452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7887 .loc 1 3452 29 view .LVU2526 + 7888 011c 1168 ldr r1, [r2] + 7889 011e 8023 movs r3, #128 + 7890 0120 DB01 lsls r3, r3, #7 + 7891 0122 0B43 orrs r3, r1 + 7892 0124 1360 str r3, [r2] + 7893 0126 11E0 b .L434 + 7894 .L430: +3472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7895 .loc 1 3472 7 is_stmt 1 view .LVU2527 + ARM GAS /tmp/ccth6daj.s page 300 + + +3472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7896 .loc 1 3472 21 is_stmt 0 view .LVU2528 + 7897 0128 104B ldr r3, .L441+16 + 7898 012a 6363 str r3, [r4, #52] +3476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); + 7899 .loc 1 3476 7 is_stmt 1 view .LVU2529 + 7900 012c 8023 movs r3, #128 + 7901 012e D2B2 uxtb r2, r2 + 7902 0130 0B49 ldr r1, .L441+4 + 7903 0132 0091 str r1, [sp] + 7904 0134 9B04 lsls r3, r3, #18 + 7905 0136 0399 ldr r1, [sp, #12] + 7906 0138 2000 movs r0, r4 + 7907 013a FFF7FEFF bl I2C_TransferConfig + 7908 .LVL547: +3480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7909 .loc 1 3480 7 view .LVU2530 +3480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7910 .loc 1 3480 7 view .LVU2531 + 7911 013e 4023 movs r3, #64 + 7912 0140 0022 movs r2, #0 + 7913 0142 E254 strb r2, [r4, r3] +3480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7914 .loc 1 3480 7 view .LVU2532 +3489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7915 .loc 1 3489 7 view .LVU2533 + 7916 0144 0121 movs r1, #1 + 7917 0146 2000 movs r0, r4 + 7918 0148 FFF7FEFF bl I2C_Enable_IRQ + 7919 .LVL548: + 7920 .L434: +3492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7921 .loc 1 3492 5 view .LVU2534 +3492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7922 .loc 1 3492 12 is_stmt 0 view .LVU2535 + 7923 014c 0020 movs r0, #0 + 7924 014e 00E0 b .L425 + 7925 .LVL549: + 7926 .L435: +3496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 7927 .loc 1 3496 12 view .LVU2536 + 7928 0150 0220 movs r0, #2 + 7929 .LVL550: + 7930 .L425: +3498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7931 .loc 1 3498 1 view .LVU2537 + 7932 0152 05B0 add sp, sp, #20 + 7933 @ sp needed + 7934 .LVL551: + 7935 .LVL552: +3498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7936 .loc 1 3498 1 view .LVU2538 + 7937 0154 F0BD pop {r4, r5, r6, r7, pc} + 7938 .LVL553: + 7939 .L436: +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7940 .loc 1 3357 5 view .LVU2539 + ARM GAS /tmp/ccth6daj.s page 301 + + + 7941 0156 0220 movs r0, #2 + 7942 .LVL554: +3357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7943 .loc 1 3357 5 view .LVU2540 + 7944 0158 FBE7 b .L425 + 7945 .L442: + 7946 015a C046 .align 2 + 7947 .L441: + 7948 015c 00000000 .word I2C_Master_ISR_DMA + 7949 0160 00200080 .word -2147475456 + 7950 0164 00000000 .word I2C_DMAMasterTransmitCplt + 7951 0168 00000000 .word I2C_DMAError + 7952 016c 00000000 .word I2C_Master_ISR_IT + 7953 .cfi_endproc + 7954 .LFE321: + 7956 .section .text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits + 7957 .align 1 + 7958 .global HAL_I2C_Master_Seq_Receive_IT + 7959 .syntax unified + 7960 .code 16 + 7961 .thumb_func + 7962 .fpu softvfp + 7964 HAL_I2C_Master_Seq_Receive_IT: + 7965 .LVL555: + 7966 .LFB322: +3514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7967 .loc 1 3514 1 is_stmt 1 view -0 + 7968 .cfi_startproc + 7969 @ args = 4, pretend = 0, frame = 0 + 7970 @ frame_needed = 0, uses_anonymous_args = 0 +3514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 7971 .loc 1 3514 1 is_stmt 0 view .LVU2542 + 7972 0000 70B5 push {r4, r5, r6, lr} + 7973 .LCFI59: + 7974 .cfi_def_cfa_offset 16 + 7975 .cfi_offset 4, -16 + 7976 .cfi_offset 5, -12 + 7977 .cfi_offset 6, -8 + 7978 .cfi_offset 14, -4 + 7979 0002 82B0 sub sp, sp, #8 + 7980 .LCFI60: + 7981 .cfi_def_cfa_offset 24 + 7982 0004 0400 movs r4, r0 + 7983 0006 0D00 movs r5, r1 +3515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 7984 .loc 1 3515 3 is_stmt 1 view .LVU2543 +3516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7985 .loc 1 3516 3 view .LVU2544 + 7986 .LVL556: +3519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7987 .loc 1 3519 3 view .LVU2545 +3521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7988 .loc 1 3521 3 view .LVU2546 +3521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7989 .loc 1 3521 11 is_stmt 0 view .LVU2547 + 7990 0008 4121 movs r1, #65 + 7991 .LVL557: + ARM GAS /tmp/ccth6daj.s page 302 + + +3521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7992 .loc 1 3521 11 view .LVU2548 + 7993 000a 415C ldrb r1, [r0, r1] +3521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 7994 .loc 1 3521 6 view .LVU2549 + 7995 000c 2029 cmp r1, #32 + 7996 000e 4AD1 bne .L449 +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7997 .loc 1 3524 5 is_stmt 1 view .LVU2550 +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 7998 .loc 1 3524 5 view .LVU2551 + 7999 0010 2031 adds r1, r1, #32 + 8000 0012 415C ldrb r1, [r0, r1] + 8001 0014 0129 cmp r1, #1 + 8002 0016 48D0 beq .L450 +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8003 .loc 1 3524 5 discriminator 2 view .LVU2552 + 8004 0018 4021 movs r1, #64 + 8005 001a 0120 movs r0, #1 + 8006 .LVL558: +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8007 .loc 1 3524 5 is_stmt 0 discriminator 2 view .LVU2553 + 8008 001c 6054 strb r0, [r4, r1] +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8009 .loc 1 3524 5 is_stmt 1 discriminator 2 view .LVU2554 +3526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8010 .loc 1 3526 5 discriminator 2 view .LVU2555 +3526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8011 .loc 1 3526 21 is_stmt 0 discriminator 2 view .LVU2556 + 8012 001e 0131 adds r1, r1, #1 + 8013 0020 2130 adds r0, r0, #33 + 8014 0022 6054 strb r0, [r4, r1] +3527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8015 .loc 1 3527 5 is_stmt 1 discriminator 2 view .LVU2557 +3527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8016 .loc 1 3527 21 is_stmt 0 discriminator 2 view .LVU2558 + 8017 0024 0131 adds r1, r1, #1 + 8018 0026 1238 subs r0, r0, #18 + 8019 0028 6054 strb r0, [r4, r1] +3528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8020 .loc 1 3528 5 is_stmt 1 discriminator 2 view .LVU2559 +3528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8021 .loc 1 3528 21 is_stmt 0 discriminator 2 view .LVU2560 + 8022 002a 0021 movs r1, #0 + 8023 002c 6164 str r1, [r4, #68] +3531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8024 .loc 1 3531 5 is_stmt 1 discriminator 2 view .LVU2561 +3531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8025 .loc 1 3531 23 is_stmt 0 discriminator 2 view .LVU2562 + 8026 002e 6262 str r2, [r4, #36] +3532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8027 .loc 1 3532 5 is_stmt 1 discriminator 2 view .LVU2563 +3532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8028 .loc 1 3532 23 is_stmt 0 discriminator 2 view .LVU2564 + 8029 0030 6385 strh r3, [r4, #42] +3533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 8030 .loc 1 3533 5 is_stmt 1 discriminator 2 view .LVU2565 + ARM GAS /tmp/ccth6daj.s page 303 + + +3533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 8031 .loc 1 3533 23 is_stmt 0 discriminator 2 view .LVU2566 + 8032 0032 069B ldr r3, [sp, #24] + 8033 .LVL559: +3533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 8034 .loc 1 3533 23 discriminator 2 view .LVU2567 + 8035 0034 E362 str r3, [r4, #44] + 8036 .LVL560: +3534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8037 .loc 1 3534 5 is_stmt 1 discriminator 2 view .LVU2568 +3534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8038 .loc 1 3534 23 is_stmt 0 discriminator 2 view .LVU2569 + 8039 0036 1E4B ldr r3, .L453 + 8040 0038 6363 str r3, [r4, #52] +3537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8041 .loc 1 3537 5 is_stmt 1 discriminator 2 view .LVU2570 +3537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8042 .loc 1 3537 13 is_stmt 0 discriminator 2 view .LVU2571 + 8043 003a 638D ldrh r3, [r4, #42] + 8044 003c 9BB2 uxth r3, r3 +3537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8045 .loc 1 3537 8 discriminator 2 view .LVU2572 + 8046 003e FF2B cmp r3, #255 + 8047 0040 10D9 bls .L445 +3539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8048 .loc 1 3539 7 is_stmt 1 view .LVU2573 +3539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8049 .loc 1 3539 22 is_stmt 0 view .LVU2574 + 8050 0042 FF23 movs r3, #255 + 8051 0044 2385 strh r3, [r4, #40] +3540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8052 .loc 1 3540 7 is_stmt 1 view .LVU2575 + 8053 .LVL561: +3540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8054 .loc 1 3540 16 is_stmt 0 view .LVU2576 + 8055 0046 8026 movs r6, #128 + 8056 0048 7604 lsls r6, r6, #17 + 8057 .LVL562: + 8058 .L446: +3551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8059 .loc 1 3551 5 is_stmt 1 view .LVU2577 +3551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8060 .loc 1 3551 14 is_stmt 0 view .LVU2578 + 8061 004a 236B ldr r3, [r4, #48] +3551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8062 .loc 1 3551 8 view .LVU2579 + 8063 004c 122B cmp r3, #18 + 8064 004e 0DD1 bne .L447 +3552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8065 .loc 1 3552 8 view .LVU2580 + 8066 0050 069B ldr r3, [sp, #24] + 8067 0052 AA2B cmp r3, #170 + 8068 0054 0AD0 beq .L447 +3552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8069 .loc 1 3552 8 discriminator 2 view .LVU2581 + 8070 0056 AA23 movs r3, #170 + 8071 0058 1B02 lsls r3, r3, #8 + ARM GAS /tmp/ccth6daj.s page 304 + + + 8072 005a 069A ldr r2, [sp, #24] + 8073 .LVL563: +3552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8074 .loc 1 3552 8 discriminator 2 view .LVU2582 + 8075 005c 9A42 cmp r2, r3 + 8076 005e 05D0 beq .L447 +3554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8077 .loc 1 3554 19 view .LVU2583 + 8078 0060 0023 movs r3, #0 + 8079 0062 0CE0 b .L448 + 8080 .LVL564: + 8081 .L445: +3544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8082 .loc 1 3544 7 is_stmt 1 view .LVU2584 +3544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8083 .loc 1 3544 28 is_stmt 0 view .LVU2585 + 8084 0064 638D ldrh r3, [r4, #42] +3544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8085 .loc 1 3544 22 view .LVU2586 + 8086 0066 2385 strh r3, [r4, #40] +3545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8087 .loc 1 3545 7 is_stmt 1 view .LVU2587 +3545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8088 .loc 1 3545 16 is_stmt 0 view .LVU2588 + 8089 0068 E66A ldr r6, [r4, #44] + 8090 .LVL565: +3545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8091 .loc 1 3545 16 view .LVU2589 + 8092 006a EEE7 b .L446 + 8093 .LVL566: + 8094 .L447: +3559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8095 .loc 1 3559 7 is_stmt 1 view .LVU2590 + 8096 006c 2000 movs r0, r4 + 8097 006e FFF7FEFF bl I2C_ConvertOtherXferOptions + 8098 .LVL567: +3562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8099 .loc 1 3562 7 view .LVU2591 +3562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8100 .loc 1 3562 15 is_stmt 0 view .LVU2592 + 8101 0072 638D ldrh r3, [r4, #42] + 8102 0074 9BB2 uxth r3, r3 +3562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8103 .loc 1 3562 10 view .LVU2593 + 8104 0076 FF2B cmp r3, #255 + 8105 0078 13D8 bhi .L452 +3564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8106 .loc 1 3564 9 is_stmt 1 view .LVU2594 +3564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8107 .loc 1 3564 18 is_stmt 0 view .LVU2595 + 8108 007a E66A ldr r6, [r4, #44] + 8109 .LVL568: +3516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8110 .loc 1 3516 12 view .LVU2596 + 8111 007c 0D4B ldr r3, .L453+4 + 8112 .L448: + 8113 .LVL569: + ARM GAS /tmp/ccth6daj.s page 305 + + +3569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8114 .loc 1 3569 5 is_stmt 1 view .LVU2597 +3569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8115 .loc 1 3569 55 is_stmt 0 view .LVU2598 + 8116 007e 228D ldrh r2, [r4, #40] +3569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8117 .loc 1 3569 5 view .LVU2599 + 8118 0080 D2B2 uxtb r2, r2 + 8119 0082 0093 str r3, [sp] + 8120 0084 3300 movs r3, r6 + 8121 .LVL570: +3569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8122 .loc 1 3569 5 view .LVU2600 + 8123 0086 2900 movs r1, r5 + 8124 0088 2000 movs r0, r4 + 8125 008a FFF7FEFF bl I2C_TransferConfig + 8126 .LVL571: +3572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8127 .loc 1 3572 5 is_stmt 1 view .LVU2601 +3572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8128 .loc 1 3572 5 view .LVU2602 + 8129 008e 4023 movs r3, #64 + 8130 0090 0022 movs r2, #0 + 8131 0092 E254 strb r2, [r4, r3] +3572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8132 .loc 1 3572 5 view .LVU2603 +3577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8133 .loc 1 3577 5 view .LVU2604 + 8134 0094 0221 movs r1, #2 + 8135 0096 2000 movs r0, r4 + 8136 0098 FFF7FEFF bl I2C_Enable_IRQ + 8137 .LVL572: +3579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8138 .loc 1 3579 5 view .LVU2605 +3579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8139 .loc 1 3579 12 is_stmt 0 view .LVU2606 + 8140 009c 0020 movs r0, #0 + 8141 .LVL573: + 8142 .L444: +3585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8143 .loc 1 3585 1 view .LVU2607 + 8144 009e 02B0 add sp, sp, #8 + 8145 @ sp needed + 8146 .LVL574: +3585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8147 .loc 1 3585 1 view .LVU2608 + 8148 00a0 70BD pop {r4, r5, r6, pc} + 8149 .LVL575: + 8150 .L452: +3516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8151 .loc 1 3516 12 view .LVU2609 + 8152 00a2 044B ldr r3, .L453+4 + 8153 00a4 EBE7 b .L448 + 8154 .LVL576: + 8155 .L449: +3583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8156 .loc 1 3583 12 view .LVU2610 + ARM GAS /tmp/ccth6daj.s page 306 + + + 8157 00a6 0220 movs r0, #2 + 8158 .LVL577: +3583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8159 .loc 1 3583 12 view .LVU2611 + 8160 00a8 F9E7 b .L444 + 8161 .LVL578: + 8162 .L450: +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8163 .loc 1 3524 5 view .LVU2612 + 8164 00aa 0220 movs r0, #2 + 8165 .LVL579: +3524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8166 .loc 1 3524 5 view .LVU2613 + 8167 00ac F7E7 b .L444 + 8168 .L454: + 8169 00ae C046 .align 2 + 8170 .L453: + 8171 00b0 00000000 .word I2C_Master_ISR_IT + 8172 00b4 00240080 .word -2147474432 + 8173 .cfi_endproc + 8174 .LFE322: + 8176 .section .text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits + 8177 .align 1 + 8178 .global HAL_I2C_Master_Seq_Receive_DMA + 8179 .syntax unified + 8180 .code 16 + 8181 .thumb_func + 8182 .fpu softvfp + 8184 HAL_I2C_Master_Seq_Receive_DMA: + 8185 .LVL580: + 8186 .LFB323: +3601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 8187 .loc 1 3601 1 is_stmt 1 view -0 + 8188 .cfi_startproc + 8189 @ args = 4, pretend = 0, frame = 8 + 8190 @ frame_needed = 0, uses_anonymous_args = 0 +3601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 8191 .loc 1 3601 1 is_stmt 0 view .LVU2615 + 8192 0000 F0B5 push {r4, r5, r6, r7, lr} + 8193 .LCFI61: + 8194 .cfi_def_cfa_offset 20 + 8195 .cfi_offset 4, -20 + 8196 .cfi_offset 5, -16 + 8197 .cfi_offset 6, -12 + 8198 .cfi_offset 7, -8 + 8199 .cfi_offset 14, -4 + 8200 0002 85B0 sub sp, sp, #20 + 8201 .LCFI62: + 8202 .cfi_def_cfa_offset 40 + 8203 0004 0400 movs r4, r0 + 8204 0006 0391 str r1, [sp, #12] + 8205 0008 1500 movs r5, r2 +3602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 8206 .loc 1 3602 3 is_stmt 1 view .LVU2616 +3603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8207 .loc 1 3603 3 view .LVU2617 + 8208 .LVL581: + ARM GAS /tmp/ccth6daj.s page 307 + + +3604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8209 .loc 1 3604 3 view .LVU2618 +3607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8210 .loc 1 3607 3 view .LVU2619 +3609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8211 .loc 1 3609 3 view .LVU2620 +3609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8212 .loc 1 3609 11 is_stmt 0 view .LVU2621 + 8213 000a 4122 movs r2, #65 + 8214 .LVL582: +3609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8215 .loc 1 3609 11 view .LVU2622 + 8216 000c 825C ldrb r2, [r0, r2] +3609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8217 .loc 1 3609 6 view .LVU2623 + 8218 000e 202A cmp r2, #32 + 8219 0010 00D0 beq .LCB7886 + 8220 0012 9DE0 b .L466 @long jump + 8221 .LCB7886: +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8222 .loc 1 3612 5 is_stmt 1 view .LVU2624 +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8223 .loc 1 3612 5 view .LVU2625 + 8224 0014 2032 adds r2, r2, #32 + 8225 0016 825C ldrb r2, [r0, r2] + 8226 0018 012A cmp r2, #1 + 8227 001a 00D1 bne .LCB7892 + 8228 001c 9BE0 b .L467 @long jump + 8229 .LCB7892: +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8230 .loc 1 3612 5 discriminator 2 view .LVU2626 + 8231 001e 4022 movs r2, #64 + 8232 0020 0121 movs r1, #1 + 8233 .LVL583: +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8234 .loc 1 3612 5 is_stmt 0 discriminator 2 view .LVU2627 + 8235 0022 8154 strb r1, [r0, r2] +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8236 .loc 1 3612 5 is_stmt 1 discriminator 2 view .LVU2628 +3614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8237 .loc 1 3614 5 discriminator 2 view .LVU2629 +3614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 8238 .loc 1 3614 21 is_stmt 0 discriminator 2 view .LVU2630 + 8239 0024 0132 adds r2, r2, #1 + 8240 0026 2131 adds r1, r1, #33 + 8241 0028 8154 strb r1, [r0, r2] +3615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8242 .loc 1 3615 5 is_stmt 1 discriminator 2 view .LVU2631 +3615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8243 .loc 1 3615 21 is_stmt 0 discriminator 2 view .LVU2632 + 8244 002a 0132 adds r2, r2, #1 + 8245 002c 1239 subs r1, r1, #18 + 8246 002e 8154 strb r1, [r0, r2] +3616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8247 .loc 1 3616 5 is_stmt 1 discriminator 2 view .LVU2633 +3616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8248 .loc 1 3616 21 is_stmt 0 discriminator 2 view .LVU2634 + ARM GAS /tmp/ccth6daj.s page 308 + + + 8249 0030 0022 movs r2, #0 + 8250 0032 4264 str r2, [r0, #68] +3619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8251 .loc 1 3619 5 is_stmt 1 discriminator 2 view .LVU2635 +3619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8252 .loc 1 3619 23 is_stmt 0 discriminator 2 view .LVU2636 + 8253 0034 4562 str r5, [r0, #36] +3620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8254 .loc 1 3620 5 is_stmt 1 discriminator 2 view .LVU2637 +3620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8255 .loc 1 3620 23 is_stmt 0 discriminator 2 view .LVU2638 + 8256 0036 4385 strh r3, [r0, #42] +3621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 8257 .loc 1 3621 5 is_stmt 1 discriminator 2 view .LVU2639 +3621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 8258 .loc 1 3621 23 is_stmt 0 discriminator 2 view .LVU2640 + 8259 0038 0A9B ldr r3, [sp, #40] + 8260 .LVL584: +3621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 8261 .loc 1 3621 23 discriminator 2 view .LVU2641 + 8262 003a C362 str r3, [r0, #44] + 8263 .LVL585: +3622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8264 .loc 1 3622 5 is_stmt 1 discriminator 2 view .LVU2642 +3622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8265 .loc 1 3622 23 is_stmt 0 discriminator 2 view .LVU2643 + 8266 003c 474B ldr r3, .L472 + 8267 003e 4363 str r3, [r0, #52] +3625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8268 .loc 1 3625 5 is_stmt 1 discriminator 2 view .LVU2644 +3625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8269 .loc 1 3625 13 is_stmt 0 discriminator 2 view .LVU2645 + 8270 0040 438D ldrh r3, [r0, #42] + 8271 0042 9BB2 uxth r3, r3 +3625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8272 .loc 1 3625 8 discriminator 2 view .LVU2646 + 8273 0044 FF2B cmp r3, #255 + 8274 0046 10D9 bls .L457 +3627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8275 .loc 1 3627 7 is_stmt 1 view .LVU2647 +3627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 8276 .loc 1 3627 22 is_stmt 0 view .LVU2648 + 8277 0048 FF23 movs r3, #255 + 8278 004a 0385 strh r3, [r0, #40] +3628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8279 .loc 1 3628 7 is_stmt 1 view .LVU2649 + 8280 .LVL586: +3628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8281 .loc 1 3628 16 is_stmt 0 view .LVU2650 + 8282 004c 8027 movs r7, #128 + 8283 004e 7F04 lsls r7, r7, #17 + 8284 .LVL587: + 8285 .L458: +3639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8286 .loc 1 3639 5 is_stmt 1 view .LVU2651 +3639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8287 .loc 1 3639 14 is_stmt 0 view .LVU2652 + ARM GAS /tmp/ccth6daj.s page 309 + + + 8288 0050 236B ldr r3, [r4, #48] +3639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 8289 .loc 1 3639 8 view .LVU2653 + 8290 0052 122B cmp r3, #18 + 8291 0054 0DD1 bne .L459 +3640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8292 .loc 1 3640 8 view .LVU2654 + 8293 0056 0A9B ldr r3, [sp, #40] + 8294 0058 AA2B cmp r3, #170 + 8295 005a 0AD0 beq .L459 +3640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8296 .loc 1 3640 8 discriminator 2 view .LVU2655 + 8297 005c AA23 movs r3, #170 + 8298 005e 1B02 lsls r3, r3, #8 + 8299 0060 0A9A ldr r2, [sp, #40] + 8300 0062 9A42 cmp r2, r3 + 8301 0064 05D0 beq .L459 +3642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8302 .loc 1 3642 19 view .LVU2656 + 8303 0066 0026 movs r6, #0 + 8304 0068 0CE0 b .L460 + 8305 .LVL588: + 8306 .L457: +3632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8307 .loc 1 3632 7 is_stmt 1 view .LVU2657 +3632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8308 .loc 1 3632 28 is_stmt 0 view .LVU2658 + 8309 006a 438D ldrh r3, [r0, #42] +3632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 8310 .loc 1 3632 22 view .LVU2659 + 8311 006c 0385 strh r3, [r0, #40] +3633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8312 .loc 1 3633 7 is_stmt 1 view .LVU2660 +3633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8313 .loc 1 3633 16 is_stmt 0 view .LVU2661 + 8314 006e C76A ldr r7, [r0, #44] + 8315 .LVL589: +3633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8316 .loc 1 3633 16 view .LVU2662 + 8317 0070 EEE7 b .L458 + 8318 .L459: +3647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8319 .loc 1 3647 7 is_stmt 1 view .LVU2663 + 8320 0072 2000 movs r0, r4 + 8321 .LVL590: +3647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8322 .loc 1 3647 7 is_stmt 0 view .LVU2664 + 8323 0074 FFF7FEFF bl I2C_ConvertOtherXferOptions + 8324 .LVL591: +3650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8325 .loc 1 3650 7 is_stmt 1 view .LVU2665 +3650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8326 .loc 1 3650 15 is_stmt 0 view .LVU2666 + 8327 0078 638D ldrh r3, [r4, #42] + 8328 007a 9BB2 uxth r3, r3 +3650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8329 .loc 1 3650 10 view .LVU2667 + ARM GAS /tmp/ccth6daj.s page 310 + + + 8330 007c FF2B cmp r3, #255 + 8331 007e 28D8 bhi .L469 +3652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8332 .loc 1 3652 9 is_stmt 1 view .LVU2668 +3652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8333 .loc 1 3652 18 is_stmt 0 view .LVU2669 + 8334 0080 E76A ldr r7, [r4, #44] + 8335 .LVL592: +3603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8336 .loc 1 3603 12 view .LVU2670 + 8337 0082 374E ldr r6, .L472+4 + 8338 .L460: + 8339 .LVL593: +3656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8340 .loc 1 3656 5 is_stmt 1 view .LVU2671 +3656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8341 .loc 1 3656 13 is_stmt 0 view .LVU2672 + 8342 0084 228D ldrh r2, [r4, #40] +3656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8343 .loc 1 3656 8 view .LVU2673 + 8344 0086 002A cmp r2, #0 + 8345 0088 4ED0 beq .L461 +3658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8346 .loc 1 3658 7 is_stmt 1 view .LVU2674 +3658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8347 .loc 1 3658 15 is_stmt 0 view .LVU2675 + 8348 008a E36B ldr r3, [r4, #60] +3658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8349 .loc 1 3658 10 view .LVU2676 + 8350 008c 002B cmp r3, #0 + 8351 008e 22D0 beq .L462 +3661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8352 .loc 1 3661 9 is_stmt 1 view .LVU2677 +3661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8353 .loc 1 3661 40 is_stmt 0 view .LVU2678 + 8354 0090 344A ldr r2, .L472+8 + 8355 0092 DA62 str r2, [r3, #44] +3664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8356 .loc 1 3664 9 is_stmt 1 view .LVU2679 +3664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8357 .loc 1 3664 13 is_stmt 0 view .LVU2680 + 8358 0094 E36B ldr r3, [r4, #60] +3664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8359 .loc 1 3664 41 view .LVU2681 + 8360 0096 344A ldr r2, .L472+12 + 8361 0098 5A63 str r2, [r3, #52] +3667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8362 .loc 1 3667 9 is_stmt 1 view .LVU2682 +3667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8363 .loc 1 3667 13 is_stmt 0 view .LVU2683 + 8364 009a E26B ldr r2, [r4, #60] +3667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8365 .loc 1 3667 44 view .LVU2684 + 8366 009c 0023 movs r3, #0 + 8367 009e 1363 str r3, [r2, #48] +3668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8368 .loc 1 3668 9 is_stmt 1 view .LVU2685 + ARM GAS /tmp/ccth6daj.s page 311 + + +3668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8369 .loc 1 3668 13 is_stmt 0 view .LVU2686 + 8370 00a0 E26B ldr r2, [r4, #60] +3668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8371 .loc 1 3668 41 view .LVU2687 + 8372 00a2 9363 str r3, [r2, #56] +3671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8373 .loc 1 3671 9 is_stmt 1 view .LVU2688 +3671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8374 .loc 1 3671 66 is_stmt 0 view .LVU2689 + 8375 00a4 2168 ldr r1, [r4] + 8376 00a6 2431 adds r1, r1, #36 +3672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8377 .loc 1 3672 46 view .LVU2690 + 8378 00a8 238D ldrh r3, [r4, #40] +3671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8379 .loc 1 3671 25 view .LVU2691 + 8380 00aa 2A00 movs r2, r5 + 8381 00ac E06B ldr r0, [r4, #60] + 8382 00ae FFF7FEFF bl HAL_DMA_Start_IT + 8383 .LVL594: +3689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8384 .loc 1 3689 7 is_stmt 1 view .LVU2692 +3689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8385 .loc 1 3689 10 is_stmt 0 view .LVU2693 + 8386 00b2 0028 cmp r0, #0 + 8387 00b4 1DD0 beq .L471 +3712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8388 .loc 1 3712 9 is_stmt 1 view .LVU2694 +3712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8389 .loc 1 3712 25 is_stmt 0 view .LVU2695 + 8390 00b6 4123 movs r3, #65 + 8391 00b8 2022 movs r2, #32 + 8392 00ba E254 strb r2, [r4, r3] +3713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8393 .loc 1 3713 9 is_stmt 1 view .LVU2696 +3713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8394 .loc 1 3713 25 is_stmt 0 view .LVU2697 + 8395 00bc 0022 movs r2, #0 + 8396 00be 0133 adds r3, r3, #1 + 8397 00c0 E254 strb r2, [r4, r3] +3716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8398 .loc 1 3716 9 is_stmt 1 view .LVU2698 +3716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8399 .loc 1 3716 25 is_stmt 0 view .LVU2699 + 8400 00c2 636C ldr r3, [r4, #68] + 8401 00c4 1021 movs r1, #16 + 8402 00c6 0B43 orrs r3, r1 + 8403 00c8 6364 str r3, [r4, #68] +3719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8404 .loc 1 3719 9 is_stmt 1 view .LVU2700 +3719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8405 .loc 1 3719 9 view .LVU2701 + 8406 00ca 4023 movs r3, #64 + 8407 00cc E254 strb r2, [r4, r3] +3719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8408 .loc 1 3719 9 view .LVU2702 + ARM GAS /tmp/ccth6daj.s page 312 + + +3721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8409 .loc 1 3721 9 view .LVU2703 +3721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8410 .loc 1 3721 16 is_stmt 0 view .LVU2704 + 8411 00ce 0120 movs r0, #1 + 8412 .LVL595: +3721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8413 .loc 1 3721 16 view .LVU2705 + 8414 00d0 3FE0 b .L456 + 8415 .LVL596: + 8416 .L469: +3603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8417 .loc 1 3603 12 view .LVU2706 + 8418 00d2 234E ldr r6, .L472+4 + 8419 00d4 D6E7 b .L460 + 8420 .LVL597: + 8421 .L462: +3677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8422 .loc 1 3677 9 is_stmt 1 view .LVU2707 +3677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8423 .loc 1 3677 25 is_stmt 0 view .LVU2708 + 8424 00d6 4123 movs r3, #65 + 8425 00d8 2022 movs r2, #32 + 8426 00da E254 strb r2, [r4, r3] +3678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8427 .loc 1 3678 9 is_stmt 1 view .LVU2709 +3678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8428 .loc 1 3678 25 is_stmt 0 view .LVU2710 + 8429 00dc 0022 movs r2, #0 + 8430 00de 0133 adds r3, r3, #1 + 8431 00e0 E254 strb r2, [r4, r3] +3681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8432 .loc 1 3681 9 is_stmt 1 view .LVU2711 +3681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8433 .loc 1 3681 25 is_stmt 0 view .LVU2712 + 8434 00e2 636C ldr r3, [r4, #68] + 8435 00e4 8021 movs r1, #128 + 8436 00e6 0B43 orrs r3, r1 + 8437 00e8 6364 str r3, [r4, #68] +3684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8438 .loc 1 3684 9 is_stmt 1 view .LVU2713 +3684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8439 .loc 1 3684 9 view .LVU2714 + 8440 00ea 4023 movs r3, #64 + 8441 00ec E254 strb r2, [r4, r3] +3684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8442 .loc 1 3684 9 view .LVU2715 +3686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8443 .loc 1 3686 9 view .LVU2716 +3686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8444 .loc 1 3686 16 is_stmt 0 view .LVU2717 + 8445 00ee 0120 movs r0, #1 + 8446 00f0 2FE0 b .L456 + 8447 .LVL598: + 8448 .L471: +3692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8449 .loc 1 3692 9 is_stmt 1 view .LVU2718 + ARM GAS /tmp/ccth6daj.s page 313 + + +3692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8450 .loc 1 3692 59 is_stmt 0 view .LVU2719 + 8451 00f2 228D ldrh r2, [r4, #40] +3692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8452 .loc 1 3692 9 view .LVU2720 + 8453 00f4 D2B2 uxtb r2, r2 + 8454 00f6 0096 str r6, [sp] + 8455 00f8 3B00 movs r3, r7 + 8456 00fa 0399 ldr r1, [sp, #12] + 8457 00fc 2000 movs r0, r4 + 8458 .LVL599: +3692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8459 .loc 1 3692 9 view .LVU2721 + 8460 00fe FFF7FEFF bl I2C_TransferConfig + 8461 .LVL600: +3695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8462 .loc 1 3695 9 is_stmt 1 view .LVU2722 +3695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8463 .loc 1 3695 25 is_stmt 0 view .LVU2723 + 8464 0102 638D ldrh r3, [r4, #42] +3695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8465 .loc 1 3695 32 view .LVU2724 + 8466 0104 228D ldrh r2, [r4, #40] +3695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8467 .loc 1 3695 25 view .LVU2725 + 8468 0106 9B1A subs r3, r3, r2 + 8469 0108 9BB2 uxth r3, r3 + 8470 010a 6385 strh r3, [r4, #42] +3698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8471 .loc 1 3698 9 is_stmt 1 view .LVU2726 +3698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8472 .loc 1 3698 9 view .LVU2727 + 8473 010c 4023 movs r3, #64 + 8474 010e 0022 movs r2, #0 + 8475 0110 E254 strb r2, [r4, r3] +3698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8476 .loc 1 3698 9 view .LVU2728 +3704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8477 .loc 1 3704 9 view .LVU2729 + 8478 0112 1021 movs r1, #16 + 8479 0114 2000 movs r0, r4 + 8480 0116 FFF7FEFF bl I2C_Enable_IRQ + 8481 .LVL601: +3707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8482 .loc 1 3707 9 view .LVU2730 +3707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8483 .loc 1 3707 13 is_stmt 0 view .LVU2731 + 8484 011a 2268 ldr r2, [r4] +3707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8485 .loc 1 3707 29 view .LVU2732 + 8486 011c 1168 ldr r1, [r2] + 8487 011e 8023 movs r3, #128 + 8488 0120 1B02 lsls r3, r3, #8 + 8489 0122 0B43 orrs r3, r1 + 8490 0124 1360 str r3, [r2] + 8491 0126 11E0 b .L465 + 8492 .L461: + ARM GAS /tmp/ccth6daj.s page 314 + + +3727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8493 .loc 1 3727 7 is_stmt 1 view .LVU2733 +3727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8494 .loc 1 3727 21 is_stmt 0 view .LVU2734 + 8495 0128 104B ldr r3, .L472+16 + 8496 012a 6363 str r3, [r4, #52] +3731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_GENERATE_START_READ); + 8497 .loc 1 3731 7 is_stmt 1 view .LVU2735 + 8498 012c 8023 movs r3, #128 + 8499 012e D2B2 uxtb r2, r2 + 8500 0130 0B49 ldr r1, .L472+4 + 8501 0132 0091 str r1, [sp] + 8502 0134 9B04 lsls r3, r3, #18 + 8503 0136 0399 ldr r1, [sp, #12] + 8504 0138 2000 movs r0, r4 + 8505 013a FFF7FEFF bl I2C_TransferConfig + 8506 .LVL602: +3735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8507 .loc 1 3735 7 view .LVU2736 +3735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8508 .loc 1 3735 7 view .LVU2737 + 8509 013e 4023 movs r3, #64 + 8510 0140 0022 movs r2, #0 + 8511 0142 E254 strb r2, [r4, r3] +3735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8512 .loc 1 3735 7 view .LVU2738 +3744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8513 .loc 1 3744 7 view .LVU2739 + 8514 0144 0121 movs r1, #1 + 8515 0146 2000 movs r0, r4 + 8516 0148 FFF7FEFF bl I2C_Enable_IRQ + 8517 .LVL603: + 8518 .L465: +3747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8519 .loc 1 3747 5 view .LVU2740 +3747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8520 .loc 1 3747 12 is_stmt 0 view .LVU2741 + 8521 014c 0020 movs r0, #0 + 8522 014e 00E0 b .L456 + 8523 .LVL604: + 8524 .L466: +3751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8525 .loc 1 3751 12 view .LVU2742 + 8526 0150 0220 movs r0, #2 + 8527 .LVL605: + 8528 .L456: +3753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8529 .loc 1 3753 1 view .LVU2743 + 8530 0152 05B0 add sp, sp, #20 + 8531 @ sp needed + 8532 .LVL606: + 8533 .LVL607: +3753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8534 .loc 1 3753 1 view .LVU2744 + 8535 0154 F0BD pop {r4, r5, r6, r7, pc} + 8536 .LVL608: + 8537 .L467: + ARM GAS /tmp/ccth6daj.s page 315 + + +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8538 .loc 1 3612 5 view .LVU2745 + 8539 0156 0220 movs r0, #2 + 8540 .LVL609: +3612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8541 .loc 1 3612 5 view .LVU2746 + 8542 0158 FBE7 b .L456 + 8543 .L473: + 8544 015a C046 .align 2 + 8545 .L472: + 8546 015c 00000000 .word I2C_Master_ISR_DMA + 8547 0160 00240080 .word -2147474432 + 8548 0164 00000000 .word I2C_DMAMasterReceiveCplt + 8549 0168 00000000 .word I2C_DMAError + 8550 016c 00000000 .word I2C_Master_ISR_IT + 8551 .cfi_endproc + 8552 .LFE323: + 8554 .section .text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits + 8555 .align 1 + 8556 .global HAL_I2C_Slave_Seq_Transmit_IT + 8557 .syntax unified + 8558 .code 16 + 8559 .thumb_func + 8560 .fpu softvfp + 8562 HAL_I2C_Slave_Seq_Transmit_IT: + 8563 .LVL610: + 8564 .LFB324: +3767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 8565 .loc 1 3767 1 is_stmt 1 view -0 + 8566 .cfi_startproc + 8567 @ args = 0, pretend = 0, frame = 0 + 8568 @ frame_needed = 0, uses_anonymous_args = 0 +3767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 8569 .loc 1 3767 1 is_stmt 0 view .LVU2748 + 8570 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8571 .LCFI63: + 8572 .cfi_def_cfa_offset 24 + 8573 .cfi_offset 3, -24 + 8574 .cfi_offset 4, -20 + 8575 .cfi_offset 5, -16 + 8576 .cfi_offset 6, -12 + 8577 .cfi_offset 7, -8 + 8578 .cfi_offset 14, -4 + 8579 0002 0400 movs r4, r0 + 8580 0004 0D00 movs r5, r1 + 8581 0006 1600 movs r6, r2 + 8582 0008 1F00 movs r7, r3 +3769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8583 .loc 1 3769 3 is_stmt 1 view .LVU2749 +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8584 .loc 1 3771 3 view .LVU2750 +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8585 .loc 1 3771 22 is_stmt 0 view .LVU2751 + 8586 000a 4123 movs r3, #65 + 8587 .LVL611: +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8588 .loc 1 3771 22 view .LVU2752 + ARM GAS /tmp/ccth6daj.s page 316 + + + 8589 000c C35C ldrb r3, [r0, r3] +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8590 .loc 1 3771 6 view .LVU2753 + 8591 000e 2822 movs r2, #40 + 8592 .LVL612: +3771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8593 .loc 1 3771 6 view .LVU2754 + 8594 0010 1340 ands r3, r2 + 8595 0012 282B cmp r3, #40 + 8596 0014 53D1 bne .L480 +3773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8597 .loc 1 3773 5 is_stmt 1 view .LVU2755 +3773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8598 .loc 1 3773 8 is_stmt 0 view .LVU2756 + 8599 0016 0029 cmp r1, #0 + 8600 0018 01D0 beq .L476 +3773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8601 .loc 1 3773 25 discriminator 1 view .LVU2757 + 8602 001a 002E cmp r6, #0 + 8603 001c 04D1 bne .L477 + 8604 .L476: +3775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 8605 .loc 1 3775 7 is_stmt 1 view .LVU2758 +3775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 8606 .loc 1 3775 23 is_stmt 0 view .LVU2759 + 8607 001e 8023 movs r3, #128 + 8608 0020 9B00 lsls r3, r3, #2 + 8609 0022 6364 str r3, [r4, #68] +3776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8610 .loc 1 3776 7 is_stmt 1 view .LVU2760 +3776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8611 .loc 1 3776 15 is_stmt 0 view .LVU2761 + 8612 0024 0120 movs r0, #1 + 8613 .LVL613: +3776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8614 .loc 1 3776 15 view .LVU2762 + 8615 0026 4BE0 b .L475 + 8616 .LVL614: + 8617 .L477: +3780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8618 .loc 1 3780 5 is_stmt 1 view .LVU2763 + 8619 0028 2749 ldr r1, .L483 + 8620 .LVL615: +3780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8621 .loc 1 3780 5 is_stmt 0 view .LVU2764 + 8622 002a FFF7FEFF bl I2C_Disable_IRQ + 8623 .LVL616: +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8624 .loc 1 3783 5 is_stmt 1 view .LVU2765 +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8625 .loc 1 3783 5 view .LVU2766 + 8626 002e 4023 movs r3, #64 + 8627 0030 E35C ldrb r3, [r4, r3] + 8628 0032 012B cmp r3, #1 + 8629 0034 45D0 beq .L481 +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8630 .loc 1 3783 5 discriminator 2 view .LVU2767 + ARM GAS /tmp/ccth6daj.s page 317 + + + 8631 0036 4023 movs r3, #64 + 8632 0038 0122 movs r2, #1 + 8633 003a E254 strb r2, [r4, r3] +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8634 .loc 1 3783 5 discriminator 2 view .LVU2768 +3787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8635 .loc 1 3787 5 discriminator 2 view .LVU2769 +3787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8636 .loc 1 3787 13 is_stmt 0 discriminator 2 view .LVU2770 + 8637 003c 0133 adds r3, r3, #1 + 8638 003e E35C ldrb r3, [r4, r3] +3787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8639 .loc 1 3787 8 discriminator 2 view .LVU2771 + 8640 0040 2A2B cmp r3, #42 + 8641 0042 22D0 beq .L482 + 8642 .L478: +3813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8643 .loc 1 3813 5 is_stmt 1 view .LVU2772 +3813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8644 .loc 1 3813 21 is_stmt 0 view .LVU2773 + 8645 0044 4123 movs r3, #65 + 8646 0046 2922 movs r2, #41 + 8647 0048 E254 strb r2, [r4, r3] +3814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8648 .loc 1 3814 5 is_stmt 1 view .LVU2774 +3814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8649 .loc 1 3814 21 is_stmt 0 view .LVU2775 + 8650 004a 0133 adds r3, r3, #1 + 8651 004c 093A subs r2, r2, #9 + 8652 004e E254 strb r2, [r4, r3] +3815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8653 .loc 1 3815 5 is_stmt 1 view .LVU2776 +3815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8654 .loc 1 3815 21 is_stmt 0 view .LVU2777 + 8655 0050 0023 movs r3, #0 + 8656 0052 6364 str r3, [r4, #68] +3818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8657 .loc 1 3818 5 is_stmt 1 view .LVU2778 +3818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8658 .loc 1 3818 9 is_stmt 0 view .LVU2779 + 8659 0054 2268 ldr r2, [r4] +3818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8660 .loc 1 3818 25 view .LVU2780 + 8661 0056 5368 ldr r3, [r2, #4] + 8662 0058 1C49 ldr r1, .L483+4 + 8663 005a 0B40 ands r3, r1 + 8664 005c 5360 str r3, [r2, #4] +3821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8665 .loc 1 3821 5 is_stmt 1 view .LVU2781 +3821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8666 .loc 1 3821 23 is_stmt 0 view .LVU2782 + 8667 005e 6562 str r5, [r4, #36] +3822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8668 .loc 1 3822 5 is_stmt 1 view .LVU2783 +3822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8669 .loc 1 3822 23 is_stmt 0 view .LVU2784 + 8670 0060 6685 strh r6, [r4, #42] + ARM GAS /tmp/ccth6daj.s page 318 + + +3823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8671 .loc 1 3823 5 is_stmt 1 view .LVU2785 +3823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8672 .loc 1 3823 29 is_stmt 0 view .LVU2786 + 8673 0062 638D ldrh r3, [r4, #42] +3823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8674 .loc 1 3823 23 view .LVU2787 + 8675 0064 2385 strh r3, [r4, #40] +3824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8676 .loc 1 3824 5 is_stmt 1 view .LVU2788 +3824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8677 .loc 1 3824 23 is_stmt 0 view .LVU2789 + 8678 0066 E762 str r7, [r4, #44] +3825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8679 .loc 1 3825 5 is_stmt 1 view .LVU2790 +3825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8680 .loc 1 3825 23 is_stmt 0 view .LVU2791 + 8681 0068 194B ldr r3, .L483+8 + 8682 006a 6363 str r3, [r4, #52] +3827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8683 .loc 1 3827 5 is_stmt 1 view .LVU2792 +3827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8684 .loc 1 3827 9 is_stmt 0 view .LVU2793 + 8685 006c 2368 ldr r3, [r4] + 8686 006e 9A69 ldr r2, [r3, #24] +3827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8687 .loc 1 3827 8 view .LVU2794 + 8688 0070 D203 lsls r2, r2, #15 + 8689 0072 01D5 bpl .L479 +3831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8690 .loc 1 3831 7 is_stmt 1 view .LVU2795 + 8691 0074 0822 movs r2, #8 + 8692 0076 DA61 str r2, [r3, #28] + 8693 .L479: +3835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8694 .loc 1 3835 5 view .LVU2796 +3835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8695 .loc 1 3835 5 view .LVU2797 + 8696 0078 4023 movs r3, #64 + 8697 007a 0022 movs r2, #0 + 8698 007c E254 strb r2, [r4, r3] +3835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8699 .loc 1 3835 5 view .LVU2798 +3841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8700 .loc 1 3841 5 view .LVU2799 + 8701 007e 1249 ldr r1, .L483 + 8702 0080 2000 movs r0, r4 + 8703 0082 FFF7FEFF bl I2C_Enable_IRQ + 8704 .LVL617: +3843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8705 .loc 1 3843 5 view .LVU2800 +3843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8706 .loc 1 3843 12 is_stmt 0 view .LVU2801 + 8707 0086 0020 movs r0, #0 + 8708 0088 1AE0 b .L475 + 8709 .L482: +3790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 319 + + + 8710 .loc 1 3790 7 is_stmt 1 view .LVU2802 + 8711 008a 0221 movs r1, #2 + 8712 008c 2000 movs r0, r4 + 8713 008e FFF7FEFF bl I2C_Disable_IRQ + 8714 .LVL618: +3793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8715 .loc 1 3793 7 view .LVU2803 +3793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8716 .loc 1 3793 16 is_stmt 0 view .LVU2804 + 8717 0092 2368 ldr r3, [r4] +3793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8718 .loc 1 3793 26 view .LVU2805 + 8719 0094 1A68 ldr r2, [r3] +3793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8720 .loc 1 3793 10 view .LVU2806 + 8721 0096 1204 lsls r2, r2, #16 + 8722 0098 D4D5 bpl .L478 +3795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8723 .loc 1 3795 9 is_stmt 1 view .LVU2807 +3795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8724 .loc 1 3795 29 is_stmt 0 view .LVU2808 + 8725 009a 1A68 ldr r2, [r3] + 8726 009c 0B49 ldr r1, .L483+4 + 8727 009e 0A40 ands r2, r1 + 8728 00a0 1A60 str r2, [r3] +3797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8729 .loc 1 3797 9 is_stmt 1 view .LVU2809 +3797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8730 .loc 1 3797 17 is_stmt 0 view .LVU2810 + 8731 00a2 E36B ldr r3, [r4, #60] +3797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8732 .loc 1 3797 12 view .LVU2811 + 8733 00a4 002B cmp r3, #0 + 8734 00a6 CDD0 beq .L478 +3801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8735 .loc 1 3801 11 is_stmt 1 view .LVU2812 +3801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8736 .loc 1 3801 43 is_stmt 0 view .LVU2813 + 8737 00a8 0A4A ldr r2, .L483+12 + 8738 00aa 9A63 str r2, [r3, #56] +3804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8739 .loc 1 3804 11 is_stmt 1 view .LVU2814 +3804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8740 .loc 1 3804 15 is_stmt 0 view .LVU2815 + 8741 00ac E06B ldr r0, [r4, #60] + 8742 00ae FFF7FEFF bl HAL_DMA_Abort_IT + 8743 .LVL619: +3804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8744 .loc 1 3804 14 view .LVU2816 + 8745 00b2 0028 cmp r0, #0 + 8746 00b4 C6D0 beq .L478 +3807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8747 .loc 1 3807 13 is_stmt 1 view .LVU2817 +3807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8748 .loc 1 3807 17 is_stmt 0 view .LVU2818 + 8749 00b6 E06B ldr r0, [r4, #60] +3807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 320 + + + 8750 .loc 1 3807 25 view .LVU2819 + 8751 00b8 836B ldr r3, [r0, #56] +3807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8752 .loc 1 3807 13 view .LVU2820 + 8753 00ba 9847 blx r3 + 8754 .LVL620: + 8755 00bc C2E7 b .L478 + 8756 .LVL621: + 8757 .L480: +3847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8758 .loc 1 3847 12 view .LVU2821 + 8759 00be 0120 movs r0, #1 + 8760 .LVL622: + 8761 .L475: +3849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8762 .loc 1 3849 1 view .LVU2822 + 8763 @ sp needed + 8764 .LVL623: + 8765 .LVL624: + 8766 .LVL625: +3849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8767 .loc 1 3849 1 view .LVU2823 + 8768 00c0 F8BD pop {r3, r4, r5, r6, r7, pc} + 8769 .LVL626: + 8770 .L481: +3783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8771 .loc 1 3783 5 view .LVU2824 + 8772 00c2 0220 movs r0, #2 + 8773 00c4 FCE7 b .L475 + 8774 .L484: + 8775 00c6 C046 .align 2 + 8776 .L483: + 8777 00c8 01800000 .word 32769 + 8778 00cc FF7FFFFF .word -32769 + 8779 00d0 00000000 .word I2C_Slave_ISR_IT + 8780 00d4 00000000 .word I2C_DMAAbort + 8781 .cfi_endproc + 8782 .LFE324: + 8784 .section .text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits + 8785 .align 1 + 8786 .global HAL_I2C_Slave_Seq_Transmit_DMA + 8787 .syntax unified + 8788 .code 16 + 8789 .thumb_func + 8790 .fpu softvfp + 8792 HAL_I2C_Slave_Seq_Transmit_DMA: + 8793 .LVL627: + 8794 .LFB325: +3863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8795 .loc 1 3863 1 is_stmt 1 view -0 + 8796 .cfi_startproc + 8797 @ args = 0, pretend = 0, frame = 0 + 8798 @ frame_needed = 0, uses_anonymous_args = 0 +3863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 8799 .loc 1 3863 1 is_stmt 0 view .LVU2826 + 8800 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 8801 .LCFI64: + ARM GAS /tmp/ccth6daj.s page 321 + + + 8802 .cfi_def_cfa_offset 24 + 8803 .cfi_offset 3, -24 + 8804 .cfi_offset 4, -20 + 8805 .cfi_offset 5, -16 + 8806 .cfi_offset 6, -12 + 8807 .cfi_offset 7, -8 + 8808 .cfi_offset 14, -4 + 8809 0002 0400 movs r4, r0 + 8810 0004 0F00 movs r7, r1 + 8811 0006 1500 movs r5, r2 + 8812 0008 1E00 movs r6, r3 +3864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8813 .loc 1 3864 3 is_stmt 1 view .LVU2827 +3867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8814 .loc 1 3867 3 view .LVU2828 +3869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8815 .loc 1 3869 3 view .LVU2829 +3869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8816 .loc 1 3869 22 is_stmt 0 view .LVU2830 + 8817 000a 4123 movs r3, #65 + 8818 .LVL628: +3869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8819 .loc 1 3869 22 view .LVU2831 + 8820 000c C05C ldrb r0, [r0, r3] + 8821 .LVL629: +3869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8822 .loc 1 3869 6 view .LVU2832 + 8823 000e 193B subs r3, r3, #25 + 8824 0010 1840 ands r0, r3 + 8825 0012 2828 cmp r0, #40 + 8826 0014 00D0 beq .LCB8461 + 8827 0016 B0E0 b .L496 @long jump + 8828 .LCB8461: +3871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8829 .loc 1 3871 5 is_stmt 1 view .LVU2833 +3871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8830 .loc 1 3871 8 is_stmt 0 view .LVU2834 + 8831 0018 0029 cmp r1, #0 + 8832 001a 4DD0 beq .L487 +3871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8833 .loc 1 3871 25 discriminator 1 view .LVU2835 + 8834 001c 002A cmp r2, #0 + 8835 001e 4BD0 beq .L487 +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8836 .loc 1 3878 5 is_stmt 1 view .LVU2836 +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8837 .loc 1 3878 5 view .LVU2837 + 8838 0020 4023 movs r3, #64 + 8839 0022 E35C ldrb r3, [r4, r3] + 8840 0024 012B cmp r3, #1 + 8841 0026 00D1 bne .LCB8472 + 8842 0028 AAE0 b .L497 @long jump + 8843 .LCB8472: +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8844 .loc 1 3878 5 discriminator 2 view .LVU2838 + 8845 002a 4023 movs r3, #64 + 8846 002c 0122 movs r2, #1 + ARM GAS /tmp/ccth6daj.s page 322 + + + 8847 .LVL630: +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8848 .loc 1 3878 5 is_stmt 0 discriminator 2 view .LVU2839 + 8849 002e E254 strb r2, [r4, r3] +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8850 .loc 1 3878 5 is_stmt 1 discriminator 2 view .LVU2840 +3881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8851 .loc 1 3881 5 discriminator 2 view .LVU2841 + 8852 0030 5449 ldr r1, .L501 + 8853 .LVL631: +3881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8854 .loc 1 3881 5 is_stmt 0 discriminator 2 view .LVU2842 + 8855 0032 2000 movs r0, r4 + 8856 0034 FFF7FEFF bl I2C_Disable_IRQ + 8857 .LVL632: +3885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8858 .loc 1 3885 5 is_stmt 1 discriminator 2 view .LVU2843 +3885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8859 .loc 1 3885 13 is_stmt 0 discriminator 2 view .LVU2844 + 8860 0038 4123 movs r3, #65 + 8861 003a E35C ldrb r3, [r4, r3] +3885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8862 .loc 1 3885 8 discriminator 2 view .LVU2845 + 8863 003c 2A2B cmp r3, #42 + 8864 003e 40D0 beq .L499 +3910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8865 .loc 1 3910 10 is_stmt 1 view .LVU2846 +3910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8866 .loc 1 3910 18 is_stmt 0 view .LVU2847 + 8867 0040 4123 movs r3, #65 + 8868 0042 E35C ldrb r3, [r4, r3] +3910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8869 .loc 1 3910 13 view .LVU2848 + 8870 0044 292B cmp r3, #41 + 8871 0046 57D0 beq .L500 + 8872 .L490: +3935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8873 .loc 1 3935 5 is_stmt 1 view .LVU2849 +3937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8874 .loc 1 3937 5 view .LVU2850 +3937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 8875 .loc 1 3937 21 is_stmt 0 view .LVU2851 + 8876 0048 4123 movs r3, #65 + 8877 004a 2922 movs r2, #41 + 8878 004c E254 strb r2, [r4, r3] +3938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8879 .loc 1 3938 5 is_stmt 1 view .LVU2852 +3938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 8880 .loc 1 3938 21 is_stmt 0 view .LVU2853 + 8881 004e 0133 adds r3, r3, #1 + 8882 0050 093A subs r2, r2, #9 + 8883 0052 E254 strb r2, [r4, r3] +3939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8884 .loc 1 3939 5 is_stmt 1 view .LVU2854 +3939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8885 .loc 1 3939 21 is_stmt 0 view .LVU2855 + 8886 0054 0023 movs r3, #0 + ARM GAS /tmp/ccth6daj.s page 323 + + + 8887 0056 6364 str r3, [r4, #68] +3942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8888 .loc 1 3942 5 is_stmt 1 view .LVU2856 +3942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8889 .loc 1 3942 9 is_stmt 0 view .LVU2857 + 8890 0058 2268 ldr r2, [r4] +3942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8891 .loc 1 3942 25 view .LVU2858 + 8892 005a 5368 ldr r3, [r2, #4] + 8893 005c 4A49 ldr r1, .L501+4 + 8894 005e 0B40 ands r3, r1 + 8895 0060 5360 str r3, [r2, #4] +3945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8896 .loc 1 3945 5 is_stmt 1 view .LVU2859 +3945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 8897 .loc 1 3945 23 is_stmt 0 view .LVU2860 + 8898 0062 6762 str r7, [r4, #36] +3946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8899 .loc 1 3946 5 is_stmt 1 view .LVU2861 +3946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8900 .loc 1 3946 23 is_stmt 0 view .LVU2862 + 8901 0064 6585 strh r5, [r4, #42] +3947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8902 .loc 1 3947 5 is_stmt 1 view .LVU2863 +3947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8903 .loc 1 3947 29 is_stmt 0 view .LVU2864 + 8904 0066 638D ldrh r3, [r4, #42] +3947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8905 .loc 1 3947 23 view .LVU2865 + 8906 0068 2385 strh r3, [r4, #40] +3948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8907 .loc 1 3948 5 is_stmt 1 view .LVU2866 +3948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8908 .loc 1 3948 23 is_stmt 0 view .LVU2867 + 8909 006a E662 str r6, [r4, #44] +3949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8910 .loc 1 3949 5 is_stmt 1 view .LVU2868 +3949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8911 .loc 1 3949 23 is_stmt 0 view .LVU2869 + 8912 006c 474B ldr r3, .L501+8 + 8913 006e 6363 str r3, [r4, #52] +3951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8914 .loc 1 3951 5 is_stmt 1 view .LVU2870 +3951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8915 .loc 1 3951 13 is_stmt 0 view .LVU2871 + 8916 0070 A36B ldr r3, [r4, #56] +3951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8917 .loc 1 3951 8 view .LVU2872 + 8918 0072 002B cmp r3, #0 + 8919 0074 56D0 beq .L491 +3954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8920 .loc 1 3954 7 is_stmt 1 view .LVU2873 +3954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8921 .loc 1 3954 38 is_stmt 0 view .LVU2874 + 8922 0076 464A ldr r2, .L501+12 + 8923 0078 DA62 str r2, [r3, #44] +3957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 324 + + + 8924 .loc 1 3957 7 is_stmt 1 view .LVU2875 +3957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8925 .loc 1 3957 11 is_stmt 0 view .LVU2876 + 8926 007a A36B ldr r3, [r4, #56] +3957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8927 .loc 1 3957 39 view .LVU2877 + 8928 007c 454A ldr r2, .L501+16 + 8929 007e 5A63 str r2, [r3, #52] +3960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8930 .loc 1 3960 7 is_stmt 1 view .LVU2878 +3960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8931 .loc 1 3960 11 is_stmt 0 view .LVU2879 + 8932 0080 A26B ldr r2, [r4, #56] +3960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 8933 .loc 1 3960 42 view .LVU2880 + 8934 0082 0023 movs r3, #0 + 8935 0084 1363 str r3, [r2, #48] +3961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8936 .loc 1 3961 7 is_stmt 1 view .LVU2881 +3961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8937 .loc 1 3961 11 is_stmt 0 view .LVU2882 + 8938 0086 A26B ldr r2, [r4, #56] +3961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8939 .loc 1 3961 39 view .LVU2883 + 8940 0088 9363 str r3, [r2, #56] +3964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8941 .loc 1 3964 7 is_stmt 1 view .LVU2884 +3964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8942 .loc 1 3964 81 is_stmt 0 view .LVU2885 + 8943 008a 2268 ldr r2, [r4] + 8944 008c 2832 adds r2, r2, #40 +3965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8945 .loc 1 3965 44 view .LVU2886 + 8946 008e 238D ldrh r3, [r4, #40] +3964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize); + 8947 .loc 1 3964 23 view .LVU2887 + 8948 0090 3900 movs r1, r7 + 8949 0092 A06B ldr r0, [r4, #56] + 8950 0094 FFF7FEFF bl HAL_DMA_Start_IT + 8951 .LVL633: + 8952 0098 051E subs r5, r0, #0 + 8953 .LVL634: +3982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8954 .loc 1 3982 5 is_stmt 1 view .LVU2888 +3982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 8955 .loc 1 3982 8 is_stmt 0 view .LVU2889 + 8956 009a 51D0 beq .L492 +3993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8957 .loc 1 3993 7 is_stmt 1 view .LVU2890 +3993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8958 .loc 1 3993 23 is_stmt 0 view .LVU2891 + 8959 009c 4123 movs r3, #65 + 8960 009e 2822 movs r2, #40 + 8961 00a0 E254 strb r2, [r4, r3] +3994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8962 .loc 1 3994 7 is_stmt 1 view .LVU2892 +3994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 325 + + + 8963 .loc 1 3994 23 is_stmt 0 view .LVU2893 + 8964 00a2 0022 movs r2, #0 + 8965 00a4 0133 adds r3, r3, #1 + 8966 00a6 E254 strb r2, [r4, r3] +3997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8967 .loc 1 3997 7 is_stmt 1 view .LVU2894 +3997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8968 .loc 1 3997 23 is_stmt 0 view .LVU2895 + 8969 00a8 636C ldr r3, [r4, #68] + 8970 00aa 1021 movs r1, #16 + 8971 00ac 0B43 orrs r3, r1 + 8972 00ae 6364 str r3, [r4, #68] +4000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8973 .loc 1 4000 7 is_stmt 1 view .LVU2896 +4000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8974 .loc 1 4000 7 view .LVU2897 + 8975 00b0 4023 movs r3, #64 + 8976 00b2 E254 strb r2, [r4, r3] +4000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8977 .loc 1 4000 7 view .LVU2898 +4002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8978 .loc 1 4002 7 view .LVU2899 +4002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8979 .loc 1 4002 14 is_stmt 0 view .LVU2900 + 8980 00b4 0125 movs r5, #1 + 8981 00b6 61E0 b .L486 + 8982 .LVL635: + 8983 .L487: +3873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 8984 .loc 1 3873 7 is_stmt 1 view .LVU2901 +3873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 8985 .loc 1 3873 23 is_stmt 0 view .LVU2902 + 8986 00b8 8023 movs r3, #128 + 8987 00ba 9B00 lsls r3, r3, #2 + 8988 00bc 6364 str r3, [r4, #68] +3874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8989 .loc 1 3874 7 is_stmt 1 view .LVU2903 +3874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 8990 .loc 1 3874 15 is_stmt 0 view .LVU2904 + 8991 00be 0125 movs r5, #1 + 8992 00c0 5CE0 b .L486 + 8993 .LVL636: + 8994 .L499: +3888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 8995 .loc 1 3888 7 is_stmt 1 view .LVU2905 + 8996 00c2 0221 movs r1, #2 + 8997 00c4 2000 movs r0, r4 + 8998 00c6 FFF7FEFF bl I2C_Disable_IRQ + 8999 .LVL637: +3890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9000 .loc 1 3890 7 view .LVU2906 +3890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9001 .loc 1 3890 16 is_stmt 0 view .LVU2907 + 9002 00ca 2368 ldr r3, [r4] +3890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9003 .loc 1 3890 26 view .LVU2908 + 9004 00cc 1A68 ldr r2, [r3] + ARM GAS /tmp/ccth6daj.s page 326 + + +3890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9005 .loc 1 3890 10 view .LVU2909 + 9006 00ce 1204 lsls r2, r2, #16 + 9007 00d0 BAD5 bpl .L490 +3893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9008 .loc 1 3893 9 is_stmt 1 view .LVU2910 +3893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9009 .loc 1 3893 12 is_stmt 0 view .LVU2911 + 9010 00d2 E26B ldr r2, [r4, #60] + 9011 00d4 002A cmp r2, #0 + 9012 00d6 B7D0 beq .L490 +3895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9013 .loc 1 3895 11 is_stmt 1 view .LVU2912 +3895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9014 .loc 1 3895 31 is_stmt 0 view .LVU2913 + 9015 00d8 1A68 ldr r2, [r3] + 9016 00da 2B49 ldr r1, .L501+4 + 9017 00dc 0A40 ands r2, r1 + 9018 00de 1A60 str r2, [r3] +3899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9019 .loc 1 3899 11 is_stmt 1 view .LVU2914 +3899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9020 .loc 1 3899 15 is_stmt 0 view .LVU2915 + 9021 00e0 E36B ldr r3, [r4, #60] +3899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9022 .loc 1 3899 43 view .LVU2916 + 9023 00e2 2D4A ldr r2, .L501+20 + 9024 00e4 9A63 str r2, [r3, #56] +3902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9025 .loc 1 3902 11 is_stmt 1 view .LVU2917 +3902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9026 .loc 1 3902 15 is_stmt 0 view .LVU2918 + 9027 00e6 E06B ldr r0, [r4, #60] + 9028 00e8 FFF7FEFF bl HAL_DMA_Abort_IT + 9029 .LVL638: +3902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9030 .loc 1 3902 14 view .LVU2919 + 9031 00ec 0028 cmp r0, #0 + 9032 00ee ABD0 beq .L490 +3905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9033 .loc 1 3905 13 is_stmt 1 view .LVU2920 +3905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9034 .loc 1 3905 17 is_stmt 0 view .LVU2921 + 9035 00f0 E06B ldr r0, [r4, #60] +3905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9036 .loc 1 3905 25 view .LVU2922 + 9037 00f2 836B ldr r3, [r0, #56] +3905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9038 .loc 1 3905 13 view .LVU2923 + 9039 00f4 9847 blx r3 + 9040 .LVL639: + 9041 00f6 A7E7 b .L490 + 9042 .L500: +3912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9043 .loc 1 3912 7 is_stmt 1 view .LVU2924 +3912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9044 .loc 1 3912 16 is_stmt 0 view .LVU2925 + ARM GAS /tmp/ccth6daj.s page 327 + + + 9045 00f8 2368 ldr r3, [r4] +3912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9046 .loc 1 3912 26 view .LVU2926 + 9047 00fa 1A68 ldr r2, [r3] +3912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9048 .loc 1 3912 10 view .LVU2927 + 9049 00fc 5204 lsls r2, r2, #17 + 9050 00fe A3D5 bpl .L490 +3914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9051 .loc 1 3914 9 is_stmt 1 view .LVU2928 +3914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9052 .loc 1 3914 29 is_stmt 0 view .LVU2929 + 9053 0100 1A68 ldr r2, [r3] + 9054 0102 2649 ldr r1, .L501+24 + 9055 0104 0A40 ands r2, r1 + 9056 0106 1A60 str r2, [r3] +3917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9057 .loc 1 3917 9 is_stmt 1 view .LVU2930 +3917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9058 .loc 1 3917 17 is_stmt 0 view .LVU2931 + 9059 0108 A36B ldr r3, [r4, #56] +3917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9060 .loc 1 3917 12 view .LVU2932 + 9061 010a 002B cmp r3, #0 + 9062 010c 9CD0 beq .L490 +3921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9063 .loc 1 3921 11 is_stmt 1 view .LVU2933 +3921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9064 .loc 1 3921 43 is_stmt 0 view .LVU2934 + 9065 010e 224A ldr r2, .L501+20 + 9066 0110 9A63 str r2, [r3, #56] +3924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9067 .loc 1 3924 11 is_stmt 1 view .LVU2935 +3924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9068 .loc 1 3924 15 is_stmt 0 view .LVU2936 + 9069 0112 A06B ldr r0, [r4, #56] + 9070 0114 FFF7FEFF bl HAL_DMA_Abort_IT + 9071 .LVL640: +3924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9072 .loc 1 3924 14 view .LVU2937 + 9073 0118 0028 cmp r0, #0 + 9074 011a 95D0 beq .L490 +3927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9075 .loc 1 3927 13 is_stmt 1 view .LVU2938 +3927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9076 .loc 1 3927 17 is_stmt 0 view .LVU2939 + 9077 011c A06B ldr r0, [r4, #56] +3927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9078 .loc 1 3927 25 view .LVU2940 + 9079 011e 836B ldr r3, [r0, #56] +3927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9080 .loc 1 3927 13 view .LVU2941 + 9081 0120 9847 blx r3 + 9082 .LVL641: + 9083 0122 91E7 b .L490 + 9084 .L491: +3970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + ARM GAS /tmp/ccth6daj.s page 328 + + + 9085 .loc 1 3970 7 is_stmt 1 view .LVU2942 +3970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9086 .loc 1 3970 23 is_stmt 0 view .LVU2943 + 9087 0124 4123 movs r3, #65 + 9088 0126 2822 movs r2, #40 + 9089 0128 E254 strb r2, [r4, r3] +3971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9090 .loc 1 3971 7 is_stmt 1 view .LVU2944 +3971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9091 .loc 1 3971 23 is_stmt 0 view .LVU2945 + 9092 012a 0022 movs r2, #0 + 9093 012c 0133 adds r3, r3, #1 + 9094 012e E254 strb r2, [r4, r3] +3974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9095 .loc 1 3974 7 is_stmt 1 view .LVU2946 +3974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9096 .loc 1 3974 23 is_stmt 0 view .LVU2947 + 9097 0130 636C ldr r3, [r4, #68] + 9098 0132 8021 movs r1, #128 + 9099 0134 0B43 orrs r3, r1 + 9100 0136 6364 str r3, [r4, #68] +3977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9101 .loc 1 3977 7 is_stmt 1 view .LVU2948 +3977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9102 .loc 1 3977 7 view .LVU2949 + 9103 0138 4023 movs r3, #64 + 9104 013a E254 strb r2, [r4, r3] +3977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9105 .loc 1 3977 7 view .LVU2950 +3979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9106 .loc 1 3979 7 view .LVU2951 +3979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9107 .loc 1 3979 14 is_stmt 0 view .LVU2952 + 9108 013c 0125 movs r5, #1 + 9109 013e 1DE0 b .L486 + 9110 .LVL642: + 9111 .L492: +3985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9112 .loc 1 3985 7 is_stmt 1 view .LVU2953 +3985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9113 .loc 1 3985 23 is_stmt 0 view .LVU2954 + 9114 0140 638D ldrh r3, [r4, #42] +3985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9115 .loc 1 3985 30 view .LVU2955 + 9116 0142 228D ldrh r2, [r4, #40] +3985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9117 .loc 1 3985 23 view .LVU2956 + 9118 0144 9B1A subs r3, r3, r2 + 9119 0146 9BB2 uxth r3, r3 + 9120 0148 6385 strh r3, [r4, #42] +3988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9121 .loc 1 3988 7 is_stmt 1 view .LVU2957 +3988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9122 .loc 1 3988 22 is_stmt 0 view .LVU2958 + 9123 014a 0023 movs r3, #0 + 9124 014c 2385 strh r3, [r4, #40] +4005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 329 + + + 9125 .loc 1 4005 5 is_stmt 1 view .LVU2959 +4005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9126 .loc 1 4005 9 is_stmt 0 view .LVU2960 + 9127 014e 2368 ldr r3, [r4] + 9128 0150 9A69 ldr r2, [r3, #24] +4005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9129 .loc 1 4005 8 view .LVU2961 + 9130 0152 D203 lsls r2, r2, #15 + 9131 0154 0ED4 bmi .L494 + 9132 .L495: +4013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9133 .loc 1 4013 5 is_stmt 1 view .LVU2962 +4013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9134 .loc 1 4013 5 view .LVU2963 + 9135 0156 4023 movs r3, #64 + 9136 0158 0022 movs r2, #0 + 9137 015a E254 strb r2, [r4, r3] +4013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9138 .loc 1 4013 5 view .LVU2964 +4019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9139 .loc 1 4019 5 view .LVU2965 + 9140 015c 8021 movs r1, #128 + 9141 015e 0902 lsls r1, r1, #8 + 9142 0160 2000 movs r0, r4 + 9143 .LVL643: +4019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9144 .loc 1 4019 5 is_stmt 0 view .LVU2966 + 9145 0162 FFF7FEFF bl I2C_Enable_IRQ + 9146 .LVL644: +4022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9147 .loc 1 4022 5 is_stmt 1 view .LVU2967 +4022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9148 .loc 1 4022 9 is_stmt 0 view .LVU2968 + 9149 0166 2268 ldr r2, [r4] +4022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9150 .loc 1 4022 25 view .LVU2969 + 9151 0168 1168 ldr r1, [r2] + 9152 016a 8023 movs r3, #128 + 9153 016c DB01 lsls r3, r3, #7 + 9154 016e 0B43 orrs r3, r1 + 9155 0170 1360 str r3, [r2] +4024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9156 .loc 1 4024 5 is_stmt 1 view .LVU2970 +4024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9157 .loc 1 4024 12 is_stmt 0 view .LVU2971 + 9158 0172 03E0 b .L486 + 9159 .LVL645: + 9160 .L494: +4009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9161 .loc 1 4009 7 is_stmt 1 view .LVU2972 + 9162 0174 0822 movs r2, #8 + 9163 0176 DA61 str r2, [r3, #28] + 9164 0178 EDE7 b .L495 + 9165 .LVL646: + 9166 .L496: +4028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9167 .loc 1 4028 12 is_stmt 0 view .LVU2973 + ARM GAS /tmp/ccth6daj.s page 330 + + + 9168 017a 0125 movs r5, #1 + 9169 .LVL647: + 9170 .L486: +4030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9171 .loc 1 4030 1 view .LVU2974 + 9172 017c 2800 movs r0, r5 + 9173 @ sp needed + 9174 .LVL648: + 9175 .LVL649: + 9176 .LVL650: +4030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9177 .loc 1 4030 1 view .LVU2975 + 9178 017e F8BD pop {r3, r4, r5, r6, r7, pc} + 9179 .LVL651: + 9180 .L497: +3878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9181 .loc 1 3878 5 view .LVU2976 + 9182 0180 0225 movs r5, #2 + 9183 0182 FBE7 b .L486 + 9184 .L502: + 9185 .align 2 + 9186 .L501: + 9187 0184 01800000 .word 32769 + 9188 0188 FF7FFFFF .word -32769 + 9189 018c 00000000 .word I2C_Slave_ISR_DMA + 9190 0190 00000000 .word I2C_DMASlaveTransmitCplt + 9191 0194 00000000 .word I2C_DMAError + 9192 0198 00000000 .word I2C_DMAAbort + 9193 019c FFBFFFFF .word -16385 + 9194 .cfi_endproc + 9195 .LFE325: + 9197 .section .text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits + 9198 .align 1 + 9199 .global HAL_I2C_Slave_Seq_Receive_IT + 9200 .syntax unified + 9201 .code 16 + 9202 .thumb_func + 9203 .fpu softvfp + 9205 HAL_I2C_Slave_Seq_Receive_IT: + 9206 .LVL652: + 9207 .LFB326: +4044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 9208 .loc 1 4044 1 is_stmt 1 view -0 + 9209 .cfi_startproc + 9210 @ args = 0, pretend = 0, frame = 0 + 9211 @ frame_needed = 0, uses_anonymous_args = 0 +4044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Check the parameters */ + 9212 .loc 1 4044 1 is_stmt 0 view .LVU2978 + 9213 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9214 .LCFI65: + 9215 .cfi_def_cfa_offset 24 + 9216 .cfi_offset 3, -24 + 9217 .cfi_offset 4, -20 + 9218 .cfi_offset 5, -16 + 9219 .cfi_offset 6, -12 + 9220 .cfi_offset 7, -8 + 9221 .cfi_offset 14, -4 + ARM GAS /tmp/ccth6daj.s page 331 + + + 9222 0002 0400 movs r4, r0 + 9223 0004 0D00 movs r5, r1 + 9224 0006 1600 movs r6, r2 + 9225 0008 1F00 movs r7, r3 +4046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9226 .loc 1 4046 3 is_stmt 1 view .LVU2979 +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9227 .loc 1 4048 3 view .LVU2980 +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9228 .loc 1 4048 22 is_stmt 0 view .LVU2981 + 9229 000a 4123 movs r3, #65 + 9230 .LVL653: +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9231 .loc 1 4048 22 view .LVU2982 + 9232 000c C35C ldrb r3, [r0, r3] +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9233 .loc 1 4048 6 view .LVU2983 + 9234 000e 2822 movs r2, #40 + 9235 .LVL654: +4048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9236 .loc 1 4048 6 view .LVU2984 + 9237 0010 1340 ands r3, r2 + 9238 0012 282B cmp r3, #40 + 9239 0014 53D1 bne .L509 +4050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9240 .loc 1 4050 5 is_stmt 1 view .LVU2985 +4050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9241 .loc 1 4050 8 is_stmt 0 view .LVU2986 + 9242 0016 0029 cmp r1, #0 + 9243 0018 01D0 beq .L505 +4050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9244 .loc 1 4050 25 discriminator 1 view .LVU2987 + 9245 001a 002E cmp r6, #0 + 9246 001c 04D1 bne .L506 + 9247 .L505: +4052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 9248 .loc 1 4052 7 is_stmt 1 view .LVU2988 +4052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 9249 .loc 1 4052 23 is_stmt 0 view .LVU2989 + 9250 001e 8023 movs r3, #128 + 9251 0020 9B00 lsls r3, r3, #2 + 9252 0022 6364 str r3, [r4, #68] +4053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9253 .loc 1 4053 7 is_stmt 1 view .LVU2990 +4053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9254 .loc 1 4053 15 is_stmt 0 view .LVU2991 + 9255 0024 0120 movs r0, #1 + 9256 .LVL655: +4053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9257 .loc 1 4053 15 view .LVU2992 + 9258 0026 4BE0 b .L504 + 9259 .LVL656: + 9260 .L506: +4057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9261 .loc 1 4057 5 is_stmt 1 view .LVU2993 + 9262 0028 2749 ldr r1, .L512 + 9263 .LVL657: + ARM GAS /tmp/ccth6daj.s page 332 + + +4057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9264 .loc 1 4057 5 is_stmt 0 view .LVU2994 + 9265 002a FFF7FEFF bl I2C_Disable_IRQ + 9266 .LVL658: +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9267 .loc 1 4060 5 is_stmt 1 view .LVU2995 +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9268 .loc 1 4060 5 view .LVU2996 + 9269 002e 4023 movs r3, #64 + 9270 0030 E35C ldrb r3, [r4, r3] + 9271 0032 012B cmp r3, #1 + 9272 0034 45D0 beq .L510 +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9273 .loc 1 4060 5 discriminator 2 view .LVU2997 + 9274 0036 4023 movs r3, #64 + 9275 0038 0122 movs r2, #1 + 9276 003a E254 strb r2, [r4, r3] +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9277 .loc 1 4060 5 discriminator 2 view .LVU2998 +4064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9278 .loc 1 4064 5 discriminator 2 view .LVU2999 +4064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9279 .loc 1 4064 13 is_stmt 0 discriminator 2 view .LVU3000 + 9280 003c 0133 adds r3, r3, #1 + 9281 003e E35C ldrb r3, [r4, r3] +4064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9282 .loc 1 4064 8 discriminator 2 view .LVU3001 + 9283 0040 292B cmp r3, #41 + 9284 0042 22D0 beq .L511 + 9285 .L507: +4090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9286 .loc 1 4090 5 is_stmt 1 view .LVU3002 +4090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9287 .loc 1 4090 21 is_stmt 0 view .LVU3003 + 9288 0044 4123 movs r3, #65 + 9289 0046 2A22 movs r2, #42 + 9290 0048 E254 strb r2, [r4, r3] +4091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9291 .loc 1 4091 5 is_stmt 1 view .LVU3004 +4091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9292 .loc 1 4091 21 is_stmt 0 view .LVU3005 + 9293 004a 0133 adds r3, r3, #1 + 9294 004c 0A3A subs r2, r2, #10 + 9295 004e E254 strb r2, [r4, r3] +4092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9296 .loc 1 4092 5 is_stmt 1 view .LVU3006 +4092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9297 .loc 1 4092 21 is_stmt 0 view .LVU3007 + 9298 0050 0023 movs r3, #0 + 9299 0052 6364 str r3, [r4, #68] +4095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9300 .loc 1 4095 5 is_stmt 1 view .LVU3008 +4095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9301 .loc 1 4095 9 is_stmt 0 view .LVU3009 + 9302 0054 2268 ldr r2, [r4] +4095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9303 .loc 1 4095 25 view .LVU3010 + ARM GAS /tmp/ccth6daj.s page 333 + + + 9304 0056 5368 ldr r3, [r2, #4] + 9305 0058 1C49 ldr r1, .L512+4 + 9306 005a 0B40 ands r3, r1 + 9307 005c 5360 str r3, [r2, #4] +4098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 9308 .loc 1 4098 5 is_stmt 1 view .LVU3011 +4098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 9309 .loc 1 4098 23 is_stmt 0 view .LVU3012 + 9310 005e 6562 str r5, [r4, #36] +4099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9311 .loc 1 4099 5 is_stmt 1 view .LVU3013 +4099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9312 .loc 1 4099 23 is_stmt 0 view .LVU3014 + 9313 0060 6685 strh r6, [r4, #42] +4100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9314 .loc 1 4100 5 is_stmt 1 view .LVU3015 +4100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9315 .loc 1 4100 29 is_stmt 0 view .LVU3016 + 9316 0062 638D ldrh r3, [r4, #42] +4100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9317 .loc 1 4100 23 view .LVU3017 + 9318 0064 2385 strh r3, [r4, #40] +4101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9319 .loc 1 4101 5 is_stmt 1 view .LVU3018 +4101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9320 .loc 1 4101 23 is_stmt 0 view .LVU3019 + 9321 0066 E762 str r7, [r4, #44] +4102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9322 .loc 1 4102 5 is_stmt 1 view .LVU3020 +4102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9323 .loc 1 4102 23 is_stmt 0 view .LVU3021 + 9324 0068 194B ldr r3, .L512+8 + 9325 006a 6363 str r3, [r4, #52] +4104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9326 .loc 1 4104 5 is_stmt 1 view .LVU3022 +4104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9327 .loc 1 4104 9 is_stmt 0 view .LVU3023 + 9328 006c 2368 ldr r3, [r4] + 9329 006e 9A69 ldr r2, [r3, #24] +4104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9330 .loc 1 4104 8 view .LVU3024 + 9331 0070 D203 lsls r2, r2, #15 + 9332 0072 01D4 bmi .L508 +4108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9333 .loc 1 4108 7 is_stmt 1 view .LVU3025 + 9334 0074 0822 movs r2, #8 + 9335 0076 DA61 str r2, [r3, #28] + 9336 .L508: +4112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9337 .loc 1 4112 5 view .LVU3026 +4112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9338 .loc 1 4112 5 view .LVU3027 + 9339 0078 4023 movs r3, #64 + 9340 007a 0022 movs r2, #0 + 9341 007c E254 strb r2, [r4, r3] +4112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9342 .loc 1 4112 5 view .LVU3028 + ARM GAS /tmp/ccth6daj.s page 334 + + +4118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9343 .loc 1 4118 5 view .LVU3029 + 9344 007e 1249 ldr r1, .L512 + 9345 0080 2000 movs r0, r4 + 9346 0082 FFF7FEFF bl I2C_Enable_IRQ + 9347 .LVL659: +4120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9348 .loc 1 4120 5 view .LVU3030 +4120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9349 .loc 1 4120 12 is_stmt 0 view .LVU3031 + 9350 0086 0020 movs r0, #0 + 9351 0088 1AE0 b .L504 + 9352 .L511: +4067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9353 .loc 1 4067 7 is_stmt 1 view .LVU3032 + 9354 008a 0121 movs r1, #1 + 9355 008c 2000 movs r0, r4 + 9356 008e FFF7FEFF bl I2C_Disable_IRQ + 9357 .LVL660: +4069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9358 .loc 1 4069 7 view .LVU3033 +4069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9359 .loc 1 4069 16 is_stmt 0 view .LVU3034 + 9360 0092 2368 ldr r3, [r4] +4069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9361 .loc 1 4069 26 view .LVU3035 + 9362 0094 1A68 ldr r2, [r3] +4069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9363 .loc 1 4069 10 view .LVU3036 + 9364 0096 5204 lsls r2, r2, #17 + 9365 0098 D4D5 bpl .L507 +4071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9366 .loc 1 4071 9 is_stmt 1 view .LVU3037 +4071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9367 .loc 1 4071 29 is_stmt 0 view .LVU3038 + 9368 009a 1A68 ldr r2, [r3] + 9369 009c 0D49 ldr r1, .L512+12 + 9370 009e 0A40 ands r2, r1 + 9371 00a0 1A60 str r2, [r3] +4074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9372 .loc 1 4074 9 is_stmt 1 view .LVU3039 +4074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9373 .loc 1 4074 17 is_stmt 0 view .LVU3040 + 9374 00a2 A36B ldr r3, [r4, #56] +4074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9375 .loc 1 4074 12 view .LVU3041 + 9376 00a4 002B cmp r3, #0 + 9377 00a6 CDD0 beq .L507 +4078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9378 .loc 1 4078 11 is_stmt 1 view .LVU3042 +4078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9379 .loc 1 4078 43 is_stmt 0 view .LVU3043 + 9380 00a8 0B4A ldr r2, .L512+16 + 9381 00aa 9A63 str r2, [r3, #56] +4081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9382 .loc 1 4081 11 is_stmt 1 view .LVU3044 +4081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 335 + + + 9383 .loc 1 4081 15 is_stmt 0 view .LVU3045 + 9384 00ac A06B ldr r0, [r4, #56] + 9385 00ae FFF7FEFF bl HAL_DMA_Abort_IT + 9386 .LVL661: +4081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9387 .loc 1 4081 14 view .LVU3046 + 9388 00b2 0028 cmp r0, #0 + 9389 00b4 C6D0 beq .L507 +4084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9390 .loc 1 4084 13 is_stmt 1 view .LVU3047 +4084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9391 .loc 1 4084 17 is_stmt 0 view .LVU3048 + 9392 00b6 A06B ldr r0, [r4, #56] +4084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9393 .loc 1 4084 25 view .LVU3049 + 9394 00b8 836B ldr r3, [r0, #56] +4084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9395 .loc 1 4084 13 view .LVU3050 + 9396 00ba 9847 blx r3 + 9397 .LVL662: + 9398 00bc C2E7 b .L507 + 9399 .LVL663: + 9400 .L509: +4124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9401 .loc 1 4124 12 view .LVU3051 + 9402 00be 0120 movs r0, #1 + 9403 .LVL664: + 9404 .L504: +4126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9405 .loc 1 4126 1 view .LVU3052 + 9406 @ sp needed + 9407 .LVL665: + 9408 .LVL666: + 9409 .LVL667: +4126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9410 .loc 1 4126 1 view .LVU3053 + 9411 00c0 F8BD pop {r3, r4, r5, r6, r7, pc} + 9412 .LVL668: + 9413 .L510: +4060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9414 .loc 1 4060 5 view .LVU3054 + 9415 00c2 0220 movs r0, #2 + 9416 00c4 FCE7 b .L504 + 9417 .L513: + 9418 00c6 C046 .align 2 + 9419 .L512: + 9420 00c8 02800000 .word 32770 + 9421 00cc FF7FFFFF .word -32769 + 9422 00d0 00000000 .word I2C_Slave_ISR_IT + 9423 00d4 FFBFFFFF .word -16385 + 9424 00d8 00000000 .word I2C_DMAAbort + 9425 .cfi_endproc + 9426 .LFE326: + 9428 .section .text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits + 9429 .align 1 + 9430 .global HAL_I2C_Slave_Seq_Receive_DMA + 9431 .syntax unified + ARM GAS /tmp/ccth6daj.s page 336 + + + 9432 .code 16 + 9433 .thumb_func + 9434 .fpu softvfp + 9436 HAL_I2C_Slave_Seq_Receive_DMA: + 9437 .LVL669: + 9438 .LFB327: +4140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 9439 .loc 1 4140 1 is_stmt 1 view -0 + 9440 .cfi_startproc + 9441 @ args = 0, pretend = 0, frame = 0 + 9442 @ frame_needed = 0, uses_anonymous_args = 0 +4140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; + 9443 .loc 1 4140 1 is_stmt 0 view .LVU3056 + 9444 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 9445 .LCFI66: + 9446 .cfi_def_cfa_offset 24 + 9447 .cfi_offset 3, -24 + 9448 .cfi_offset 4, -20 + 9449 .cfi_offset 5, -16 + 9450 .cfi_offset 6, -12 + 9451 .cfi_offset 7, -8 + 9452 .cfi_offset 14, -4 + 9453 0002 0400 movs r4, r0 + 9454 0004 0F00 movs r7, r1 + 9455 0006 1500 movs r5, r2 + 9456 0008 1E00 movs r6, r3 +4141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9457 .loc 1 4141 3 is_stmt 1 view .LVU3057 +4144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9458 .loc 1 4144 3 view .LVU3058 +4146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9459 .loc 1 4146 3 view .LVU3059 +4146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9460 .loc 1 4146 22 is_stmt 0 view .LVU3060 + 9461 000a 4123 movs r3, #65 + 9462 .LVL670: +4146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9463 .loc 1 4146 22 view .LVU3061 + 9464 000c C05C ldrb r0, [r0, r3] + 9465 .LVL671: +4146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9466 .loc 1 4146 6 view .LVU3062 + 9467 000e 193B subs r3, r3, #25 + 9468 0010 1840 ands r0, r3 + 9469 0012 2828 cmp r0, #40 + 9470 0014 00D0 beq .LCB9055 + 9471 0016 AFE0 b .L525 @long jump + 9472 .LCB9055: +4148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9473 .loc 1 4148 5 is_stmt 1 view .LVU3063 +4148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9474 .loc 1 4148 8 is_stmt 0 view .LVU3064 + 9475 0018 0029 cmp r1, #0 + 9476 001a 01D0 beq .L516 +4148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9477 .loc 1 4148 25 discriminator 1 view .LVU3065 + 9478 001c 002A cmp r2, #0 + ARM GAS /tmp/ccth6daj.s page 337 + + + 9479 001e 04D1 bne .L517 + 9480 .L516: +4150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 9481 .loc 1 4150 7 is_stmt 1 view .LVU3066 +4150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return HAL_ERROR; + 9482 .loc 1 4150 23 is_stmt 0 view .LVU3067 + 9483 0020 8023 movs r3, #128 + 9484 0022 9B00 lsls r3, r3, #2 + 9485 0024 6364 str r3, [r4, #68] +4151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9486 .loc 1 4151 7 is_stmt 1 view .LVU3068 +4151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9487 .loc 1 4151 15 is_stmt 0 view .LVU3069 + 9488 0026 0125 movs r5, #1 + 9489 0028 A7E0 b .L515 + 9490 .L517: +4155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9491 .loc 1 4155 5 is_stmt 1 view .LVU3070 + 9492 002a 5649 ldr r1, .L530 + 9493 .LVL672: +4155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9494 .loc 1 4155 5 is_stmt 0 view .LVU3071 + 9495 002c 2000 movs r0, r4 + 9496 002e FFF7FEFF bl I2C_Disable_IRQ + 9497 .LVL673: +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9498 .loc 1 4158 5 is_stmt 1 view .LVU3072 +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9499 .loc 1 4158 5 view .LVU3073 + 9500 0032 4023 movs r3, #64 + 9501 0034 E35C ldrb r3, [r4, r3] + 9502 0036 012B cmp r3, #1 + 9503 0038 00D1 bne .LCB9084 + 9504 003a A0E0 b .L526 @long jump + 9505 .LCB9084: +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9506 .loc 1 4158 5 discriminator 2 view .LVU3074 + 9507 003c 4023 movs r3, #64 + 9508 003e 0122 movs r2, #1 + 9509 0040 E254 strb r2, [r4, r3] +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9510 .loc 1 4158 5 discriminator 2 view .LVU3075 +4162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9511 .loc 1 4162 5 discriminator 2 view .LVU3076 +4162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9512 .loc 1 4162 13 is_stmt 0 discriminator 2 view .LVU3077 + 9513 0042 0133 adds r3, r3, #1 + 9514 0044 E35C ldrb r3, [r4, r3] +4162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9515 .loc 1 4162 8 discriminator 2 view .LVU3078 + 9516 0046 292B cmp r3, #41 + 9517 0048 3BD0 beq .L528 +4187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9518 .loc 1 4187 10 is_stmt 1 view .LVU3079 +4187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9519 .loc 1 4187 18 is_stmt 0 view .LVU3080 + 9520 004a 4123 movs r3, #65 + ARM GAS /tmp/ccth6daj.s page 338 + + + 9521 004c E35C ldrb r3, [r4, r3] +4187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9522 .loc 1 4187 13 view .LVU3081 + 9523 004e 2A2B cmp r3, #42 + 9524 0050 52D0 beq .L529 + 9525 .L519: +4212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9526 .loc 1 4212 5 is_stmt 1 view .LVU3082 +4214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9527 .loc 1 4214 5 view .LVU3083 +4214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 9528 .loc 1 4214 21 is_stmt 0 view .LVU3084 + 9529 0052 4123 movs r3, #65 + 9530 0054 2A22 movs r2, #42 + 9531 0056 E254 strb r2, [r4, r3] +4215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9532 .loc 1 4215 5 is_stmt 1 view .LVU3085 +4215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 9533 .loc 1 4215 21 is_stmt 0 view .LVU3086 + 9534 0058 0133 adds r3, r3, #1 + 9535 005a 0A3A subs r2, r2, #10 + 9536 005c E254 strb r2, [r4, r3] +4216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9537 .loc 1 4216 5 is_stmt 1 view .LVU3087 +4216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9538 .loc 1 4216 21 is_stmt 0 view .LVU3088 + 9539 005e 0023 movs r3, #0 + 9540 0060 6364 str r3, [r4, #68] +4219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9541 .loc 1 4219 5 is_stmt 1 view .LVU3089 +4219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9542 .loc 1 4219 9 is_stmt 0 view .LVU3090 + 9543 0062 2268 ldr r2, [r4] +4219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9544 .loc 1 4219 25 view .LVU3091 + 9545 0064 5368 ldr r3, [r2, #4] + 9546 0066 4849 ldr r1, .L530+4 + 9547 0068 0B40 ands r3, r1 + 9548 006a 5360 str r3, [r2, #4] +4222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 9549 .loc 1 4222 5 is_stmt 1 view .LVU3092 +4222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = Size; + 9550 .loc 1 4222 23 is_stmt 0 view .LVU3093 + 9551 006c 6762 str r7, [r4, #36] +4223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9552 .loc 1 4223 5 is_stmt 1 view .LVU3094 +4223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9553 .loc 1 4223 23 is_stmt 0 view .LVU3095 + 9554 006e 6585 strh r5, [r4, #42] +4224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9555 .loc 1 4224 5 is_stmt 1 view .LVU3096 +4224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9556 .loc 1 4224 29 is_stmt 0 view .LVU3097 + 9557 0070 638D ldrh r3, [r4, #42] +4224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 9558 .loc 1 4224 23 view .LVU3098 + 9559 0072 2385 strh r3, [r4, #40] + ARM GAS /tmp/ccth6daj.s page 339 + + +4225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 9560 .loc 1 4225 5 is_stmt 1 view .LVU3099 +4225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 9561 .loc 1 4225 23 is_stmt 0 view .LVU3100 + 9562 0074 E662 str r6, [r4, #44] +4226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9563 .loc 1 4226 5 is_stmt 1 view .LVU3101 +4226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9564 .loc 1 4226 23 is_stmt 0 view .LVU3102 + 9565 0076 454B ldr r3, .L530+8 + 9566 0078 6363 str r3, [r4, #52] +4228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9567 .loc 1 4228 5 is_stmt 1 view .LVU3103 +4228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9568 .loc 1 4228 13 is_stmt 0 view .LVU3104 + 9569 007a E36B ldr r3, [r4, #60] +4228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9570 .loc 1 4228 8 view .LVU3105 + 9571 007c 002B cmp r3, #0 + 9572 007e 51D0 beq .L520 +4231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9573 .loc 1 4231 7 is_stmt 1 view .LVU3106 +4231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9574 .loc 1 4231 38 is_stmt 0 view .LVU3107 + 9575 0080 434A ldr r2, .L530+12 + 9576 0082 DA62 str r2, [r3, #44] +4234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9577 .loc 1 4234 7 is_stmt 1 view .LVU3108 +4234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9578 .loc 1 4234 11 is_stmt 0 view .LVU3109 + 9579 0084 E36B ldr r3, [r4, #60] +4234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9580 .loc 1 4234 39 view .LVU3110 + 9581 0086 434A ldr r2, .L530+16 + 9582 0088 5A63 str r2, [r3, #52] +4237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9583 .loc 1 4237 7 is_stmt 1 view .LVU3111 +4237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9584 .loc 1 4237 11 is_stmt 0 view .LVU3112 + 9585 008a E26B ldr r2, [r4, #60] +4237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 9586 .loc 1 4237 42 view .LVU3113 + 9587 008c 0023 movs r3, #0 + 9588 008e 1363 str r3, [r2, #48] +4238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9589 .loc 1 4238 7 is_stmt 1 view .LVU3114 +4238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9590 .loc 1 4238 11 is_stmt 0 view .LVU3115 + 9591 0090 E26B ldr r2, [r4, #60] +4238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9592 .loc 1 4238 39 view .LVU3116 + 9593 0092 9363 str r3, [r2, #56] +4241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9594 .loc 1 4241 7 is_stmt 1 view .LVU3117 +4241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9595 .loc 1 4241 64 is_stmt 0 view .LVU3118 + 9596 0094 2168 ldr r1, [r4] + ARM GAS /tmp/ccth6daj.s page 340 + + + 9597 0096 2431 adds r1, r1, #36 +4242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9598 .loc 1 4242 61 view .LVU3119 + 9599 0098 238D ldrh r3, [r4, #40] +4241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 9600 .loc 1 4241 23 view .LVU3120 + 9601 009a 3A00 movs r2, r7 + 9602 009c E06B ldr r0, [r4, #60] + 9603 009e FFF7FEFF bl HAL_DMA_Start_IT + 9604 .LVL674: + 9605 00a2 051E subs r5, r0, #0 + 9606 .LVL675: +4259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9607 .loc 1 4259 5 is_stmt 1 view .LVU3121 +4259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9608 .loc 1 4259 8 is_stmt 0 view .LVU3122 + 9609 00a4 4CD0 beq .L521 +4270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9610 .loc 1 4270 7 is_stmt 1 view .LVU3123 +4270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9611 .loc 1 4270 23 is_stmt 0 view .LVU3124 + 9612 00a6 4123 movs r3, #65 + 9613 00a8 2822 movs r2, #40 + 9614 00aa E254 strb r2, [r4, r3] +4271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9615 .loc 1 4271 7 is_stmt 1 view .LVU3125 +4271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9616 .loc 1 4271 23 is_stmt 0 view .LVU3126 + 9617 00ac 0022 movs r2, #0 + 9618 00ae 0133 adds r3, r3, #1 + 9619 00b0 E254 strb r2, [r4, r3] +4274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9620 .loc 1 4274 7 is_stmt 1 view .LVU3127 +4274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9621 .loc 1 4274 23 is_stmt 0 view .LVU3128 + 9622 00b2 636C ldr r3, [r4, #68] + 9623 00b4 1021 movs r1, #16 + 9624 00b6 0B43 orrs r3, r1 + 9625 00b8 6364 str r3, [r4, #68] +4277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9626 .loc 1 4277 7 is_stmt 1 view .LVU3129 +4277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9627 .loc 1 4277 7 view .LVU3130 + 9628 00ba 4023 movs r3, #64 + 9629 00bc E254 strb r2, [r4, r3] +4277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9630 .loc 1 4277 7 view .LVU3131 +4279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9631 .loc 1 4279 7 view .LVU3132 +4279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9632 .loc 1 4279 14 is_stmt 0 view .LVU3133 + 9633 00be 0125 movs r5, #1 + 9634 00c0 5BE0 b .L515 + 9635 .LVL676: + 9636 .L528: +4165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9637 .loc 1 4165 7 is_stmt 1 view .LVU3134 + ARM GAS /tmp/ccth6daj.s page 341 + + + 9638 00c2 0121 movs r1, #1 + 9639 00c4 2000 movs r0, r4 + 9640 00c6 FFF7FEFF bl I2C_Disable_IRQ + 9641 .LVL677: +4167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9642 .loc 1 4167 7 view .LVU3135 +4167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9643 .loc 1 4167 16 is_stmt 0 view .LVU3136 + 9644 00ca 2368 ldr r3, [r4] +4167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9645 .loc 1 4167 26 view .LVU3137 + 9646 00cc 1A68 ldr r2, [r3] +4167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9647 .loc 1 4167 10 view .LVU3138 + 9648 00ce 5204 lsls r2, r2, #17 + 9649 00d0 BFD5 bpl .L519 +4170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9650 .loc 1 4170 9 is_stmt 1 view .LVU3139 +4170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9651 .loc 1 4170 12 is_stmt 0 view .LVU3140 + 9652 00d2 A26B ldr r2, [r4, #56] + 9653 00d4 002A cmp r2, #0 + 9654 00d6 BCD0 beq .L519 +4172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9655 .loc 1 4172 11 is_stmt 1 view .LVU3141 +4172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9656 .loc 1 4172 31 is_stmt 0 view .LVU3142 + 9657 00d8 1A68 ldr r2, [r3] + 9658 00da 2F49 ldr r1, .L530+20 + 9659 00dc 0A40 ands r2, r1 + 9660 00de 1A60 str r2, [r3] +4176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9661 .loc 1 4176 11 is_stmt 1 view .LVU3143 +4176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9662 .loc 1 4176 15 is_stmt 0 view .LVU3144 + 9663 00e0 A36B ldr r3, [r4, #56] +4176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9664 .loc 1 4176 43 view .LVU3145 + 9665 00e2 2E4A ldr r2, .L530+24 + 9666 00e4 9A63 str r2, [r3, #56] +4179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9667 .loc 1 4179 11 is_stmt 1 view .LVU3146 +4179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9668 .loc 1 4179 15 is_stmt 0 view .LVU3147 + 9669 00e6 A06B ldr r0, [r4, #56] + 9670 00e8 FFF7FEFF bl HAL_DMA_Abort_IT + 9671 .LVL678: +4179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9672 .loc 1 4179 14 view .LVU3148 + 9673 00ec 0028 cmp r0, #0 + 9674 00ee B0D0 beq .L519 +4182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9675 .loc 1 4182 13 is_stmt 1 view .LVU3149 +4182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9676 .loc 1 4182 17 is_stmt 0 view .LVU3150 + 9677 00f0 A06B ldr r0, [r4, #56] +4182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 342 + + + 9678 .loc 1 4182 25 view .LVU3151 + 9679 00f2 836B ldr r3, [r0, #56] +4182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9680 .loc 1 4182 13 view .LVU3152 + 9681 00f4 9847 blx r3 + 9682 .LVL679: + 9683 00f6 ACE7 b .L519 + 9684 .L529: +4189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9685 .loc 1 4189 7 is_stmt 1 view .LVU3153 +4189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9686 .loc 1 4189 16 is_stmt 0 view .LVU3154 + 9687 00f8 2368 ldr r3, [r4] +4189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9688 .loc 1 4189 26 view .LVU3155 + 9689 00fa 1A68 ldr r2, [r3] +4189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9690 .loc 1 4189 10 view .LVU3156 + 9691 00fc 1204 lsls r2, r2, #16 + 9692 00fe A8D5 bpl .L519 +4191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9693 .loc 1 4191 9 is_stmt 1 view .LVU3157 +4191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9694 .loc 1 4191 29 is_stmt 0 view .LVU3158 + 9695 0100 1A68 ldr r2, [r3] + 9696 0102 2149 ldr r1, .L530+4 + 9697 0104 0A40 ands r2, r1 + 9698 0106 1A60 str r2, [r3] +4194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9699 .loc 1 4194 9 is_stmt 1 view .LVU3159 +4194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9700 .loc 1 4194 17 is_stmt 0 view .LVU3160 + 9701 0108 E36B ldr r3, [r4, #60] +4194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9702 .loc 1 4194 12 view .LVU3161 + 9703 010a 002B cmp r3, #0 + 9704 010c A1D0 beq .L519 +4198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9705 .loc 1 4198 11 is_stmt 1 view .LVU3162 +4198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9706 .loc 1 4198 43 is_stmt 0 view .LVU3163 + 9707 010e 234A ldr r2, .L530+24 + 9708 0110 9A63 str r2, [r3, #56] +4201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9709 .loc 1 4201 11 is_stmt 1 view .LVU3164 +4201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9710 .loc 1 4201 15 is_stmt 0 view .LVU3165 + 9711 0112 E06B ldr r0, [r4, #60] + 9712 0114 FFF7FEFF bl HAL_DMA_Abort_IT + 9713 .LVL680: +4201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9714 .loc 1 4201 14 view .LVU3166 + 9715 0118 0028 cmp r0, #0 + 9716 011a 9AD0 beq .L519 +4204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9717 .loc 1 4204 13 is_stmt 1 view .LVU3167 +4204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 343 + + + 9718 .loc 1 4204 17 is_stmt 0 view .LVU3168 + 9719 011c E06B ldr r0, [r4, #60] +4204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9720 .loc 1 4204 25 view .LVU3169 + 9721 011e 836B ldr r3, [r0, #56] +4204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9722 .loc 1 4204 13 view .LVU3170 + 9723 0120 9847 blx r3 + 9724 .LVL681: + 9725 0122 96E7 b .L519 + 9726 .L520: +4247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9727 .loc 1 4247 7 is_stmt 1 view .LVU3171 +4247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9728 .loc 1 4247 23 is_stmt 0 view .LVU3172 + 9729 0124 4123 movs r3, #65 + 9730 0126 2822 movs r2, #40 + 9731 0128 E254 strb r2, [r4, r3] +4248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9732 .loc 1 4248 7 is_stmt 1 view .LVU3173 +4248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9733 .loc 1 4248 23 is_stmt 0 view .LVU3174 + 9734 012a 0022 movs r2, #0 + 9735 012c 0133 adds r3, r3, #1 + 9736 012e E254 strb r2, [r4, r3] +4251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9737 .loc 1 4251 7 is_stmt 1 view .LVU3175 +4251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9738 .loc 1 4251 23 is_stmt 0 view .LVU3176 + 9739 0130 636C ldr r3, [r4, #68] + 9740 0132 8021 movs r1, #128 + 9741 0134 0B43 orrs r3, r1 + 9742 0136 6364 str r3, [r4, #68] +4254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9743 .loc 1 4254 7 is_stmt 1 view .LVU3177 +4254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9744 .loc 1 4254 7 view .LVU3178 + 9745 0138 4023 movs r3, #64 + 9746 013a E254 strb r2, [r4, r3] +4254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9747 .loc 1 4254 7 view .LVU3179 +4256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9748 .loc 1 4256 7 view .LVU3180 +4256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9749 .loc 1 4256 14 is_stmt 0 view .LVU3181 + 9750 013c 0125 movs r5, #1 + 9751 013e 1CE0 b .L515 + 9752 .LVL682: + 9753 .L521: +4262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9754 .loc 1 4262 7 is_stmt 1 view .LVU3182 +4262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9755 .loc 1 4262 23 is_stmt 0 view .LVU3183 + 9756 0140 638D ldrh r3, [r4, #42] +4262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9757 .loc 1 4262 30 view .LVU3184 + 9758 0142 228D ldrh r2, [r4, #40] + ARM GAS /tmp/ccth6daj.s page 344 + + +4262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9759 .loc 1 4262 23 view .LVU3185 + 9760 0144 9B1A subs r3, r3, r2 + 9761 0146 9BB2 uxth r3, r3 + 9762 0148 6385 strh r3, [r4, #42] +4265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9763 .loc 1 4265 7 is_stmt 1 view .LVU3186 +4265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9764 .loc 1 4265 22 is_stmt 0 view .LVU3187 + 9765 014a 0023 movs r3, #0 + 9766 014c 2385 strh r3, [r4, #40] +4282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9767 .loc 1 4282 5 is_stmt 1 view .LVU3188 +4282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9768 .loc 1 4282 9 is_stmt 0 view .LVU3189 + 9769 014e 2368 ldr r3, [r4] + 9770 0150 9A69 ldr r2, [r3, #24] +4282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9771 .loc 1 4282 8 view .LVU3190 + 9772 0152 D203 lsls r2, r2, #15 + 9773 0154 0DD5 bpl .L523 + 9774 .L524: +4290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9775 .loc 1 4290 5 is_stmt 1 view .LVU3191 +4290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9776 .loc 1 4290 5 view .LVU3192 + 9777 0156 4023 movs r3, #64 + 9778 0158 0022 movs r2, #0 + 9779 015a E254 strb r2, [r4, r3] +4290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9780 .loc 1 4290 5 view .LVU3193 +4296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9781 .loc 1 4296 5 view .LVU3194 + 9782 015c 0949 ldr r1, .L530 + 9783 015e 2000 movs r0, r4 + 9784 .LVL683: +4296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9785 .loc 1 4296 5 is_stmt 0 view .LVU3195 + 9786 0160 FFF7FEFF bl I2C_Enable_IRQ + 9787 .LVL684: +4299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9788 .loc 1 4299 5 is_stmt 1 view .LVU3196 +4299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9789 .loc 1 4299 9 is_stmt 0 view .LVU3197 + 9790 0164 2268 ldr r2, [r4] +4299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9791 .loc 1 4299 25 view .LVU3198 + 9792 0166 1168 ldr r1, [r2] + 9793 0168 8023 movs r3, #128 + 9794 016a 1B02 lsls r3, r3, #8 + 9795 016c 0B43 orrs r3, r1 + 9796 016e 1360 str r3, [r2] +4301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9797 .loc 1 4301 5 is_stmt 1 view .LVU3199 +4301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9798 .loc 1 4301 12 is_stmt 0 view .LVU3200 + 9799 0170 03E0 b .L515 + ARM GAS /tmp/ccth6daj.s page 345 + + + 9800 .LVL685: + 9801 .L523: +4286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9802 .loc 1 4286 7 is_stmt 1 view .LVU3201 + 9803 0172 0822 movs r2, #8 + 9804 0174 DA61 str r2, [r3, #28] + 9805 0176 EEE7 b .L524 + 9806 .LVL686: + 9807 .L525: +4305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9808 .loc 1 4305 12 is_stmt 0 view .LVU3202 + 9809 0178 0125 movs r5, #1 + 9810 .LVL687: + 9811 .L515: +4307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9812 .loc 1 4307 1 view .LVU3203 + 9813 017a 2800 movs r0, r5 + 9814 @ sp needed + 9815 .LVL688: + 9816 .LVL689: + 9817 .LVL690: +4307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9818 .loc 1 4307 1 view .LVU3204 + 9819 017c F8BD pop {r3, r4, r5, r6, r7, pc} + 9820 .LVL691: + 9821 .L526: +4158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9822 .loc 1 4158 5 view .LVU3205 + 9823 017e 0225 movs r5, #2 + 9824 0180 FBE7 b .L515 + 9825 .L531: + 9826 0182 C046 .align 2 + 9827 .L530: + 9828 0184 02800000 .word 32770 + 9829 0188 FF7FFFFF .word -32769 + 9830 018c 00000000 .word I2C_Slave_ISR_DMA + 9831 0190 00000000 .word I2C_DMASlaveReceiveCplt + 9832 0194 00000000 .word I2C_DMAError + 9833 0198 FFBFFFFF .word -16385 + 9834 019c 00000000 .word I2C_DMAAbort + 9835 .cfi_endproc + 9836 .LFE327: + 9838 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 9839 .align 1 + 9840 .global HAL_I2C_EnableListen_IT + 9841 .syntax unified + 9842 .code 16 + 9843 .thumb_func + 9844 .fpu softvfp + 9846 HAL_I2C_EnableListen_IT: + 9847 .LVL692: + 9848 .LFB328: +4316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9849 .loc 1 4316 1 is_stmt 1 view -0 + 9850 .cfi_startproc + 9851 @ args = 0, pretend = 0, frame = 0 + 9852 @ frame_needed = 0, uses_anonymous_args = 0 + ARM GAS /tmp/ccth6daj.s page 346 + + +4316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 9853 .loc 1 4316 1 is_stmt 0 view .LVU3207 + 9854 0000 10B5 push {r4, lr} + 9855 .LCFI67: + 9856 .cfi_def_cfa_offset 8 + 9857 .cfi_offset 4, -8 + 9858 .cfi_offset 14, -4 +4317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9859 .loc 1 4317 3 is_stmt 1 view .LVU3208 +4317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9860 .loc 1 4317 11 is_stmt 0 view .LVU3209 + 9861 0002 4123 movs r3, #65 + 9862 0004 C35C ldrb r3, [r0, r3] +4317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9863 .loc 1 4317 6 view .LVU3210 + 9864 0006 202B cmp r3, #32 + 9865 0008 01D0 beq .L535 +4329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9866 .loc 1 4329 12 view .LVU3211 + 9867 000a 0220 movs r0, #2 + 9868 .LVL693: + 9869 .L533: +4331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9870 .loc 1 4331 1 view .LVU3212 + 9871 @ sp needed + 9872 000c 10BD pop {r4, pc} + 9873 .LVL694: + 9874 .L535: +4319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9875 .loc 1 4319 5 is_stmt 1 view .LVU3213 +4319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 9876 .loc 1 4319 17 is_stmt 0 view .LVU3214 + 9877 000e 2133 adds r3, r3, #33 + 9878 0010 2822 movs r2, #40 + 9879 0012 C254 strb r2, [r0, r3] +4320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9880 .loc 1 4320 5 is_stmt 1 view .LVU3215 +4320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9881 .loc 1 4320 19 is_stmt 0 view .LVU3216 + 9882 0014 034B ldr r3, .L536 + 9883 0016 4363 str r3, [r0, #52] +4323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9884 .loc 1 4323 5 is_stmt 1 view .LVU3217 + 9885 0018 8021 movs r1, #128 + 9886 001a 0902 lsls r1, r1, #8 + 9887 001c FFF7FEFF bl I2C_Enable_IRQ + 9888 .LVL695: +4325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9889 .loc 1 4325 5 view .LVU3218 +4325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9890 .loc 1 4325 12 is_stmt 0 view .LVU3219 + 9891 0020 0020 movs r0, #0 + 9892 0022 F3E7 b .L533 + 9893 .L537: + 9894 .align 2 + 9895 .L536: + 9896 0024 00000000 .word I2C_Slave_ISR_IT + ARM GAS /tmp/ccth6daj.s page 347 + + + 9897 .cfi_endproc + 9898 .LFE328: + 9900 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 9901 .align 1 + 9902 .global HAL_I2C_DisableListen_IT + 9903 .syntax unified + 9904 .code 16 + 9905 .thumb_func + 9906 .fpu softvfp + 9908 HAL_I2C_DisableListen_IT: + 9909 .LVL696: + 9910 .LFB329: +4340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9911 .loc 1 4340 1 is_stmt 1 view -0 + 9912 .cfi_startproc + 9913 @ args = 0, pretend = 0, frame = 0 + 9914 @ frame_needed = 0, uses_anonymous_args = 0 +4340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ + 9915 .loc 1 4340 1 is_stmt 0 view .LVU3221 + 9916 0000 70B5 push {r4, r5, r6, lr} + 9917 .LCFI68: + 9918 .cfi_def_cfa_offset 16 + 9919 .cfi_offset 4, -16 + 9920 .cfi_offset 5, -12 + 9921 .cfi_offset 6, -8 + 9922 .cfi_offset 14, -4 +4342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9923 .loc 1 4342 3 is_stmt 1 view .LVU3222 +4345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9924 .loc 1 4345 3 view .LVU3223 +4345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9925 .loc 1 4345 11 is_stmt 0 view .LVU3224 + 9926 0002 4123 movs r3, #65 + 9927 0004 C35C ldrb r3, [r0, r3] +4345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 9928 .loc 1 4345 6 view .LVU3225 + 9929 0006 282B cmp r3, #40 + 9930 0008 01D0 beq .L541 +4360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9931 .loc 1 4360 12 view .LVU3226 + 9932 000a 0220 movs r0, #2 + 9933 .LVL697: + 9934 .L539: +4362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9935 .loc 1 4362 1 view .LVU3227 + 9936 @ sp needed + 9937 000c 70BD pop {r4, r5, r6, pc} + 9938 .LVL698: + 9939 .L541: +4347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9940 .loc 1 4347 5 is_stmt 1 view .LVU3228 +4347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 9941 .loc 1 4347 26 is_stmt 0 view .LVU3229 + 9942 000e 4124 movs r4, #65 + 9943 0010 025D ldrb r2, [r0, r4] + 9944 .LVL699: +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/ccth6daj.s page 348 + + + 9945 .loc 1 4348 5 is_stmt 1 view .LVU3230 +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9946 .loc 1 4348 48 is_stmt 0 view .LVU3231 + 9947 0012 4221 movs r1, #66 + 9948 0014 435C ldrb r3, [r0, r1] +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9949 .loc 1 4348 31 view .LVU3232 + 9950 0016 0325 movs r5, #3 + 9951 0018 2A40 ands r2, r5 + 9952 .LVL700: +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9953 .loc 1 4348 31 view .LVU3233 + 9954 001a 1343 orrs r3, r2 +4348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 9955 .loc 1 4348 25 view .LVU3234 + 9956 001c 0363 str r3, [r0, #48] +4349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9957 .loc 1 4349 5 is_stmt 1 view .LVU3235 +4349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 9958 .loc 1 4349 17 is_stmt 0 view .LVU3236 + 9959 001e 2023 movs r3, #32 + 9960 0020 0355 strb r3, [r0, r4] +4350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9961 .loc 1 4350 5 is_stmt 1 view .LVU3237 +4350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 9962 .loc 1 4350 16 is_stmt 0 view .LVU3238 + 9963 0022 0023 movs r3, #0 + 9964 0024 4354 strb r3, [r0, r1] +4351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9965 .loc 1 4351 5 is_stmt 1 view .LVU3239 +4351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9966 .loc 1 4351 19 is_stmt 0 view .LVU3240 + 9967 0026 4363 str r3, [r0, #52] +4354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 9968 .loc 1 4354 5 is_stmt 1 view .LVU3241 + 9969 0028 3E31 adds r1, r1, #62 + 9970 002a 0902 lsls r1, r1, #8 + 9971 002c FFF7FEFF bl I2C_Disable_IRQ + 9972 .LVL701: +4356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9973 .loc 1 4356 5 view .LVU3242 +4356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 9974 .loc 1 4356 12 is_stmt 0 view .LVU3243 + 9975 0030 0020 movs r0, #0 + 9976 0032 EBE7 b .L539 + 9977 .cfi_endproc + 9978 .LFE329: + 9980 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 9981 .align 1 + 9982 .global HAL_I2C_Master_Abort_IT + 9983 .syntax unified + 9984 .code 16 + 9985 .thumb_func + 9986 .fpu softvfp + 9988 HAL_I2C_Master_Abort_IT: + 9989 .LVL702: + 9990 .LFB330: + ARM GAS /tmp/ccth6daj.s page 349 + + +4373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9991 .loc 1 4373 1 is_stmt 1 view -0 + 9992 .cfi_startproc + 9993 @ args = 0, pretend = 0, frame = 0 + 9994 @ frame_needed = 0, uses_anonymous_args = 0 +4373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 9995 .loc 1 4373 1 is_stmt 0 view .LVU3245 + 9996 0000 30B5 push {r4, r5, lr} + 9997 .LCFI69: + 9998 .cfi_def_cfa_offset 12 + 9999 .cfi_offset 4, -12 + 10000 .cfi_offset 5, -8 + 10001 .cfi_offset 14, -4 + 10002 0002 83B0 sub sp, sp, #12 + 10003 .LCFI70: + 10004 .cfi_def_cfa_offset 24 + 10005 0004 0400 movs r4, r0 + 10006 0006 0D00 movs r5, r1 +4374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10007 .loc 1 4374 3 is_stmt 1 view .LVU3246 +4374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10008 .loc 1 4374 11 is_stmt 0 view .LVU3247 + 10009 0008 4223 movs r3, #66 + 10010 000a C35C ldrb r3, [r0, r3] +4374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10011 .loc 1 4374 6 view .LVU3248 + 10012 000c 102B cmp r3, #16 + 10013 000e 2FD1 bne .L546 +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10014 .loc 1 4377 5 is_stmt 1 view .LVU3249 +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10015 .loc 1 4377 5 view .LVU3250 + 10016 0010 3033 adds r3, r3, #48 + 10017 0012 C35C ldrb r3, [r0, r3] + 10018 0014 012B cmp r3, #1 + 10019 0016 2ED0 beq .L547 +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10020 .loc 1 4377 5 discriminator 2 view .LVU3251 + 10021 0018 4023 movs r3, #64 + 10022 001a 0122 movs r2, #1 + 10023 001c C254 strb r2, [r0, r3] +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10024 .loc 1 4377 5 discriminator 2 view .LVU3252 +4380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10025 .loc 1 4380 5 discriminator 2 view .LVU3253 +4380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10026 .loc 1 4380 13 is_stmt 0 discriminator 2 view .LVU3254 + 10027 001e 0133 adds r3, r3, #1 + 10028 0020 C35C ldrb r3, [r0, r3] +4380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10029 .loc 1 4380 8 discriminator 2 view .LVU3255 + 10030 0022 212B cmp r3, #33 + 10031 0024 18D0 beq .L548 +4385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10032 .loc 1 4385 10 is_stmt 1 view .LVU3256 +4385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10033 .loc 1 4385 18 is_stmt 0 view .LVU3257 + ARM GAS /tmp/ccth6daj.s page 350 + + + 10034 0026 4123 movs r3, #65 + 10035 0028 C35C ldrb r3, [r0, r3] +4385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10036 .loc 1 4385 13 view .LVU3258 + 10037 002a 222B cmp r3, #34 + 10038 002c 1AD0 beq .L549 + 10039 .LVL703: + 10040 .L545: +4393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10041 .loc 1 4393 5 is_stmt 1 view .LVU3259 +4396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10042 .loc 1 4396 5 view .LVU3260 +4396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10043 .loc 1 4396 17 is_stmt 0 view .LVU3261 + 10044 002e 4123 movs r3, #65 + 10045 0030 6022 movs r2, #96 + 10046 0032 E254 strb r2, [r4, r3] +4400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10047 .loc 1 4400 5 is_stmt 1 view .LVU3262 + 10048 0034 3F33 adds r3, r3, #63 + 10049 0036 114A ldr r2, .L550 + 10050 0038 0092 str r2, [sp] + 10051 003a 9B04 lsls r3, r3, #18 + 10052 003c 0122 movs r2, #1 + 10053 003e 2900 movs r1, r5 + 10054 0040 2000 movs r0, r4 + 10055 0042 FFF7FEFF bl I2C_TransferConfig + 10056 .LVL704: +4403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10057 .loc 1 4403 5 view .LVU3263 +4403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10058 .loc 1 4403 5 view .LVU3264 + 10059 0046 4023 movs r3, #64 + 10060 0048 0022 movs r2, #0 + 10061 004a E254 strb r2, [r4, r3] +4403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10062 .loc 1 4403 5 view .LVU3265 +4408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10063 .loc 1 4408 5 view .LVU3266 + 10064 004c 2021 movs r1, #32 + 10065 004e 2000 movs r0, r4 + 10066 0050 FFF7FEFF bl I2C_Enable_IRQ + 10067 .LVL705: +4410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10068 .loc 1 4410 5 view .LVU3267 +4410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10069 .loc 1 4410 12 is_stmt 0 view .LVU3268 + 10070 0054 0020 movs r0, #0 + 10071 0056 0CE0 b .L543 + 10072 .LVL706: + 10073 .L548: +4382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10074 .loc 1 4382 7 is_stmt 1 view .LVU3269 + 10075 0058 0121 movs r1, #1 + 10076 .LVL707: +4382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10077 .loc 1 4382 7 is_stmt 0 view .LVU3270 + ARM GAS /tmp/ccth6daj.s page 351 + + + 10078 005a FFF7FEFF bl I2C_Disable_IRQ + 10079 .LVL708: +4383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10080 .loc 1 4383 7 is_stmt 1 view .LVU3271 +4383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10081 .loc 1 4383 27 is_stmt 0 view .LVU3272 + 10082 005e 1123 movs r3, #17 + 10083 0060 2363 str r3, [r4, #48] + 10084 0062 E4E7 b .L545 + 10085 .LVL709: + 10086 .L549: +4387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10087 .loc 1 4387 7 is_stmt 1 view .LVU3273 + 10088 0064 0221 movs r1, #2 + 10089 .LVL710: +4387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10090 .loc 1 4387 7 is_stmt 0 view .LVU3274 + 10091 0066 FFF7FEFF bl I2C_Disable_IRQ + 10092 .LVL711: +4388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10093 .loc 1 4388 7 is_stmt 1 view .LVU3275 +4388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10094 .loc 1 4388 27 is_stmt 0 view .LVU3276 + 10095 006a 1223 movs r3, #18 + 10096 006c 2363 str r3, [r4, #48] + 10097 006e DEE7 b .L545 + 10098 .LVL712: + 10099 .L546: +4416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10100 .loc 1 4416 12 view .LVU3277 + 10101 0070 0120 movs r0, #1 + 10102 .LVL713: + 10103 .L543: +4418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10104 .loc 1 4418 1 view .LVU3278 + 10105 0072 03B0 add sp, sp, #12 + 10106 @ sp needed + 10107 .LVL714: +4418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10108 .loc 1 4418 1 view .LVU3279 + 10109 0074 30BD pop {r4, r5, pc} + 10110 .LVL715: + 10111 .L547: +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10112 .loc 1 4377 5 view .LVU3280 + 10113 0076 0220 movs r0, #2 + 10114 .LVL716: +4377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10115 .loc 1 4377 5 view .LVU3281 + 10116 0078 FBE7 b .L543 + 10117 .L551: + 10118 007a C046 .align 2 + 10119 .L550: + 10120 007c 00400080 .word -2147467264 + 10121 .cfi_endproc + 10122 .LFE330: + 10124 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + ARM GAS /tmp/ccth6daj.s page 352 + + + 10125 .align 1 + 10126 .global HAL_I2C_EV_IRQHandler + 10127 .syntax unified + 10128 .code 16 + 10129 .thumb_func + 10130 .fpu softvfp + 10132 HAL_I2C_EV_IRQHandler: + 10133 .LVL717: + 10134 .LFB331: +4435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 10135 .loc 1 4435 1 is_stmt 1 view -0 + 10136 .cfi_startproc + 10137 @ args = 0, pretend = 0, frame = 0 + 10138 @ frame_needed = 0, uses_anonymous_args = 0 +4435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ + 10139 .loc 1 4435 1 is_stmt 0 view .LVU3283 + 10140 0000 10B5 push {r4, lr} + 10141 .LCFI71: + 10142 .cfi_def_cfa_offset 8 + 10143 .cfi_offset 4, -8 + 10144 .cfi_offset 14, -4 +4437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10145 .loc 1 4437 3 is_stmt 1 view .LVU3284 +4437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10146 .loc 1 4437 24 is_stmt 0 view .LVU3285 + 10147 0002 0368 ldr r3, [r0] +4437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 10148 .loc 1 4437 12 view .LVU3286 + 10149 0004 9969 ldr r1, [r3, #24] + 10150 .LVL718: +4438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10151 .loc 1 4438 3 is_stmt 1 view .LVU3287 +4438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10152 .loc 1 4438 12 is_stmt 0 view .LVU3288 + 10153 0006 1A68 ldr r2, [r3] + 10154 .LVL719: +4441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10155 .loc 1 4441 3 is_stmt 1 view .LVU3289 +4441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10156 .loc 1 4441 11 is_stmt 0 view .LVU3290 + 10157 0008 436B ldr r3, [r0, #52] +4441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10158 .loc 1 4441 6 view .LVU3291 + 10159 000a 002B cmp r3, #0 + 10160 000c 00D0 beq .L552 +4443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10161 .loc 1 4443 5 is_stmt 1 view .LVU3292 + 10162 000e 9847 blx r3 + 10163 .LVL720: + 10164 .L552: +4445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10165 .loc 1 4445 1 is_stmt 0 view .LVU3293 + 10166 @ sp needed + 10167 0010 10BD pop {r4, pc} + 10168 .cfi_endproc + 10169 .LFE331: + 10171 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + ARM GAS /tmp/ccth6daj.s page 353 + + + 10172 .align 1 + 10173 .weak HAL_I2C_MasterTxCpltCallback + 10174 .syntax unified + 10175 .code 16 + 10176 .thumb_func + 10177 .fpu softvfp + 10179 HAL_I2C_MasterTxCpltCallback: + 10180 .LVL721: + 10181 .LFB333: +4506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10182 .loc 1 4506 1 is_stmt 1 view -0 + 10183 .cfi_startproc + 10184 @ args = 0, pretend = 0, frame = 0 + 10185 @ frame_needed = 0, uses_anonymous_args = 0 + 10186 @ link register save eliminated. +4508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10187 .loc 1 4508 3 view .LVU3295 +4513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10188 .loc 1 4513 1 is_stmt 0 view .LVU3296 + 10189 @ sp needed + 10190 0000 7047 bx lr + 10191 .cfi_endproc + 10192 .LFE333: + 10194 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 10195 .align 1 + 10196 .weak HAL_I2C_MasterRxCpltCallback + 10197 .syntax unified + 10198 .code 16 + 10199 .thumb_func + 10200 .fpu softvfp + 10202 HAL_I2C_MasterRxCpltCallback: + 10203 .LVL722: + 10204 .LFB334: +4522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10205 .loc 1 4522 1 is_stmt 1 view -0 + 10206 .cfi_startproc + 10207 @ args = 0, pretend = 0, frame = 0 + 10208 @ frame_needed = 0, uses_anonymous_args = 0 + 10209 @ link register save eliminated. +4524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10210 .loc 1 4524 3 view .LVU3298 +4529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10211 .loc 1 4529 1 is_stmt 0 view .LVU3299 + 10212 @ sp needed + 10213 0000 7047 bx lr + 10214 .cfi_endproc + 10215 .LFE334: + 10217 .section .text.I2C_ITMasterSeqCplt,"ax",%progbits + 10218 .align 1 + 10219 .syntax unified + 10220 .code 16 + 10221 .thumb_func + 10222 .fpu softvfp + 10224 I2C_ITMasterSeqCplt: + 10225 .LVL723: + 10226 .LFB353: +5507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset I2C handle mode */ + ARM GAS /tmp/ccth6daj.s page 354 + + + 10227 .loc 1 5507 1 is_stmt 1 view -0 + 10228 .cfi_startproc + 10229 @ args = 0, pretend = 0, frame = 0 + 10230 @ frame_needed = 0, uses_anonymous_args = 0 +5507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset I2C handle mode */ + 10231 .loc 1 5507 1 is_stmt 0 view .LVU3301 + 10232 0000 70B5 push {r4, r5, r6, lr} + 10233 .LCFI72: + 10234 .cfi_def_cfa_offset 16 + 10235 .cfi_offset 4, -16 + 10236 .cfi_offset 5, -12 + 10237 .cfi_offset 6, -8 + 10238 .cfi_offset 14, -4 + 10239 0002 0400 movs r4, r0 +5509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10240 .loc 1 5509 3 is_stmt 1 view .LVU3302 +5509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10241 .loc 1 5509 14 is_stmt 0 view .LVU3303 + 10242 0004 4223 movs r3, #66 + 10243 0006 0022 movs r2, #0 + 10244 0008 C254 strb r2, [r0, r3] +5513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10245 .loc 1 5513 3 is_stmt 1 view .LVU3304 +5513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10246 .loc 1 5513 11 is_stmt 0 view .LVU3305 + 10247 000a 013B subs r3, r3, #1 + 10248 000c C35C ldrb r3, [r0, r3] +5513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10249 .loc 1 5513 6 view .LVU3306 + 10250 000e 212B cmp r3, #33 + 10251 0010 0FD0 beq .L559 +5535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10252 .loc 1 5535 5 is_stmt 1 view .LVU3307 +5535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 10253 .loc 1 5535 25 is_stmt 0 view .LVU3308 + 10254 0012 4123 movs r3, #65 + 10255 0014 2022 movs r2, #32 + 10256 0016 C254 strb r2, [r0, r3] +5536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10257 .loc 1 5536 5 is_stmt 1 view .LVU3309 +5536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10258 .loc 1 5536 25 is_stmt 0 view .LVU3310 + 10259 0018 2F3B subs r3, r3, #47 + 10260 001a 0363 str r3, [r0, #48] +5537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10261 .loc 1 5537 5 is_stmt 1 view .LVU3311 +5537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10262 .loc 1 5537 25 is_stmt 0 view .LVU3312 + 10263 001c 0025 movs r5, #0 + 10264 001e 4563 str r5, [r0, #52] +5540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10265 .loc 1 5540 5 is_stmt 1 view .LVU3313 + 10266 0020 0221 movs r1, #2 + 10267 0022 FFF7FEFF bl I2C_Disable_IRQ + 10268 .LVL724: +5543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10269 .loc 1 5543 5 view .LVU3314 + ARM GAS /tmp/ccth6daj.s page 355 + + +5543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10270 .loc 1 5543 5 view .LVU3315 + 10271 0026 4023 movs r3, #64 + 10272 0028 E554 strb r5, [r4, r3] +5543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10273 .loc 1 5543 5 view .LVU3316 +5549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10274 .loc 1 5549 5 view .LVU3317 + 10275 002a 2000 movs r0, r4 + 10276 002c FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 10277 .LVL725: + 10278 .L556: +5552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10279 .loc 1 5552 1 is_stmt 0 view .LVU3318 + 10280 @ sp needed + 10281 .LVL726: +5552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10282 .loc 1 5552 1 view .LVU3319 + 10283 0030 70BD pop {r4, r5, r6, pc} + 10284 .LVL727: + 10285 .L559: +5515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10286 .loc 1 5515 5 is_stmt 1 view .LVU3320 +5515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 10287 .loc 1 5515 25 is_stmt 0 view .LVU3321 + 10288 0032 2033 adds r3, r3, #32 + 10289 0034 2032 adds r2, r2, #32 + 10290 0036 C254 strb r2, [r0, r3] +5516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10291 .loc 1 5516 5 is_stmt 1 view .LVU3322 +5516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10292 .loc 1 5516 25 is_stmt 0 view .LVU3323 + 10293 0038 303B subs r3, r3, #48 + 10294 003a 0363 str r3, [r0, #48] +5517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10295 .loc 1 5517 5 is_stmt 1 view .LVU3324 +5517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10296 .loc 1 5517 25 is_stmt 0 view .LVU3325 + 10297 003c 0025 movs r5, #0 + 10298 003e 4563 str r5, [r0, #52] +5520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10299 .loc 1 5520 5 is_stmt 1 view .LVU3326 + 10300 0040 0121 movs r1, #1 + 10301 0042 FFF7FEFF bl I2C_Disable_IRQ + 10302 .LVL728: +5523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10303 .loc 1 5523 5 view .LVU3327 +5523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10304 .loc 1 5523 5 view .LVU3328 + 10305 0046 4023 movs r3, #64 + 10306 0048 E554 strb r5, [r4, r3] +5523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10307 .loc 1 5523 5 view .LVU3329 +5529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10308 .loc 1 5529 5 view .LVU3330 + 10309 004a 2000 movs r0, r4 + 10310 004c FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + ARM GAS /tmp/ccth6daj.s page 356 + + + 10311 .LVL729: + 10312 0050 EEE7 b .L556 + 10313 .cfi_endproc + 10314 .LFE353: + 10316 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 10317 .align 1 + 10318 .weak HAL_I2C_SlaveTxCpltCallback + 10319 .syntax unified + 10320 .code 16 + 10321 .thumb_func + 10322 .fpu softvfp + 10324 HAL_I2C_SlaveTxCpltCallback: + 10325 .LVL730: + 10326 .LFB335: +4537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10327 .loc 1 4537 1 view -0 + 10328 .cfi_startproc + 10329 @ args = 0, pretend = 0, frame = 0 + 10330 @ frame_needed = 0, uses_anonymous_args = 0 + 10331 @ link register save eliminated. +4539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10332 .loc 1 4539 3 view .LVU3332 +4544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10333 .loc 1 4544 1 is_stmt 0 view .LVU3333 + 10334 @ sp needed + 10335 0000 7047 bx lr + 10336 .cfi_endproc + 10337 .LFE335: + 10339 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 10340 .align 1 + 10341 .weak HAL_I2C_SlaveRxCpltCallback + 10342 .syntax unified + 10343 .code 16 + 10344 .thumb_func + 10345 .fpu softvfp + 10347 HAL_I2C_SlaveRxCpltCallback: + 10348 .LVL731: + 10349 .LFB336: +4553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10350 .loc 1 4553 1 is_stmt 1 view -0 + 10351 .cfi_startproc + 10352 @ args = 0, pretend = 0, frame = 0 + 10353 @ frame_needed = 0, uses_anonymous_args = 0 + 10354 @ link register save eliminated. +4555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10355 .loc 1 4555 3 view .LVU3335 +4560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10356 .loc 1 4560 1 is_stmt 0 view .LVU3336 + 10357 @ sp needed + 10358 0000 7047 bx lr + 10359 .cfi_endproc + 10360 .LFE336: + 10362 .section .text.I2C_ITSlaveSeqCplt,"ax",%progbits + 10363 .align 1 + 10364 .syntax unified + 10365 .code 16 + 10366 .thumb_func + ARM GAS /tmp/ccth6daj.s page 357 + + + 10367 .fpu softvfp + 10369 I2C_ITSlaveSeqCplt: + 10370 .LVL732: + 10371 .LFB354: +5560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10372 .loc 1 5560 1 is_stmt 1 view -0 + 10373 .cfi_startproc + 10374 @ args = 0, pretend = 0, frame = 0 + 10375 @ frame_needed = 0, uses_anonymous_args = 0 +5560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 10376 .loc 1 5560 1 is_stmt 0 view .LVU3338 + 10377 0000 10B5 push {r4, lr} + 10378 .LCFI73: + 10379 .cfi_def_cfa_offset 8 + 10380 .cfi_offset 4, -8 + 10381 .cfi_offset 14, -4 + 10382 0002 0400 movs r4, r0 +5561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10383 .loc 1 5561 3 is_stmt 1 view .LVU3339 +5561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10384 .loc 1 5561 26 is_stmt 0 view .LVU3340 + 10385 0004 0368 ldr r3, [r0] +5561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10386 .loc 1 5561 12 view .LVU3341 + 10387 0006 1A68 ldr r2, [r3] + 10388 .LVL733: +5564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10389 .loc 1 5564 3 is_stmt 1 view .LVU3342 +5564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10390 .loc 1 5564 14 is_stmt 0 view .LVU3343 + 10391 0008 4221 movs r1, #66 + 10392 000a 0020 movs r0, #0 + 10393 .LVL734: +5564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10394 .loc 1 5564 14 view .LVU3344 + 10395 000c 6054 strb r0, [r4, r1] +5567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10396 .loc 1 5567 3 is_stmt 1 view .LVU3345 +5567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10397 .loc 1 5567 6 is_stmt 0 view .LVU3346 + 10398 000e 5104 lsls r1, r2, #17 + 10399 0010 0CD5 bpl .L563 +5570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10400 .loc 1 5570 5 is_stmt 1 view .LVU3347 +5570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10401 .loc 1 5570 25 is_stmt 0 view .LVU3348 + 10402 0012 1A68 ldr r2, [r3] + 10403 .LVL735: +5570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10404 .loc 1 5570 25 view .LVU3349 + 10405 0014 1949 ldr r1, .L569 + 10406 0016 0A40 ands r2, r1 + 10407 0018 1A60 str r2, [r3] + 10408 .L564: +5580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10409 .loc 1 5580 3 is_stmt 1 view .LVU3350 +5582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 358 + + + 10410 .loc 1 5582 3 view .LVU3351 +5582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10411 .loc 1 5582 11 is_stmt 0 view .LVU3352 + 10412 001a 4123 movs r3, #65 + 10413 001c E35C ldrb r3, [r4, r3] +5582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10414 .loc 1 5582 6 view .LVU3353 + 10415 001e 292B cmp r3, #41 + 10416 0020 0BD0 beq .L567 +5602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10417 .loc 1 5602 8 is_stmt 1 view .LVU3354 +5602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10418 .loc 1 5602 16 is_stmt 0 view .LVU3355 + 10419 0022 4123 movs r3, #65 + 10420 0024 E35C ldrb r3, [r4, r3] +5602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10421 .loc 1 5602 11 view .LVU3356 + 10422 0026 2A2B cmp r3, #42 + 10423 0028 17D0 beq .L568 + 10424 .L562: +5625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10425 .loc 1 5625 1 view .LVU3357 + 10426 @ sp needed + 10427 .LVL736: +5625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10428 .loc 1 5625 1 view .LVU3358 + 10429 002a 10BD pop {r4, pc} + 10430 .LVL737: + 10431 .L563: +5572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10432 .loc 1 5572 8 is_stmt 1 view .LVU3359 +5572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10433 .loc 1 5572 11 is_stmt 0 view .LVU3360 + 10434 002c 1204 lsls r2, r2, #16 + 10435 002e F4D5 bpl .L564 + 10436 .LVL738: +5575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10437 .loc 1 5575 5 is_stmt 1 view .LVU3361 +5575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10438 .loc 1 5575 25 is_stmt 0 view .LVU3362 + 10439 0030 1A68 ldr r2, [r3] + 10440 0032 1349 ldr r1, .L569+4 + 10441 0034 0A40 ands r2, r1 + 10442 0036 1A60 str r2, [r3] + 10443 0038 EFE7 b .L564 + 10444 .L567: +5585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10445 .loc 1 5585 5 is_stmt 1 view .LVU3363 +5585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 10446 .loc 1 5585 25 is_stmt 0 view .LVU3364 + 10447 003a 1833 adds r3, r3, #24 + 10448 003c 2822 movs r2, #40 + 10449 003e E254 strb r2, [r4, r3] +5586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10450 .loc 1 5586 5 is_stmt 1 view .LVU3365 +5586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10451 .loc 1 5586 25 is_stmt 0 view .LVU3366 + ARM GAS /tmp/ccth6daj.s page 359 + + + 10452 0040 203B subs r3, r3, #32 + 10453 0042 2363 str r3, [r4, #48] +5589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10454 .loc 1 5589 5 is_stmt 1 view .LVU3367 + 10455 0044 0121 movs r1, #1 + 10456 0046 2000 movs r0, r4 + 10457 0048 FFF7FEFF bl I2C_Disable_IRQ + 10458 .LVL739: +5592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10459 .loc 1 5592 5 view .LVU3368 +5592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10460 .loc 1 5592 5 view .LVU3369 + 10461 004c 4023 movs r3, #64 + 10462 004e 0022 movs r2, #0 + 10463 0050 E254 strb r2, [r4, r3] +5592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10464 .loc 1 5592 5 view .LVU3370 +5598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10465 .loc 1 5598 5 view .LVU3371 + 10466 0052 2000 movs r0, r4 + 10467 0054 FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 10468 .LVL740: + 10469 0058 E7E7 b .L562 + 10470 .L568: +5605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10471 .loc 1 5605 5 view .LVU3372 +5605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 10472 .loc 1 5605 25 is_stmt 0 view .LVU3373 + 10473 005a 1733 adds r3, r3, #23 + 10474 005c 2822 movs r2, #40 + 10475 005e E254 strb r2, [r4, r3] +5606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10476 .loc 1 5606 5 is_stmt 1 view .LVU3374 +5606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10477 .loc 1 5606 25 is_stmt 0 view .LVU3375 + 10478 0060 1F3B subs r3, r3, #31 + 10479 0062 2363 str r3, [r4, #48] +5609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10480 .loc 1 5609 5 is_stmt 1 view .LVU3376 + 10481 0064 0221 movs r1, #2 + 10482 0066 2000 movs r0, r4 + 10483 0068 FFF7FEFF bl I2C_Disable_IRQ + 10484 .LVL741: +5612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10485 .loc 1 5612 5 view .LVU3377 +5612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10486 .loc 1 5612 5 view .LVU3378 + 10487 006c 4023 movs r3, #64 + 10488 006e 0022 movs r2, #0 + 10489 0070 E254 strb r2, [r4, r3] +5612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10490 .loc 1 5612 5 view .LVU3379 +5618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10491 .loc 1 5618 5 view .LVU3380 + 10492 0072 2000 movs r0, r4 + 10493 0074 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 10494 .LVL742: + ARM GAS /tmp/ccth6daj.s page 360 + + +5624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10495 .loc 1 5624 3 view .LVU3381 +5625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10496 .loc 1 5625 1 is_stmt 0 view .LVU3382 + 10497 0078 D7E7 b .L562 + 10498 .L570: + 10499 007a C046 .align 2 + 10500 .L569: + 10501 007c FFBFFFFF .word -16385 + 10502 0080 FF7FFFFF .word -32769 + 10503 .cfi_endproc + 10504 .LFE354: + 10506 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 10507 .align 1 + 10508 .syntax unified + 10509 .code 16 + 10510 .thumb_func + 10511 .fpu softvfp + 10513 I2C_DMASlaveTransmitCplt: + 10514 .LVL743: + 10515 .LFB362: +6208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10516 .loc 1 6208 1 is_stmt 1 view -0 + 10517 .cfi_startproc + 10518 @ args = 0, pretend = 0, frame = 0 + 10519 @ frame_needed = 0, uses_anonymous_args = 0 +6208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10520 .loc 1 6208 1 is_stmt 0 view .LVU3384 + 10521 0000 10B5 push {r4, lr} + 10522 .LCFI74: + 10523 .cfi_def_cfa_offset 8 + 10524 .cfi_offset 4, -8 + 10525 .cfi_offset 14, -4 +6210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10526 .loc 1 6210 3 is_stmt 1 view .LVU3385 +6210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10527 .loc 1 6210 22 is_stmt 0 view .LVU3386 + 10528 0002 806A ldr r0, [r0, #40] + 10529 .LVL744: +6211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10530 .loc 1 6211 3 is_stmt 1 view .LVU3387 +6211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10531 .loc 1 6211 12 is_stmt 0 view .LVU3388 + 10532 0004 C36A ldr r3, [r0, #44] + 10533 .LVL745: +6213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10534 .loc 1 6213 3 is_stmt 1 view .LVU3389 +6213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10535 .loc 1 6213 6 is_stmt 0 view .LVU3390 + 10536 0006 8022 movs r2, #128 + 10537 0008 5204 lsls r2, r2, #17 + 10538 000a 9342 cmp r3, r2 + 10539 000c 01D0 beq .L572 +6213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10540 .loc 1 6213 38 discriminator 1 view .LVU3391 + 10541 000e 002B cmp r3, #0 + 10542 0010 06D1 bne .L571 + ARM GAS /tmp/ccth6daj.s page 361 + + + 10543 .L572: +6216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10544 .loc 1 6216 5 is_stmt 1 view .LVU3392 +6216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10545 .loc 1 6216 9 is_stmt 0 view .LVU3393 + 10546 0012 0268 ldr r2, [r0] +6216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10547 .loc 1 6216 25 view .LVU3394 + 10548 0014 1368 ldr r3, [r2] + 10549 .LVL746: +6216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10550 .loc 1 6216 25 view .LVU3395 + 10551 0016 0349 ldr r1, .L574 + 10552 0018 0B40 ands r3, r1 + 10553 001a 1360 str r3, [r2] +6220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10554 .loc 1 6220 5 is_stmt 1 view .LVU3396 + 10555 001c FFF7FEFF bl I2C_ITSlaveSeqCplt + 10556 .LVL747: + 10557 .L571: +6228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10558 .loc 1 6228 1 is_stmt 0 view .LVU3397 + 10559 @ sp needed + 10560 0020 10BD pop {r4, pc} + 10561 .L575: + 10562 0022 C046 .align 2 + 10563 .L574: + 10564 0024 FFBFFFFF .word -16385 + 10565 .cfi_endproc + 10566 .LFE362: + 10568 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 10569 .align 1 + 10570 .syntax unified + 10571 .code 16 + 10572 .thumb_func + 10573 .fpu softvfp + 10575 I2C_DMASlaveReceiveCplt: + 10576 .LVL748: + 10577 .LFB364: +6286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10578 .loc 1 6286 1 is_stmt 1 view -0 + 10579 .cfi_startproc + 10580 @ args = 0, pretend = 0, frame = 0 + 10581 @ frame_needed = 0, uses_anonymous_args = 0 +6286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 10582 .loc 1 6286 1 is_stmt 0 view .LVU3399 + 10583 0000 10B5 push {r4, lr} + 10584 .LCFI75: + 10585 .cfi_def_cfa_offset 8 + 10586 .cfi_offset 4, -8 + 10587 .cfi_offset 14, -4 +6288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10588 .loc 1 6288 3 is_stmt 1 view .LVU3400 +6288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 10589 .loc 1 6288 22 is_stmt 0 view .LVU3401 + 10590 0002 806A ldr r0, [r0, #40] + 10591 .LVL749: + ARM GAS /tmp/ccth6daj.s page 362 + + +6289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10592 .loc 1 6289 3 is_stmt 1 view .LVU3402 +6289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10593 .loc 1 6289 12 is_stmt 0 view .LVU3403 + 10594 0004 C26A ldr r2, [r0, #44] + 10595 .LVL750: +6291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10596 .loc 1 6291 3 is_stmt 1 view .LVU3404 +6291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10597 .loc 1 6291 8 is_stmt 0 view .LVU3405 + 10598 0006 C36B ldr r3, [r0, #60] + 10599 0008 1B68 ldr r3, [r3] + 10600 000a 5B68 ldr r3, [r3, #4] +6291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10601 .loc 1 6291 6 view .LVU3406 + 10602 000c 002B cmp r3, #0 + 10603 000e 02D1 bne .L576 +6291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10604 .loc 1 6291 51 discriminator 1 view .LVU3407 + 10605 0010 054B ldr r3, .L579 + 10606 0012 9A42 cmp r2, r3 + 10607 0014 00D1 bne .L578 + 10608 .LVL751: + 10609 .L576: +6306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10610 .loc 1 6306 1 view .LVU3408 + 10611 @ sp needed + 10612 0016 10BD pop {r4, pc} + 10613 .LVL752: + 10614 .L578: +6295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10615 .loc 1 6295 5 is_stmt 1 view .LVU3409 +6295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10616 .loc 1 6295 9 is_stmt 0 view .LVU3410 + 10617 0018 0268 ldr r2, [r0] + 10618 .LVL753: +6295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10619 .loc 1 6295 25 view .LVU3411 + 10620 001a 1368 ldr r3, [r2] + 10621 001c 0349 ldr r1, .L579+4 + 10622 001e 0B40 ands r3, r1 + 10623 0020 1360 str r3, [r2] +6298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10624 .loc 1 6298 5 is_stmt 1 view .LVU3412 + 10625 0022 FFF7FEFF bl I2C_ITSlaveSeqCplt + 10626 .LVL754: +6305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10627 .loc 1 6305 3 view .LVU3413 +6306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10628 .loc 1 6306 1 is_stmt 0 view .LVU3414 + 10629 0026 F6E7 b .L576 + 10630 .L580: + 10631 .align 2 + 10632 .L579: + 10633 0028 0000FFFF .word -65536 + 10634 002c FF7FFFFF .word -32769 + 10635 .cfi_endproc + ARM GAS /tmp/ccth6daj.s page 363 + + + 10636 .LFE364: + 10638 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 10639 .align 1 + 10640 .weak HAL_I2C_AddrCallback + 10641 .syntax unified + 10642 .code 16 + 10643 .thumb_func + 10644 .fpu softvfp + 10646 HAL_I2C_AddrCallback: + 10647 .LVL755: + 10648 .LFB337: +4571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10649 .loc 1 4571 1 is_stmt 1 view -0 + 10650 .cfi_startproc + 10651 @ args = 0, pretend = 0, frame = 0 + 10652 @ frame_needed = 0, uses_anonymous_args = 0 + 10653 @ link register save eliminated. +4573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(TransferDirection); + 10654 .loc 1 4573 3 view .LVU3416 +4574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(AddrMatchCode); + 10655 .loc 1 4574 3 view .LVU3417 +4575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10656 .loc 1 4575 3 view .LVU3418 +4580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10657 .loc 1 4580 1 is_stmt 0 view .LVU3419 + 10658 @ sp needed + 10659 0000 7047 bx lr + 10660 .cfi_endproc + 10661 .LFE337: + 10663 .section .text.I2C_ITAddrCplt,"ax",%progbits + 10664 .align 1 + 10665 .syntax unified + 10666 .code 16 + 10667 .thumb_func + 10668 .fpu softvfp + 10670 I2C_ITAddrCplt: + 10671 .LVL756: + 10672 .LFB352: +5412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint8_t transferdirection; + 10673 .loc 1 5412 1 is_stmt 1 view -0 + 10674 .cfi_startproc + 10675 @ args = 0, pretend = 0, frame = 0 + 10676 @ frame_needed = 0, uses_anonymous_args = 0 +5412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint8_t transferdirection; + 10677 .loc 1 5412 1 is_stmt 0 view .LVU3421 + 10678 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 10679 .LCFI76: + 10680 .cfi_def_cfa_offset 24 + 10681 .cfi_offset 3, -24 + 10682 .cfi_offset 4, -20 + 10683 .cfi_offset 5, -16 + 10684 .cfi_offset 6, -12 + 10685 .cfi_offset 7, -8 + 10686 .cfi_offset 14, -4 + 10687 0002 0400 movs r4, r0 +5413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t slaveaddrcode; + 10688 .loc 1 5413 3 is_stmt 1 view .LVU3422 + ARM GAS /tmp/ccth6daj.s page 364 + + +5414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t ownadd1code; + 10689 .loc 1 5414 3 view .LVU3423 +5415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t ownadd2code; + 10690 .loc 1 5415 3 view .LVU3424 +5416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10691 .loc 1 5416 3 view .LVU3425 +5419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10692 .loc 1 5419 3 view .LVU3426 +5422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10693 .loc 1 5422 3 view .LVU3427 +5422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10694 .loc 1 5422 22 is_stmt 0 view .LVU3428 + 10695 0004 4123 movs r3, #65 + 10696 0006 C35C ldrb r3, [r0, r3] +5422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10697 .loc 1 5422 6 view .LVU3429 + 10698 0008 2822 movs r2, #40 + 10699 000a 1340 ands r3, r2 + 10700 000c 282B cmp r3, #40 + 10701 000e 06D0 beq .L587 +5494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10702 .loc 1 5494 5 is_stmt 1 view .LVU3430 + 10703 0010 0368 ldr r3, [r0] + 10704 0012 0822 movs r2, #8 + 10705 0014 DA61 str r2, [r3, #28] +5497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10706 .loc 1 5497 5 view .LVU3431 +5497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10707 .loc 1 5497 5 view .LVU3432 + 10708 0016 4023 movs r3, #64 + 10709 0018 0022 movs r2, #0 + 10710 001a C254 strb r2, [r0, r3] +5497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10711 .loc 1 5497 5 view .LVU3433 + 10712 .LVL757: + 10713 .L582: +5499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10714 .loc 1 5499 1 is_stmt 0 view .LVU3434 + 10715 @ sp needed + 10716 .LVL758: +5499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10717 .loc 1 5499 1 view .LVU3435 + 10718 001c F8BD pop {r3, r4, r5, r6, r7, pc} + 10719 .LVL759: + 10720 .L587: +5424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10721 .loc 1 5424 5 is_stmt 1 view .LVU3436 +5424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10722 .loc 1 5424 25 is_stmt 0 view .LVU3437 + 10723 001e 0168 ldr r1, [r0] + 10724 .LVL760: +5424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10725 .loc 1 5424 25 view .LVU3438 + 10726 0020 8E69 ldr r6, [r1, #24] + 10727 0022 360C lsrs r6, r6, #16 +5424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 10728 .loc 1 5424 23 view .LVU3439 + ARM GAS /tmp/ccth6daj.s page 365 + + + 10729 0024 273B subs r3, r3, #39 + 10730 0026 1E40 ands r6, r3 + 10731 .LVL761: +5425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10732 .loc 1 5425 5 is_stmt 1 view .LVU3440 +5425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10733 .loc 1 5425 25 is_stmt 0 view .LVU3441 + 10734 0028 8D69 ldr r5, [r1, #24] + 10735 002a 2D0C lsrs r5, r5, #16 +5425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 10736 .loc 1 5425 23 view .LVU3442 + 10737 002c FE27 movs r7, #254 + 10738 002e 3D40 ands r5, r7 + 10739 .LVL762: +5426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10740 .loc 1 5426 5 is_stmt 1 view .LVU3443 +5426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10741 .loc 1 5426 25 is_stmt 0 view .LVU3444 + 10742 0030 8B68 ldr r3, [r1, #8] +5426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 10743 .loc 1 5426 23 view .LVU3445 + 10744 0032 9B05 lsls r3, r3, #22 + 10745 0034 9B0D lsrs r3, r3, #22 + 10746 .LVL763: +5427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10747 .loc 1 5427 5 is_stmt 1 view .LVU3446 +5427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10748 .loc 1 5427 25 is_stmt 0 view .LVU3447 + 10749 0036 CA68 ldr r2, [r1, #12] +5427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10750 .loc 1 5427 23 view .LVU3448 + 10751 0038 1740 ands r7, r2 + 10752 .LVL764: +5430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10753 .loc 1 5430 5 is_stmt 1 view .LVU3449 +5430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10754 .loc 1 5430 8 is_stmt 0 view .LVU3450 + 10755 003a C268 ldr r2, [r0, #12] + 10756 003c 022A cmp r2, #2 + 10757 003e 24D1 bne .L584 +5432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10758 .loc 1 5432 7 is_stmt 1 view .LVU3451 +5432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10759 .loc 1 5432 44 is_stmt 0 view .LVU3452 + 10760 0040 DA09 lsrs r2, r3, #7 + 10761 0042 6A40 eors r2, r5 +5432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10762 .loc 1 5432 10 view .LVU3453 + 10763 0044 0620 movs r0, #6 + 10764 .LVL765: +5432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10765 .loc 1 5432 10 view .LVU3454 + 10766 0046 1042 tst r0, r2 + 10767 0048 11D1 bne .L585 +5434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->AddrEventCount++; + 10768 .loc 1 5434 9 is_stmt 1 view .LVU3455 + 10769 .LVL766: + ARM GAS /tmp/ccth6daj.s page 366 + + +5435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10770 .loc 1 5435 9 view .LVU3456 +5435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10771 .loc 1 5435 13 is_stmt 0 view .LVU3457 + 10772 004a A26C ldr r2, [r4, #72] +5435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 10773 .loc 1 5435 29 view .LVU3458 + 10774 004c 0132 adds r2, r2, #1 + 10775 004e A264 str r2, [r4, #72] +5436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10776 .loc 1 5436 9 is_stmt 1 view .LVU3459 +5436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10777 .loc 1 5436 17 is_stmt 0 view .LVU3460 + 10778 0050 A26C ldr r2, [r4, #72] +5436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10779 .loc 1 5436 12 view .LVU3461 + 10780 0052 022A cmp r2, #2 + 10781 0054 E2D1 bne .L582 +5439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10782 .loc 1 5439 11 is_stmt 1 view .LVU3462 +5439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10783 .loc 1 5439 32 is_stmt 0 view .LVU3463 + 10784 0056 0022 movs r2, #0 + 10785 0058 A264 str r2, [r4, #72] +5442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10786 .loc 1 5442 11 is_stmt 1 view .LVU3464 + 10787 005a 0230 adds r0, r0, #2 + 10788 005c C861 str r0, [r1, #28] +5445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10789 .loc 1 5445 11 view .LVU3465 +5445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10790 .loc 1 5445 11 view .LVU3466 + 10791 005e 4021 movs r1, #64 + 10792 0060 6254 strb r2, [r4, r1] +5445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10793 .loc 1 5445 11 view .LVU3467 +5451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10794 .loc 1 5451 11 view .LVU3468 + 10795 0062 1A00 movs r2, r3 + 10796 0064 3100 movs r1, r6 + 10797 0066 2000 movs r0, r4 + 10798 0068 FFF7FEFF bl HAL_I2C_AddrCallback + 10799 .LVL767: +5451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10800 .loc 1 5451 11 is_stmt 0 view .LVU3469 + 10801 006c D6E7 b .L582 + 10802 .LVL768: + 10803 .L585: +5457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10804 .loc 1 5457 9 is_stmt 1 view .LVU3470 +5460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10805 .loc 1 5460 9 view .LVU3471 + 10806 006e 8021 movs r1, #128 + 10807 0070 0902 lsls r1, r1, #8 + 10808 0072 2000 movs r0, r4 + 10809 0074 FFF7FEFF bl I2C_Disable_IRQ + 10810 .LVL769: + ARM GAS /tmp/ccth6daj.s page 367 + + +5463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10811 .loc 1 5463 9 view .LVU3472 +5463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10812 .loc 1 5463 9 view .LVU3473 + 10813 0078 4023 movs r3, #64 + 10814 007a 0022 movs r2, #0 + 10815 007c E254 strb r2, [r4, r3] +5463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10816 .loc 1 5463 9 view .LVU3474 +5469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10817 .loc 1 5469 9 view .LVU3475 + 10818 007e 3A00 movs r2, r7 + 10819 0080 3100 movs r1, r6 + 10820 0082 2000 movs r0, r4 + 10821 0084 FFF7FEFF bl HAL_I2C_AddrCallback + 10822 .LVL770: + 10823 0088 C8E7 b .L582 + 10824 .LVL771: + 10825 .L584: +5477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10826 .loc 1 5477 7 view .LVU3476 + 10827 008a 8021 movs r1, #128 + 10828 008c 0902 lsls r1, r1, #8 + 10829 008e FFF7FEFF bl I2C_Disable_IRQ + 10830 .LVL772: +5480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10831 .loc 1 5480 7 view .LVU3477 +5480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10832 .loc 1 5480 7 view .LVU3478 + 10833 0092 4023 movs r3, #64 + 10834 0094 0022 movs r2, #0 + 10835 0096 E254 strb r2, [r4, r3] +5480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10836 .loc 1 5480 7 view .LVU3479 +5486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10837 .loc 1 5486 7 view .LVU3480 + 10838 0098 2A00 movs r2, r5 + 10839 009a 3100 movs r1, r6 + 10840 009c 2000 movs r0, r4 + 10841 009e FFF7FEFF bl HAL_I2C_AddrCallback + 10842 .LVL773: + 10843 00a2 BBE7 b .L582 + 10844 .cfi_endproc + 10845 .LFE352: + 10847 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 10848 .align 1 + 10849 .weak HAL_I2C_ListenCpltCallback + 10850 .syntax unified + 10851 .code 16 + 10852 .thumb_func + 10853 .fpu softvfp + 10855 HAL_I2C_ListenCpltCallback: + 10856 .LVL774: + 10857 .LFB338: +4589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10858 .loc 1 4589 1 view -0 + 10859 .cfi_startproc + ARM GAS /tmp/ccth6daj.s page 368 + + + 10860 @ args = 0, pretend = 0, frame = 0 + 10861 @ frame_needed = 0, uses_anonymous_args = 0 + 10862 @ link register save eliminated. +4591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10863 .loc 1 4591 3 view .LVU3482 +4596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10864 .loc 1 4596 1 is_stmt 0 view .LVU3483 + 10865 @ sp needed + 10866 0000 7047 bx lr + 10867 .cfi_endproc + 10868 .LFE338: + 10870 .section .text.I2C_ITListenCplt,"ax",%progbits + 10871 .align 1 + 10872 .syntax unified + 10873 .code 16 + 10874 .thumb_func + 10875 .fpu softvfp + 10877 I2C_ITListenCplt: + 10878 .LVL775: + 10879 .LFB357: +5936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset handle parameters */ + 10880 .loc 1 5936 1 is_stmt 1 view -0 + 10881 .cfi_startproc + 10882 @ args = 0, pretend = 0, frame = 0 + 10883 @ frame_needed = 0, uses_anonymous_args = 0 +5936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Reset handle parameters */ + 10884 .loc 1 5936 1 is_stmt 0 view .LVU3485 + 10885 0000 10B5 push {r4, lr} + 10886 .LCFI77: + 10887 .cfi_def_cfa_offset 8 + 10888 .cfi_offset 4, -8 + 10889 .cfi_offset 14, -4 + 10890 0002 0400 movs r4, r0 +5938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10891 .loc 1 5938 3 is_stmt 1 view .LVU3486 +5938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 10892 .loc 1 5938 21 is_stmt 0 view .LVU3487 + 10893 0004 164B ldr r3, .L591 + 10894 0006 C362 str r3, [r0, #44] +5939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10895 .loc 1 5939 3 is_stmt 1 view .LVU3488 +5939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 10896 .loc 1 5939 23 is_stmt 0 view .LVU3489 + 10897 0008 0023 movs r3, #0 + 10898 000a 0363 str r3, [r0, #48] +5940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10899 .loc 1 5940 3 is_stmt 1 view .LVU3490 +5940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10900 .loc 1 5940 15 is_stmt 0 view .LVU3491 + 10901 000c 4122 movs r2, #65 + 10902 000e 2020 movs r0, #32 + 10903 .LVL776: +5940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 10904 .loc 1 5940 15 view .LVU3492 + 10905 0010 A054 strb r0, [r4, r2] +5941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10906 .loc 1 5941 3 is_stmt 1 view .LVU3493 + ARM GAS /tmp/ccth6daj.s page 369 + + +5941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 10907 .loc 1 5941 14 is_stmt 0 view .LVU3494 + 10908 0012 0132 adds r2, r2, #1 + 10909 0014 A354 strb r3, [r4, r2] +5942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10910 .loc 1 5942 3 is_stmt 1 view .LVU3495 +5942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10911 .loc 1 5942 17 is_stmt 0 view .LVU3496 + 10912 0016 6363 str r3, [r4, #52] +5945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10913 .loc 1 5945 3 is_stmt 1 view .LVU3497 +5945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10914 .loc 1 5945 6 is_stmt 0 view .LVU3498 + 10915 0018 4B07 lsls r3, r1, #29 + 10916 001a 13D5 bpl .L590 +5948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10917 .loc 1 5948 5 is_stmt 1 view .LVU3499 +5948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10918 .loc 1 5948 36 is_stmt 0 view .LVU3500 + 10919 001c 2368 ldr r3, [r4] +5948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10920 .loc 1 5948 46 view .LVU3501 + 10921 001e 5B6A ldr r3, [r3, #36] +5948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10922 .loc 1 5948 21 view .LVU3502 + 10923 0020 626A ldr r2, [r4, #36] + 10924 0022 1370 strb r3, [r2] +5951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10925 .loc 1 5951 5 is_stmt 1 view .LVU3503 +5951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10926 .loc 1 5951 19 is_stmt 0 view .LVU3504 + 10927 0024 636A ldr r3, [r4, #36] + 10928 0026 0133 adds r3, r3, #1 + 10929 0028 6362 str r3, [r4, #36] +5953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10930 .loc 1 5953 5 is_stmt 1 view .LVU3505 +5953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10931 .loc 1 5953 14 is_stmt 0 view .LVU3506 + 10932 002a 238D ldrh r3, [r4, #40] +5953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 10933 .loc 1 5953 8 view .LVU3507 + 10934 002c 002B cmp r3, #0 + 10935 002e 09D0 beq .L590 +5955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 10936 .loc 1 5955 7 is_stmt 1 view .LVU3508 +5955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 10937 .loc 1 5955 21 is_stmt 0 view .LVU3509 + 10938 0030 013B subs r3, r3, #1 + 10939 0032 2385 strh r3, [r4, #40] +5956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10940 .loc 1 5956 7 is_stmt 1 view .LVU3510 +5956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10941 .loc 1 5956 11 is_stmt 0 view .LVU3511 + 10942 0034 638D ldrh r3, [r4, #42] +5956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10943 .loc 1 5956 22 view .LVU3512 + 10944 0036 013B subs r3, r3, #1 + ARM GAS /tmp/ccth6daj.s page 370 + + + 10945 0038 9BB2 uxth r3, r3 + 10946 003a 6385 strh r3, [r4, #42] +5959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10947 .loc 1 5959 7 is_stmt 1 view .LVU3513 +5959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 10948 .loc 1 5959 23 is_stmt 0 view .LVU3514 + 10949 003c 636C ldr r3, [r4, #68] + 10950 003e 0422 movs r2, #4 + 10951 0040 1343 orrs r3, r2 + 10952 0042 6364 str r3, [r4, #68] + 10953 .L590: +5964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10954 .loc 1 5964 3 is_stmt 1 view .LVU3515 + 10955 0044 0749 ldr r1, .L591+4 + 10956 .LVL777: +5964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10957 .loc 1 5964 3 is_stmt 0 view .LVU3516 + 10958 0046 2000 movs r0, r4 + 10959 0048 FFF7FEFF bl I2C_Disable_IRQ + 10960 .LVL778: +5967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10961 .loc 1 5967 3 is_stmt 1 view .LVU3517 + 10962 004c 2368 ldr r3, [r4] + 10963 004e 1022 movs r2, #16 + 10964 0050 DA61 str r2, [r3, #28] +5970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10965 .loc 1 5970 3 view .LVU3518 +5970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10966 .loc 1 5970 3 view .LVU3519 + 10967 0052 4023 movs r3, #64 + 10968 0054 0022 movs r2, #0 + 10969 0056 E254 strb r2, [r4, r3] +5970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10970 .loc 1 5970 3 view .LVU3520 +5976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 10971 .loc 1 5976 3 view .LVU3521 + 10972 0058 2000 movs r0, r4 + 10973 005a FFF7FEFF bl HAL_I2C_ListenCpltCallback + 10974 .LVL779: +5978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10975 .loc 1 5978 1 is_stmt 0 view .LVU3522 + 10976 @ sp needed + 10977 .LVL780: +5978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 10978 .loc 1 5978 1 view .LVU3523 + 10979 005e 10BD pop {r4, pc} + 10980 .L592: + 10981 .align 2 + 10982 .L591: + 10983 0060 0000FFFF .word -65536 + 10984 0064 03800000 .word 32771 + 10985 .cfi_endproc + 10986 .LFE357: + 10988 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 10989 .align 1 + 10990 .weak HAL_I2C_MemTxCpltCallback + 10991 .syntax unified + ARM GAS /tmp/ccth6daj.s page 371 + + + 10992 .code 16 + 10993 .thumb_func + 10994 .fpu softvfp + 10996 HAL_I2C_MemTxCpltCallback: + 10997 .LVL781: + 10998 .LFB339: +4605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 10999 .loc 1 4605 1 is_stmt 1 view -0 + 11000 .cfi_startproc + 11001 @ args = 0, pretend = 0, frame = 0 + 11002 @ frame_needed = 0, uses_anonymous_args = 0 + 11003 @ link register save eliminated. +4607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11004 .loc 1 4607 3 view .LVU3525 +4612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11005 .loc 1 4612 1 is_stmt 0 view .LVU3526 + 11006 @ sp needed + 11007 0000 7047 bx lr + 11008 .cfi_endproc + 11009 .LFE339: + 11011 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 11012 .align 1 + 11013 .weak HAL_I2C_MemRxCpltCallback + 11014 .syntax unified + 11015 .code 16 + 11016 .thumb_func + 11017 .fpu softvfp + 11019 HAL_I2C_MemRxCpltCallback: + 11020 .LVL782: + 11021 .LFB340: +4621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 11022 .loc 1 4621 1 is_stmt 1 view -0 + 11023 .cfi_startproc + 11024 @ args = 0, pretend = 0, frame = 0 + 11025 @ frame_needed = 0, uses_anonymous_args = 0 + 11026 @ link register save eliminated. +4623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11027 .loc 1 4623 3 view .LVU3528 +4628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11028 .loc 1 4628 1 is_stmt 0 view .LVU3529 + 11029 @ sp needed + 11030 0000 7047 bx lr + 11031 .cfi_endproc + 11032 .LFE340: + 11034 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 11035 .align 1 + 11036 .weak HAL_I2C_ErrorCallback + 11037 .syntax unified + 11038 .code 16 + 11039 .thumb_func + 11040 .fpu softvfp + 11042 HAL_I2C_ErrorCallback: + 11043 .LVL783: + 11044 .LFB341: +4637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 11045 .loc 1 4637 1 is_stmt 1 view -0 + 11046 .cfi_startproc + ARM GAS /tmp/ccth6daj.s page 372 + + + 11047 @ args = 0, pretend = 0, frame = 0 + 11048 @ frame_needed = 0, uses_anonymous_args = 0 + 11049 @ link register save eliminated. +4639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11050 .loc 1 4639 3 view .LVU3531 +4644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11051 .loc 1 4644 1 is_stmt 0 view .LVU3532 + 11052 @ sp needed + 11053 0000 7047 bx lr + 11054 .cfi_endproc + 11055 .LFE341: + 11057 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 11058 .align 1 + 11059 .weak HAL_I2C_AbortCpltCallback + 11060 .syntax unified + 11061 .code 16 + 11062 .thumb_func + 11063 .fpu softvfp + 11065 HAL_I2C_AbortCpltCallback: + 11066 .LVL784: + 11067 .LFB342: +4653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 11068 .loc 1 4653 1 is_stmt 1 view -0 + 11069 .cfi_startproc + 11070 @ args = 0, pretend = 0, frame = 0 + 11071 @ frame_needed = 0, uses_anonymous_args = 0 + 11072 @ link register save eliminated. +4655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11073 .loc 1 4655 3 view .LVU3534 +4660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11074 .loc 1 4660 1 is_stmt 0 view .LVU3535 + 11075 @ sp needed + 11076 0000 7047 bx lr + 11077 .cfi_endproc + 11078 .LFE342: + 11080 .section .text.I2C_TreatErrorCallback,"ax",%progbits + 11081 .align 1 + 11082 .syntax unified + 11083 .code 16 + 11084 .thumb_func + 11085 .fpu softvfp + 11087 I2C_TreatErrorCallback: + 11088 .LVL785: + 11089 .LFB359: +6099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 11090 .loc 1 6099 1 is_stmt 1 view -0 + 11091 .cfi_startproc + 11092 @ args = 0, pretend = 0, frame = 0 + 11093 @ frame_needed = 0, uses_anonymous_args = 0 +6099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 11094 .loc 1 6099 1 is_stmt 0 view .LVU3537 + 11095 0000 10B5 push {r4, lr} + 11096 .LCFI78: + 11097 .cfi_def_cfa_offset 8 + 11098 .cfi_offset 4, -8 + 11099 .cfi_offset 14, -4 +6100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 373 + + + 11100 .loc 1 6100 3 is_stmt 1 view .LVU3538 +6100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11101 .loc 1 6100 11 is_stmt 0 view .LVU3539 + 11102 0002 4123 movs r3, #65 + 11103 0004 C35C ldrb r3, [r0, r3] +6100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11104 .loc 1 6100 6 view .LVU3540 + 11105 0006 602B cmp r3, #96 + 11106 0008 06D0 beq .L600 +6117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11107 .loc 1 6117 5 is_stmt 1 view .LVU3541 +6117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11108 .loc 1 6117 25 is_stmt 0 view .LVU3542 + 11109 000a 0023 movs r3, #0 + 11110 000c 0363 str r3, [r0, #48] +6120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11111 .loc 1 6120 5 is_stmt 1 view .LVU3543 +6120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11112 .loc 1 6120 5 view .LVU3544 + 11113 000e 4022 movs r2, #64 + 11114 0010 8354 strb r3, [r0, r2] +6120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11115 .loc 1 6120 5 view .LVU3545 +6126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11116 .loc 1 6126 5 view .LVU3546 + 11117 0012 FFF7FEFF bl HAL_I2C_ErrorCallback + 11118 .LVL786: + 11119 .L597: +6129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11120 .loc 1 6129 1 is_stmt 0 view .LVU3547 + 11121 @ sp needed + 11122 0016 10BD pop {r4, pc} + 11123 .LVL787: + 11124 .L600: +6102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11125 .loc 1 6102 5 is_stmt 1 view .LVU3548 +6102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11126 .loc 1 6102 17 is_stmt 0 view .LVU3549 + 11127 0018 1F3B subs r3, r3, #31 + 11128 001a 2022 movs r2, #32 + 11129 001c C254 strb r2, [r0, r3] +6103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11130 .loc 1 6103 5 is_stmt 1 view .LVU3550 +6103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11131 .loc 1 6103 25 is_stmt 0 view .LVU3551 + 11132 001e 0023 movs r3, #0 + 11133 0020 0363 str r3, [r0, #48] +6106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11134 .loc 1 6106 5 is_stmt 1 view .LVU3552 +6106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11135 .loc 1 6106 5 view .LVU3553 + 11136 0022 2032 adds r2, r2, #32 + 11137 0024 8354 strb r3, [r0, r2] +6106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11138 .loc 1 6106 5 view .LVU3554 +6112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11139 .loc 1 6112 5 view .LVU3555 + ARM GAS /tmp/ccth6daj.s page 374 + + + 11140 0026 FFF7FEFF bl HAL_I2C_AbortCpltCallback + 11141 .LVL788: +6112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11142 .loc 1 6112 5 is_stmt 0 view .LVU3556 + 11143 002a F4E7 b .L597 + 11144 .cfi_endproc + 11145 .LFE359: + 11147 .section .text.I2C_ITError,"ax",%progbits + 11148 .align 1 + 11149 .syntax unified + 11150 .code 16 + 11151 .thumb_func + 11152 .fpu softvfp + 11154 I2C_ITError: + 11155 .LVL789: + 11156 .LFB358: +5987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 11157 .loc 1 5987 1 is_stmt 1 view -0 + 11158 .cfi_startproc + 11159 @ args = 0, pretend = 0, frame = 0 + 11160 @ frame_needed = 0, uses_anonymous_args = 0 +5987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 11161 .loc 1 5987 1 is_stmt 0 view .LVU3558 + 11162 0000 10B5 push {r4, lr} + 11163 .LCFI79: + 11164 .cfi_def_cfa_offset 8 + 11165 .cfi_offset 4, -8 + 11166 .cfi_offset 14, -4 + 11167 0002 0400 movs r4, r0 +5988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmppreviousstate; + 11168 .loc 1 5988 3 is_stmt 1 view .LVU3559 +5988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmppreviousstate; + 11169 .loc 1 5988 24 is_stmt 0 view .LVU3560 + 11170 0004 4123 movs r3, #65 + 11171 0006 C35C ldrb r3, [r0, r3] + 11172 .LVL790: +5989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11173 .loc 1 5989 3 is_stmt 1 view .LVU3561 +5992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11174 .loc 1 5992 3 view .LVU3562 +5992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11175 .loc 1 5992 23 is_stmt 0 view .LVU3563 + 11176 0008 0020 movs r0, #0 + 11177 .LVL791: +5992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 11178 .loc 1 5992 23 view .LVU3564 + 11179 000a 4222 movs r2, #66 + 11180 000c A054 strb r0, [r4, r2] +5993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = 0U; + 11181 .loc 1 5993 3 is_stmt 1 view .LVU3565 +5993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount = 0U; + 11182 .loc 1 5993 23 is_stmt 0 view .LVU3566 + 11183 000e 3A4A ldr r2, .L614 + 11184 0010 E262 str r2, [r4, #44] +5994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11185 .loc 1 5994 3 is_stmt 1 view .LVU3567 +5994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 375 + + + 11186 .loc 1 5994 23 is_stmt 0 view .LVU3568 + 11187 0012 6085 strh r0, [r4, #42] +5997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11188 .loc 1 5997 3 is_stmt 1 view .LVU3569 +5997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11189 .loc 1 5997 19 is_stmt 0 view .LVU3570 + 11190 0014 626C ldr r2, [r4, #68] + 11191 0016 0A43 orrs r2, r1 + 11192 0018 6264 str r2, [r4, #68] +6000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 11193 .loc 1 6000 3 is_stmt 1 view .LVU3571 +6001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 11194 .loc 1 6001 50 is_stmt 0 view .LVU3572 + 11195 001a 283B subs r3, r3, #40 + 11196 .LVL792: +6001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 11197 .loc 1 6001 50 view .LVU3573 + 11198 001c DBB2 uxtb r3, r3 +6000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 11199 .loc 1 6000 6 view .LVU3574 + 11200 001e 022B cmp r3, #2 + 11201 0020 1BD8 bhi .L602 +6005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11202 .loc 1 6005 5 is_stmt 1 view .LVU3575 + 11203 0022 0321 movs r1, #3 + 11204 .LVL793: +6005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11205 .loc 1 6005 5 is_stmt 0 view .LVU3576 + 11206 0024 2000 movs r0, r4 + 11207 0026 FFF7FEFF bl I2C_Disable_IRQ + 11208 .LVL794: +6008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 11209 .loc 1 6008 5 is_stmt 1 view .LVU3577 +6008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 11210 .loc 1 6008 25 is_stmt 0 view .LVU3578 + 11211 002a 4123 movs r3, #65 + 11212 002c 2822 movs r2, #40 + 11213 002e E254 strb r2, [r4, r3] +6009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11214 .loc 1 6009 5 is_stmt 1 view .LVU3579 +6009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11215 .loc 1 6009 25 is_stmt 0 view .LVU3580 + 11216 0030 324B ldr r3, .L614+4 + 11217 0032 6363 str r3, [r4, #52] + 11218 .L603: +6027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 11219 .loc 1 6027 3 is_stmt 1 view .LVU3581 +6027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 11220 .loc 1 6027 20 is_stmt 0 view .LVU3582 + 11221 0034 236B ldr r3, [r4, #48] + 11222 .LVL795: +6028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11223 .loc 1 6028 3 is_stmt 1 view .LVU3583 +6028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11224 .loc 1 6028 6 is_stmt 0 view .LVU3584 + 11225 0036 A26B ldr r2, [r4, #56] + 11226 0038 002A cmp r2, #0 + ARM GAS /tmp/ccth6daj.s page 376 + + + 11227 003a 03D0 beq .L605 +6028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11228 .loc 1 6028 30 discriminator 1 view .LVU3585 + 11229 003c 112B cmp r3, #17 + 11230 003e 1AD0 beq .L606 +6028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + 11231 .loc 1 6028 81 discriminator 2 view .LVU3586 + 11232 0040 212B cmp r3, #33 + 11233 0042 18D0 beq .L606 + 11234 .L605: +6058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11235 .loc 1 6058 8 is_stmt 1 view .LVU3587 +6058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11236 .loc 1 6058 11 is_stmt 0 view .LVU3588 + 11237 0044 E26B ldr r2, [r4, #60] + 11238 0046 002A cmp r2, #0 + 11239 0048 03D0 beq .L610 +6058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11240 .loc 1 6058 35 discriminator 1 view .LVU3589 + 11241 004a 122B cmp r3, #18 + 11242 004c 33D0 beq .L611 +6058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + 11243 .loc 1 6058 86 discriminator 2 view .LVU3590 + 11244 004e 222B cmp r3, #34 + 11245 0050 31D0 beq .L611 + 11246 .L610: +6089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11247 .loc 1 6089 5 is_stmt 1 view .LVU3591 + 11248 0052 2000 movs r0, r4 + 11249 0054 FFF7FEFF bl I2C_TreatErrorCallback + 11250 .LVL796: + 11251 .L601: +6091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11252 .loc 1 6091 1 is_stmt 0 view .LVU3592 + 11253 @ sp needed + 11254 .LVL797: +6091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11255 .loc 1 6091 1 view .LVU3593 + 11256 0058 10BD pop {r4, pc} + 11257 .LVL798: + 11258 .L602: +6014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11259 .loc 1 6014 5 is_stmt 1 view .LVU3594 + 11260 005a 2949 ldr r1, .L614+8 + 11261 .LVL799: +6014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11262 .loc 1 6014 5 is_stmt 0 view .LVU3595 + 11263 005c 2000 movs r0, r4 + 11264 005e FFF7FEFF bl I2C_Disable_IRQ + 11265 .LVL800: +6018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11266 .loc 1 6018 5 is_stmt 1 view .LVU3596 +6018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11267 .loc 1 6018 13 is_stmt 0 view .LVU3597 + 11268 0062 4123 movs r3, #65 + 11269 0064 E35C ldrb r3, [r4, r3] +6018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 377 + + + 11270 .loc 1 6018 8 view .LVU3598 + 11271 0066 602B cmp r3, #96 + 11272 0068 02D0 beq .L604 +6021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11273 .loc 1 6021 7 is_stmt 1 view .LVU3599 +6021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11274 .loc 1 6021 27 is_stmt 0 view .LVU3600 + 11275 006a 4123 movs r3, #65 + 11276 006c 2022 movs r2, #32 + 11277 006e E254 strb r2, [r4, r3] + 11278 .L604: +6023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11279 .loc 1 6023 5 is_stmt 1 view .LVU3601 +6023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11280 .loc 1 6023 25 is_stmt 0 view .LVU3602 + 11281 0070 0023 movs r3, #0 + 11282 0072 6363 str r3, [r4, #52] + 11283 0074 DEE7 b .L603 + 11284 .LVL801: + 11285 .L606: +6031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11286 .loc 1 6031 5 is_stmt 1 view .LVU3603 +6031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11287 .loc 1 6031 14 is_stmt 0 view .LVU3604 + 11288 0076 2368 ldr r3, [r4] + 11289 .LVL802: +6031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11290 .loc 1 6031 24 view .LVU3605 + 11291 0078 1A68 ldr r2, [r3] +6031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11292 .loc 1 6031 8 view .LVU3606 + 11293 007a 5204 lsls r2, r2, #17 + 11294 007c 03D5 bpl .L607 +6033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11295 .loc 1 6033 7 is_stmt 1 view .LVU3607 +6033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11296 .loc 1 6033 27 is_stmt 0 view .LVU3608 + 11297 007e 1A68 ldr r2, [r3] + 11298 0080 2049 ldr r1, .L614+12 + 11299 0082 0A40 ands r2, r1 + 11300 0084 1A60 str r2, [r3] + 11301 .L607: +6036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11302 .loc 1 6036 5 is_stmt 1 view .LVU3609 +6036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11303 .loc 1 6036 9 is_stmt 0 view .LVU3610 + 11304 0086 A06B ldr r0, [r4, #56] + 11305 0088 FFF7FEFF bl HAL_DMA_GetState + 11306 .LVL803: +6036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11307 .loc 1 6036 8 view .LVU3611 + 11308 008c 0128 cmp r0, #1 + 11309 008e 0ED0 beq .L608 +6040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11310 .loc 1 6040 7 is_stmt 1 view .LVU3612 +6040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11311 .loc 1 6040 11 is_stmt 0 view .LVU3613 + ARM GAS /tmp/ccth6daj.s page 378 + + + 11312 0090 A36B ldr r3, [r4, #56] +6040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11313 .loc 1 6040 39 view .LVU3614 + 11314 0092 1D4A ldr r2, .L614+16 + 11315 0094 9A63 str r2, [r3, #56] +6043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11316 .loc 1 6043 7 is_stmt 1 view .LVU3615 +6043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11317 .loc 1 6043 7 view .LVU3616 + 11318 0096 4023 movs r3, #64 + 11319 0098 0022 movs r2, #0 + 11320 009a E254 strb r2, [r4, r3] +6043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11321 .loc 1 6043 7 view .LVU3617 +6046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11322 .loc 1 6046 7 view .LVU3618 +6046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11323 .loc 1 6046 11 is_stmt 0 view .LVU3619 + 11324 009c A06B ldr r0, [r4, #56] + 11325 009e FFF7FEFF bl HAL_DMA_Abort_IT + 11326 .LVL804: +6046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11327 .loc 1 6046 10 view .LVU3620 + 11328 00a2 0028 cmp r0, #0 + 11329 00a4 D8D0 beq .L601 +6049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11330 .loc 1 6049 9 is_stmt 1 view .LVU3621 +6049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11331 .loc 1 6049 13 is_stmt 0 view .LVU3622 + 11332 00a6 A06B ldr r0, [r4, #56] +6049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11333 .loc 1 6049 21 view .LVU3623 + 11334 00a8 836B ldr r3, [r0, #56] +6049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11335 .loc 1 6049 9 view .LVU3624 + 11336 00aa 9847 blx r3 + 11337 .LVL805: + 11338 00ac D4E7 b .L601 + 11339 .L608: +6054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11340 .loc 1 6054 7 is_stmt 1 view .LVU3625 + 11341 00ae 2000 movs r0, r4 + 11342 00b0 FFF7FEFF bl I2C_TreatErrorCallback + 11343 .LVL806: + 11344 00b4 D0E7 b .L601 + 11345 .LVL807: + 11346 .L611: +6061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11347 .loc 1 6061 5 view .LVU3626 +6061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11348 .loc 1 6061 14 is_stmt 0 view .LVU3627 + 11349 00b6 2368 ldr r3, [r4] + 11350 .LVL808: +6061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11351 .loc 1 6061 24 view .LVU3628 + 11352 00b8 1A68 ldr r2, [r3] +6061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 379 + + + 11353 .loc 1 6061 8 view .LVU3629 + 11354 00ba 1204 lsls r2, r2, #16 + 11355 00bc 03D5 bpl .L612 +6063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11356 .loc 1 6063 7 is_stmt 1 view .LVU3630 +6063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11357 .loc 1 6063 27 is_stmt 0 view .LVU3631 + 11358 00be 1A68 ldr r2, [r3] + 11359 00c0 1249 ldr r1, .L614+20 + 11360 00c2 0A40 ands r2, r1 + 11361 00c4 1A60 str r2, [r3] + 11362 .L612: +6066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11363 .loc 1 6066 5 is_stmt 1 view .LVU3632 +6066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11364 .loc 1 6066 9 is_stmt 0 view .LVU3633 + 11365 00c6 E06B ldr r0, [r4, #60] + 11366 00c8 FFF7FEFF bl HAL_DMA_GetState + 11367 .LVL809: +6066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11368 .loc 1 6066 8 view .LVU3634 + 11369 00cc 0128 cmp r0, #1 + 11370 00ce 0ED0 beq .L613 +6070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11371 .loc 1 6070 7 is_stmt 1 view .LVU3635 +6070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11372 .loc 1 6070 11 is_stmt 0 view .LVU3636 + 11373 00d0 E36B ldr r3, [r4, #60] +6070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11374 .loc 1 6070 39 view .LVU3637 + 11375 00d2 0D4A ldr r2, .L614+16 + 11376 00d4 9A63 str r2, [r3, #56] +6073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11377 .loc 1 6073 7 is_stmt 1 view .LVU3638 +6073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11378 .loc 1 6073 7 view .LVU3639 + 11379 00d6 4023 movs r3, #64 + 11380 00d8 0022 movs r2, #0 + 11381 00da E254 strb r2, [r4, r3] +6073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11382 .loc 1 6073 7 view .LVU3640 +6076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11383 .loc 1 6076 7 view .LVU3641 +6076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11384 .loc 1 6076 11 is_stmt 0 view .LVU3642 + 11385 00dc E06B ldr r0, [r4, #60] + 11386 00de FFF7FEFF bl HAL_DMA_Abort_IT + 11387 .LVL810: +6076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11388 .loc 1 6076 10 view .LVU3643 + 11389 00e2 0028 cmp r0, #0 + 11390 00e4 B8D0 beq .L601 +6079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11391 .loc 1 6079 9 is_stmt 1 view .LVU3644 +6079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11392 .loc 1 6079 13 is_stmt 0 view .LVU3645 + 11393 00e6 E06B ldr r0, [r4, #60] + ARM GAS /tmp/ccth6daj.s page 380 + + +6079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11394 .loc 1 6079 21 view .LVU3646 + 11395 00e8 836B ldr r3, [r0, #56] +6079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11396 .loc 1 6079 9 view .LVU3647 + 11397 00ea 9847 blx r3 + 11398 .LVL811: + 11399 00ec B4E7 b .L601 + 11400 .L613: +6084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11401 .loc 1 6084 7 is_stmt 1 view .LVU3648 + 11402 00ee 2000 movs r0, r4 + 11403 00f0 FFF7FEFF bl I2C_TreatErrorCallback + 11404 .LVL812: + 11405 00f4 B0E7 b .L601 + 11406 .L615: + 11407 00f6 C046 .align 2 + 11408 .L614: + 11409 00f8 0000FFFF .word -65536 + 11410 00fc 00000000 .word I2C_Slave_ISR_IT + 11411 0100 03800000 .word 32771 + 11412 0104 FFBFFFFF .word -16385 + 11413 0108 00000000 .word I2C_DMAAbort + 11414 010c FF7FFFFF .word -32769 + 11415 .cfi_endproc + 11416 .LFE358: + 11418 .section .text.I2C_ITSlaveCplt,"ax",%progbits + 11419 .align 1 + 11420 .syntax unified + 11421 .code 16 + 11422 .thumb_func + 11423 .fpu softvfp + 11425 I2C_ITSlaveCplt: + 11426 .LVL813: + 11427 .LFB356: +5777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 11428 .loc 1 5777 1 view -0 + 11429 .cfi_startproc + 11430 @ args = 0, pretend = 0, frame = 0 + 11431 @ frame_needed = 0, uses_anonymous_args = 0 +5777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 11432 .loc 1 5777 1 is_stmt 0 view .LVU3650 + 11433 0000 70B5 push {r4, r5, r6, lr} + 11434 .LCFI80: + 11435 .cfi_def_cfa_offset 16 + 11436 .cfi_offset 4, -16 + 11437 .cfi_offset 5, -12 + 11438 .cfi_offset 6, -8 + 11439 .cfi_offset 14, -4 + 11440 0002 0400 movs r4, r0 + 11441 0004 0D00 movs r5, r1 +5778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11442 .loc 1 5778 3 is_stmt 1 view .LVU3651 +5778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11443 .loc 1 5778 26 is_stmt 0 view .LVU3652 + 11444 0006 0268 ldr r2, [r0] +5778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + ARM GAS /tmp/ccth6daj.s page 381 + + + 11445 .loc 1 5778 12 view .LVU3653 + 11446 0008 1668 ldr r6, [r2] + 11447 .LVL814: +5779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 11448 .loc 1 5779 3 is_stmt 1 view .LVU3654 +5780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11449 .loc 1 5780 3 view .LVU3655 +5780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11450 .loc 1 5780 24 is_stmt 0 view .LVU3656 + 11451 000a 4123 movs r3, #65 + 11452 000c C35C ldrb r3, [r0, r3] + 11453 000e D9B2 uxtb r1, r3 + 11454 .LVL815: +5783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11455 .loc 1 5783 3 is_stmt 1 view .LVU3657 + 11456 0010 2020 movs r0, #32 + 11457 .LVL816: +5783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11458 .loc 1 5783 3 is_stmt 0 view .LVU3658 + 11459 0012 D061 str r0, [r2, #28] +5786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11460 .loc 1 5786 3 is_stmt 1 view .LVU3659 +5786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11461 .loc 1 5786 6 is_stmt 0 view .LVU3660 + 11462 0014 212B cmp r3, #33 + 11463 0016 0CD0 beq .L617 +5786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11464 .loc 1 5786 43 discriminator 1 view .LVU3661 + 11465 0018 2929 cmp r1, #41 + 11466 001a 0AD0 beq .L617 +5791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11467 .loc 1 5791 8 is_stmt 1 view .LVU3662 +5791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11468 .loc 1 5791 11 is_stmt 0 view .LVU3663 + 11469 001c 2229 cmp r1, #34 + 11470 001e 01D0 beq .L620 +5791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11471 .loc 1 5791 48 discriminator 1 view .LVU3664 + 11472 0020 2A29 cmp r1, #42 + 11473 0022 0CD1 bne .L619 + 11474 .L620: +5793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 11475 .loc 1 5793 5 is_stmt 1 view .LVU3665 + 11476 0024 4A49 ldr r1, .L632 + 11477 .LVL817: +5793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 11478 .loc 1 5793 5 is_stmt 0 view .LVU3666 + 11479 0026 2000 movs r0, r4 + 11480 0028 FFF7FEFF bl I2C_Disable_IRQ + 11481 .LVL818: +5794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11482 .loc 1 5794 5 is_stmt 1 view .LVU3667 +5794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11483 .loc 1 5794 25 is_stmt 0 view .LVU3668 + 11484 002c 2223 movs r3, #34 + 11485 002e 2363 str r3, [r4, #48] + 11486 0030 05E0 b .L619 + ARM GAS /tmp/ccth6daj.s page 382 + + + 11487 .LVL819: + 11488 .L617: +5788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 11489 .loc 1 5788 5 is_stmt 1 view .LVU3669 + 11490 0032 4849 ldr r1, .L632+4 + 11491 .LVL820: +5788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 11492 .loc 1 5788 5 is_stmt 0 view .LVU3670 + 11493 0034 2000 movs r0, r4 + 11494 0036 FFF7FEFF bl I2C_Disable_IRQ + 11495 .LVL821: +5789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11496 .loc 1 5789 5 is_stmt 1 view .LVU3671 +5789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11497 .loc 1 5789 25 is_stmt 0 view .LVU3672 + 11498 003a 2123 movs r3, #33 + 11499 003c 2363 str r3, [r4, #48] + 11500 .L619: +5802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11501 .loc 1 5802 3 is_stmt 1 view .LVU3673 +5802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11502 .loc 1 5802 7 is_stmt 0 view .LVU3674 + 11503 003e 2268 ldr r2, [r4] +5802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11504 .loc 1 5802 23 view .LVU3675 + 11505 0040 5168 ldr r1, [r2, #4] + 11506 0042 8023 movs r3, #128 + 11507 0044 1B02 lsls r3, r3, #8 + 11508 0046 0B43 orrs r3, r1 + 11509 0048 5360 str r3, [r2, #4] +5805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11510 .loc 1 5805 3 is_stmt 1 view .LVU3676 + 11511 004a 2268 ldr r2, [r4] + 11512 004c 5368 ldr r3, [r2, #4] + 11513 004e 4249 ldr r1, .L632+8 + 11514 0050 0B40 ands r3, r1 + 11515 0052 5360 str r3, [r2, #4] +5808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11516 .loc 1 5808 3 view .LVU3677 + 11517 0054 2000 movs r0, r4 + 11518 0056 FFF7FEFF bl I2C_Flush_TXDR + 11519 .LVL822: +5811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11520 .loc 1 5811 3 view .LVU3678 +5811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11521 .loc 1 5811 6 is_stmt 0 view .LVU3679 + 11522 005a 7304 lsls r3, r6, #17 + 11523 005c 41D5 bpl .L621 +5814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11524 .loc 1 5814 5 is_stmt 1 view .LVU3680 +5814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11525 .loc 1 5814 9 is_stmt 0 view .LVU3681 + 11526 005e 2268 ldr r2, [r4] +5814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11527 .loc 1 5814 25 view .LVU3682 + 11528 0060 1368 ldr r3, [r2] + 11529 0062 3E49 ldr r1, .L632+12 + ARM GAS /tmp/ccth6daj.s page 383 + + + 11530 0064 0B40 ands r3, r1 + 11531 0066 1360 str r3, [r2] +5816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11532 .loc 1 5816 5 is_stmt 1 view .LVU3683 +5816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11533 .loc 1 5816 13 is_stmt 0 view .LVU3684 + 11534 0068 A36B ldr r3, [r4, #56] +5816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11535 .loc 1 5816 8 view .LVU3685 + 11536 006a 002B cmp r3, #0 + 11537 006c 03D0 beq .L622 +5818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11538 .loc 1 5818 7 is_stmt 1 view .LVU3686 +5818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11539 .loc 1 5818 35 is_stmt 0 view .LVU3687 + 11540 006e 1B68 ldr r3, [r3] + 11541 0070 5B68 ldr r3, [r3, #4] +5818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11542 .loc 1 5818 25 view .LVU3688 + 11543 0072 9BB2 uxth r3, r3 +5818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11544 .loc 1 5818 23 view .LVU3689 + 11545 0074 6385 strh r3, [r4, #42] + 11546 .L622: +5834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11547 .loc 1 5834 3 is_stmt 1 view .LVU3690 +5837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11548 .loc 1 5837 3 view .LVU3691 +5837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11549 .loc 1 5837 6 is_stmt 0 view .LVU3692 + 11550 0076 6B07 lsls r3, r5, #29 + 11551 0078 11D5 bpl .L623 +5840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11552 .loc 1 5840 5 is_stmt 1 view .LVU3693 +5840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11553 .loc 1 5840 16 is_stmt 0 view .LVU3694 + 11554 007a 0423 movs r3, #4 + 11555 007c 9D43 bics r5, r3 + 11556 .LVL823: +5843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11557 .loc 1 5843 5 is_stmt 1 view .LVU3695 +5843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11558 .loc 1 5843 36 is_stmt 0 view .LVU3696 + 11559 007e 2368 ldr r3, [r4] +5843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11560 .loc 1 5843 46 view .LVU3697 + 11561 0080 5B6A ldr r3, [r3, #36] +5843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11562 .loc 1 5843 21 view .LVU3698 + 11563 0082 626A ldr r2, [r4, #36] + 11564 0084 1370 strb r3, [r2] +5846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11565 .loc 1 5846 5 is_stmt 1 view .LVU3699 +5846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11566 .loc 1 5846 19 is_stmt 0 view .LVU3700 + 11567 0086 636A ldr r3, [r4, #36] + 11568 0088 0133 adds r3, r3, #1 + ARM GAS /tmp/ccth6daj.s page 384 + + + 11569 008a 6362 str r3, [r4, #36] +5848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11570 .loc 1 5848 5 is_stmt 1 view .LVU3701 +5848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11571 .loc 1 5848 14 is_stmt 0 view .LVU3702 + 11572 008c 238D ldrh r3, [r4, #40] +5848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11573 .loc 1 5848 8 view .LVU3703 + 11574 008e 002B cmp r3, #0 + 11575 0090 05D0 beq .L623 +5850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 11576 .loc 1 5850 7 is_stmt 1 view .LVU3704 +5850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 11577 .loc 1 5850 21 is_stmt 0 view .LVU3705 + 11578 0092 013B subs r3, r3, #1 + 11579 0094 2385 strh r3, [r4, #40] +5851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11580 .loc 1 5851 7 is_stmt 1 view .LVU3706 +5851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11581 .loc 1 5851 11 is_stmt 0 view .LVU3707 + 11582 0096 638D ldrh r3, [r4, #42] +5851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11583 .loc 1 5851 22 view .LVU3708 + 11584 0098 013B subs r3, r3, #1 + 11585 009a 9BB2 uxth r3, r3 + 11586 009c 6385 strh r3, [r4, #42] + 11587 .L623: +5856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11588 .loc 1 5856 3 is_stmt 1 view .LVU3709 +5856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11589 .loc 1 5856 11 is_stmt 0 view .LVU3710 + 11590 009e 638D ldrh r3, [r4, #42] + 11591 00a0 9BB2 uxth r3, r3 +5856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11592 .loc 1 5856 6 view .LVU3711 + 11593 00a2 002B cmp r3, #0 + 11594 00a4 03D0 beq .L624 +5859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11595 .loc 1 5859 5 is_stmt 1 view .LVU3712 +5859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11596 .loc 1 5859 21 is_stmt 0 view .LVU3713 + 11597 00a6 636C ldr r3, [r4, #68] + 11598 00a8 0422 movs r2, #4 + 11599 00aa 1343 orrs r3, r2 + 11600 00ac 6364 str r3, [r4, #68] + 11601 .L624: +5862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11602 .loc 1 5862 3 is_stmt 1 view .LVU3714 +5862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11603 .loc 1 5862 14 is_stmt 0 view .LVU3715 + 11604 00ae 0023 movs r3, #0 + 11605 00b0 4222 movs r2, #66 + 11606 00b2 A354 strb r3, [r4, r2] +5863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11607 .loc 1 5863 3 is_stmt 1 view .LVU3716 +5863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11608 .loc 1 5863 17 is_stmt 0 view .LVU3717 + ARM GAS /tmp/ccth6daj.s page 385 + + + 11609 00b4 6363 str r3, [r4, #52] +5865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11610 .loc 1 5865 3 is_stmt 1 view .LVU3718 +5865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11611 .loc 1 5865 11 is_stmt 0 view .LVU3719 + 11612 00b6 636C ldr r3, [r4, #68] +5865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11613 .loc 1 5865 6 view .LVU3720 + 11614 00b8 002B cmp r3, #0 + 11615 00ba 21D1 bne .L629 +5877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11616 .loc 1 5877 8 is_stmt 1 view .LVU3721 +5877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11617 .loc 1 5877 16 is_stmt 0 view .LVU3722 + 11618 00bc E26A ldr r2, [r4, #44] +5877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11619 .loc 1 5877 11 view .LVU3723 + 11620 00be 284B ldr r3, .L632+16 + 11621 00c0 9A42 cmp r2, r3 + 11622 00c2 2AD1 bne .L630 +5897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11623 .loc 1 5897 8 is_stmt 1 view .LVU3724 +5897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11624 .loc 1 5897 16 is_stmt 0 view .LVU3725 + 11625 00c4 4123 movs r3, #65 + 11626 00c6 E35C ldrb r3, [r4, r3] +5897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11627 .loc 1 5897 11 view .LVU3726 + 11628 00c8 222B cmp r3, #34 + 11629 00ca 36D0 beq .L631 +5914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11630 .loc 1 5914 5 is_stmt 1 view .LVU3727 +5914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11631 .loc 1 5914 17 is_stmt 0 view .LVU3728 + 11632 00cc 4123 movs r3, #65 + 11633 00ce 2022 movs r2, #32 + 11634 00d0 E254 strb r2, [r4, r3] +5915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11635 .loc 1 5915 5 is_stmt 1 view .LVU3729 +5915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11636 .loc 1 5915 25 is_stmt 0 view .LVU3730 + 11637 00d2 0023 movs r3, #0 + 11638 00d4 2363 str r3, [r4, #48] +5918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11639 .loc 1 5918 5 is_stmt 1 view .LVU3731 +5918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11640 .loc 1 5918 5 view .LVU3732 + 11641 00d6 2032 adds r2, r2, #32 + 11642 00d8 A354 strb r3, [r4, r2] +5918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11643 .loc 1 5918 5 view .LVU3733 +5924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11644 .loc 1 5924 5 view .LVU3734 + 11645 00da 2000 movs r0, r4 + 11646 00dc FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 11647 .LVL824: +5927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 386 + + + 11648 .loc 1 5927 1 is_stmt 0 view .LVU3735 + 11649 00e0 2AE0 b .L616 + 11650 .LVL825: + 11651 .L621: +5821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11652 .loc 1 5821 8 is_stmt 1 view .LVU3736 +5821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11653 .loc 1 5821 11 is_stmt 0 view .LVU3737 + 11654 00e2 3304 lsls r3, r6, #16 + 11655 00e4 C7D5 bpl .L622 +5824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11656 .loc 1 5824 5 is_stmt 1 view .LVU3738 +5824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11657 .loc 1 5824 9 is_stmt 0 view .LVU3739 + 11658 00e6 2268 ldr r2, [r4] +5824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11659 .loc 1 5824 25 view .LVU3740 + 11660 00e8 1368 ldr r3, [r2] + 11661 00ea 1E49 ldr r1, .L632+20 + 11662 00ec 0B40 ands r3, r1 + 11663 00ee 1360 str r3, [r2] +5826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11664 .loc 1 5826 5 is_stmt 1 view .LVU3741 +5826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11665 .loc 1 5826 13 is_stmt 0 view .LVU3742 + 11666 00f0 E36B ldr r3, [r4, #60] +5826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11667 .loc 1 5826 8 view .LVU3743 + 11668 00f2 002B cmp r3, #0 + 11669 00f4 BFD0 beq .L622 +5828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11670 .loc 1 5828 7 is_stmt 1 view .LVU3744 +5828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11671 .loc 1 5828 35 is_stmt 0 view .LVU3745 + 11672 00f6 1B68 ldr r3, [r3] + 11673 00f8 5B68 ldr r3, [r3, #4] +5828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11674 .loc 1 5828 25 view .LVU3746 + 11675 00fa 9BB2 uxth r3, r3 +5828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11676 .loc 1 5828 23 view .LVU3747 + 11677 00fc 6385 strh r3, [r4, #42] + 11678 00fe BAE7 b .L622 + 11679 .LVL826: + 11680 .L629: +5868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11681 .loc 1 5868 5 is_stmt 1 view .LVU3748 + 11682 0100 616C ldr r1, [r4, #68] + 11683 0102 2000 movs r0, r4 + 11684 0104 FFF7FEFF bl I2C_ITError + 11685 .LVL827: +5871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11686 .loc 1 5871 5 view .LVU3749 +5871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11687 .loc 1 5871 13 is_stmt 0 view .LVU3750 + 11688 0108 4123 movs r3, #65 + 11689 010a E35C ldrb r3, [r4, r3] + ARM GAS /tmp/ccth6daj.s page 387 + + +5871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11690 .loc 1 5871 8 view .LVU3751 + 11691 010c 282B cmp r3, #40 + 11692 010e 13D1 bne .L616 +5874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11693 .loc 1 5874 7 is_stmt 1 view .LVU3752 + 11694 0110 2900 movs r1, r5 + 11695 0112 2000 movs r0, r4 + 11696 0114 FFF7FEFF bl I2C_ITListenCplt + 11697 .LVL828: + 11698 0118 0EE0 b .L616 + 11699 .L630: +5880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11700 .loc 1 5880 5 view .LVU3753 + 11701 011a 2000 movs r0, r4 + 11702 011c FFF7FEFF bl I2C_ITSlaveSeqCplt + 11703 .LVL829: +5882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11704 .loc 1 5882 5 view .LVU3754 +5882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11705 .loc 1 5882 23 is_stmt 0 view .LVU3755 + 11706 0120 0F4B ldr r3, .L632+16 + 11707 0122 E362 str r3, [r4, #44] +5883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11708 .loc 1 5883 5 is_stmt 1 view .LVU3756 +5883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11709 .loc 1 5883 17 is_stmt 0 view .LVU3757 + 11710 0124 4123 movs r3, #65 + 11711 0126 2022 movs r2, #32 + 11712 0128 E254 strb r2, [r4, r3] +5884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11713 .loc 1 5884 5 is_stmt 1 view .LVU3758 +5884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11714 .loc 1 5884 25 is_stmt 0 view .LVU3759 + 11715 012a 0023 movs r3, #0 + 11716 012c 2363 str r3, [r4, #48] +5887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11717 .loc 1 5887 5 is_stmt 1 view .LVU3760 +5887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11718 .loc 1 5887 5 view .LVU3761 + 11719 012e 2032 adds r2, r2, #32 + 11720 0130 A354 strb r3, [r4, r2] +5887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11721 .loc 1 5887 5 view .LVU3762 +5893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11722 .loc 1 5893 5 view .LVU3763 + 11723 0132 2000 movs r0, r4 + 11724 0134 FFF7FEFF bl HAL_I2C_ListenCpltCallback + 11725 .LVL830: + 11726 .L616: +5927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11727 .loc 1 5927 1 is_stmt 0 view .LVU3764 + 11728 @ sp needed + 11729 .LVL831: + 11730 .LVL832: + 11731 .LVL833: +5927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 388 + + + 11732 .loc 1 5927 1 view .LVU3765 + 11733 0138 70BD pop {r4, r5, r6, pc} + 11734 .LVL834: + 11735 .L631: +5899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11736 .loc 1 5899 5 is_stmt 1 view .LVU3766 +5899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 11737 .loc 1 5899 17 is_stmt 0 view .LVU3767 + 11738 013a 1F33 adds r3, r3, #31 + 11739 013c 2022 movs r2, #32 + 11740 013e E254 strb r2, [r4, r3] +5900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11741 .loc 1 5900 5 is_stmt 1 view .LVU3768 +5900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11742 .loc 1 5900 25 is_stmt 0 view .LVU3769 + 11743 0140 0023 movs r3, #0 + 11744 0142 2363 str r3, [r4, #48] +5903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11745 .loc 1 5903 5 is_stmt 1 view .LVU3770 +5903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11746 .loc 1 5903 5 view .LVU3771 + 11747 0144 2032 adds r2, r2, #32 + 11748 0146 A354 strb r3, [r4, r2] +5903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11749 .loc 1 5903 5 view .LVU3772 +5909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11750 .loc 1 5909 5 view .LVU3773 + 11751 0148 2000 movs r0, r4 + 11752 014a FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 11753 .LVL835: + 11754 014e F3E7 b .L616 + 11755 .L633: + 11756 .align 2 + 11757 .L632: + 11758 0150 02800000 .word 32770 + 11759 0154 01800000 .word 32769 + 11760 0158 00E800FE .word -33495040 + 11761 015c FFBFFFFF .word -16385 + 11762 0160 0000FFFF .word -65536 + 11763 0164 FF7FFFFF .word -32769 + 11764 .cfi_endproc + 11765 .LFE356: + 11767 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 11768 .align 1 + 11769 .syntax unified + 11770 .code 16 + 11771 .thumb_func + 11772 .fpu softvfp + 11774 I2C_Slave_ISR_IT: + 11775 .LVL836: + 11776 .LFB347: +4883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11777 .loc 1 4883 1 view -0 + 11778 .cfi_startproc + 11779 @ args = 0, pretend = 0, frame = 0 + 11780 @ frame_needed = 0, uses_anonymous_args = 0 +4883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + ARM GAS /tmp/ccth6daj.s page 389 + + + 11781 .loc 1 4883 1 is_stmt 0 view .LVU3775 + 11782 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 11783 .LCFI81: + 11784 .cfi_def_cfa_offset 24 + 11785 .cfi_offset 3, -24 + 11786 .cfi_offset 4, -20 + 11787 .cfi_offset 5, -16 + 11788 .cfi_offset 6, -12 + 11789 .cfi_offset 7, -8 + 11790 .cfi_offset 14, -4 + 11791 0002 0400 movs r4, r0 + 11792 0004 0D00 movs r5, r1 + 11793 0006 1600 movs r6, r2 +4884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11794 .loc 1 4884 3 is_stmt 1 view .LVU3776 +4884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 11795 .loc 1 4884 12 is_stmt 0 view .LVU3777 + 11796 0008 C76A ldr r7, [r0, #44] + 11797 .LVL837: +4885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11798 .loc 1 4885 3 is_stmt 1 view .LVU3778 +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11799 .loc 1 4888 3 view .LVU3779 +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11800 .loc 1 4888 3 view .LVU3780 + 11801 000a 4023 movs r3, #64 + 11802 000c C35C ldrb r3, [r0, r3] + 11803 000e 012B cmp r3, #1 + 11804 0010 00D1 bne .LCB11064 + 11805 0012 96E0 b .L648 @long jump + 11806 .LCB11064: +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11807 .loc 1 4888 3 discriminator 2 view .LVU3781 + 11808 0014 0123 movs r3, #1 + 11809 0016 4022 movs r2, #64 + 11810 .LVL838: +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11811 .loc 1 4888 3 is_stmt 0 discriminator 2 view .LVU3782 + 11812 0018 8354 strb r3, [r0, r2] +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11813 .loc 1 4888 3 is_stmt 1 discriminator 2 view .LVU3783 +4891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11814 .loc 1 4891 3 discriminator 2 view .LVU3784 +4891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11815 .loc 1 4891 8 is_stmt 0 discriminator 2 view .LVU3785 + 11816 001a 4A09 lsrs r2, r1, #5 +4891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11817 .loc 1 4891 6 discriminator 2 view .LVU3786 + 11818 001c 1342 tst r3, r2 + 11819 001e 01D0 beq .L636 +4891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11820 .loc 1 4891 61 discriminator 1 view .LVU3787 + 11821 0020 B306 lsls r3, r6, #26 + 11822 0022 17D4 bmi .L649 + 11823 .LVL839: + 11824 .L636: +4898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + ARM GAS /tmp/ccth6daj.s page 390 + + + 11825 .loc 1 4898 3 is_stmt 1 view .LVU3788 +4898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11826 .loc 1 4898 6 is_stmt 0 view .LVU3789 + 11827 0024 EB06 lsls r3, r5, #27 + 11828 0026 40D5 bpl .L637 +4898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11829 .loc 1 4898 58 discriminator 1 view .LVU3790 + 11830 0028 F306 lsls r3, r6, #27 + 11831 002a 3ED5 bpl .L637 +4905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11832 .loc 1 4905 5 is_stmt 1 view .LVU3791 +4905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11833 .loc 1 4905 13 is_stmt 0 view .LVU3792 + 11834 002c 638D ldrh r3, [r4, #42] + 11835 002e 9BB2 uxth r3, r3 +4905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11836 .loc 1 4905 8 view .LVU3793 + 11837 0030 002B cmp r3, #0 + 11838 0032 28D1 bne .L638 +4907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11839 .loc 1 4907 7 is_stmt 1 view .LVU3794 +4907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11840 .loc 1 4907 16 is_stmt 0 view .LVU3795 + 11841 0034 4133 adds r3, r3, #65 + 11842 0036 E35C ldrb r3, [r4, r3] +4907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11843 .loc 1 4907 10 view .LVU3796 + 11844 0038 282B cmp r3, #40 + 11845 003a 0ED0 beq .L650 + 11846 .L639: +4914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11847 .loc 1 4914 12 is_stmt 1 view .LVU3797 +4914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11848 .loc 1 4914 21 is_stmt 0 view .LVU3798 + 11849 003c 4123 movs r3, #65 + 11850 003e E35C ldrb r3, [r4, r3] +4914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11851 .loc 1 4914 15 view .LVU3799 + 11852 0040 292B cmp r3, #41 + 11853 0042 13D0 beq .L651 + 11854 .L641: +4929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11855 .loc 1 4929 9 is_stmt 1 view .LVU3800 + 11856 0044 2368 ldr r3, [r4] + 11857 0046 1022 movs r2, #16 + 11858 0048 DA61 str r2, [r3, #28] + 11859 .L640: +5006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11860 .loc 1 5006 3 view .LVU3801 +5009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11861 .loc 1 5009 3 view .LVU3802 +5009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11862 .loc 1 5009 3 view .LVU3803 + 11863 004a 4023 movs r3, #64 + 11864 004c 0022 movs r2, #0 + 11865 004e E254 strb r2, [r4, r3] +5009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 391 + + + 11866 .loc 1 5009 3 view .LVU3804 +5011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11867 .loc 1 5011 3 view .LVU3805 +5011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11868 .loc 1 5011 10 is_stmt 0 view .LVU3806 + 11869 0050 0020 movs r0, #0 + 11870 .L635: +5012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11871 .loc 1 5012 1 view .LVU3807 + 11872 @ sp needed + 11873 .LVL840: + 11874 .LVL841: + 11875 .LVL842: + 11876 .LVL843: +5012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11877 .loc 1 5012 1 view .LVU3808 + 11878 0052 F8BD pop {r3, r4, r5, r6, r7, pc} + 11879 .LVL844: + 11880 .L649: +4895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11881 .loc 1 4895 5 is_stmt 1 view .LVU3809 + 11882 0054 FFF7FEFF bl I2C_ITSlaveCplt + 11883 .LVL845: +4895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11884 .loc 1 4895 5 is_stmt 0 view .LVU3810 + 11885 0058 E4E7 b .L636 + 11886 .L650: +4907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 11887 .loc 1 4907 49 discriminator 1 view .LVU3811 + 11888 005a 8023 movs r3, #128 + 11889 005c 9B04 lsls r3, r3, #18 + 11890 005e 9F42 cmp r7, r3 + 11891 0060 ECD1 bne .L639 +4912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11892 .loc 1 4912 9 is_stmt 1 view .LVU3812 + 11893 0062 2900 movs r1, r5 + 11894 0064 2000 movs r0, r4 + 11895 0066 FFF7FEFF bl I2C_ITListenCplt + 11896 .LVL846: + 11897 006a EEE7 b .L640 + 11898 .L651: +4914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11899 .loc 1 4914 62 is_stmt 0 discriminator 1 view .LVU3813 + 11900 006c 364B ldr r3, .L653 + 11901 006e 9F42 cmp r7, r3 + 11902 0070 E8D0 beq .L641 +4917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11903 .loc 1 4917 9 is_stmt 1 view .LVU3814 + 11904 0072 2368 ldr r3, [r4] + 11905 0074 1022 movs r2, #16 + 11906 0076 DA61 str r2, [r3, #28] +4920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11907 .loc 1 4920 9 view .LVU3815 + 11908 0078 2000 movs r0, r4 + 11909 007a FFF7FEFF bl I2C_Flush_TXDR + 11910 .LVL847: +4924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 392 + + + 11911 .loc 1 4924 9 view .LVU3816 + 11912 007e 2000 movs r0, r4 + 11913 0080 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11914 .LVL848: + 11915 0084 E1E7 b .L640 + 11916 .L638: +4936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11917 .loc 1 4936 7 view .LVU3817 + 11918 0086 2368 ldr r3, [r4] + 11919 0088 1022 movs r2, #16 + 11920 008a DA61 str r2, [r3, #28] +4939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11921 .loc 1 4939 7 view .LVU3818 +4939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11922 .loc 1 4939 23 is_stmt 0 view .LVU3819 + 11923 008c 636C ldr r3, [r4, #68] + 11924 008e 0C3A subs r2, r2, #12 + 11925 0090 1343 orrs r3, r2 + 11926 0092 6364 str r3, [r4, #68] +4941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11927 .loc 1 4941 7 is_stmt 1 view .LVU3820 +4941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11928 .loc 1 4941 10 is_stmt 0 view .LVU3821 + 11929 0094 002F cmp r7, #0 + 11930 0096 03D0 beq .L642 +4941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11931 .loc 1 4941 43 discriminator 1 view .LVU3822 + 11932 0098 8023 movs r3, #128 + 11933 009a 5B04 lsls r3, r3, #17 + 11934 009c 9F42 cmp r7, r3 + 11935 009e D4D1 bne .L640 + 11936 .L642: +4944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11937 .loc 1 4944 9 is_stmt 1 view .LVU3823 + 11938 00a0 616C ldr r1, [r4, #68] + 11939 00a2 2000 movs r0, r4 + 11940 00a4 FFF7FEFF bl I2C_ITError + 11941 .LVL849: + 11942 00a8 CFE7 b .L640 + 11943 .L637: +4948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11944 .loc 1 4948 8 view .LVU3824 +4948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11945 .loc 1 4948 11 is_stmt 0 view .LVU3825 + 11946 00aa 6B07 lsls r3, r5, #29 + 11947 00ac 1ED5 bpl .L643 +4948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 11948 .loc 1 4948 65 discriminator 1 view .LVU3826 + 11949 00ae 7307 lsls r3, r6, #29 + 11950 00b0 1CD5 bpl .L643 +4951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11951 .loc 1 4951 5 is_stmt 1 view .LVU3827 +4951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 11952 .loc 1 4951 13 is_stmt 0 view .LVU3828 + 11953 00b2 638D ldrh r3, [r4, #42] + 11954 00b4 9BB2 uxth r3, r3 +4951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 393 + + + 11955 .loc 1 4951 8 view .LVU3829 + 11956 00b6 002B cmp r3, #0 + 11957 00b8 0DD0 beq .L644 +4954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11958 .loc 1 4954 7 is_stmt 1 view .LVU3830 +4954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11959 .loc 1 4954 38 is_stmt 0 view .LVU3831 + 11960 00ba 2368 ldr r3, [r4] +4954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11961 .loc 1 4954 48 view .LVU3832 + 11962 00bc 5B6A ldr r3, [r3, #36] +4954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11963 .loc 1 4954 23 view .LVU3833 + 11964 00be 626A ldr r2, [r4, #36] + 11965 00c0 1370 strb r3, [r2] +4957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11966 .loc 1 4957 7 is_stmt 1 view .LVU3834 +4957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 11967 .loc 1 4957 21 is_stmt 0 view .LVU3835 + 11968 00c2 636A ldr r3, [r4, #36] + 11969 00c4 0133 adds r3, r3, #1 + 11970 00c6 6362 str r3, [r4, #36] +4959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 11971 .loc 1 4959 7 is_stmt 1 view .LVU3836 +4959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 11972 .loc 1 4959 11 is_stmt 0 view .LVU3837 + 11973 00c8 238D ldrh r3, [r4, #40] +4959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 11974 .loc 1 4959 21 view .LVU3838 + 11975 00ca 013B subs r3, r3, #1 + 11976 00cc 2385 strh r3, [r4, #40] +4960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11977 .loc 1 4960 7 is_stmt 1 view .LVU3839 +4960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11978 .loc 1 4960 11 is_stmt 0 view .LVU3840 + 11979 00ce 638D ldrh r3, [r4, #42] +4960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11980 .loc 1 4960 22 view .LVU3841 + 11981 00d0 013B subs r3, r3, #1 + 11982 00d2 9BB2 uxth r3, r3 + 11983 00d4 6385 strh r3, [r4, #42] + 11984 .L644: +4963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11985 .loc 1 4963 5 is_stmt 1 view .LVU3842 +4963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11986 .loc 1 4963 14 is_stmt 0 view .LVU3843 + 11987 00d6 638D ldrh r3, [r4, #42] + 11988 00d8 9BB2 uxth r3, r3 +4963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11989 .loc 1 4963 8 view .LVU3844 + 11990 00da 002B cmp r3, #0 + 11991 00dc B5D1 bne .L640 +4963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 11992 .loc 1 4963 33 discriminator 1 view .LVU3845 + 11993 00de 1A4B ldr r3, .L653 + 11994 00e0 9F42 cmp r7, r3 + 11995 00e2 B2D0 beq .L640 + ARM GAS /tmp/ccth6daj.s page 394 + + +4967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 11996 .loc 1 4967 7 is_stmt 1 view .LVU3846 + 11997 00e4 2000 movs r0, r4 + 11998 00e6 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11999 .LVL850: + 12000 00ea AEE7 b .L640 + 12001 .L643: +4970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 12002 .loc 1 4970 8 view .LVU3847 +4970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 12003 .loc 1 4970 11 is_stmt 0 view .LVU3848 + 12004 00ec 2B07 lsls r3, r5, #28 + 12005 00ee 01D5 bpl .L645 +4970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 12006 .loc 1 4970 65 discriminator 1 view .LVU3849 + 12007 00f0 3307 lsls r3, r6, #28 + 12008 00f2 16D4 bmi .L652 + 12009 .L645: +4975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12010 .loc 1 4975 8 is_stmt 1 view .LVU3850 +4975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12011 .loc 1 4975 11 is_stmt 0 view .LVU3851 + 12012 00f4 AB07 lsls r3, r5, #30 + 12013 00f6 A8D5 bpl .L640 +4975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12014 .loc 1 4975 65 discriminator 1 view .LVU3852 + 12015 00f8 B307 lsls r3, r6, #30 + 12016 00fa A6D5 bpl .L640 +4982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12017 .loc 1 4982 5 is_stmt 1 view .LVU3853 +4982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12018 .loc 1 4982 13 is_stmt 0 view .LVU3854 + 12019 00fc 638D ldrh r3, [r4, #42] + 12020 00fe 9BB2 uxth r3, r3 +4982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12021 .loc 1 4982 8 view .LVU3855 + 12022 0100 002B cmp r3, #0 + 12023 0102 13D0 beq .L646 +4985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12024 .loc 1 4985 7 is_stmt 1 view .LVU3856 +4985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12025 .loc 1 4985 11 is_stmt 0 view .LVU3857 + 12026 0104 2368 ldr r3, [r4] +4985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12027 .loc 1 4985 30 view .LVU3858 + 12028 0106 626A ldr r2, [r4, #36] + 12029 0108 1278 ldrb r2, [r2] +4985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12030 .loc 1 4985 28 view .LVU3859 + 12031 010a 9A62 str r2, [r3, #40] +4988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12032 .loc 1 4988 7 is_stmt 1 view .LVU3860 +4988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12033 .loc 1 4988 21 is_stmt 0 view .LVU3861 + 12034 010c 636A ldr r3, [r4, #36] + 12035 010e 0133 adds r3, r3, #1 + 12036 0110 6362 str r3, [r4, #36] + ARM GAS /tmp/ccth6daj.s page 395 + + +4990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 12037 .loc 1 4990 7 is_stmt 1 view .LVU3862 +4990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 12038 .loc 1 4990 11 is_stmt 0 view .LVU3863 + 12039 0112 638D ldrh r3, [r4, #42] +4990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize--; + 12040 .loc 1 4990 22 view .LVU3864 + 12041 0114 013B subs r3, r3, #1 + 12042 0116 9BB2 uxth r3, r3 + 12043 0118 6385 strh r3, [r4, #42] +4991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12044 .loc 1 4991 7 is_stmt 1 view .LVU3865 +4991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12045 .loc 1 4991 11 is_stmt 0 view .LVU3866 + 12046 011a 238D ldrh r3, [r4, #40] +4991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12047 .loc 1 4991 21 view .LVU3867 + 12048 011c 013B subs r3, r3, #1 + 12049 011e 2385 strh r3, [r4, #40] + 12050 0120 93E7 b .L640 + 12051 .L652: +4973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12052 .loc 1 4973 5 is_stmt 1 view .LVU3868 + 12053 0122 2900 movs r1, r5 + 12054 0124 2000 movs r0, r4 + 12055 0126 FFF7FEFF bl I2C_ITAddrCplt + 12056 .LVL851: + 12057 012a 8EE7 b .L640 + 12058 .L646: +4995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12059 .loc 1 4995 7 view .LVU3869 +4995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12060 .loc 1 4995 10 is_stmt 0 view .LVU3870 + 12061 012c 8023 movs r3, #128 + 12062 012e 5B04 lsls r3, r3, #17 + 12063 0130 9F42 cmp r7, r3 + 12064 0132 02D0 beq .L647 +4995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12065 .loc 1 4995 42 discriminator 1 view .LVU3871 + 12066 0134 002F cmp r7, #0 + 12067 0136 00D0 beq .LCB11351 + 12068 0138 87E7 b .L640 @long jump + 12069 .LCB11351: + 12070 .L647: +4999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12071 .loc 1 4999 9 is_stmt 1 view .LVU3872 + 12072 013a 2000 movs r0, r4 + 12073 013c FFF7FEFF bl I2C_ITSlaveSeqCplt + 12074 .LVL852: + 12075 0140 83E7 b .L640 + 12076 .LVL853: + 12077 .L648: +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12078 .loc 1 4888 3 is_stmt 0 view .LVU3873 + 12079 0142 0220 movs r0, #2 + 12080 .LVL854: +4888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 396 + + + 12081 .loc 1 4888 3 view .LVU3874 + 12082 0144 85E7 b .L635 + 12083 .L654: + 12084 0146 C046 .align 2 + 12085 .L653: + 12086 0148 0000FFFF .word -65536 + 12087 .cfi_endproc + 12088 .LFE347: + 12090 .section .text.I2C_ITMasterCplt,"ax",%progbits + 12091 .align 1 + 12092 .syntax unified + 12093 .code 16 + 12094 .thumb_func + 12095 .fpu softvfp + 12097 I2C_ITMasterCplt: + 12098 .LVL855: + 12099 .LFB355: +5634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; + 12100 .loc 1 5634 1 is_stmt 1 view -0 + 12101 .cfi_startproc + 12102 @ args = 0, pretend = 0, frame = 8 + 12103 @ frame_needed = 0, uses_anonymous_args = 0 +5634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; + 12104 .loc 1 5634 1 is_stmt 0 view .LVU3876 + 12105 0000 30B5 push {r4, r5, lr} + 12106 .LCFI82: + 12107 .cfi_def_cfa_offset 12 + 12108 .cfi_offset 4, -12 + 12109 .cfi_offset 5, -8 + 12110 .cfi_offset 14, -4 + 12111 0002 83B0 sub sp, sp, #12 + 12112 .LCFI83: + 12113 .cfi_def_cfa_offset 24 + 12114 0004 0400 movs r4, r0 + 12115 0006 0D00 movs r5, r1 +5635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12116 .loc 1 5635 3 is_stmt 1 view .LVU3877 +5636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** __IO uint32_t tmpreg; + 12117 .loc 1 5636 3 view .LVU3878 + 12118 .LVL856: +5637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12119 .loc 1 5637 3 view .LVU3879 +5640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12120 .loc 1 5640 3 view .LVU3880 + 12121 0008 0368 ldr r3, [r0] + 12122 000a 2022 movs r2, #32 + 12123 000c DA61 str r2, [r3, #28] +5643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12124 .loc 1 5643 3 view .LVU3881 +5643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12125 .loc 1 5643 11 is_stmt 0 view .LVU3882 + 12126 000e 4123 movs r3, #65 + 12127 0010 C35C ldrb r3, [r0, r3] +5643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12128 .loc 1 5643 6 view .LVU3883 + 12129 0012 212B cmp r3, #33 + 12130 0014 29D0 beq .L666 + ARM GAS /tmp/ccth6daj.s page 397 + + +5648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12131 .loc 1 5648 8 is_stmt 1 view .LVU3884 +5648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12132 .loc 1 5648 16 is_stmt 0 view .LVU3885 + 12133 0016 4123 movs r3, #65 + 12134 0018 C35C ldrb r3, [r0, r3] +5648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12135 .loc 1 5648 11 view .LVU3886 + 12136 001a 222B cmp r3, #34 + 12137 001c 2BD0 beq .L667 + 12138 .LVL857: + 12139 .L657: +5656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12140 .loc 1 5656 3 is_stmt 1 view .LVU3887 +5659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12141 .loc 1 5659 3 view .LVU3888 + 12142 001e 2268 ldr r2, [r4] + 12143 0020 5368 ldr r3, [r2, #4] + 12144 0022 3B49 ldr r1, .L672 + 12145 0024 0B40 ands r3, r1 + 12146 0026 5360 str r3, [r2, #4] +5662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12147 .loc 1 5662 3 view .LVU3889 +5662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12148 .loc 1 5662 23 is_stmt 0 view .LVU3890 + 12149 0028 0023 movs r3, #0 + 12150 002a 6363 str r3, [r4, #52] +5663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12151 .loc 1 5663 3 is_stmt 1 view .LVU3891 +5663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12152 .loc 1 5663 23 is_stmt 0 view .LVU3892 + 12153 002c 394B ldr r3, .L672+4 + 12154 002e E362 str r3, [r4, #44] +5665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12155 .loc 1 5665 3 is_stmt 1 view .LVU3893 +5665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12156 .loc 1 5665 6 is_stmt 0 view .LVU3894 + 12157 0030 EB06 lsls r3, r5, #27 + 12158 0032 06D5 bpl .L658 +5668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12159 .loc 1 5668 5 is_stmt 1 view .LVU3895 + 12160 0034 2368 ldr r3, [r4] + 12161 0036 1022 movs r2, #16 + 12162 0038 DA61 str r2, [r3, #28] +5671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12163 .loc 1 5671 5 view .LVU3896 +5671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12164 .loc 1 5671 21 is_stmt 0 view .LVU3897 + 12165 003a 636C ldr r3, [r4, #68] + 12166 003c 0C3A subs r2, r2, #12 + 12167 003e 1343 orrs r3, r2 + 12168 0040 6364 str r3, [r4, #68] + 12169 .L658: +5675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12170 .loc 1 5675 3 is_stmt 1 view .LVU3898 +5675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12171 .loc 1 5675 12 is_stmt 0 view .LVU3899 + ARM GAS /tmp/ccth6daj.s page 398 + + + 12172 0042 4123 movs r3, #65 + 12173 0044 E35C ldrb r3, [r4, r3] +5675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12174 .loc 1 5675 6 view .LVU3900 + 12175 0046 602B cmp r3, #96 + 12176 0048 1BD0 beq .L668 + 12177 .L659: +5683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12178 .loc 1 5683 3 is_stmt 1 view .LVU3901 + 12179 004a 2000 movs r0, r4 + 12180 004c FFF7FEFF bl I2C_Flush_TXDR + 12181 .LVL858: +5686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12182 .loc 1 5686 3 view .LVU3902 +5686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12183 .loc 1 5686 12 is_stmt 0 view .LVU3903 + 12184 0050 626C ldr r2, [r4, #68] + 12185 .LVL859: +5689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12186 .loc 1 5689 3 is_stmt 1 view .LVU3904 +5689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12187 .loc 1 5689 12 is_stmt 0 view .LVU3905 + 12188 0052 4123 movs r3, #65 + 12189 0054 E35C ldrb r3, [r4, r3] +5689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12190 .loc 1 5689 6 view .LVU3906 + 12191 0056 602B cmp r3, #96 + 12192 0058 01D0 beq .L660 +5689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12193 .loc 1 5689 44 discriminator 1 view .LVU3907 + 12194 005a 002A cmp r2, #0 + 12195 005c 1AD0 beq .L661 + 12196 .L660: +5692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12197 .loc 1 5692 5 is_stmt 1 view .LVU3908 + 12198 005e 616C ldr r1, [r4, #68] + 12199 0060 2000 movs r0, r4 + 12200 0062 FFF7FEFF bl I2C_ITError + 12201 .LVL860: + 12202 .L655: +5768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12203 .loc 1 5768 1 is_stmt 0 view .LVU3909 + 12204 0066 03B0 add sp, sp, #12 + 12205 @ sp needed + 12206 .LVL861: + 12207 .LVL862: +5768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12208 .loc 1 5768 1 view .LVU3910 + 12209 0068 30BD pop {r4, r5, pc} + 12210 .LVL863: + 12211 .L666: +5645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 12212 .loc 1 5645 5 is_stmt 1 view .LVU3911 + 12213 006a 0121 movs r1, #1 + 12214 .LVL864: +5645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 12215 .loc 1 5645 5 is_stmt 0 view .LVU3912 + ARM GAS /tmp/ccth6daj.s page 399 + + + 12216 006c FFF7FEFF bl I2C_Disable_IRQ + 12217 .LVL865: +5646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12218 .loc 1 5646 5 is_stmt 1 view .LVU3913 +5646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12219 .loc 1 5646 25 is_stmt 0 view .LVU3914 + 12220 0070 1123 movs r3, #17 + 12221 0072 2363 str r3, [r4, #48] + 12222 0074 D3E7 b .L657 + 12223 .LVL866: + 12224 .L667: +5650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 12225 .loc 1 5650 5 is_stmt 1 view .LVU3915 + 12226 0076 0221 movs r1, #2 + 12227 .LVL867: +5650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 12228 .loc 1 5650 5 is_stmt 0 view .LVU3916 + 12229 0078 FFF7FEFF bl I2C_Disable_IRQ + 12230 .LVL868: +5651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12231 .loc 1 5651 5 is_stmt 1 view .LVU3917 +5651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12232 .loc 1 5651 25 is_stmt 0 view .LVU3918 + 12233 007c 1223 movs r3, #18 + 12234 007e 2363 str r3, [r4, #48] + 12235 0080 CDE7 b .L657 + 12236 .L668: +5675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12237 .loc 1 5675 44 discriminator 1 view .LVU3919 + 12238 0082 6B07 lsls r3, r5, #29 + 12239 0084 E1D5 bpl .L659 +5678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(tmpreg); + 12240 .loc 1 5678 5 is_stmt 1 view .LVU3920 +5678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(tmpreg); + 12241 .loc 1 5678 27 is_stmt 0 view .LVU3921 + 12242 0086 2368 ldr r3, [r4] +5678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(tmpreg); + 12243 .loc 1 5678 37 view .LVU3922 + 12244 0088 5A6A ldr r2, [r3, #36] + 12245 008a FF23 movs r3, #255 + 12246 008c 1340 ands r3, r2 +5678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** UNUSED(tmpreg); + 12247 .loc 1 5678 12 view .LVU3923 + 12248 008e 0193 str r3, [sp, #4] +5679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12249 .loc 1 5679 5 is_stmt 1 view .LVU3924 + 12250 0090 019B ldr r3, [sp, #4] + 12251 0092 DAE7 b .L659 + 12252 .LVL869: + 12253 .L661: +5695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12254 .loc 1 5695 8 view .LVU3925 +5695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12255 .loc 1 5695 16 is_stmt 0 view .LVU3926 + 12256 0094 4123 movs r3, #65 + 12257 0096 E35C ldrb r3, [r4, r3] +5695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 400 + + + 12258 .loc 1 5695 11 view .LVU3927 + 12259 0098 212B cmp r3, #33 + 12260 009a 15D0 beq .L669 +5730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12261 .loc 1 5730 8 is_stmt 1 view .LVU3928 +5730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12262 .loc 1 5730 16 is_stmt 0 view .LVU3929 + 12263 009c 4123 movs r3, #65 + 12264 009e E35C ldrb r3, [r4, r3] +5730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12265 .loc 1 5730 11 view .LVU3930 + 12266 00a0 222B cmp r3, #34 + 12267 00a2 E0D1 bne .L655 +5732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12268 .loc 1 5732 5 is_stmt 1 view .LVU3931 +5732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12269 .loc 1 5732 17 is_stmt 0 view .LVU3932 + 12270 00a4 1F33 adds r3, r3, #31 + 12271 00a6 2022 movs r2, #32 + 12272 .LVL870: +5732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12273 .loc 1 5732 17 view .LVU3933 + 12274 00a8 E254 strb r2, [r4, r3] +5733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12275 .loc 1 5733 5 is_stmt 1 view .LVU3934 +5733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12276 .loc 1 5733 25 is_stmt 0 view .LVU3935 + 12277 00aa 0023 movs r3, #0 + 12278 00ac 2363 str r3, [r4, #48] +5735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12279 .loc 1 5735 5 is_stmt 1 view .LVU3936 +5735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12280 .loc 1 5735 13 is_stmt 0 view .LVU3937 + 12281 00ae 4233 adds r3, r3, #66 + 12282 00b0 E35C ldrb r3, [r4, r3] +5735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12283 .loc 1 5735 8 view .LVU3938 + 12284 00b2 402B cmp r3, #64 + 12285 00b4 23D0 beq .L670 +5751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12286 .loc 1 5751 7 is_stmt 1 view .LVU3939 +5751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12287 .loc 1 5751 18 is_stmt 0 view .LVU3940 + 12288 00b6 0023 movs r3, #0 + 12289 00b8 4222 movs r2, #66 + 12290 00ba A354 strb r3, [r4, r2] +5754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12291 .loc 1 5754 7 is_stmt 1 view .LVU3941 +5754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12292 .loc 1 5754 7 view .LVU3942 + 12293 00bc 023A subs r2, r2, #2 + 12294 00be A354 strb r3, [r4, r2] +5754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12295 .loc 1 5754 7 view .LVU3943 +5760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12296 .loc 1 5760 7 view .LVU3944 + 12297 00c0 2000 movs r0, r4 + ARM GAS /tmp/ccth6daj.s page 401 + + + 12298 00c2 FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 12299 .LVL871: +5767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12300 .loc 1 5767 3 view .LVU3945 +5768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12301 .loc 1 5768 1 is_stmt 0 view .LVU3946 + 12302 00c6 CEE7 b .L655 + 12303 .LVL872: + 12304 .L669: +5697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12305 .loc 1 5697 5 is_stmt 1 view .LVU3947 +5697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12306 .loc 1 5697 17 is_stmt 0 view .LVU3948 + 12307 00c8 2033 adds r3, r3, #32 + 12308 00ca 2022 movs r2, #32 + 12309 .LVL873: +5697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12310 .loc 1 5697 17 view .LVU3949 + 12311 00cc E254 strb r2, [r4, r3] +5698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12312 .loc 1 5698 5 is_stmt 1 view .LVU3950 +5698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12313 .loc 1 5698 25 is_stmt 0 view .LVU3951 + 12314 00ce 0023 movs r3, #0 + 12315 00d0 2363 str r3, [r4, #48] +5700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12316 .loc 1 5700 5 is_stmt 1 view .LVU3952 +5700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12317 .loc 1 5700 13 is_stmt 0 view .LVU3953 + 12318 00d2 4233 adds r3, r3, #66 + 12319 00d4 E35C ldrb r3, [r4, r3] +5700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12320 .loc 1 5700 8 view .LVU3954 + 12321 00d6 402B cmp r3, #64 + 12322 00d8 08D0 beq .L671 +5716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12323 .loc 1 5716 7 is_stmt 1 view .LVU3955 +5716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12324 .loc 1 5716 18 is_stmt 0 view .LVU3956 + 12325 00da 0023 movs r3, #0 + 12326 00dc 4222 movs r2, #66 + 12327 00de A354 strb r3, [r4, r2] +5719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12328 .loc 1 5719 7 is_stmt 1 view .LVU3957 +5719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12329 .loc 1 5719 7 view .LVU3958 + 12330 00e0 023A subs r2, r2, #2 + 12331 00e2 A354 strb r3, [r4, r2] +5719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12332 .loc 1 5719 7 view .LVU3959 +5725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12333 .loc 1 5725 7 view .LVU3960 + 12334 00e4 2000 movs r0, r4 + 12335 00e6 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 12336 .LVL874: + 12337 00ea BCE7 b .L655 + 12338 .L671: + ARM GAS /tmp/ccth6daj.s page 402 + + +5702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12339 .loc 1 5702 7 view .LVU3961 +5702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12340 .loc 1 5702 18 is_stmt 0 view .LVU3962 + 12341 00ec 0023 movs r3, #0 + 12342 00ee 2232 adds r2, r2, #34 + 12343 00f0 A354 strb r3, [r4, r2] +5705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12344 .loc 1 5705 7 is_stmt 1 view .LVU3963 +5705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12345 .loc 1 5705 7 view .LVU3964 + 12346 00f2 023A subs r2, r2, #2 + 12347 00f4 A354 strb r3, [r4, r2] +5705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12348 .loc 1 5705 7 view .LVU3965 +5711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12349 .loc 1 5711 7 view .LVU3966 + 12350 00f6 2000 movs r0, r4 + 12351 00f8 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 12352 .LVL875: + 12353 00fc B3E7 b .L655 + 12354 .L670: +5737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12355 .loc 1 5737 7 view .LVU3967 +5737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12356 .loc 1 5737 18 is_stmt 0 view .LVU3968 + 12357 00fe 0023 movs r3, #0 + 12358 0100 2232 adds r2, r2, #34 + 12359 0102 A354 strb r3, [r4, r2] +5740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12360 .loc 1 5740 7 is_stmt 1 view .LVU3969 +5740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12361 .loc 1 5740 7 view .LVU3970 + 12362 0104 023A subs r2, r2, #2 + 12363 0106 A354 strb r3, [r4, r2] +5740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12364 .loc 1 5740 7 view .LVU3971 +5746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12365 .loc 1 5746 7 view .LVU3972 + 12366 0108 2000 movs r0, r4 + 12367 010a FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 12368 .LVL876: + 12369 010e AAE7 b .L655 + 12370 .L673: + 12371 .align 2 + 12372 .L672: + 12373 0110 00E800FE .word -33495040 + 12374 0114 0000FFFF .word -65536 + 12375 .cfi_endproc + 12376 .LFE355: + 12378 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 12379 .align 1 + 12380 .syntax unified + 12381 .code 16 + 12382 .thumb_func + 12383 .fpu softvfp + 12385 I2C_Master_ISR_IT: + ARM GAS /tmp/ccth6daj.s page 403 + + + 12386 .LVL877: + 12387 .LFB346: +4737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; + 12388 .loc 1 4737 1 view -0 + 12389 .cfi_startproc + 12390 @ args = 0, pretend = 0, frame = 0 + 12391 @ frame_needed = 0, uses_anonymous_args = 0 +4737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; + 12392 .loc 1 4737 1 is_stmt 0 view .LVU3974 + 12393 0000 70B5 push {r4, r5, r6, lr} + 12394 .LCFI84: + 12395 .cfi_def_cfa_offset 16 + 12396 .cfi_offset 4, -16 + 12397 .cfi_offset 5, -12 + 12398 .cfi_offset 6, -8 + 12399 .cfi_offset 14, -4 + 12400 0002 82B0 sub sp, sp, #8 + 12401 .LCFI85: + 12402 .cfi_def_cfa_offset 24 + 12403 0004 0400 movs r4, r0 + 12404 0006 0D00 movs r5, r1 + 12405 0008 1600 movs r6, r2 +4738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12406 .loc 1 4738 3 is_stmt 1 view .LVU3975 +4739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12407 .loc 1 4739 3 view .LVU3976 + 12408 .LVL878: +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12409 .loc 1 4742 3 view .LVU3977 +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12410 .loc 1 4742 3 view .LVU3978 + 12411 000a 4023 movs r3, #64 + 12412 000c C35C ldrb r3, [r0, r3] + 12413 000e 012B cmp r3, #1 + 12414 0010 00D1 bne .LCB11684 + 12415 0012 ADE0 b .L688 @long jump + 12416 .LCB11684: +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12417 .loc 1 4742 3 discriminator 2 view .LVU3979 + 12418 0014 0123 movs r3, #1 + 12419 0016 4022 movs r2, #64 + 12420 .LVL879: +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12421 .loc 1 4742 3 is_stmt 0 discriminator 2 view .LVU3980 + 12422 0018 8354 strb r3, [r0, r2] +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12423 .loc 1 4742 3 is_stmt 1 discriminator 2 view .LVU3981 +4744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12424 .loc 1 4744 3 discriminator 2 view .LVU3982 +4744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12425 .loc 1 4744 8 is_stmt 0 discriminator 2 view .LVU3983 + 12426 001a 0A09 lsrs r2, r1, #4 +4744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12427 .loc 1 4744 6 discriminator 2 view .LVU3984 + 12428 001c 1342 tst r3, r2 + 12429 001e 01D0 beq .L676 +4744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + ARM GAS /tmp/ccth6daj.s page 404 + + + 12430 .loc 1 4744 58 discriminator 1 view .LVU3985 + 12431 0020 F306 lsls r3, r6, #27 + 12432 0022 1ED4 bmi .L689 + 12433 .L676: +4758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12434 .loc 1 4758 8 is_stmt 1 view .LVU3986 +4758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12435 .loc 1 4758 11 is_stmt 0 view .LVU3987 + 12436 0024 6B07 lsls r3, r5, #29 + 12437 0026 26D5 bpl .L678 +4758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 12438 .loc 1 4758 65 discriminator 1 view .LVU3988 + 12439 0028 7307 lsls r3, r6, #29 + 12440 002a 24D5 bpl .L678 +4762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12441 .loc 1 4762 5 is_stmt 1 view .LVU3989 +4762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12442 .loc 1 4762 16 is_stmt 0 view .LVU3990 + 12443 002c 0423 movs r3, #4 + 12444 002e 9D43 bics r5, r3 + 12445 .LVL880: +4765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12446 .loc 1 4765 5 is_stmt 1 view .LVU3991 +4765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12447 .loc 1 4765 36 is_stmt 0 view .LVU3992 + 12448 0030 2368 ldr r3, [r4] +4765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12449 .loc 1 4765 46 view .LVU3993 + 12450 0032 5B6A ldr r3, [r3, #36] +4765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12451 .loc 1 4765 21 view .LVU3994 + 12452 0034 626A ldr r2, [r4, #36] + 12453 0036 1370 strb r3, [r2] +4768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12454 .loc 1 4768 5 is_stmt 1 view .LVU3995 +4768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12455 .loc 1 4768 19 is_stmt 0 view .LVU3996 + 12456 0038 636A ldr r3, [r4, #36] + 12457 003a 0133 adds r3, r3, #1 + 12458 003c 6362 str r3, [r4, #36] +4770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12459 .loc 1 4770 5 is_stmt 1 view .LVU3997 +4770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12460 .loc 1 4770 9 is_stmt 0 view .LVU3998 + 12461 003e 238D ldrh r3, [r4, #40] +4770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12462 .loc 1 4770 19 view .LVU3999 + 12463 0040 013B subs r3, r3, #1 + 12464 0042 2385 strh r3, [r4, #40] +4771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12465 .loc 1 4771 5 is_stmt 1 view .LVU4000 +4771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12466 .loc 1 4771 9 is_stmt 0 view .LVU4001 + 12467 0044 638D ldrh r3, [r4, #42] +4771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12468 .loc 1 4771 20 view .LVU4002 + 12469 0046 013B subs r3, r3, #1 + ARM GAS /tmp/ccth6daj.s page 405 + + + 12470 0048 9BB2 uxth r3, r3 + 12471 004a 6385 strh r3, [r4, #42] + 12472 .LVL881: + 12473 .L677: +4858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12474 .loc 1 4858 3 is_stmt 1 view .LVU4003 +4860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12475 .loc 1 4860 3 view .LVU4004 +4860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12476 .loc 1 4860 6 is_stmt 0 view .LVU4005 + 12477 004c AB06 lsls r3, r5, #26 + 12478 004e 02D5 bpl .L687 +4860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12479 .loc 1 4860 61 discriminator 1 view .LVU4006 + 12480 0050 B306 lsls r3, r6, #26 + 12481 0052 00D5 bpl .LCB11757 + 12482 0054 87E0 b .L690 @long jump + 12483 .LCB11757: + 12484 .L687: +4868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12485 .loc 1 4868 3 is_stmt 1 view .LVU4007 +4868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12486 .loc 1 4868 3 view .LVU4008 + 12487 0056 4023 movs r3, #64 + 12488 0058 0022 movs r2, #0 + 12489 005a E254 strb r2, [r4, r3] +4868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12490 .loc 1 4868 3 view .LVU4009 +4870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12491 .loc 1 4870 3 view .LVU4010 +4870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12492 .loc 1 4870 10 is_stmt 0 view .LVU4011 + 12493 005c 0020 movs r0, #0 + 12494 .L675: +4871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12495 .loc 1 4871 1 view .LVU4012 + 12496 005e 02B0 add sp, sp, #8 + 12497 @ sp needed + 12498 .LVL882: + 12499 .LVL883: + 12500 .LVL884: +4871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12501 .loc 1 4871 1 view .LVU4013 + 12502 0060 70BD pop {r4, r5, r6, pc} + 12503 .LVL885: + 12504 .L689: +4748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12505 .loc 1 4748 5 is_stmt 1 view .LVU4014 + 12506 0062 0368 ldr r3, [r0] + 12507 0064 1022 movs r2, #16 + 12508 0066 DA61 str r2, [r3, #28] +4753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12509 .loc 1 4753 5 view .LVU4015 +4753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12510 .loc 1 4753 21 is_stmt 0 view .LVU4016 + 12511 0068 436C ldr r3, [r0, #68] + 12512 006a 0C3A subs r2, r2, #12 + ARM GAS /tmp/ccth6daj.s page 406 + + + 12513 006c 1343 orrs r3, r2 + 12514 006e 4364 str r3, [r0, #68] +4756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12515 .loc 1 4756 5 is_stmt 1 view .LVU4017 + 12516 0070 FFF7FEFF bl I2C_Flush_TXDR + 12517 .LVL886: +4756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12518 .loc 1 4756 5 is_stmt 0 view .LVU4018 + 12519 0074 EAE7 b .L677 + 12520 .LVL887: + 12521 .L678: +4773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12522 .loc 1 4773 8 is_stmt 1 view .LVU4019 +4773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12523 .loc 1 4773 11 is_stmt 0 view .LVU4020 + 12524 0076 AB07 lsls r3, r5, #30 + 12525 0078 10D5 bpl .L679 +4773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 12526 .loc 1 4773 65 discriminator 1 view .LVU4021 + 12527 007a B307 lsls r3, r6, #30 + 12528 007c 0ED5 bpl .L679 +4777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12529 .loc 1 4777 5 is_stmt 1 view .LVU4022 +4777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12530 .loc 1 4777 9 is_stmt 0 view .LVU4023 + 12531 007e 2368 ldr r3, [r4] +4777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12532 .loc 1 4777 28 view .LVU4024 + 12533 0080 626A ldr r2, [r4, #36] + 12534 0082 1278 ldrb r2, [r2] +4777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12535 .loc 1 4777 26 view .LVU4025 + 12536 0084 9A62 str r2, [r3, #40] +4780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12537 .loc 1 4780 5 is_stmt 1 view .LVU4026 +4780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12538 .loc 1 4780 19 is_stmt 0 view .LVU4027 + 12539 0086 636A ldr r3, [r4, #36] + 12540 0088 0133 adds r3, r3, #1 + 12541 008a 6362 str r3, [r4, #36] +4782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12542 .loc 1 4782 5 is_stmt 1 view .LVU4028 +4782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12543 .loc 1 4782 9 is_stmt 0 view .LVU4029 + 12544 008c 238D ldrh r3, [r4, #40] +4782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferCount--; + 12545 .loc 1 4782 19 view .LVU4030 + 12546 008e 013B subs r3, r3, #1 + 12547 0090 2385 strh r3, [r4, #40] +4783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12548 .loc 1 4783 5 is_stmt 1 view .LVU4031 +4783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12549 .loc 1 4783 9 is_stmt 0 view .LVU4032 + 12550 0092 638D ldrh r3, [r4, #42] +4783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12551 .loc 1 4783 20 view .LVU4033 + 12552 0094 013B subs r3, r3, #1 + ARM GAS /tmp/ccth6daj.s page 407 + + + 12553 0096 9BB2 uxth r3, r3 + 12554 0098 6385 strh r3, [r4, #42] + 12555 009a D7E7 b .L677 + 12556 .L679: +4785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12557 .loc 1 4785 8 is_stmt 1 view .LVU4034 +4785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12558 .loc 1 4785 11 is_stmt 0 view .LVU4035 + 12559 009c 2B06 lsls r3, r5, #24 + 12560 009e 40D5 bpl .L680 +4785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12561 .loc 1 4785 64 discriminator 1 view .LVU4036 + 12562 00a0 7306 lsls r3, r6, #25 + 12563 00a2 3ED5 bpl .L680 +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12564 .loc 1 4788 5 is_stmt 1 view .LVU4037 +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12565 .loc 1 4788 14 is_stmt 0 view .LVU4038 + 12566 00a4 638D ldrh r3, [r4, #42] + 12567 00a6 9BB2 uxth r3, r3 +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12568 .loc 1 4788 8 view .LVU4039 + 12569 00a8 002B cmp r3, #0 + 12570 00aa 2DD0 beq .L681 +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12571 .loc 1 4788 41 discriminator 1 view .LVU4040 + 12572 00ac 238D ldrh r3, [r4, #40] +4788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12573 .loc 1 4788 33 discriminator 1 view .LVU4041 + 12574 00ae 002B cmp r3, #0 + 12575 00b0 2AD1 bne .L681 +4790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12576 .loc 1 4790 7 is_stmt 1 view .LVU4042 +4790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12577 .loc 1 4790 35 is_stmt 0 view .LVU4043 + 12578 00b2 2368 ldr r3, [r4] +4790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12579 .loc 1 4790 45 view .LVU4044 + 12580 00b4 5968 ldr r1, [r3, #4] + 12581 .LVL888: +4790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12582 .loc 1 4790 18 view .LVU4045 + 12583 00b6 8905 lsls r1, r1, #22 + 12584 00b8 890D lsrs r1, r1, #22 + 12585 .LVL889: +4792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12586 .loc 1 4792 7 is_stmt 1 view .LVU4046 +4792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12587 .loc 1 4792 15 is_stmt 0 view .LVU4047 + 12588 00ba 638D ldrh r3, [r4, #42] + 12589 00bc 9BB2 uxth r3, r3 +4792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12590 .loc 1 4792 10 view .LVU4048 + 12591 00be FF2B cmp r3, #255 + 12592 00c0 0ED8 bhi .L691 +4799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12593 .loc 1 4799 9 is_stmt 1 view .LVU4049 + ARM GAS /tmp/ccth6daj.s page 408 + + +4799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12594 .loc 1 4799 30 is_stmt 0 view .LVU4050 + 12595 00c2 628D ldrh r2, [r4, #42] + 12596 00c4 92B2 uxth r2, r2 +4799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 12597 .loc 1 4799 24 view .LVU4051 + 12598 00c6 2285 strh r2, [r4, #40] +4800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12599 .loc 1 4800 9 is_stmt 1 view .LVU4052 +4800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12600 .loc 1 4800 17 is_stmt 0 view .LVU4053 + 12601 00c8 E06A ldr r0, [r4, #44] + 12602 .LVL890: +4800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12603 .loc 1 4800 12 view .LVU4054 + 12604 00ca 2A4B ldr r3, .L692 + 12605 00cc 9842 cmp r0, r3 + 12606 00ce 12D0 beq .L683 +4802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 12607 .loc 1 4802 11 is_stmt 1 view .LVU4055 + 12608 00d0 E36A ldr r3, [r4, #44] + 12609 00d2 D2B2 uxtb r2, r2 + 12610 00d4 0020 movs r0, #0 + 12611 00d6 0090 str r0, [sp] + 12612 00d8 2000 movs r0, r4 + 12613 00da FFF7FEFF bl I2C_TransferConfig + 12614 .LVL891: +4802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 12615 .loc 1 4802 11 is_stmt 0 view .LVU4056 + 12616 00de B5E7 b .L677 + 12617 .LVL892: + 12618 .L691: +4794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 12619 .loc 1 4794 9 is_stmt 1 view .LVU4057 +4794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 12620 .loc 1 4794 24 is_stmt 0 view .LVU4058 + 12621 00e0 FF23 movs r3, #255 + 12622 00e2 2385 strh r3, [r4, #40] +4795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12623 .loc 1 4795 9 is_stmt 1 view .LVU4059 + 12624 00e4 7F3B subs r3, r3, #127 + 12625 00e6 0022 movs r2, #0 + 12626 00e8 0092 str r2, [sp] + 12627 00ea 5B04 lsls r3, r3, #17 + 12628 00ec FF32 adds r2, r2, #255 + 12629 00ee 2000 movs r0, r4 + 12630 .LVL893: +4795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12631 .loc 1 4795 9 is_stmt 0 view .LVU4060 + 12632 00f0 FFF7FEFF bl I2C_TransferConfig + 12633 .LVL894: +4795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12634 .loc 1 4795 9 view .LVU4061 + 12635 00f4 AAE7 b .L677 + 12636 .LVL895: + 12637 .L683: +4807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + ARM GAS /tmp/ccth6daj.s page 409 + + + 12638 .loc 1 4807 11 is_stmt 1 view .LVU4062 + 12639 00f6 8023 movs r3, #128 + 12640 00f8 D2B2 uxtb r2, r2 + 12641 00fa 0020 movs r0, #0 + 12642 00fc 0090 str r0, [sp] + 12643 00fe 9B04 lsls r3, r3, #18 + 12644 0100 2000 movs r0, r4 + 12645 0102 FFF7FEFF bl I2C_TransferConfig + 12646 .LVL896: +4807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + 12647 .loc 1 4807 11 is_stmt 0 view .LVU4063 + 12648 0106 A1E7 b .L677 + 12649 .LVL897: + 12650 .L681: +4815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12651 .loc 1 4815 7 is_stmt 1 view .LVU4064 +4815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12652 .loc 1 4815 11 is_stmt 0 view .LVU4065 + 12653 0108 2368 ldr r3, [r4] + 12654 010a 5B68 ldr r3, [r3, #4] +4815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12655 .loc 1 4815 10 view .LVU4066 + 12656 010c 9B01 lsls r3, r3, #6 + 12657 010e 03D4 bmi .L684 +4818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12658 .loc 1 4818 9 is_stmt 1 view .LVU4067 + 12659 0110 2000 movs r0, r4 + 12660 .LVL898: +4818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12661 .loc 1 4818 9 is_stmt 0 view .LVU4068 + 12662 0112 FFF7FEFF bl I2C_ITMasterSeqCplt + 12663 .LVL899: +4818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12664 .loc 1 4818 9 view .LVU4069 + 12665 0116 99E7 b .L677 + 12666 .LVL900: + 12667 .L684: +4824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12668 .loc 1 4824 9 is_stmt 1 view .LVU4070 + 12669 0118 4021 movs r1, #64 + 12670 .LVL901: +4824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12671 .loc 1 4824 9 is_stmt 0 view .LVU4071 + 12672 011a 2000 movs r0, r4 + 12673 .LVL902: +4824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12674 .loc 1 4824 9 view .LVU4072 + 12675 011c FFF7FEFF bl I2C_ITError + 12676 .LVL903: + 12677 0120 94E7 b .L677 + 12678 .LVL904: + 12679 .L680: +4828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12680 .loc 1 4828 8 is_stmt 1 view .LVU4073 +4828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12681 .loc 1 4828 11 is_stmt 0 view .LVU4074 + 12682 0122 6B06 lsls r3, r5, #25 + ARM GAS /tmp/ccth6daj.s page 410 + + + 12683 0124 00D4 bmi .LCB11981 + 12684 0126 91E7 b .L677 @long jump + 12685 .LCB11981: +4828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 12686 .loc 1 4828 63 discriminator 1 view .LVU4075 + 12687 0128 7306 lsls r3, r6, #25 + 12688 012a 00D4 bmi .LCB11986 + 12689 012c 8EE7 b .L677 @long jump + 12690 .LCB11986: +4831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12691 .loc 1 4831 5 is_stmt 1 view .LVU4076 +4831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12692 .loc 1 4831 13 is_stmt 0 view .LVU4077 + 12693 012e 638D ldrh r3, [r4, #42] + 12694 0130 9BB2 uxth r3, r3 +4831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12695 .loc 1 4831 8 view .LVU4078 + 12696 0132 002B cmp r3, #0 + 12697 0134 12D1 bne .L685 +4833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12698 .loc 1 4833 7 is_stmt 1 view .LVU4079 +4833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12699 .loc 1 4833 11 is_stmt 0 view .LVU4080 + 12700 0136 2368 ldr r3, [r4] + 12701 0138 5A68 ldr r2, [r3, #4] +4833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12702 .loc 1 4833 10 view .LVU4081 + 12703 013a 9201 lsls r2, r2, #6 + 12704 013c 00D5 bpl .LCB11998 + 12705 013e 85E7 b .L677 @long jump + 12706 .LCB11998: +4836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12707 .loc 1 4836 9 is_stmt 1 view .LVU4082 +4836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12708 .loc 1 4836 17 is_stmt 0 view .LVU4083 + 12709 0140 E16A ldr r1, [r4, #44] + 12710 .LVL905: +4836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12711 .loc 1 4836 12 view .LVU4084 + 12712 0142 0C4A ldr r2, .L692 + 12713 0144 9142 cmp r1, r2 + 12714 0146 05D1 bne .L686 +4839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12715 .loc 1 4839 11 is_stmt 1 view .LVU4085 +4839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12716 .loc 1 4839 31 is_stmt 0 view .LVU4086 + 12717 0148 5968 ldr r1, [r3, #4] + 12718 014a 8022 movs r2, #128 + 12719 014c D201 lsls r2, r2, #7 + 12720 014e 0A43 orrs r2, r1 + 12721 0150 5A60 str r2, [r3, #4] + 12722 0152 7BE7 b .L677 + 12723 .L686: +4844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12724 .loc 1 4844 11 is_stmt 1 view .LVU4087 + 12725 0154 2000 movs r0, r4 + 12726 .LVL906: + ARM GAS /tmp/ccth6daj.s page 411 + + +4844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12727 .loc 1 4844 11 is_stmt 0 view .LVU4088 + 12728 0156 FFF7FEFF bl I2C_ITMasterSeqCplt + 12729 .LVL907: + 12730 015a 77E7 b .L677 + 12731 .LVL908: + 12732 .L685: +4852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12733 .loc 1 4852 7 is_stmt 1 view .LVU4089 + 12734 015c 4021 movs r1, #64 + 12735 .LVL909: +4852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12736 .loc 1 4852 7 is_stmt 0 view .LVU4090 + 12737 015e 2000 movs r0, r4 + 12738 .LVL910: +4852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12739 .loc 1 4852 7 view .LVU4091 + 12740 0160 FFF7FEFF bl I2C_ITError + 12741 .LVL911: + 12742 0164 72E7 b .L677 + 12743 .LVL912: + 12744 .L690: +4864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12745 .loc 1 4864 5 is_stmt 1 view .LVU4092 + 12746 0166 2900 movs r1, r5 + 12747 0168 2000 movs r0, r4 + 12748 016a FFF7FEFF bl I2C_ITMasterCplt + 12749 .LVL913: + 12750 016e 72E7 b .L687 + 12751 .LVL914: + 12752 .L688: +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12753 .loc 1 4742 3 is_stmt 0 view .LVU4093 + 12754 0170 0220 movs r0, #2 + 12755 .LVL915: +4742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12756 .loc 1 4742 3 view .LVU4094 + 12757 0172 74E7 b .L675 + 12758 .L693: + 12759 .align 2 + 12760 .L692: + 12761 0174 0000FFFF .word -65536 + 12762 .cfi_endproc + 12763 .LFE346: + 12765 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 12766 .align 1 + 12767 .syntax unified + 12768 .code 16 + 12769 .thumb_func + 12770 .fpu softvfp + 12772 I2C_Slave_ISR_DMA: + 12773 .LVL916: + 12774 .LFB349: +5164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 12775 .loc 1 5164 1 is_stmt 1 view -0 + 12776 .cfi_startproc + 12777 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccth6daj.s page 412 + + + 12778 @ frame_needed = 0, uses_anonymous_args = 0 +5164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 12779 .loc 1 5164 1 is_stmt 0 view .LVU4096 + 12780 0000 F8B5 push {r3, r4, r5, r6, r7, lr} + 12781 .LCFI86: + 12782 .cfi_def_cfa_offset 24 + 12783 .cfi_offset 3, -24 + 12784 .cfi_offset 4, -20 + 12785 .cfi_offset 5, -16 + 12786 .cfi_offset 6, -12 + 12787 .cfi_offset 7, -8 + 12788 .cfi_offset 14, -4 + 12789 0002 0400 movs r4, r0 + 12790 0004 0D00 movs r5, r1 + 12791 0006 1600 movs r6, r2 +5165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 12792 .loc 1 5165 3 is_stmt 1 view .LVU4097 +5165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 12793 .loc 1 5165 12 is_stmt 0 view .LVU4098 + 12794 0008 C76A ldr r7, [r0, #44] + 12795 .LVL917: +5166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12796 .loc 1 5166 3 is_stmt 1 view .LVU4099 +5167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12797 .loc 1 5167 3 view .LVU4100 +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12798 .loc 1 5170 3 view .LVU4101 +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12799 .loc 1 5170 3 view .LVU4102 + 12800 000a 4023 movs r3, #64 + 12801 000c C35C ldrb r3, [r0, r3] + 12802 000e 012B cmp r3, #1 + 12803 0010 00D1 bne .LCB12094 + 12804 0012 87E0 b .L712 @long jump + 12805 .LCB12094: +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12806 .loc 1 5170 3 discriminator 2 view .LVU4103 + 12807 0014 0123 movs r3, #1 + 12808 0016 4022 movs r2, #64 + 12809 .LVL918: +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12810 .loc 1 5170 3 is_stmt 0 discriminator 2 view .LVU4104 + 12811 0018 8354 strb r3, [r0, r2] +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12812 .loc 1 5170 3 is_stmt 1 discriminator 2 view .LVU4105 +5173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12813 .loc 1 5173 3 discriminator 2 view .LVU4106 +5173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12814 .loc 1 5173 8 is_stmt 0 discriminator 2 view .LVU4107 + 12815 001a 4A09 lsrs r2, r1, #5 +5173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12816 .loc 1 5173 6 discriminator 2 view .LVU4108 + 12817 001c 1342 tst r3, r2 + 12818 001e 01D0 beq .L696 +5173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 12819 .loc 1 5173 58 discriminator 1 view .LVU4109 + 12820 0020 B306 lsls r3, r6, #26 + ARM GAS /tmp/ccth6daj.s page 413 + + + 12821 0022 16D4 bmi .L716 + 12822 .LVL919: + 12823 .L696: +5180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12824 .loc 1 5180 3 is_stmt 1 view .LVU4110 +5180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12825 .loc 1 5180 6 is_stmt 0 view .LVU4111 + 12826 0024 EB06 lsls r3, r5, #27 + 12827 0026 6FD5 bpl .L697 +5180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 12828 .loc 1 5180 55 discriminator 1 view .LVU4112 + 12829 0028 F306 lsls r3, r6, #27 + 12830 002a 6DD5 bpl .L697 +5187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12831 .loc 1 5187 5 is_stmt 1 view .LVU4113 +5187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12832 .loc 1 5187 10 is_stmt 0 view .LVU4114 + 12833 002c B30B lsrs r3, r6, #14 + 12834 002e 0122 movs r2, #1 + 12835 0030 1100 movs r1, r2 + 12836 0032 1940 ands r1, r3 +5187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12837 .loc 1 5187 8 view .LVU4115 + 12838 0034 1A42 tst r2, r3 + 12839 0036 01D1 bne .L698 +5187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 12840 .loc 1 5187 68 discriminator 1 view .LVU4116 + 12841 0038 3304 lsls r3, r6, #16 + 12842 003a 61D5 bpl .L699 + 12843 .L698: +5191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12844 .loc 1 5191 7 is_stmt 1 view .LVU4117 +5191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12845 .loc 1 5191 15 is_stmt 0 view .LVU4118 + 12846 003c E36B ldr r3, [r4, #60] +5191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12847 .loc 1 5191 10 view .LVU4119 + 12848 003e 002B cmp r3, #0 + 12849 0040 0AD0 beq .L713 +5193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12850 .loc 1 5193 9 is_stmt 1 view .LVU4120 +5193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12851 .loc 1 5193 12 is_stmt 0 view .LVU4121 + 12852 0042 3204 lsls r2, r6, #16 + 12853 0044 0AD5 bpl .L714 +5195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12854 .loc 1 5195 11 is_stmt 1 view .LVU4122 +5195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12855 .loc 1 5195 15 is_stmt 0 view .LVU4123 + 12856 0046 1B68 ldr r3, [r3] + 12857 0048 5B68 ldr r3, [r3, #4] +5195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12858 .loc 1 5195 14 view .LVU4124 + 12859 004a 002B cmp r3, #0 + 12860 004c 2DD0 beq .L715 +5166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12861 .loc 1 5166 12 view .LVU4125 + ARM GAS /tmp/ccth6daj.s page 414 + + + 12862 004e 0022 movs r2, #0 + 12863 0050 05E0 b .L700 + 12864 .LVL920: + 12865 .L716: +5177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12866 .loc 1 5177 5 is_stmt 1 view .LVU4126 + 12867 0052 FFF7FEFF bl I2C_ITSlaveCplt + 12868 .LVL921: +5177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12869 .loc 1 5177 5 is_stmt 0 view .LVU4127 + 12870 0056 E5E7 b .L696 + 12871 .L713: +5166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; + 12872 .loc 1 5166 12 view .LVU4128 + 12873 0058 0022 movs r2, #0 + 12874 005a 00E0 b .L700 + 12875 .L714: + 12876 005c 0022 movs r2, #0 + 12877 .L700: + 12878 .LVL922: +5203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12879 .loc 1 5203 7 is_stmt 1 view .LVU4129 +5203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12880 .loc 1 5203 15 is_stmt 0 view .LVU4130 + 12881 005e A36B ldr r3, [r4, #56] +5203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12882 .loc 1 5203 10 view .LVU4131 + 12883 0060 002B cmp r3, #0 + 12884 0062 05D0 beq .L701 +5205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12885 .loc 1 5205 9 is_stmt 1 view .LVU4132 +5205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12886 .loc 1 5205 12 is_stmt 0 view .LVU4133 + 12887 0064 0029 cmp r1, #0 + 12888 0066 03D0 beq .L701 +5207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12889 .loc 1 5207 11 is_stmt 1 view .LVU4134 +5207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12890 .loc 1 5207 15 is_stmt 0 view .LVU4135 + 12891 0068 1B68 ldr r3, [r3] + 12892 006a 5B68 ldr r3, [r3, #4] +5207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12893 .loc 1 5207 14 view .LVU4136 + 12894 006c 002B cmp r3, #0 + 12895 006e 1ED0 beq .L702 + 12896 .L701: +5214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12897 .loc 1 5214 7 is_stmt 1 view .LVU4137 +5214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12898 .loc 1 5214 10 is_stmt 0 view .LVU4138 + 12899 0070 012A cmp r2, #1 + 12900 0072 1CD0 beq .L702 +5245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12901 .loc 1 5245 9 is_stmt 1 view .LVU4139 + 12902 0074 2368 ldr r3, [r4] + 12903 0076 1022 movs r2, #16 + 12904 .LVL923: + ARM GAS /tmp/ccth6daj.s page 415 + + +5245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12905 .loc 1 5245 9 is_stmt 0 view .LVU4140 + 12906 0078 DA61 str r2, [r3, #28] +5248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12907 .loc 1 5248 9 is_stmt 1 view .LVU4141 +5248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12908 .loc 1 5248 25 is_stmt 0 view .LVU4142 + 12909 007a 636C ldr r3, [r4, #68] + 12910 007c 0C3A subs r2, r2, #12 + 12911 007e 1343 orrs r3, r2 + 12912 0080 6364 str r3, [r4, #68] +5251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12913 .loc 1 5251 9 is_stmt 1 view .LVU4143 +5251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12914 .loc 1 5251 18 is_stmt 0 view .LVU4144 + 12915 0082 4123 movs r3, #65 + 12916 0084 E35C ldrb r3, [r4, r3] + 12917 0086 DBB2 uxtb r3, r3 + 12918 .LVL924: +5253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12919 .loc 1 5253 9 is_stmt 1 view .LVU4145 +5253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12920 .loc 1 5253 12 is_stmt 0 view .LVU4146 + 12921 0088 002F cmp r7, #0 + 12922 008a 03D0 beq .L707 +5253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12923 .loc 1 5253 45 discriminator 1 view .LVU4147 + 12924 008c 8022 movs r2, #128 + 12925 008e 5204 lsls r2, r2, #17 + 12926 0090 9742 cmp r7, r2 + 12927 0092 3DD1 bne .L705 + 12928 .L707: +5255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12929 .loc 1 5255 11 is_stmt 1 view .LVU4148 +5255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12930 .loc 1 5255 14 is_stmt 0 view .LVU4149 + 12931 0094 212B cmp r3, #33 + 12932 0096 2CD0 beq .L708 +5255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12933 .loc 1 5255 51 discriminator 1 view .LVU4150 + 12934 0098 292B cmp r3, #41 + 12935 009a 2AD0 beq .L708 +5259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12936 .loc 1 5259 16 is_stmt 1 view .LVU4151 +5259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12937 .loc 1 5259 19 is_stmt 0 view .LVU4152 + 12938 009c 222B cmp r3, #34 + 12939 009e 01D0 beq .L711 +5259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12940 .loc 1 5259 56 discriminator 1 view .LVU4153 + 12941 00a0 2A2B cmp r3, #42 + 12942 00a2 28D1 bne .L710 + 12943 .L711: +5261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12944 .loc 1 5261 13 is_stmt 1 view .LVU4154 +5261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12945 .loc 1 5261 33 is_stmt 0 view .LVU4155 + ARM GAS /tmp/ccth6daj.s page 416 + + + 12946 00a4 2223 movs r3, #34 + 12947 .LVL925: +5261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12948 .loc 1 5261 33 view .LVU4156 + 12949 00a6 2363 str r3, [r4, #48] + 12950 00a8 25E0 b .L710 + 12951 .LVL926: + 12952 .L715: +5197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12953 .loc 1 5197 26 view .LVU4157 + 12954 00aa 0122 movs r2, #1 + 12955 00ac D7E7 b .L700 + 12956 .LVL927: + 12957 .L702: +5216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 12958 .loc 1 5216 9 is_stmt 1 view .LVU4158 +5216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 12959 .loc 1 5216 18 is_stmt 0 view .LVU4159 + 12960 00ae 4123 movs r3, #65 + 12961 00b0 E35C ldrb r3, [r4, r3] +5216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 12962 .loc 1 5216 12 view .LVU4160 + 12963 00b2 282B cmp r3, #40 + 12964 00b4 07D0 beq .L717 + 12965 .L704: +5223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12966 .loc 1 5223 14 is_stmt 1 view .LVU4161 +5223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12967 .loc 1 5223 23 is_stmt 0 view .LVU4162 + 12968 00b6 4123 movs r3, #65 + 12969 00b8 E35C ldrb r3, [r4, r3] +5223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12970 .loc 1 5223 17 view .LVU4163 + 12971 00ba 292B cmp r3, #41 + 12972 00bc 0CD0 beq .L718 + 12973 .L706: +5238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12974 .loc 1 5238 11 is_stmt 1 view .LVU4164 + 12975 00be 2368 ldr r3, [r4] + 12976 00c0 1022 movs r2, #16 + 12977 00c2 DA61 str r2, [r3, #28] + 12978 00c4 24E0 b .L705 + 12979 .L717: +5216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + 12980 .loc 1 5216 51 is_stmt 0 discriminator 1 view .LVU4165 + 12981 00c6 8023 movs r3, #128 + 12982 00c8 9B04 lsls r3, r3, #18 + 12983 00ca 9F42 cmp r7, r3 + 12984 00cc F3D1 bne .L704 +5221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 12985 .loc 1 5221 11 is_stmt 1 view .LVU4166 + 12986 00ce 2900 movs r1, r5 + 12987 00d0 2000 movs r0, r4 + 12988 00d2 FFF7FEFF bl I2C_ITListenCplt + 12989 .LVL928: + 12990 00d6 1BE0 b .L705 + 12991 .L718: + ARM GAS /tmp/ccth6daj.s page 417 + + +5223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 12992 .loc 1 5223 64 is_stmt 0 discriminator 1 view .LVU4167 + 12993 00d8 134B ldr r3, .L720 + 12994 00da 9F42 cmp r7, r3 + 12995 00dc EFD0 beq .L706 +5226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 12996 .loc 1 5226 11 is_stmt 1 view .LVU4168 + 12997 00de 2368 ldr r3, [r4] + 12998 00e0 1022 movs r2, #16 + 12999 00e2 DA61 str r2, [r3, #28] +5229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13000 .loc 1 5229 11 view .LVU4169 + 13001 00e4 2000 movs r0, r4 + 13002 00e6 FFF7FEFF bl I2C_Flush_TXDR + 13003 .LVL929: +5233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13004 .loc 1 5233 11 view .LVU4170 + 13005 00ea 2000 movs r0, r4 + 13006 00ec FFF7FEFF bl I2C_ITSlaveSeqCplt + 13007 .LVL930: + 13008 00f0 0EE0 b .L705 + 13009 .LVL931: + 13010 .L708: +5257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13011 .loc 1 5257 13 view .LVU4171 +5257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13012 .loc 1 5257 33 is_stmt 0 view .LVU4172 + 13013 00f2 2123 movs r3, #33 + 13014 .LVL932: +5257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13015 .loc 1 5257 33 view .LVU4173 + 13016 00f4 2363 str r3, [r4, #48] + 13017 .L710: +5269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13018 .loc 1 5269 11 is_stmt 1 view .LVU4174 + 13019 00f6 616C ldr r1, [r4, #68] + 13020 00f8 2000 movs r0, r4 + 13021 00fa FFF7FEFF bl I2C_ITError + 13022 .LVL933: + 13023 00fe 07E0 b .L705 + 13024 .LVL934: + 13025 .L699: +5276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13026 .loc 1 5276 7 view .LVU4175 + 13027 0100 2368 ldr r3, [r4] + 13028 0102 1022 movs r2, #16 + 13029 0104 DA61 str r2, [r3, #28] + 13030 0106 03E0 b .L705 + 13031 .L697: +5279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13032 .loc 1 5279 8 view .LVU4176 +5279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13033 .loc 1 5279 11 is_stmt 0 view .LVU4177 + 13034 0108 2B07 lsls r3, r5, #28 + 13035 010a 01D5 bpl .L705 +5279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 13036 .loc 1 5279 62 discriminator 1 view .LVU4178 + ARM GAS /tmp/ccth6daj.s page 418 + + + 13037 010c 3307 lsls r3, r6, #28 + 13038 010e 04D4 bmi .L719 + 13039 .LVL935: + 13040 .L705: +5287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13041 .loc 1 5287 3 is_stmt 1 view .LVU4179 +5290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13042 .loc 1 5290 3 view .LVU4180 +5290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13043 .loc 1 5290 3 view .LVU4181 + 13044 0110 4023 movs r3, #64 + 13045 0112 0022 movs r2, #0 + 13046 0114 E254 strb r2, [r4, r3] +5290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13047 .loc 1 5290 3 view .LVU4182 +5292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13048 .loc 1 5292 3 view .LVU4183 +5292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13049 .loc 1 5292 10 is_stmt 0 view .LVU4184 + 13050 0116 0020 movs r0, #0 + 13051 .L695: +5293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13052 .loc 1 5293 1 view .LVU4185 + 13053 @ sp needed + 13054 .LVL936: + 13055 .LVL937: + 13056 .LVL938: + 13057 .LVL939: +5293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13058 .loc 1 5293 1 view .LVU4186 + 13059 0118 F8BD pop {r3, r4, r5, r6, r7, pc} + 13060 .LVL940: + 13061 .L719: +5282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13062 .loc 1 5282 5 is_stmt 1 view .LVU4187 + 13063 011a 2900 movs r1, r5 + 13064 011c 2000 movs r0, r4 + 13065 011e FFF7FEFF bl I2C_ITAddrCplt + 13066 .LVL941: + 13067 0122 F5E7 b .L705 + 13068 .LVL942: + 13069 .L712: +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13070 .loc 1 5170 3 is_stmt 0 view .LVU4188 + 13071 0124 0220 movs r0, #2 + 13072 .LVL943: +5170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13073 .loc 1 5170 3 view .LVU4189 + 13074 0126 F7E7 b .L695 + 13075 .L721: + 13076 .align 2 + 13077 .L720: + 13078 0128 0000FFFF .word -65536 + 13079 .cfi_endproc + 13080 .LFE349: + 13082 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 13083 .align 1 + ARM GAS /tmp/ccth6daj.s page 419 + + + 13084 .syntax unified + 13085 .code 16 + 13086 .thumb_func + 13087 .fpu softvfp + 13089 I2C_Master_ISR_DMA: + 13090 .LVL944: + 13091 .LFB348: +5024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; + 13092 .loc 1 5024 1 is_stmt 1 view -0 + 13093 .cfi_startproc + 13094 @ args = 0, pretend = 0, frame = 0 + 13095 @ frame_needed = 0, uses_anonymous_args = 0 +5024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint16_t devaddress; + 13096 .loc 1 5024 1 is_stmt 0 view .LVU4191 + 13097 0000 10B5 push {r4, lr} + 13098 .LCFI87: + 13099 .cfi_def_cfa_offset 8 + 13100 .cfi_offset 4, -8 + 13101 .cfi_offset 14, -4 + 13102 0002 82B0 sub sp, sp, #8 + 13103 .LCFI88: + 13104 .cfi_def_cfa_offset 16 + 13105 0004 0400 movs r4, r0 +5025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t xfermode; + 13106 .loc 1 5025 3 is_stmt 1 view .LVU4192 +5026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13107 .loc 1 5026 3 view .LVU4193 +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13108 .loc 1 5029 3 view .LVU4194 +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13109 .loc 1 5029 3 view .LVU4195 + 13110 0006 4023 movs r3, #64 + 13111 0008 C35C ldrb r3, [r0, r3] + 13112 000a 012B cmp r3, #1 + 13113 000c 00D1 bne .LCB12426 + 13114 000e 91E0 b .L735 @long jump + 13115 .LCB12426: +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13116 .loc 1 5029 3 discriminator 2 view .LVU4196 + 13117 0010 0123 movs r3, #1 + 13118 0012 4020 movs r0, #64 + 13119 .LVL945: +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13120 .loc 1 5029 3 is_stmt 0 discriminator 2 view .LVU4197 + 13121 0014 2354 strb r3, [r4, r0] +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13122 .loc 1 5029 3 is_stmt 1 discriminator 2 view .LVU4198 +5031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13123 .loc 1 5031 3 discriminator 2 view .LVU4199 +5031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13124 .loc 1 5031 8 is_stmt 0 discriminator 2 view .LVU4200 + 13125 0016 0809 lsrs r0, r1, #4 +5031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 13126 .loc 1 5031 6 discriminator 2 view .LVU4201 + 13127 0018 0342 tst r3, r0 + 13128 001a 01D0 beq .L724 +5031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + ARM GAS /tmp/ccth6daj.s page 420 + + + 13129 .loc 1 5031 55 discriminator 1 view .LVU4202 + 13130 001c D306 lsls r3, r2, #27 + 13131 001e 2FD4 bmi .L737 + 13132 .L724: +5048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13133 .loc 1 5048 8 is_stmt 1 view .LVU4203 +5048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13134 .loc 1 5048 11 is_stmt 0 view .LVU4204 + 13135 0020 0B06 lsls r3, r1, #24 + 13136 0022 60D5 bpl .L726 +5048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13137 .loc 1 5048 61 discriminator 1 view .LVU4205 + 13138 0024 5306 lsls r3, r2, #25 + 13139 0026 5ED5 bpl .L726 +5052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13140 .loc 1 5052 5 is_stmt 1 view .LVU4206 + 13141 0028 2268 ldr r2, [r4] + 13142 .LVL946: +5052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13143 .loc 1 5052 5 is_stmt 0 view .LVU4207 + 13144 002a 1368 ldr r3, [r2] + 13145 002c 4021 movs r1, #64 + 13146 .LVL947: +5052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13147 .loc 1 5052 5 view .LVU4208 + 13148 002e 8B43 bics r3, r1 + 13149 0030 1360 str r3, [r2] +5054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13150 .loc 1 5054 5 is_stmt 1 view .LVU4209 +5054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13151 .loc 1 5054 13 is_stmt 0 view .LVU4210 + 13152 0032 638D ldrh r3, [r4, #42] + 13153 0034 9BB2 uxth r3, r3 +5054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13154 .loc 1 5054 8 view .LVU4211 + 13155 0036 002B cmp r3, #0 + 13156 0038 48D0 beq .L727 +5057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13157 .loc 1 5057 7 is_stmt 1 view .LVU4212 +5057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13158 .loc 1 5057 35 is_stmt 0 view .LVU4213 + 13159 003a 2368 ldr r3, [r4] +5057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13160 .loc 1 5057 45 view .LVU4214 + 13161 003c 5968 ldr r1, [r3, #4] +5057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13162 .loc 1 5057 18 view .LVU4215 + 13163 003e 8905 lsls r1, r1, #22 + 13164 0040 890D lsrs r1, r1, #22 + 13165 .LVL948: +5060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13166 .loc 1 5060 7 is_stmt 1 view .LVU4216 +5060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13167 .loc 1 5060 15 is_stmt 0 view .LVU4217 + 13168 0042 638D ldrh r3, [r4, #42] + 13169 0044 9BB2 uxth r3, r3 +5060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 421 + + + 13170 .loc 1 5060 10 view .LVU4218 + 13171 0046 FF2B cmp r3, #255 + 13172 0048 2ED9 bls .L728 +5062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 13173 .loc 1 5062 9 is_stmt 1 view .LVU4219 +5062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 13174 .loc 1 5062 24 is_stmt 0 view .LVU4220 + 13175 004a FF23 movs r3, #255 + 13176 004c 2385 strh r3, [r4, #40] +5063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13177 .loc 1 5063 9 is_stmt 1 view .LVU4221 + 13178 .LVL949: +5063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13179 .loc 1 5063 18 is_stmt 0 view .LVU4222 + 13180 004e 8023 movs r3, #128 + 13181 0050 5B04 lsls r3, r3, #17 + 13182 .LVL950: + 13183 .L729: +5079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13184 .loc 1 5079 7 is_stmt 1 view .LVU4223 +5079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13185 .loc 1 5079 57 is_stmt 0 view .LVU4224 + 13186 0052 228D ldrh r2, [r4, #40] +5079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13187 .loc 1 5079 7 view .LVU4225 + 13188 0054 D2B2 uxtb r2, r2 + 13189 0056 0020 movs r0, #0 + 13190 0058 0090 str r0, [sp] + 13191 005a 2000 movs r0, r4 + 13192 005c FFF7FEFF bl I2C_TransferConfig + 13193 .LVL951: +5082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13194 .loc 1 5082 7 is_stmt 1 view .LVU4226 +5082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13195 .loc 1 5082 23 is_stmt 0 view .LVU4227 + 13196 0060 638D ldrh r3, [r4, #42] +5082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13197 .loc 1 5082 30 view .LVU4228 + 13198 0062 228D ldrh r2, [r4, #40] +5082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13199 .loc 1 5082 23 view .LVU4229 + 13200 0064 9B1A subs r3, r3, r2 + 13201 0066 9BB2 uxth r3, r3 + 13202 0068 6385 strh r3, [r4, #42] +5085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13203 .loc 1 5085 7 is_stmt 1 view .LVU4230 +5085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13204 .loc 1 5085 15 is_stmt 0 view .LVU4231 + 13205 006a 4123 movs r3, #65 + 13206 006c E35C ldrb r3, [r4, r3] +5085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13207 .loc 1 5085 10 view .LVU4232 + 13208 006e 222B cmp r3, #34 + 13209 0070 25D0 beq .L738 +5091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13210 .loc 1 5091 9 is_stmt 1 view .LVU4233 +5091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 422 + + + 13211 .loc 1 5091 13 is_stmt 0 view .LVU4234 + 13212 0072 2268 ldr r2, [r4] +5091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13213 .loc 1 5091 29 view .LVU4235 + 13214 0074 1168 ldr r1, [r2] + 13215 0076 8023 movs r3, #128 + 13216 0078 DB01 lsls r3, r3, #7 + 13217 007a 0B43 orrs r3, r1 + 13218 007c 1360 str r3, [r2] + 13219 007e 0DE0 b .L725 + 13220 .LVL952: + 13221 .L737: +5035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13222 .loc 1 5035 5 is_stmt 1 view .LVU4236 + 13223 0080 2368 ldr r3, [r4] + 13224 0082 1022 movs r2, #16 + 13225 .LVL953: +5035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13226 .loc 1 5035 5 is_stmt 0 view .LVU4237 + 13227 0084 DA61 str r2, [r3, #28] +5038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13228 .loc 1 5038 5 is_stmt 1 view .LVU4238 +5038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13229 .loc 1 5038 21 is_stmt 0 view .LVU4239 + 13230 0086 636C ldr r3, [r4, #68] + 13231 0088 0C3A subs r2, r2, #12 + 13232 008a 1343 orrs r3, r2 + 13233 008c 6364 str r3, [r4, #68] +5043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13234 .loc 1 5043 5 is_stmt 1 view .LVU4240 + 13235 008e 2021 movs r1, #32 + 13236 .LVL954: +5043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13237 .loc 1 5043 5 is_stmt 0 view .LVU4241 + 13238 0090 2000 movs r0, r4 + 13239 0092 FFF7FEFF bl I2C_Enable_IRQ + 13240 .LVL955: +5046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13241 .loc 1 5046 5 is_stmt 1 view .LVU4242 + 13242 0096 2000 movs r0, r4 + 13243 0098 FFF7FEFF bl I2C_Flush_TXDR + 13244 .LVL956: + 13245 .L725: +5146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13246 .loc 1 5146 3 view .LVU4243 +5149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13247 .loc 1 5149 3 view .LVU4244 +5149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13248 .loc 1 5149 3 view .LVU4245 + 13249 009c 4023 movs r3, #64 + 13250 009e 0022 movs r2, #0 + 13251 00a0 E254 strb r2, [r4, r3] +5149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13252 .loc 1 5149 3 view .LVU4246 +5151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13253 .loc 1 5151 3 view .LVU4247 +5151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + ARM GAS /tmp/ccth6daj.s page 423 + + + 13254 .loc 1 5151 10 is_stmt 0 view .LVU4248 + 13255 00a2 0020 movs r0, #0 + 13256 .L723: +5152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13257 .loc 1 5152 1 view .LVU4249 + 13258 00a4 02B0 add sp, sp, #8 + 13259 @ sp needed + 13260 .LVL957: +5152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13261 .loc 1 5152 1 view .LVU4250 + 13262 00a6 10BD pop {r4, pc} + 13263 .LVL958: + 13264 .L728: +5067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13265 .loc 1 5067 9 is_stmt 1 view .LVU4251 +5067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13266 .loc 1 5067 30 is_stmt 0 view .LVU4252 + 13267 00a8 638D ldrh r3, [r4, #42] +5067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 13268 .loc 1 5067 24 view .LVU4253 + 13269 00aa 2385 strh r3, [r4, #40] +5068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13270 .loc 1 5068 9 is_stmt 1 view .LVU4254 +5068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13271 .loc 1 5068 17 is_stmt 0 view .LVU4255 + 13272 00ac E26A ldr r2, [r4, #44] +5068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13273 .loc 1 5068 12 view .LVU4256 + 13274 00ae 224B ldr r3, .L739 + 13275 00b0 9A42 cmp r2, r3 + 13276 00b2 01D0 beq .L736 +5070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13277 .loc 1 5070 11 is_stmt 1 view .LVU4257 +5070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13278 .loc 1 5070 20 is_stmt 0 view .LVU4258 + 13279 00b4 E36A ldr r3, [r4, #44] + 13280 .LVL959: +5070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13281 .loc 1 5070 20 view .LVU4259 + 13282 00b6 CCE7 b .L729 + 13283 .LVL960: + 13284 .L736: +5074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13285 .loc 1 5074 20 view .LVU4260 + 13286 00b8 8023 movs r3, #128 + 13287 00ba 9B04 lsls r3, r3, #18 + 13288 00bc C9E7 b .L729 + 13289 .LVL961: + 13290 .L738: +5087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13291 .loc 1 5087 9 is_stmt 1 view .LVU4261 +5087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13292 .loc 1 5087 13 is_stmt 0 view .LVU4262 + 13293 00be 2268 ldr r2, [r4] +5087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13294 .loc 1 5087 29 view .LVU4263 + 13295 00c0 1168 ldr r1, [r2] + ARM GAS /tmp/ccth6daj.s page 424 + + + 13296 00c2 8023 movs r3, #128 + 13297 00c4 1B02 lsls r3, r3, #8 + 13298 00c6 0B43 orrs r3, r1 + 13299 00c8 1360 str r3, [r2] + 13300 00ca E7E7 b .L725 + 13301 .L727: +5097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13302 .loc 1 5097 7 is_stmt 1 view .LVU4264 +5097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13303 .loc 1 5097 11 is_stmt 0 view .LVU4265 + 13304 00cc 2368 ldr r3, [r4] + 13305 00ce 5B68 ldr r3, [r3, #4] +5097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13306 .loc 1 5097 10 view .LVU4266 + 13307 00d0 9B01 lsls r3, r3, #6 + 13308 00d2 03D4 bmi .L731 +5100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13309 .loc 1 5100 9 is_stmt 1 view .LVU4267 + 13310 00d4 2000 movs r0, r4 + 13311 00d6 FFF7FEFF bl I2C_ITMasterSeqCplt + 13312 .LVL962: + 13313 00da DFE7 b .L725 + 13314 .L731: +5106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13315 .loc 1 5106 9 view .LVU4268 + 13316 00dc 4021 movs r1, #64 + 13317 00de 2000 movs r0, r4 + 13318 00e0 FFF7FEFF bl I2C_ITError + 13319 .LVL963: + 13320 00e4 DAE7 b .L725 + 13321 .LVL964: + 13322 .L726: +5110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13323 .loc 1 5110 8 view .LVU4269 +5110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13324 .loc 1 5110 11 is_stmt 0 view .LVU4270 + 13325 00e6 4B06 lsls r3, r1, #25 + 13326 00e8 1CD5 bpl .L732 +5110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 13327 .loc 1 5110 60 discriminator 1 view .LVU4271 + 13328 00ea 5306 lsls r3, r2, #25 + 13329 00ec 1AD5 bpl .L732 +5113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13330 .loc 1 5113 5 is_stmt 1 view .LVU4272 +5113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13331 .loc 1 5113 13 is_stmt 0 view .LVU4273 + 13332 00ee 638D ldrh r3, [r4, #42] + 13333 00f0 9BB2 uxth r3, r3 +5113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13334 .loc 1 5113 8 view .LVU4274 + 13335 00f2 002B cmp r3, #0 + 13336 00f4 11D1 bne .L733 +5115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13337 .loc 1 5115 7 is_stmt 1 view .LVU4275 +5115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13338 .loc 1 5115 11 is_stmt 0 view .LVU4276 + 13339 00f6 2368 ldr r3, [r4] + ARM GAS /tmp/ccth6daj.s page 425 + + + 13340 00f8 5A68 ldr r2, [r3, #4] + 13341 .LVL965: +5115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13342 .loc 1 5115 10 view .LVU4277 + 13343 00fa 9201 lsls r2, r2, #6 + 13344 00fc CED4 bmi .L725 +5118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13345 .loc 1 5118 9 is_stmt 1 view .LVU4278 +5118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13346 .loc 1 5118 17 is_stmt 0 view .LVU4279 + 13347 00fe E16A ldr r1, [r4, #44] + 13348 .LVL966: +5118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13349 .loc 1 5118 12 view .LVU4280 + 13350 0100 0D4A ldr r2, .L739 + 13351 0102 9142 cmp r1, r2 + 13352 0104 05D1 bne .L734 +5121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13353 .loc 1 5121 11 is_stmt 1 view .LVU4281 +5121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13354 .loc 1 5121 31 is_stmt 0 view .LVU4282 + 13355 0106 5968 ldr r1, [r3, #4] + 13356 0108 8022 movs r2, #128 + 13357 010a D201 lsls r2, r2, #7 + 13358 010c 0A43 orrs r2, r1 + 13359 010e 5A60 str r2, [r3, #4] + 13360 0110 C4E7 b .L725 + 13361 .L734: +5126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13362 .loc 1 5126 11 is_stmt 1 view .LVU4283 + 13363 0112 2000 movs r0, r4 + 13364 0114 FFF7FEFF bl I2C_ITMasterSeqCplt + 13365 .LVL967: + 13366 0118 C0E7 b .L725 + 13367 .LVL968: + 13368 .L733: +5134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13369 .loc 1 5134 7 view .LVU4284 + 13370 011a 4021 movs r1, #64 + 13371 .LVL969: +5134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13372 .loc 1 5134 7 is_stmt 0 view .LVU4285 + 13373 011c 2000 movs r0, r4 + 13374 011e FFF7FEFF bl I2C_ITError + 13375 .LVL970: +5134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13376 .loc 1 5134 7 view .LVU4286 + 13377 0122 BBE7 b .L725 + 13378 .LVL971: + 13379 .L732: +5137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13380 .loc 1 5137 8 is_stmt 1 view .LVU4287 +5137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 13381 .loc 1 5137 11 is_stmt 0 view .LVU4288 + 13382 0124 8B06 lsls r3, r1, #26 + 13383 0126 B9D5 bpl .L725 +5137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + ARM GAS /tmp/ccth6daj.s page 426 + + + 13384 .loc 1 5137 63 discriminator 1 view .LVU4289 + 13385 0128 9306 lsls r3, r2, #26 + 13386 012a B7D5 bpl .L725 +5141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13387 .loc 1 5141 5 is_stmt 1 view .LVU4290 + 13388 012c 2000 movs r0, r4 + 13389 012e FFF7FEFF bl I2C_ITMasterCplt + 13390 .LVL972: +5141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13391 .loc 1 5141 5 is_stmt 0 view .LVU4291 + 13392 0132 B3E7 b .L725 + 13393 .LVL973: + 13394 .L735: +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13395 .loc 1 5029 3 view .LVU4292 + 13396 0134 0220 movs r0, #2 + 13397 .LVL974: +5029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13398 .loc 1 5029 3 view .LVU4293 + 13399 0136 B5E7 b .L723 + 13400 .L740: + 13401 .align 2 + 13402 .L739: + 13403 0138 0000FFFF .word -65536 + 13404 .cfi_endproc + 13405 .LFE348: + 13407 .section .text.I2C_DMAError,"ax",%progbits + 13408 .align 1 + 13409 .syntax unified + 13410 .code 16 + 13411 .thumb_func + 13412 .fpu softvfp + 13414 I2C_DMAError: + 13415 .LVL975: + 13416 .LFB365: +6314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13417 .loc 1 6314 1 is_stmt 1 view -0 + 13418 .cfi_startproc + 13419 @ args = 0, pretend = 0, frame = 0 + 13420 @ frame_needed = 0, uses_anonymous_args = 0 +6314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13421 .loc 1 6314 1 is_stmt 0 view .LVU4295 + 13422 0000 10B5 push {r4, lr} + 13423 .LCFI89: + 13424 .cfi_def_cfa_offset 8 + 13425 .cfi_offset 4, -8 + 13426 .cfi_offset 14, -4 +6316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13427 .loc 1 6316 3 is_stmt 1 view .LVU4296 +6316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13428 .loc 1 6316 22 is_stmt 0 view .LVU4297 + 13429 0002 806A ldr r0, [r0, #40] + 13430 .LVL976: +6319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13431 .loc 1 6319 3 is_stmt 1 view .LVU4298 +6319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13432 .loc 1 6319 7 is_stmt 0 view .LVU4299 + ARM GAS /tmp/ccth6daj.s page 427 + + + 13433 0004 0268 ldr r2, [r0] +6319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13434 .loc 1 6319 23 view .LVU4300 + 13435 0006 5168 ldr r1, [r2, #4] + 13436 0008 8023 movs r3, #128 + 13437 000a 1B02 lsls r3, r3, #8 + 13438 000c 0B43 orrs r3, r1 + 13439 000e 5360 str r3, [r2, #4] +6322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13440 .loc 1 6322 3 is_stmt 1 view .LVU4301 + 13441 0010 1021 movs r1, #16 + 13442 0012 FFF7FEFF bl I2C_ITError + 13443 .LVL977: +6323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13444 .loc 1 6323 1 is_stmt 0 view .LVU4302 + 13445 @ sp needed + 13446 0016 10BD pop {r4, pc} + 13447 .cfi_endproc + 13448 .LFE365: + 13450 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 13451 .align 1 + 13452 .syntax unified + 13453 .code 16 + 13454 .thumb_func + 13455 .fpu softvfp + 13457 I2C_DMAMasterTransmitCplt: + 13458 .LVL978: + 13459 .LFB361: +6158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13460 .loc 1 6158 1 is_stmt 1 view -0 + 13461 .cfi_startproc + 13462 @ args = 0, pretend = 0, frame = 0 + 13463 @ frame_needed = 0, uses_anonymous_args = 0 +6158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13464 .loc 1 6158 1 is_stmt 0 view .LVU4304 + 13465 0000 10B5 push {r4, lr} + 13466 .LCFI90: + 13467 .cfi_def_cfa_offset 8 + 13468 .cfi_offset 4, -8 + 13469 .cfi_offset 14, -4 +6160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13470 .loc 1 6160 3 is_stmt 1 view .LVU4305 +6160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13471 .loc 1 6160 22 is_stmt 0 view .LVU4306 + 13472 0002 846A ldr r4, [r0, #40] + 13473 .LVL979: +6163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13474 .loc 1 6163 3 is_stmt 1 view .LVU4307 +6163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13475 .loc 1 6163 7 is_stmt 0 view .LVU4308 + 13476 0004 2268 ldr r2, [r4] +6163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13477 .loc 1 6163 23 view .LVU4309 + 13478 0006 1368 ldr r3, [r2] + 13479 0008 1549 ldr r1, .L749 + 13480 000a 0B40 ands r3, r1 + 13481 000c 1360 str r3, [r2] + ARM GAS /tmp/ccth6daj.s page 428 + + +6166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13482 .loc 1 6166 3 is_stmt 1 view .LVU4310 +6166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13483 .loc 1 6166 11 is_stmt 0 view .LVU4311 + 13484 000e 638D ldrh r3, [r4, #42] + 13485 0010 9BB2 uxth r3, r3 +6166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13486 .loc 1 6166 6 view .LVU4312 + 13487 0012 002B cmp r3, #0 + 13488 0014 17D0 beq .L748 +6175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13489 .loc 1 6175 5 is_stmt 1 view .LVU4313 +6175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13490 .loc 1 6175 27 is_stmt 0 view .LVU4314 + 13491 0016 218D ldrh r1, [r4, #40] +6175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13492 .loc 1 6175 20 view .LVU4315 + 13493 0018 636A ldr r3, [r4, #36] + 13494 001a 9C46 mov ip, r3 + 13495 001c 6144 add r1, r1, ip + 13496 001e 6162 str r1, [r4, #36] +6178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13497 .loc 1 6178 5 is_stmt 1 view .LVU4316 +6178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13498 .loc 1 6178 13 is_stmt 0 view .LVU4317 + 13499 0020 638D ldrh r3, [r4, #42] + 13500 0022 9BB2 uxth r3, r3 +6178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13501 .loc 1 6178 8 view .LVU4318 + 13502 0024 FF2B cmp r3, #255 + 13503 0026 13D9 bls .L745 +6180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13504 .loc 1 6180 7 is_stmt 1 view .LVU4319 +6180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13505 .loc 1 6180 22 is_stmt 0 view .LVU4320 + 13506 0028 FF23 movs r3, #255 + 13507 002a 2385 strh r3, [r4, #40] + 13508 .L746: +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13509 .loc 1 6188 5 is_stmt 1 view .LVU4321 +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13510 .loc 1 6188 76 is_stmt 0 view .LVU4322 + 13511 002c 2268 ldr r2, [r4] + 13512 002e 2832 adds r2, r2, #40 +6189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13513 .loc 1 6189 30 view .LVU4323 + 13514 0030 238D ldrh r3, [r4, #40] +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13515 .loc 1 6188 9 view .LVU4324 + 13516 0032 A06B ldr r0, [r4, #56] + 13517 .LVL980: +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13518 .loc 1 6188 9 view .LVU4325 + 13519 0034 FFF7FEFF bl HAL_DMA_Start_IT + 13520 .LVL981: +6188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13521 .loc 1 6188 8 view .LVU4326 + ARM GAS /tmp/ccth6daj.s page 429 + + + 13522 0038 0028 cmp r0, #0 + 13523 003a 0CD0 beq .L747 +6192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13524 .loc 1 6192 7 is_stmt 1 view .LVU4327 + 13525 003c 1021 movs r1, #16 + 13526 003e 2000 movs r0, r4 + 13527 0040 FFF7FEFF bl I2C_ITError + 13528 .LVL982: + 13529 .L742: +6200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13530 .loc 1 6200 1 is_stmt 0 view .LVU4328 + 13531 @ sp needed + 13532 .LVL983: +6200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13533 .loc 1 6200 1 view .LVU4329 + 13534 0044 10BD pop {r4, pc} + 13535 .LVL984: + 13536 .L748: +6169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13537 .loc 1 6169 5 is_stmt 1 view .LVU4330 + 13538 0046 2021 movs r1, #32 + 13539 0048 2000 movs r0, r4 + 13540 .LVL985: +6169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13541 .loc 1 6169 5 is_stmt 0 view .LVU4331 + 13542 004a FFF7FEFF bl I2C_Enable_IRQ + 13543 .LVL986: + 13544 004e F9E7 b .L742 + 13545 .LVL987: + 13546 .L745: +6184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13547 .loc 1 6184 7 is_stmt 1 view .LVU4332 +6184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13548 .loc 1 6184 28 is_stmt 0 view .LVU4333 + 13549 0050 638D ldrh r3, [r4, #42] +6184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13550 .loc 1 6184 22 view .LVU4334 + 13551 0052 2385 strh r3, [r4, #40] + 13552 0054 EAE7 b .L746 + 13553 .LVL988: + 13554 .L747: +6197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13555 .loc 1 6197 7 is_stmt 1 view .LVU4335 + 13556 0056 4021 movs r1, #64 + 13557 0058 2000 movs r0, r4 + 13558 005a FFF7FEFF bl I2C_Enable_IRQ + 13559 .LVL989: +6200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13560 .loc 1 6200 1 is_stmt 0 view .LVU4336 + 13561 005e F1E7 b .L742 + 13562 .L750: + 13563 .align 2 + 13564 .L749: + 13565 0060 FFBFFFFF .word -16385 + 13566 .cfi_endproc + 13567 .LFE361: + 13569 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + ARM GAS /tmp/ccth6daj.s page 430 + + + 13570 .align 1 + 13571 .syntax unified + 13572 .code 16 + 13573 .thumb_func + 13574 .fpu softvfp + 13576 I2C_DMAMasterReceiveCplt: + 13577 .LVL990: + 13578 .LFB363: +6236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13579 .loc 1 6236 1 is_stmt 1 view -0 + 13580 .cfi_startproc + 13581 @ args = 0, pretend = 0, frame = 0 + 13582 @ frame_needed = 0, uses_anonymous_args = 0 +6236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13583 .loc 1 6236 1 is_stmt 0 view .LVU4338 + 13584 0000 10B5 push {r4, lr} + 13585 .LCFI91: + 13586 .cfi_def_cfa_offset 8 + 13587 .cfi_offset 4, -8 + 13588 .cfi_offset 14, -4 +6238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13589 .loc 1 6238 3 is_stmt 1 view .LVU4339 +6238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13590 .loc 1 6238 22 is_stmt 0 view .LVU4340 + 13591 0002 846A ldr r4, [r0, #40] + 13592 .LVL991: +6241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13593 .loc 1 6241 3 is_stmt 1 view .LVU4341 +6241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13594 .loc 1 6241 7 is_stmt 0 view .LVU4342 + 13595 0004 2268 ldr r2, [r4] +6241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13596 .loc 1 6241 23 view .LVU4343 + 13597 0006 1368 ldr r3, [r2] + 13598 0008 1549 ldr r1, .L758 + 13599 000a 0B40 ands r3, r1 + 13600 000c 1360 str r3, [r2] +6244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13601 .loc 1 6244 3 is_stmt 1 view .LVU4344 +6244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13602 .loc 1 6244 11 is_stmt 0 view .LVU4345 + 13603 000e 638D ldrh r3, [r4, #42] + 13604 0010 9BB2 uxth r3, r3 +6244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13605 .loc 1 6244 6 view .LVU4346 + 13606 0012 002B cmp r3, #0 + 13607 0014 17D0 beq .L757 +6253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13608 .loc 1 6253 5 is_stmt 1 view .LVU4347 +6253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13609 .loc 1 6253 27 is_stmt 0 view .LVU4348 + 13610 0016 228D ldrh r2, [r4, #40] +6253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13611 .loc 1 6253 20 view .LVU4349 + 13612 0018 636A ldr r3, [r4, #36] + 13613 001a 9C46 mov ip, r3 + 13614 001c 6244 add r2, r2, ip + ARM GAS /tmp/ccth6daj.s page 431 + + + 13615 001e 6262 str r2, [r4, #36] +6256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13616 .loc 1 6256 5 is_stmt 1 view .LVU4350 +6256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13617 .loc 1 6256 13 is_stmt 0 view .LVU4351 + 13618 0020 638D ldrh r3, [r4, #42] + 13619 0022 9BB2 uxth r3, r3 +6256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13620 .loc 1 6256 8 view .LVU4352 + 13621 0024 FF2B cmp r3, #255 + 13622 0026 13D9 bls .L754 +6258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13623 .loc 1 6258 7 is_stmt 1 view .LVU4353 +6258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13624 .loc 1 6258 22 is_stmt 0 view .LVU4354 + 13625 0028 FF23 movs r3, #255 + 13626 002a 2385 strh r3, [r4, #40] + 13627 .L755: +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13628 .loc 1 6266 5 is_stmt 1 view .LVU4355 +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13629 .loc 1 6266 50 is_stmt 0 view .LVU4356 + 13630 002c 2168 ldr r1, [r4] + 13631 002e 2431 adds r1, r1, #36 +6267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13632 .loc 1 6267 30 view .LVU4357 + 13633 0030 238D ldrh r3, [r4, #40] +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13634 .loc 1 6266 9 view .LVU4358 + 13635 0032 E06B ldr r0, [r4, #60] + 13636 .LVL992: +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13637 .loc 1 6266 9 view .LVU4359 + 13638 0034 FFF7FEFF bl HAL_DMA_Start_IT + 13639 .LVL993: +6266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13640 .loc 1 6266 8 view .LVU4360 + 13641 0038 0028 cmp r0, #0 + 13642 003a 0CD0 beq .L756 +6270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13643 .loc 1 6270 7 is_stmt 1 view .LVU4361 + 13644 003c 1021 movs r1, #16 + 13645 003e 2000 movs r0, r4 + 13646 0040 FFF7FEFF bl I2C_ITError + 13647 .LVL994: + 13648 .L751: +6278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13649 .loc 1 6278 1 is_stmt 0 view .LVU4362 + 13650 @ sp needed + 13651 .LVL995: +6278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13652 .loc 1 6278 1 view .LVU4363 + 13653 0044 10BD pop {r4, pc} + 13654 .LVL996: + 13655 .L757: +6247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13656 .loc 1 6247 5 is_stmt 1 view .LVU4364 + ARM GAS /tmp/ccth6daj.s page 432 + + + 13657 0046 2021 movs r1, #32 + 13658 0048 2000 movs r0, r4 + 13659 .LVL997: +6247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13660 .loc 1 6247 5 is_stmt 0 view .LVU4365 + 13661 004a FFF7FEFF bl I2C_Enable_IRQ + 13662 .LVL998: + 13663 004e F9E7 b .L751 + 13664 .LVL999: + 13665 .L754: +6262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13666 .loc 1 6262 7 is_stmt 1 view .LVU4366 +6262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13667 .loc 1 6262 28 is_stmt 0 view .LVU4367 + 13668 0050 638D ldrh r3, [r4, #42] +6262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13669 .loc 1 6262 22 view .LVU4368 + 13670 0052 2385 strh r3, [r4, #40] + 13671 0054 EAE7 b .L755 + 13672 .LVL1000: + 13673 .L756: +6275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13674 .loc 1 6275 7 is_stmt 1 view .LVU4369 + 13675 0056 4021 movs r1, #64 + 13676 0058 2000 movs r0, r4 + 13677 005a FFF7FEFF bl I2C_Enable_IRQ + 13678 .LVL1001: +6278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13679 .loc 1 6278 1 is_stmt 0 view .LVU4370 + 13680 005e F1E7 b .L751 + 13681 .L759: + 13682 .align 2 + 13683 .L758: + 13684 0060 FF7FFFFF .word -32769 + 13685 .cfi_endproc + 13686 .LFE363: + 13688 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 13689 .align 1 + 13690 .global HAL_I2C_ER_IRQHandler + 13691 .syntax unified + 13692 .code 16 + 13693 .thumb_func + 13694 .fpu softvfp + 13696 HAL_I2C_ER_IRQHandler: + 13697 .LVL1002: + 13698 .LFB332: +4454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 13699 .loc 1 4454 1 is_stmt 1 view -0 + 13700 .cfi_startproc + 13701 @ args = 0, pretend = 0, frame = 0 + 13702 @ frame_needed = 0, uses_anonymous_args = 0 +4454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 13703 .loc 1 4454 1 is_stmt 0 view .LVU4372 + 13704 0000 70B5 push {r4, r5, r6, lr} + 13705 .LCFI92: + 13706 .cfi_def_cfa_offset 16 + 13707 .cfi_offset 4, -16 + ARM GAS /tmp/ccth6daj.s page 433 + + + 13708 .cfi_offset 5, -12 + 13709 .cfi_offset 6, -8 + 13710 .cfi_offset 14, -4 +4455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13711 .loc 1 4455 3 is_stmt 1 view .LVU4373 +4455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13712 .loc 1 4455 24 is_stmt 0 view .LVU4374 + 13713 0002 0268 ldr r2, [r0] +4455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 13714 .loc 1 4455 12 view .LVU4375 + 13715 0004 9369 ldr r3, [r2, #24] + 13716 .LVL1003: +4456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; + 13717 .loc 1 4456 3 is_stmt 1 view .LVU4376 +4456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** uint32_t tmperror; + 13718 .loc 1 4456 12 is_stmt 0 view .LVU4377 + 13719 0006 1168 ldr r1, [r2] + 13720 .LVL1004: +4457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13721 .loc 1 4457 3 is_stmt 1 view .LVU4378 +4460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13722 .loc 1 4460 3 view .LVU4379 +4460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13723 .loc 1 4460 6 is_stmt 0 view .LVU4380 + 13724 0008 DC05 lsls r4, r3, #23 + 13725 000a 08D5 bpl .L761 +4460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13726 .loc 1 4460 57 discriminator 1 view .LVU4381 + 13727 000c 0C06 lsls r4, r1, #24 + 13728 000e 06D5 bpl .L761 +4463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13729 .loc 1 4463 5 is_stmt 1 view .LVU4382 +4463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13730 .loc 1 4463 21 is_stmt 0 view .LVU4383 + 13731 0010 446C ldr r4, [r0, #68] + 13732 0012 0125 movs r5, #1 + 13733 0014 2C43 orrs r4, r5 + 13734 0016 4464 str r4, [r0, #68] +4466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13735 .loc 1 4466 5 is_stmt 1 view .LVU4384 + 13736 0018 8024 movs r4, #128 + 13737 001a 6400 lsls r4, r4, #1 + 13738 001c D461 str r4, [r2, #28] + 13739 .L761: +4470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13740 .loc 1 4470 3 view .LVU4385 +4470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13741 .loc 1 4470 6 is_stmt 0 view .LVU4386 + 13742 001e 5A05 lsls r2, r3, #21 + 13743 0020 09D5 bpl .L762 +4470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13744 .loc 1 4470 56 discriminator 1 view .LVU4387 + 13745 0022 0A06 lsls r2, r1, #24 + 13746 0024 07D5 bpl .L762 +4473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13747 .loc 1 4473 5 is_stmt 1 view .LVU4388 +4473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + ARM GAS /tmp/ccth6daj.s page 434 + + + 13748 .loc 1 4473 21 is_stmt 0 view .LVU4389 + 13749 0026 426C ldr r2, [r0, #68] + 13750 0028 0824 movs r4, #8 + 13751 002a 2243 orrs r2, r4 + 13752 002c 4264 str r2, [r0, #68] +4476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13753 .loc 1 4476 5 is_stmt 1 view .LVU4390 + 13754 002e 0268 ldr r2, [r0] + 13755 0030 8024 movs r4, #128 + 13756 0032 E400 lsls r4, r4, #3 + 13757 0034 D461 str r4, [r2, #28] + 13758 .L762: +4480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13759 .loc 1 4480 3 view .LVU4391 +4480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13760 .loc 1 4480 6 is_stmt 0 view .LVU4392 + 13761 0036 9B05 lsls r3, r3, #22 + 13762 0038 09D5 bpl .L763 + 13763 .LVL1005: +4480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 13764 .loc 1 4480 57 discriminator 1 view .LVU4393 + 13765 003a 0B06 lsls r3, r1, #24 + 13766 003c 07D5 bpl .L763 +4483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13767 .loc 1 4483 5 is_stmt 1 view .LVU4394 +4483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13768 .loc 1 4483 21 is_stmt 0 view .LVU4395 + 13769 003e 436C ldr r3, [r0, #68] + 13770 0040 0222 movs r2, #2 + 13771 0042 1343 orrs r3, r2 + 13772 0044 4364 str r3, [r0, #68] +4486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13773 .loc 1 4486 5 is_stmt 1 view .LVU4396 + 13774 0046 0368 ldr r3, [r0] + 13775 0048 FF32 adds r2, r2, #255 + 13776 004a FF32 adds r2, r2, #255 + 13777 004c DA61 str r2, [r3, #28] + 13778 .L763: +4490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13779 .loc 1 4490 3 view .LVU4397 +4490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13780 .loc 1 4490 12 is_stmt 0 view .LVU4398 + 13781 004e 416C ldr r1, [r0, #68] + 13782 .LVL1006: +4493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13783 .loc 1 4493 3 is_stmt 1 view .LVU4399 +4493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13784 .loc 1 4493 17 is_stmt 0 view .LVU4400 + 13785 0050 0B23 movs r3, #11 +4493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13786 .loc 1 4493 6 view .LVU4401 + 13787 0052 0B42 tst r3, r1 + 13788 0054 00D1 bne .L765 + 13789 .LVL1007: + 13790 .L760: +4497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13791 .loc 1 4497 1 view .LVU4402 + ARM GAS /tmp/ccth6daj.s page 435 + + + 13792 @ sp needed + 13793 0056 70BD pop {r4, r5, r6, pc} + 13794 .LVL1008: + 13795 .L765: +4495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13796 .loc 1 4495 5 is_stmt 1 view .LVU4403 + 13797 0058 FFF7FEFF bl I2C_ITError + 13798 .LVL1009: +4497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13799 .loc 1 4497 1 is_stmt 0 view .LVU4404 + 13800 005c FBE7 b .L760 + 13801 .cfi_endproc + 13802 .LFE332: + 13804 .section .text.I2C_DMAAbort,"ax",%progbits + 13805 .align 1 + 13806 .syntax unified + 13807 .code 16 + 13808 .thumb_func + 13809 .fpu softvfp + 13811 I2C_DMAAbort: + 13812 .LVL1010: + 13813 .LFB366: +6332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13814 .loc 1 6332 1 is_stmt 1 view -0 + 13815 .cfi_startproc + 13816 @ args = 0, pretend = 0, frame = 0 + 13817 @ frame_needed = 0, uses_anonymous_args = 0 +6332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ + 13818 .loc 1 6332 1 is_stmt 0 view .LVU4406 + 13819 0000 10B5 push {r4, lr} + 13820 .LCFI93: + 13821 .cfi_def_cfa_offset 8 + 13822 .cfi_offset 4, -8 + 13823 .cfi_offset 14, -4 +6334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13824 .loc 1 6334 3 is_stmt 1 view .LVU4407 +6334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13825 .loc 1 6334 22 is_stmt 0 view .LVU4408 + 13826 0002 806A ldr r0, [r0, #40] + 13827 .LVL1011: +6337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13828 .loc 1 6337 3 is_stmt 1 view .LVU4409 +6337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13829 .loc 1 6337 11 is_stmt 0 view .LVU4410 + 13830 0004 836B ldr r3, [r0, #56] +6337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13831 .loc 1 6337 6 view .LVU4411 + 13832 0006 002B cmp r3, #0 + 13833 0008 01D0 beq .L767 +6339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13834 .loc 1 6339 5 is_stmt 1 view .LVU4412 +6339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13835 .loc 1 6339 37 is_stmt 0 view .LVU4413 + 13836 000a 0022 movs r2, #0 + 13837 000c 9A63 str r2, [r3, #56] + 13838 .L767: +6341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + ARM GAS /tmp/ccth6daj.s page 436 + + + 13839 .loc 1 6341 3 is_stmt 1 view .LVU4414 +6341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13840 .loc 1 6341 11 is_stmt 0 view .LVU4415 + 13841 000e C36B ldr r3, [r0, #60] +6341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** { + 13842 .loc 1 6341 6 view .LVU4416 + 13843 0010 002B cmp r3, #0 + 13844 0012 01D0 beq .L768 +6343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13845 .loc 1 6343 5 is_stmt 1 view .LVU4417 +6343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13846 .loc 1 6343 37 is_stmt 0 view .LVU4418 + 13847 0014 0022 movs r2, #0 + 13848 0016 9A63 str r2, [r3, #56] + 13849 .L768: +6346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13850 .loc 1 6346 3 is_stmt 1 view .LVU4419 + 13851 0018 FFF7FEFF bl I2C_TreatErrorCallback + 13852 .LVL1012: +6347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13853 .loc 1 6347 1 is_stmt 0 view .LVU4420 + 13854 @ sp needed + 13855 001c 10BD pop {r4, pc} + 13856 .cfi_endproc + 13857 .LFE366: + 13859 .section .text.HAL_I2C_GetState,"ax",%progbits + 13860 .align 1 + 13861 .global HAL_I2C_GetState + 13862 .syntax unified + 13863 .code 16 + 13864 .thumb_func + 13865 .fpu softvfp + 13867 HAL_I2C_GetState: + 13868 .LVL1013: + 13869 .LFB343: +4688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** /* Return I2C handle state */ + 13870 .loc 1 4688 1 is_stmt 1 view -0 + 13871 .cfi_startproc + 13872 @ args = 0, pretend = 0, frame = 0 + 13873 @ frame_needed = 0, uses_anonymous_args = 0 + 13874 @ link register save eliminated. +4690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13875 .loc 1 4690 3 view .LVU4422 +4690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13876 .loc 1 4690 14 is_stmt 0 view .LVU4423 + 13877 0000 4123 movs r3, #65 + 13878 0002 C05C ldrb r0, [r0, r3] + 13879 .LVL1014: +4690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13880 .loc 1 4690 14 view .LVU4424 + 13881 0004 C0B2 uxtb r0, r0 +4691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13882 .loc 1 4691 1 view .LVU4425 + 13883 @ sp needed + 13884 0006 7047 bx lr + 13885 .cfi_endproc + 13886 .LFE343: + ARM GAS /tmp/ccth6daj.s page 437 + + + 13888 .section .text.HAL_I2C_GetMode,"ax",%progbits + 13889 .align 1 + 13890 .global HAL_I2C_GetMode + 13891 .syntax unified + 13892 .code 16 + 13893 .thumb_func + 13894 .fpu softvfp + 13896 HAL_I2C_GetMode: + 13897 .LVL1015: + 13898 .LFB344: +4700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return hi2c->Mode; + 13899 .loc 1 4700 1 is_stmt 1 view -0 + 13900 .cfi_startproc + 13901 @ args = 0, pretend = 0, frame = 0 + 13902 @ frame_needed = 0, uses_anonymous_args = 0 + 13903 @ link register save eliminated. +4701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13904 .loc 1 4701 3 view .LVU4427 +4701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13905 .loc 1 4701 14 is_stmt 0 view .LVU4428 + 13906 0000 4223 movs r3, #66 + 13907 0002 C05C ldrb r0, [r0, r3] + 13908 .LVL1016: +4701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13909 .loc 1 4701 14 view .LVU4429 + 13910 0004 C0B2 uxtb r0, r0 +4702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13911 .loc 1 4702 1 view .LVU4430 + 13912 @ sp needed + 13913 0006 7047 bx lr + 13914 .cfi_endproc + 13915 .LFE344: + 13917 .section .text.HAL_I2C_GetError,"ax",%progbits + 13918 .align 1 + 13919 .global HAL_I2C_GetError + 13920 .syntax unified + 13921 .code 16 + 13922 .thumb_func + 13923 .fpu softvfp + 13925 HAL_I2C_GetError: + 13926 .LVL1017: + 13927 .LFB345: +4711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** return hi2c->ErrorCode; + 13928 .loc 1 4711 1 is_stmt 1 view -0 + 13929 .cfi_startproc + 13930 @ args = 0, pretend = 0, frame = 0 + 13931 @ frame_needed = 0, uses_anonymous_args = 0 + 13932 @ link register save eliminated. +4712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13933 .loc 1 4712 3 view .LVU4432 +4712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** } + 13934 .loc 1 4712 14 is_stmt 0 view .LVU4433 + 13935 0000 406C ldr r0, [r0, #68] + 13936 .LVL1018: +4713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c.c **** + 13937 .loc 1 4713 1 view .LVU4434 + 13938 @ sp needed + ARM GAS /tmp/ccth6daj.s page 438 + + + 13939 0002 7047 bx lr + 13940 .cfi_endproc + 13941 .LFE345: + 13943 .text + 13944 .Letext0: + 13945 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 13946 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 13947 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h" + 13948 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 13949 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 13950 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h" + 13951 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 13952 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + ARM GAS /tmp/ccth6daj.s page 439 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_i2c.c + /tmp/ccth6daj.s:16 .text.I2C_Flush_TXDR:0000000000000000 $t + /tmp/ccth6daj.s:23 .text.I2C_Flush_TXDR:0000000000000000 I2C_Flush_TXDR + /tmp/ccth6daj.s:64 .text.I2C_TransferConfig:0000000000000000 $t + /tmp/ccth6daj.s:70 .text.I2C_TransferConfig:0000000000000000 I2C_TransferConfig + /tmp/ccth6daj.s:122 .text.I2C_TransferConfig:000000000000002c $d + /tmp/ccth6daj.s:127 .text.I2C_Enable_IRQ:0000000000000000 $t + /tmp/ccth6daj.s:133 .text.I2C_Enable_IRQ:0000000000000000 I2C_Enable_IRQ + /tmp/ccth6daj.s:271 .text.I2C_Enable_IRQ:0000000000000068 $d + /tmp/ccth6daj.s:13089 .text.I2C_Master_ISR_DMA:0000000000000000 I2C_Master_ISR_DMA + /tmp/ccth6daj.s:12772 .text.I2C_Slave_ISR_DMA:0000000000000000 I2C_Slave_ISR_DMA + /tmp/ccth6daj.s:277 .text.I2C_Disable_IRQ:0000000000000000 $t + /tmp/ccth6daj.s:283 .text.I2C_Disable_IRQ:0000000000000000 I2C_Disable_IRQ + /tmp/ccth6daj.s:425 .text.I2C_ConvertOtherXferOptions:0000000000000000 $t + /tmp/ccth6daj.s:431 .text.I2C_ConvertOtherXferOptions:0000000000000000 I2C_ConvertOtherXferOptions + /tmp/ccth6daj.s:476 .text.I2C_IsAcknowledgeFailed:0000000000000000 $t + /tmp/ccth6daj.s:482 .text.I2C_IsAcknowledgeFailed:0000000000000000 I2C_IsAcknowledgeFailed + /tmp/ccth6daj.s:633 .text.I2C_IsAcknowledgeFailed:000000000000008c $d + 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© Copyright (c) 2018 STMicroelectronics. + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * All rights reserved.
+ 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * the "License"; You may not use this file except in compliance with the + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * License. You may obtain a copy of the License at: + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * opensource.org/licenses/BSD-3-Clause + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** ****************************************************************************** + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** #include "stm32g0xx_hal.h" + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Filter Mode Functions + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @verbatim + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** ##### Filter Mode Functions ##### + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @endverbatim + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + ARM GAS /tmp/ccgSBUcl.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval HAL status + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 28 .loc 1 96 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 96 1 is_stmt 0 view .LVU1 + 33 0000 F0B5 push {r4, r5, r6, r7, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 20 + 36 .cfi_offset 4, -20 + 37 .cfi_offset 5, -16 + 38 .cfi_offset 6, -12 + 39 .cfi_offset 7, -8 + 40 .cfi_offset 14, -4 + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameters */ + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 41 .loc 1 98 3 is_stmt 1 view .LVU2 + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 42 .loc 1 99 3 view .LVU3 + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 43 .loc 1 101 3 view .LVU4 + 44 .loc 1 101 11 is_stmt 0 view .LVU5 + 45 0002 4123 movs r3, #65 + 46 0004 C35C ldrb r3, [r0, r3] + 47 .loc 1 101 6 view .LVU6 + 48 0006 202B cmp r3, #32 + 49 0008 20D1 bne .L3 + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Locked */ + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 50 .loc 1 104 5 is_stmt 1 view .LVU7 + 51 .loc 1 104 5 view .LVU8 + 52 000a 2033 adds r3, r3, #32 + 53 000c C35C ldrb r3, [r0, r3] + 54 000e 012B cmp r3, #1 + 55 0010 1ED0 beq .L4 + 56 .loc 1 104 5 discriminator 2 view .LVU9 + 57 0012 4024 movs r4, #64 + 58 0014 0122 movs r2, #1 + 59 0016 0255 strb r2, [r0, r4] + 60 .loc 1 104 5 discriminator 2 view .LVU10 + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 61 .loc 1 106 5 discriminator 2 view .LVU11 + 62 .loc 1 106 17 is_stmt 0 discriminator 2 view .LVU12 + 63 0018 4125 movs r5, #65 + 64 001a 2423 movs r3, #36 + 65 001c 4355 strb r3, [r0, r5] + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccgSBUcl.s page 4 + + + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 66 .loc 1 109 5 is_stmt 1 discriminator 2 view .LVU13 + 67 001e 0668 ldr r6, [r0] + 68 0020 3368 ldr r3, [r6] + 69 0022 9343 bics r3, r2 + 70 0024 3360 str r3, [r6] + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 71 .loc 1 112 5 discriminator 2 view .LVU14 + 72 .loc 1 112 9 is_stmt 0 discriminator 2 view .LVU15 + 73 0026 0668 ldr r6, [r0] + 74 .loc 1 112 25 discriminator 2 view .LVU16 + 75 0028 3368 ldr r3, [r6] + 76 002a 0A4F ldr r7, .L5 + 77 002c 3B40 ands r3, r7 + 78 002e 3360 str r3, [r6] + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 79 .loc 1 115 5 is_stmt 1 discriminator 2 view .LVU17 + 80 .loc 1 115 9 is_stmt 0 discriminator 2 view .LVU18 + 81 0030 0668 ldr r6, [r0] + 82 .loc 1 115 25 discriminator 2 view .LVU19 + 83 0032 3368 ldr r3, [r6] + 84 0034 1943 orrs r1, r3 + 85 .LVL1: + 86 .loc 1 115 25 discriminator 2 view .LVU20 + 87 0036 3160 str r1, [r6] + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 88 .loc 1 117 5 is_stmt 1 discriminator 2 view .LVU21 + 89 0038 0168 ldr r1, [r0] + 90 003a 0B68 ldr r3, [r1] + 91 003c 1343 orrs r3, r2 + 92 003e 0B60 str r3, [r1] + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 93 .loc 1 119 5 discriminator 2 view .LVU22 + 94 .loc 1 119 17 is_stmt 0 discriminator 2 view .LVU23 + 95 0040 2023 movs r3, #32 + 96 0042 4355 strb r3, [r0, r5] + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 97 .loc 1 122 5 is_stmt 1 discriminator 2 view .LVU24 + 98 .loc 1 122 5 discriminator 2 view .LVU25 + 99 0044 0023 movs r3, #0 + 100 0046 0355 strb r3, [r0, r4] + 101 .loc 1 122 5 discriminator 2 view .LVU26 + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_OK; + 102 .loc 1 124 5 discriminator 2 view .LVU27 + 103 .loc 1 124 12 is_stmt 0 discriminator 2 view .LVU28 + 104 0048 0020 movs r0, #0 + 105 .LVL2: + ARM GAS /tmp/ccgSBUcl.s page 5 + + + 106 .L2: + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** else + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_BUSY; + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 107 .loc 1 130 1 view .LVU29 + 108 @ sp needed + 109 004a F0BD pop {r4, r5, r6, r7, pc} + 110 .LVL3: + 111 .L3: + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 112 .loc 1 128 12 view .LVU30 + 113 004c 0220 movs r0, #2 + 114 .LVL4: + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 115 .loc 1 128 12 view .LVU31 + 116 004e FCE7 b .L2 + 117 .LVL5: + 118 .L4: + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 119 .loc 1 104 5 view .LVU32 + 120 0050 0220 movs r0, #2 + 121 .LVL6: + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 122 .loc 1 104 5 view .LVU33 + 123 0052 FAE7 b .L2 + 124 .L6: + 125 .align 2 + 126 .L5: + 127 0054 FFEFFFFF .word -4097 + 128 .cfi_endproc + 129 .LFE297: + 131 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 132 .align 1 + 133 .global HAL_I2CEx_ConfigDigitalFilter + 134 .syntax unified + 135 .code 16 + 136 .thumb_func + 137 .fpu softvfp + 139 HAL_I2CEx_ConfigDigitalFilter: + 140 .LVL7: + 141 .LFB298: + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval HAL status + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 142 .loc 1 140 1 is_stmt 1 view -0 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccgSBUcl.s page 6 + + + 145 @ frame_needed = 0, uses_anonymous_args = 0 + 146 .loc 1 140 1 is_stmt 0 view .LVU35 + 147 0000 F0B5 push {r4, r5, r6, r7, lr} + 148 .LCFI1: + 149 .cfi_def_cfa_offset 20 + 150 .cfi_offset 4, -20 + 151 .cfi_offset 5, -16 + 152 .cfi_offset 6, -12 + 153 .cfi_offset 7, -8 + 154 .cfi_offset 14, -4 + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** uint32_t tmpreg; + 155 .loc 1 141 3 is_stmt 1 view .LVU36 + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameters */ + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 156 .loc 1 144 3 view .LVU37 + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 157 .loc 1 145 3 view .LVU38 + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 158 .loc 1 147 3 view .LVU39 + 159 .loc 1 147 11 is_stmt 0 view .LVU40 + 160 0002 4123 movs r3, #65 + 161 0004 C35C ldrb r3, [r0, r3] + 162 .loc 1 147 6 view .LVU41 + 163 0006 202B cmp r3, #32 + 164 0008 1ED1 bne .L9 + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Locked */ + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 165 .loc 1 150 5 is_stmt 1 view .LVU42 + 166 .loc 1 150 5 view .LVU43 + 167 000a 2033 adds r3, r3, #32 + 168 000c C35C ldrb r3, [r0, r3] + 169 000e 012B cmp r3, #1 + 170 0010 1CD0 beq .L10 + 171 .loc 1 150 5 discriminator 2 view .LVU44 + 172 0012 4024 movs r4, #64 + 173 0014 0122 movs r2, #1 + 174 0016 0255 strb r2, [r0, r4] + 175 .loc 1 150 5 discriminator 2 view .LVU45 + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 176 .loc 1 152 5 discriminator 2 view .LVU46 + 177 .loc 1 152 17 is_stmt 0 discriminator 2 view .LVU47 + 178 0018 4125 movs r5, #65 + 179 001a 2423 movs r3, #36 + 180 001c 4355 strb r3, [r0, r5] + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 181 .loc 1 155 5 is_stmt 1 discriminator 2 view .LVU48 + 182 001e 0668 ldr r6, [r0] + 183 0020 3368 ldr r3, [r6] + 184 0022 9343 bics r3, r2 + 185 0024 3360 str r3, [r6] + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccgSBUcl.s page 7 + + + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Get the old register value */ + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 186 .loc 1 158 5 discriminator 2 view .LVU49 + 187 .loc 1 158 18 is_stmt 0 discriminator 2 view .LVU50 + 188 0026 0668 ldr r6, [r0] + 189 .loc 1 158 12 discriminator 2 view .LVU51 + 190 0028 3368 ldr r3, [r6] + 191 .LVL8: + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 192 .loc 1 161 5 is_stmt 1 discriminator 2 view .LVU52 + 193 .loc 1 161 12 is_stmt 0 discriminator 2 view .LVU53 + 194 002a 094F ldr r7, .L11 + 195 002c 3B40 ands r3, r7 + 196 .LVL9: + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 197 .loc 1 164 5 is_stmt 1 discriminator 2 view .LVU54 + 198 .loc 1 164 29 is_stmt 0 discriminator 2 view .LVU55 + 199 002e 0902 lsls r1, r1, #8 + 200 .LVL10: + 201 .loc 1 164 12 discriminator 2 view .LVU56 + 202 0030 1943 orrs r1, r3 + 203 .LVL11: + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Store the new register value */ + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 204 .loc 1 167 5 is_stmt 1 discriminator 2 view .LVU57 + 205 .loc 1 167 25 is_stmt 0 discriminator 2 view .LVU58 + 206 0032 3160 str r1, [r6] + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 207 .loc 1 169 5 is_stmt 1 discriminator 2 view .LVU59 + 208 0034 0168 ldr r1, [r0] + 209 .LVL12: + 210 .loc 1 169 5 is_stmt 0 discriminator 2 view .LVU60 + 211 0036 0B68 ldr r3, [r1] + 212 0038 1343 orrs r3, r2 + 213 003a 0B60 str r3, [r1] + 214 .LVL13: + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 215 .loc 1 171 5 is_stmt 1 discriminator 2 view .LVU61 + 216 .loc 1 171 17 is_stmt 0 discriminator 2 view .LVU62 + 217 003c 2023 movs r3, #32 + 218 003e 4355 strb r3, [r0, r5] + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 219 .loc 1 174 5 is_stmt 1 discriminator 2 view .LVU63 + 220 .loc 1 174 5 discriminator 2 view .LVU64 + 221 0040 0023 movs r3, #0 + 222 0042 0355 strb r3, [r0, r4] + 223 .loc 1 174 5 discriminator 2 view .LVU65 + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccgSBUcl.s page 8 + + + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_OK; + 224 .loc 1 176 5 discriminator 2 view .LVU66 + 225 .loc 1 176 12 is_stmt 0 discriminator 2 view .LVU67 + 226 0044 0020 movs r0, #0 + 227 .LVL14: + 228 .L8: + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** else + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_BUSY; + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 229 .loc 1 182 1 view .LVU68 + 230 @ sp needed + 231 0046 F0BD pop {r4, r5, r6, r7, pc} + 232 .LVL15: + 233 .L9: + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 234 .loc 1 180 12 view .LVU69 + 235 0048 0220 movs r0, #2 + 236 .LVL16: + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 237 .loc 1 180 12 view .LVU70 + 238 004a FCE7 b .L8 + 239 .LVL17: + 240 .L10: + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 241 .loc 1 150 5 view .LVU71 + 242 004c 0220 movs r0, #2 + 243 .LVL18: + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 244 .loc 1 150 5 view .LVU72 + 245 004e FAE7 b .L8 + 246 .L12: + 247 .align 2 + 248 .L11: + 249 0050 FFF0FFFF .word -3841 + 250 .cfi_endproc + 251 .LFE298: + 253 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits + 254 .align 1 + 255 .global HAL_I2CEx_EnableWakeUp + 256 .syntax unified + 257 .code 16 + 258 .thumb_func + 259 .fpu softvfp + 261 HAL_I2CEx_EnableWakeUp: + 262 .LVL19: + 263 .LFB299: + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @} + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief WakeUp Mode Functions + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @verbatim + ARM GAS /tmp/ccgSBUcl.s page 9 + + + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** ##### WakeUp Mode Functions ##### + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @endverbatim + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s). + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval HAL status + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 264 .loc 1 208 1 is_stmt 1 view -0 + 265 .cfi_startproc + 266 @ args = 0, pretend = 0, frame = 0 + 267 @ frame_needed = 0, uses_anonymous_args = 0 + 268 .loc 1 208 1 is_stmt 0 view .LVU74 + 269 0000 70B5 push {r4, r5, r6, lr} + 270 .LCFI2: + 271 .cfi_def_cfa_offset 16 + 272 .cfi_offset 4, -16 + 273 .cfi_offset 5, -12 + 274 .cfi_offset 6, -8 + 275 .cfi_offset 14, -4 + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameters */ + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 276 .loc 1 210 3 is_stmt 1 view .LVU75 + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 277 .loc 1 212 3 view .LVU76 + 278 .loc 1 212 11 is_stmt 0 view .LVU77 + 279 0002 4123 movs r3, #65 + 280 0004 C35C ldrb r3, [r0, r3] + 281 .loc 1 212 6 view .LVU78 + 282 0006 202B cmp r3, #32 + 283 0008 1DD1 bne .L15 + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Locked */ + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 284 .loc 1 215 5 is_stmt 1 view .LVU79 + 285 .loc 1 215 5 view .LVU80 + 286 000a 2033 adds r3, r3, #32 + 287 000c C35C ldrb r3, [r0, r3] + 288 000e 012B cmp r3, #1 + 289 0010 1BD0 beq .L16 + 290 .loc 1 215 5 discriminator 2 view .LVU81 + 291 0012 4021 movs r1, #64 + 292 0014 0122 movs r2, #1 + 293 0016 4254 strb r2, [r0, r1] + 294 .loc 1 215 5 discriminator 2 view .LVU82 + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccgSBUcl.s page 10 + + + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 295 .loc 1 217 5 discriminator 2 view .LVU83 + 296 .loc 1 217 17 is_stmt 0 discriminator 2 view .LVU84 + 297 0018 4124 movs r4, #65 + 298 001a 2423 movs r3, #36 + 299 001c 0355 strb r3, [r0, r4] + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 300 .loc 1 220 5 is_stmt 1 discriminator 2 view .LVU85 + 301 001e 0568 ldr r5, [r0] + 302 0020 2B68 ldr r3, [r5] + 303 0022 9343 bics r3, r2 + 304 0024 2B60 str r3, [r5] + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + 305 .loc 1 223 5 discriminator 2 view .LVU86 + 306 .loc 1 223 9 is_stmt 0 discriminator 2 view .LVU87 + 307 0026 0568 ldr r5, [r0] + 308 .loc 1 223 25 discriminator 2 view .LVU88 + 309 0028 2E68 ldr r6, [r5] + 310 002a 8023 movs r3, #128 + 311 002c DB02 lsls r3, r3, #11 + 312 002e 3343 orrs r3, r6 + 313 0030 2B60 str r3, [r5] + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 314 .loc 1 225 5 is_stmt 1 discriminator 2 view .LVU89 + 315 0032 0568 ldr r5, [r0] + 316 0034 2B68 ldr r3, [r5] + 317 0036 1343 orrs r3, r2 + 318 0038 2B60 str r3, [r5] + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 319 .loc 1 227 5 discriminator 2 view .LVU90 + 320 .loc 1 227 17 is_stmt 0 discriminator 2 view .LVU91 + 321 003a 2023 movs r3, #32 + 322 003c 0355 strb r3, [r0, r4] + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 323 .loc 1 230 5 is_stmt 1 discriminator 2 view .LVU92 + 324 .loc 1 230 5 discriminator 2 view .LVU93 + 325 003e 0023 movs r3, #0 + 326 0040 4354 strb r3, [r0, r1] + 327 .loc 1 230 5 discriminator 2 view .LVU94 + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_OK; + 328 .loc 1 232 5 discriminator 2 view .LVU95 + 329 .loc 1 232 12 is_stmt 0 discriminator 2 view .LVU96 + 330 0042 0020 movs r0, #0 + 331 .LVL20: + 332 .L14: + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** else + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + ARM GAS /tmp/ccgSBUcl.s page 11 + + + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_BUSY; + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 333 .loc 1 238 1 view .LVU97 + 334 @ sp needed + 335 0044 70BD pop {r4, r5, r6, pc} + 336 .LVL21: + 337 .L15: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 338 .loc 1 236 12 view .LVU98 + 339 0046 0220 movs r0, #2 + 340 .LVL22: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 341 .loc 1 236 12 view .LVU99 + 342 0048 FCE7 b .L14 + 343 .LVL23: + 344 .L16: + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 345 .loc 1 215 5 view .LVU100 + 346 004a 0220 movs r0, #2 + 347 .LVL24: + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 348 .loc 1 215 5 view .LVU101 + 349 004c FAE7 b .L14 + 350 .cfi_endproc + 351 .LFE299: + 353 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits + 354 .align 1 + 355 .global HAL_I2CEx_DisableWakeUp + 356 .syntax unified + 357 .code 16 + 358 .thumb_func + 359 .fpu softvfp + 361 HAL_I2CEx_DisableWakeUp: + 362 .LVL25: + 363 .LFB300: + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s). + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval HAL status + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 364 .loc 1 247 1 is_stmt 1 view -0 + 365 .cfi_startproc + 366 @ args = 0, pretend = 0, frame = 0 + 367 @ frame_needed = 0, uses_anonymous_args = 0 + 368 .loc 1 247 1 is_stmt 0 view .LVU103 + 369 0000 70B5 push {r4, r5, r6, lr} + 370 .LCFI3: + 371 .cfi_def_cfa_offset 16 + 372 .cfi_offset 4, -16 + 373 .cfi_offset 5, -12 + 374 .cfi_offset 6, -8 + 375 .cfi_offset 14, -4 + ARM GAS /tmp/ccgSBUcl.s page 12 + + + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameters */ + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 376 .loc 1 249 3 is_stmt 1 view .LVU104 + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 377 .loc 1 251 3 view .LVU105 + 378 .loc 1 251 11 is_stmt 0 view .LVU106 + 379 0002 4123 movs r3, #65 + 380 0004 C35C ldrb r3, [r0, r3] + 381 .loc 1 251 6 view .LVU107 + 382 0006 202B cmp r3, #32 + 383 0008 1CD1 bne .L19 + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Locked */ + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 384 .loc 1 254 5 is_stmt 1 view .LVU108 + 385 .loc 1 254 5 view .LVU109 + 386 000a 2033 adds r3, r3, #32 + 387 000c C35C ldrb r3, [r0, r3] + 388 000e 012B cmp r3, #1 + 389 0010 1AD0 beq .L20 + 390 .loc 1 254 5 discriminator 2 view .LVU110 + 391 0012 4021 movs r1, #64 + 392 0014 0122 movs r2, #1 + 393 0016 4254 strb r2, [r0, r1] + 394 .loc 1 254 5 discriminator 2 view .LVU111 + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 395 .loc 1 256 5 discriminator 2 view .LVU112 + 396 .loc 1 256 17 is_stmt 0 discriminator 2 view .LVU113 + 397 0018 4124 movs r4, #65 + 398 001a 2423 movs r3, #36 + 399 001c 0355 strb r3, [r0, r4] + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 400 .loc 1 259 5 is_stmt 1 discriminator 2 view .LVU114 + 401 001e 0568 ldr r5, [r0] + 402 0020 2B68 ldr r3, [r5] + 403 0022 9343 bics r3, r2 + 404 0024 2B60 str r3, [r5] + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + 405 .loc 1 262 5 discriminator 2 view .LVU115 + 406 .loc 1 262 9 is_stmt 0 discriminator 2 view .LVU116 + 407 0026 0568 ldr r5, [r0] + 408 .loc 1 262 25 discriminator 2 view .LVU117 + 409 0028 2B68 ldr r3, [r5] + 410 002a 084E ldr r6, .L21 + 411 002c 3340 ands r3, r6 + 412 002e 2B60 str r3, [r5] + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 413 .loc 1 264 5 is_stmt 1 discriminator 2 view .LVU118 + 414 0030 0568 ldr r5, [r0] + 415 0032 2B68 ldr r3, [r5] + ARM GAS /tmp/ccgSBUcl.s page 13 + + + 416 0034 1343 orrs r3, r2 + 417 0036 2B60 str r3, [r5] + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 418 .loc 1 266 5 discriminator 2 view .LVU119 + 419 .loc 1 266 17 is_stmt 0 discriminator 2 view .LVU120 + 420 0038 2023 movs r3, #32 + 421 003a 0355 strb r3, [r0, r4] + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Process Unlocked */ + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 422 .loc 1 269 5 is_stmt 1 discriminator 2 view .LVU121 + 423 .loc 1 269 5 discriminator 2 view .LVU122 + 424 003c 0023 movs r3, #0 + 425 003e 4354 strb r3, [r0, r1] + 426 .loc 1 269 5 discriminator 2 view .LVU123 + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_OK; + 427 .loc 1 271 5 discriminator 2 view .LVU124 + 428 .loc 1 271 12 is_stmt 0 discriminator 2 view .LVU125 + 429 0040 0020 movs r0, #0 + 430 .LVL26: + 431 .L18: + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** else + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** return HAL_BUSY; + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 432 .loc 1 277 1 view .LVU126 + 433 @ sp needed + 434 0042 70BD pop {r4, r5, r6, pc} + 435 .LVL27: + 436 .L19: + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 437 .loc 1 275 12 view .LVU127 + 438 0044 0220 movs r0, #2 + 439 .LVL28: + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 440 .loc 1 275 12 view .LVU128 + 441 0046 FCE7 b .L18 + 442 .LVL29: + 443 .L20: + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 444 .loc 1 254 5 view .LVU129 + 445 0048 0220 movs r0, #2 + 446 .LVL30: + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 447 .loc 1 254 5 view .LVU130 + 448 004a FAE7 b .L18 + 449 .L22: + 450 .align 2 + 451 .L21: + 452 004c FFFFFBFF .word -262145 + 453 .cfi_endproc + 454 .LFE300: + 456 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + ARM GAS /tmp/ccgSBUcl.s page 14 + + + 457 .align 1 + 458 .global HAL_I2CEx_EnableFastModePlus + 459 .syntax unified + 460 .code 16 + 461 .thumb_func + 462 .fpu softvfp + 464 HAL_I2CEx_EnableFastModePlus: + 465 .LVL31: + 466 .LFB301: + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @} + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @verbatim + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** ##### Fast Mode Plus Functions ##### + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** =============================================================================== + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** @endverbatim + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @{ + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval None + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 467 .loc 1 312 1 is_stmt 1 view -0 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 8 + 470 @ frame_needed = 0, uses_anonymous_args = 0 + 471 @ link register save eliminated. + 472 .loc 1 312 1 is_stmt 0 view .LVU132 + 473 0000 82B0 sub sp, sp, #8 + 474 .LCFI4: + 475 .cfi_def_cfa_offset 8 + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameter */ + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 476 .loc 1 314 3 is_stmt 1 view .LVU133 + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccgSBUcl.s page 15 + + + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 477 .loc 1 317 3 view .LVU134 + 478 .LBB2: + 479 .loc 1 317 3 view .LVU135 + 480 .loc 1 317 3 view .LVU136 + 481 0002 074A ldr r2, .L24 + 482 0004 116C ldr r1, [r2, #64] + 483 0006 0123 movs r3, #1 + 484 0008 1943 orrs r1, r3 + 485 000a 1164 str r1, [r2, #64] + 486 .loc 1 317 3 view .LVU137 + 487 000c 126C ldr r2, [r2, #64] + 488 000e 1340 ands r3, r2 + 489 0010 0193 str r3, [sp, #4] + 490 .loc 1 317 3 view .LVU138 + 491 0012 019B ldr r3, [sp, #4] + 492 .LBE2: + 493 .loc 1 317 3 view .LVU139 + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 494 .loc 1 320 3 view .LVU140 + 495 0014 034A ldr r2, .L24+4 + 496 0016 1368 ldr r3, [r2] + 497 0018 0343 orrs r3, r0 + 498 001a 1360 str r3, [r2] + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 499 .loc 1 321 1 is_stmt 0 view .LVU141 + 500 001c 02B0 add sp, sp, #8 + 501 @ sp needed + 502 001e 7047 bx lr + 503 .L25: + 504 .align 2 + 505 .L24: + 506 0020 00100240 .word 1073876992 + 507 0024 00000140 .word 1073807360 + 508 .cfi_endproc + 509 .LFE301: + 511 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 512 .align 1 + 513 .global HAL_I2CEx_DisableFastModePlus + 514 .syntax unified + 515 .code 16 + 516 .thumb_func + 517 .fpu softvfp + 519 HAL_I2CEx_DisableFastModePlus: + 520 .LVL32: + 521 .LFB302: + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /** + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + ARM GAS /tmp/ccgSBUcl.s page 16 + + + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** * @retval None + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** */ + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** { + 522 .loc 1 339 1 is_stmt 1 view -0 + 523 .cfi_startproc + 524 @ args = 0, pretend = 0, frame = 8 + 525 @ frame_needed = 0, uses_anonymous_args = 0 + 526 @ link register save eliminated. + 527 .loc 1 339 1 is_stmt 0 view .LVU143 + 528 0000 82B0 sub sp, sp, #8 + 529 .LCFI5: + 530 .cfi_def_cfa_offset 8 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Check the parameter */ + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 531 .loc 1 341 3 is_stmt 1 view .LVU144 + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 532 .loc 1 344 3 view .LVU145 + 533 .LBB3: + 534 .loc 1 344 3 view .LVU146 + 535 .loc 1 344 3 view .LVU147 + 536 0002 074A ldr r2, .L27 + 537 0004 116C ldr r1, [r2, #64] + 538 0006 0123 movs r3, #1 + 539 0008 1943 orrs r1, r3 + 540 000a 1164 str r1, [r2, #64] + 541 .loc 1 344 3 view .LVU148 + 542 000c 126C ldr r2, [r2, #64] + 543 000e 1340 ands r3, r2 + 544 0010 0193 str r3, [sp, #4] + 545 .loc 1 344 3 view .LVU149 + 546 0012 019B ldr r3, [sp, #4] + 547 .LBE3: + 548 .loc 1 344 3 view .LVU150 + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 549 .loc 1 347 3 view .LVU151 + 550 0014 034A ldr r2, .L27+4 + 551 0016 1368 ldr r3, [r2] + 552 0018 8343 bics r3, r0 + 553 001a 1360 str r3, [r2] + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_i2c_ex.c **** } + 554 .loc 1 348 1 is_stmt 0 view .LVU152 + 555 001c 02B0 add sp, sp, #8 + 556 @ sp needed + 557 001e 7047 bx lr + 558 .L28: + 559 .align 2 + ARM GAS /tmp/ccgSBUcl.s page 17 + + + 560 .L27: + 561 0020 00100240 .word 1073876992 + 562 0024 00000140 .word 1073807360 + 563 .cfi_endproc + 564 .LFE302: + 566 .text + 567 .Letext0: + 568 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 569 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 570 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 571 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 572 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h" + 573 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccgSBUcl.s page 18 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_i2c_ex.c + /tmp/ccgSBUcl.s:16 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 $t + /tmp/ccgSBUcl.s:24 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/ccgSBUcl.s:127 .text.HAL_I2CEx_ConfigAnalogFilter:0000000000000054 $d + /tmp/ccgSBUcl.s:132 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 $t + /tmp/ccgSBUcl.s:139 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/ccgSBUcl.s:249 .text.HAL_I2CEx_ConfigDigitalFilter:0000000000000050 $d + /tmp/ccgSBUcl.s:254 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 $t + /tmp/ccgSBUcl.s:261 .text.HAL_I2CEx_EnableWakeUp:0000000000000000 HAL_I2CEx_EnableWakeUp + /tmp/ccgSBUcl.s:354 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 $t + /tmp/ccgSBUcl.s:361 .text.HAL_I2CEx_DisableWakeUp:0000000000000000 HAL_I2CEx_DisableWakeUp + /tmp/ccgSBUcl.s:452 .text.HAL_I2CEx_DisableWakeUp:000000000000004c $d + /tmp/ccgSBUcl.s:457 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 $t + /tmp/ccgSBUcl.s:464 .text.HAL_I2CEx_EnableFastModePlus:0000000000000000 HAL_I2CEx_EnableFastModePlus + /tmp/ccgSBUcl.s:506 .text.HAL_I2CEx_EnableFastModePlus:0000000000000020 $d + /tmp/ccgSBUcl.s:512 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 $t + /tmp/ccgSBUcl.s:519 .text.HAL_I2CEx_DisableFastModePlus:0000000000000000 HAL_I2CEx_DisableFastModePlus + /tmp/ccgSBUcl.s:561 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@@ +build/stm32g0xx_hal_msp.o: Core/Src/stm32g0xx_hal_msp.c Core/Inc/main.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Core/Inc/main.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_msp.lst b/squero/build/stm32g0xx_hal_msp.lst new file mode 100644 index 0000000..0a537ae --- /dev/null +++ b/squero/build/stm32g0xx_hal_msp.lst @@ -0,0 +1,480 @@ +ARM GAS /tmp/cc4Hkhf7.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_msp.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_MspInit,"ax",%progbits + 16 .align 1 + 17 .global HAL_MspInit + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_MspInit: + 25 .LFB297: + 26 .file 1 "Core/Src/stm32g0xx_hal_msp.c" + 1:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32g0xx_hal_msp.c **** /** + 3:Core/Src/stm32g0xx_hal_msp.c **** ****************************************************************************** + 4:Core/Src/stm32g0xx_hal_msp.c **** * @file stm32g0xx_hal_msp.c + 5:Core/Src/stm32g0xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization + 6:Core/Src/stm32g0xx_hal_msp.c **** * and de-Initialization codes. + 7:Core/Src/stm32g0xx_hal_msp.c **** ****************************************************************************** + 8:Core/Src/stm32g0xx_hal_msp.c **** * @attention + 9:Core/Src/stm32g0xx_hal_msp.c **** * + 10:Core/Src/stm32g0xx_hal_msp.c **** * Copyright (c) 2021 STMicroelectronics. + 11:Core/Src/stm32g0xx_hal_msp.c **** * All rights reserved. + 12:Core/Src/stm32g0xx_hal_msp.c **** * + 13:Core/Src/stm32g0xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file + 14:Core/Src/stm32g0xx_hal_msp.c **** * in the root directory of this software component. + 15:Core/Src/stm32g0xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 16:Core/Src/stm32g0xx_hal_msp.c **** * + 17:Core/Src/stm32g0xx_hal_msp.c **** ****************************************************************************** + 18:Core/Src/stm32g0xx_hal_msp.c **** */ + 19:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END Header */ + 20:Core/Src/stm32g0xx_hal_msp.c **** + 21:Core/Src/stm32g0xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ + 22:Core/Src/stm32g0xx_hal_msp.c **** #include "main.h" + 23:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN Includes */ + 24:Core/Src/stm32g0xx_hal_msp.c **** + 25:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END Includes */ + 26:Core/Src/stm32g0xx_hal_msp.c **** + 27:Core/Src/stm32g0xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN TD */ + 29:Core/Src/stm32g0xx_hal_msp.c **** + 30:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END TD */ + 31:Core/Src/stm32g0xx_hal_msp.c **** + 32:Core/Src/stm32g0xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ + ARM GAS /tmp/cc4Hkhf7.s page 2 + + + 33:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN Define */ + 34:Core/Src/stm32g0xx_hal_msp.c **** + 35:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END Define */ + 36:Core/Src/stm32g0xx_hal_msp.c **** + 37:Core/Src/stm32g0xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ + 38:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN Macro */ + 39:Core/Src/stm32g0xx_hal_msp.c **** + 40:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END Macro */ + 41:Core/Src/stm32g0xx_hal_msp.c **** + 42:Core/Src/stm32g0xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ + 43:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN PV */ + 44:Core/Src/stm32g0xx_hal_msp.c **** + 45:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END PV */ + 46:Core/Src/stm32g0xx_hal_msp.c **** + 47:Core/Src/stm32g0xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN PFP */ + 49:Core/Src/stm32g0xx_hal_msp.c **** + 50:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END PFP */ + 51:Core/Src/stm32g0xx_hal_msp.c **** + 52:Core/Src/stm32g0xx_hal_msp.c **** /* External functions --------------------------------------------------------*/ + 53:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */ + 54:Core/Src/stm32g0xx_hal_msp.c **** + 55:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END ExternalFunctions */ + 56:Core/Src/stm32g0xx_hal_msp.c **** + 57:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN 0 */ + 58:Core/Src/stm32g0xx_hal_msp.c **** + 59:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END 0 */ + 60:Core/Src/stm32g0xx_hal_msp.c **** /** + 61:Core/Src/stm32g0xx_hal_msp.c **** * Initializes the Global MSP. + 62:Core/Src/stm32g0xx_hal_msp.c **** */ + 63:Core/Src/stm32g0xx_hal_msp.c **** void HAL_MspInit(void) + 64:Core/Src/stm32g0xx_hal_msp.c **** { + 27 .loc 1 64 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 8 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 32 0000 82B0 sub sp, sp, #8 + 33 .LCFI0: + 34 .cfi_def_cfa_offset 8 + 65:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */ + 66:Core/Src/stm32g0xx_hal_msp.c **** + 67:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END MspInit 0 */ + 68:Core/Src/stm32g0xx_hal_msp.c **** + 69:Core/Src/stm32g0xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 35 .loc 1 69 3 view .LVU1 + 36 .LBB2: + 37 .loc 1 69 3 view .LVU2 + 38 .loc 1 69 3 view .LVU3 + 39 0002 0A4B ldr r3, .L2 + 40 0004 196C ldr r1, [r3, #64] + 41 0006 0122 movs r2, #1 + 42 0008 1143 orrs r1, r2 + 43 000a 1964 str r1, [r3, #64] + 44 .loc 1 69 3 view .LVU4 + 45 000c 196C ldr r1, [r3, #64] + 46 000e 0A40 ands r2, r1 + ARM GAS /tmp/cc4Hkhf7.s page 3 + + + 47 0010 0092 str r2, [sp] + 48 .loc 1 69 3 view .LVU5 + 49 0012 009A ldr r2, [sp] + 50 .LBE2: + 51 .loc 1 69 3 view .LVU6 + 70:Core/Src/stm32g0xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 52 .loc 1 70 3 view .LVU7 + 53 .LBB3: + 54 .loc 1 70 3 view .LVU8 + 55 .loc 1 70 3 view .LVU9 + 56 0014 DA6B ldr r2, [r3, #60] + 57 0016 8021 movs r1, #128 + 58 0018 4905 lsls r1, r1, #21 + 59 001a 0A43 orrs r2, r1 + 60 001c DA63 str r2, [r3, #60] + 61 .loc 1 70 3 view .LVU10 + 62 001e DB6B ldr r3, [r3, #60] + 63 0020 0B40 ands r3, r1 + 64 0022 0193 str r3, [sp, #4] + 65 .loc 1 70 3 view .LVU11 + 66 0024 019B ldr r3, [sp, #4] + 67 .LBE3: + 68 .loc 1 70 3 view .LVU12 + 71:Core/Src/stm32g0xx_hal_msp.c **** + 72:Core/Src/stm32g0xx_hal_msp.c **** /* System interrupt init*/ + 73:Core/Src/stm32g0xx_hal_msp.c **** + 74:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */ + 75:Core/Src/stm32g0xx_hal_msp.c **** + 76:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END MspInit 1 */ + 77:Core/Src/stm32g0xx_hal_msp.c **** } + 69 .loc 1 77 1 is_stmt 0 view .LVU13 + 70 0026 02B0 add sp, sp, #8 + 71 @ sp needed + 72 0028 7047 bx lr + 73 .L3: + 74 002a C046 .align 2 + 75 .L2: + 76 002c 00100240 .word 1073876992 + 77 .cfi_endproc + 78 .LFE297: + 80 .section .text.HAL_I2C_MspInit,"ax",%progbits + 81 .align 1 + 82 .global HAL_I2C_MspInit + 83 .syntax unified + 84 .code 16 + 85 .thumb_func + 86 .fpu softvfp + 88 HAL_I2C_MspInit: + 89 .LVL0: + 90 .LFB298: + 78:Core/Src/stm32g0xx_hal_msp.c **** + 79:Core/Src/stm32g0xx_hal_msp.c **** /** + 80:Core/Src/stm32g0xx_hal_msp.c **** * @brief I2C MSP Initialization + 81:Core/Src/stm32g0xx_hal_msp.c **** * This function configures the hardware resources used in this example + 82:Core/Src/stm32g0xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 83:Core/Src/stm32g0xx_hal_msp.c **** * @retval None + 84:Core/Src/stm32g0xx_hal_msp.c **** */ + ARM GAS /tmp/cc4Hkhf7.s page 4 + + + 85:Core/Src/stm32g0xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) + 86:Core/Src/stm32g0xx_hal_msp.c **** { + 91 .loc 1 86 1 is_stmt 1 view -0 + 92 .cfi_startproc + 93 @ args = 0, pretend = 0, frame = 32 + 94 @ frame_needed = 0, uses_anonymous_args = 0 + 95 .loc 1 86 1 is_stmt 0 view .LVU15 + 96 0000 10B5 push {r4, lr} + 97 .LCFI1: + 98 .cfi_def_cfa_offset 8 + 99 .cfi_offset 4, -8 + 100 .cfi_offset 14, -4 + 101 0002 88B0 sub sp, sp, #32 + 102 .LCFI2: + 103 .cfi_def_cfa_offset 40 + 104 0004 0400 movs r4, r0 + 87:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 105 .loc 1 87 3 is_stmt 1 view .LVU16 + 106 .loc 1 87 20 is_stmt 0 view .LVU17 + 107 0006 1422 movs r2, #20 + 108 0008 0021 movs r1, #0 + 109 000a 03A8 add r0, sp, #12 + 110 .LVL1: + 111 .loc 1 87 20 view .LVU18 + 112 000c FFF7FEFF bl memset + 113 .LVL2: + 88:Core/Src/stm32g0xx_hal_msp.c **** if(hi2c->Instance==I2C2) + 114 .loc 1 88 3 is_stmt 1 view .LVU19 + 115 .loc 1 88 10 is_stmt 0 view .LVU20 + 116 0010 2268 ldr r2, [r4] + 117 .loc 1 88 5 view .LVU21 + 118 0012 124B ldr r3, .L7 + 119 0014 9A42 cmp r2, r3 + 120 0016 01D0 beq .L6 + 121 .LVL3: + 122 .L4: + 89:Core/Src/stm32g0xx_hal_msp.c **** { + 90:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 0 */ + 91:Core/Src/stm32g0xx_hal_msp.c **** + 92:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 0 */ + 93:Core/Src/stm32g0xx_hal_msp.c **** + 94:Core/Src/stm32g0xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 95:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 96:Core/Src/stm32g0xx_hal_msp.c **** PA11 [PA9] ------> I2C2_SCL + 97:Core/Src/stm32g0xx_hal_msp.c **** PA12 [PA10] ------> I2C2_SDA + 98:Core/Src/stm32g0xx_hal_msp.c **** */ + 99:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 100:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 101:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 102:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 103:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF6_I2C2; + 104:Core/Src/stm32g0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 105:Core/Src/stm32g0xx_hal_msp.c **** + 106:Core/Src/stm32g0xx_hal_msp.c **** /* Peripheral clock enable */ + 107:Core/Src/stm32g0xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE(); + 108:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 109:Core/Src/stm32g0xx_hal_msp.c **** + ARM GAS /tmp/cc4Hkhf7.s page 5 + + + 110:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 1 */ + 111:Core/Src/stm32g0xx_hal_msp.c **** } + 112:Core/Src/stm32g0xx_hal_msp.c **** + 113:Core/Src/stm32g0xx_hal_msp.c **** } + 123 .loc 1 113 1 view .LVU22 + 124 0018 08B0 add sp, sp, #32 + 125 @ sp needed + 126 001a 10BD pop {r4, pc} + 127 .LVL4: + 128 .L6: + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 129 .loc 1 94 5 is_stmt 1 view .LVU23 + 130 .LBB4: + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 131 .loc 1 94 5 view .LVU24 + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 132 .loc 1 94 5 view .LVU25 + 133 001c 104C ldr r4, .L7+4 + 134 .LVL5: + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 135 .loc 1 94 5 is_stmt 0 view .LVU26 + 136 001e 626B ldr r2, [r4, #52] + 137 0020 0123 movs r3, #1 + 138 0022 1A43 orrs r2, r3 + 139 0024 6263 str r2, [r4, #52] + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 140 .loc 1 94 5 is_stmt 1 view .LVU27 + 141 0026 626B ldr r2, [r4, #52] + 142 0028 1340 ands r3, r2 + 143 002a 0193 str r3, [sp, #4] + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 144 .loc 1 94 5 view .LVU28 + 145 002c 019B ldr r3, [sp, #4] + 146 .LBE4: + 94:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 147 .loc 1 94 5 view .LVU29 + 99:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 148 .loc 1 99 5 view .LVU30 + 99:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 149 .loc 1 99 25 is_stmt 0 view .LVU31 + 150 002e C023 movs r3, #192 + 151 0030 5B01 lsls r3, r3, #5 + 152 0032 0393 str r3, [sp, #12] + 100:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 153 .loc 1 100 5 is_stmt 1 view .LVU32 + 100:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 154 .loc 1 100 26 is_stmt 0 view .LVU33 + 155 0034 1223 movs r3, #18 + 156 0036 0493 str r3, [sp, #16] + 101:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 157 .loc 1 101 5 is_stmt 1 view .LVU34 + 102:Core/Src/stm32g0xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF6_I2C2; + 158 .loc 1 102 5 view .LVU35 + 103:Core/Src/stm32g0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 159 .loc 1 103 5 view .LVU36 + 103:Core/Src/stm32g0xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 160 .loc 1 103 31 is_stmt 0 view .LVU37 + ARM GAS /tmp/cc4Hkhf7.s page 6 + + + 161 0038 0C3B subs r3, r3, #12 + 162 003a 0793 str r3, [sp, #28] + 104:Core/Src/stm32g0xx_hal_msp.c **** + 163 .loc 1 104 5 is_stmt 1 view .LVU38 + 164 003c A020 movs r0, #160 + 165 003e 03A9 add r1, sp, #12 + 166 0040 C005 lsls r0, r0, #23 + 167 0042 FFF7FEFF bl HAL_GPIO_Init + 168 .LVL6: + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 169 .loc 1 107 5 view .LVU39 + 170 .LBB5: + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 171 .loc 1 107 5 view .LVU40 + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 172 .loc 1 107 5 view .LVU41 + 173 0046 E26B ldr r2, [r4, #60] + 174 0048 8021 movs r1, #128 + 175 004a C903 lsls r1, r1, #15 + 176 004c 0A43 orrs r2, r1 + 177 004e E263 str r2, [r4, #60] + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 178 .loc 1 107 5 view .LVU42 + 179 0050 E36B ldr r3, [r4, #60] + 180 0052 0B40 ands r3, r1 + 181 0054 0293 str r3, [sp, #8] + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 182 .loc 1 107 5 view .LVU43 + 183 0056 029B ldr r3, [sp, #8] + 184 .LBE5: + 107:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 185 .loc 1 107 5 view .LVU44 + 186 .loc 1 113 1 is_stmt 0 view .LVU45 + 187 0058 DEE7 b .L4 + 188 .L8: + 189 005a C046 .align 2 + 190 .L7: + 191 005c 00580040 .word 1073764352 + 192 0060 00100240 .word 1073876992 + 193 .cfi_endproc + 194 .LFE298: + 196 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 197 .align 1 + 198 .global HAL_I2C_MspDeInit + 199 .syntax unified + 200 .code 16 + 201 .thumb_func + 202 .fpu softvfp + 204 HAL_I2C_MspDeInit: + 205 .LVL7: + 206 .LFB299: + 114:Core/Src/stm32g0xx_hal_msp.c **** + 115:Core/Src/stm32g0xx_hal_msp.c **** /** + 116:Core/Src/stm32g0xx_hal_msp.c **** * @brief I2C MSP De-Initialization + 117:Core/Src/stm32g0xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 118:Core/Src/stm32g0xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 119:Core/Src/stm32g0xx_hal_msp.c **** * @retval None + ARM GAS /tmp/cc4Hkhf7.s page 7 + + + 120:Core/Src/stm32g0xx_hal_msp.c **** */ + 121:Core/Src/stm32g0xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) + 122:Core/Src/stm32g0xx_hal_msp.c **** { + 207 .loc 1 122 1 is_stmt 1 view -0 + 208 .cfi_startproc + 209 @ args = 0, pretend = 0, frame = 0 + 210 @ frame_needed = 0, uses_anonymous_args = 0 + 211 .loc 1 122 1 is_stmt 0 view .LVU47 + 212 0000 10B5 push {r4, lr} + 213 .LCFI3: + 214 .cfi_def_cfa_offset 8 + 215 .cfi_offset 4, -8 + 216 .cfi_offset 14, -4 + 123:Core/Src/stm32g0xx_hal_msp.c **** if(hi2c->Instance==I2C2) + 217 .loc 1 123 3 is_stmt 1 view .LVU48 + 218 .loc 1 123 10 is_stmt 0 view .LVU49 + 219 0002 0268 ldr r2, [r0] + 220 .loc 1 123 5 view .LVU50 + 221 0004 0A4B ldr r3, .L12 + 222 0006 9A42 cmp r2, r3 + 223 0008 00D0 beq .L11 + 224 .LVL8: + 225 .L9: + 124:Core/Src/stm32g0xx_hal_msp.c **** { + 125:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 0 */ + 126:Core/Src/stm32g0xx_hal_msp.c **** + 127:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 0 */ + 128:Core/Src/stm32g0xx_hal_msp.c **** /* Peripheral clock disable */ + 129:Core/Src/stm32g0xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_DISABLE(); + 130:Core/Src/stm32g0xx_hal_msp.c **** + 131:Core/Src/stm32g0xx_hal_msp.c **** /**I2C2 GPIO Configuration + 132:Core/Src/stm32g0xx_hal_msp.c **** PA11 [PA9] ------> I2C2_SCL + 133:Core/Src/stm32g0xx_hal_msp.c **** PA12 [PA10] ------> I2C2_SDA + 134:Core/Src/stm32g0xx_hal_msp.c **** */ + 135:Core/Src/stm32g0xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11); + 136:Core/Src/stm32g0xx_hal_msp.c **** + 137:Core/Src/stm32g0xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12); + 138:Core/Src/stm32g0xx_hal_msp.c **** + 139:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 1 */ + 140:Core/Src/stm32g0xx_hal_msp.c **** + 141:Core/Src/stm32g0xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 1 */ + 142:Core/Src/stm32g0xx_hal_msp.c **** } + 143:Core/Src/stm32g0xx_hal_msp.c **** + 144:Core/Src/stm32g0xx_hal_msp.c **** } + 226 .loc 1 144 1 view .LVU51 + 227 @ sp needed + 228 000a 10BD pop {r4, pc} + 229 .LVL9: + 230 .L11: + 129:Core/Src/stm32g0xx_hal_msp.c **** + 231 .loc 1 129 5 is_stmt 1 view .LVU52 + 232 000c 094A ldr r2, .L12+4 + 233 000e D36B ldr r3, [r2, #60] + 234 0010 0949 ldr r1, .L12+8 + 235 0012 0B40 ands r3, r1 + 236 0014 D363 str r3, [r2, #60] + 135:Core/Src/stm32g0xx_hal_msp.c **** + ARM GAS /tmp/cc4Hkhf7.s page 8 + + + 237 .loc 1 135 5 view .LVU53 + 238 0016 8021 movs r1, #128 + 239 0018 A024 movs r4, #160 + 240 001a E405 lsls r4, r4, #23 + 241 001c 0901 lsls r1, r1, #4 + 242 001e 2000 movs r0, r4 + 243 .LVL10: + 135:Core/Src/stm32g0xx_hal_msp.c **** + 244 .loc 1 135 5 is_stmt 0 view .LVU54 + 245 0020 FFF7FEFF bl HAL_GPIO_DeInit + 246 .LVL11: + 137:Core/Src/stm32g0xx_hal_msp.c **** + 247 .loc 1 137 5 is_stmt 1 view .LVU55 + 248 0024 8021 movs r1, #128 + 249 0026 4901 lsls r1, r1, #5 + 250 0028 2000 movs r0, r4 + 251 002a FFF7FEFF bl HAL_GPIO_DeInit + 252 .LVL12: + 253 .loc 1 144 1 is_stmt 0 view .LVU56 + 254 002e ECE7 b .L9 + 255 .L13: + 256 .align 2 + 257 .L12: + 258 0030 00580040 .word 1073764352 + 259 0034 00100240 .word 1073876992 + 260 0038 FFFFBFFF .word -4194305 + 261 .cfi_endproc + 262 .LFE299: + 264 .text + 265 .Letext0: + 266 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 267 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 268 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 269 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h" + 270 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h" + 271 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h" + 272 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 273 .file 9 "" + ARM GAS /tmp/cc4Hkhf7.s page 9 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_msp.c + /tmp/cc4Hkhf7.s:16 .text.HAL_MspInit:0000000000000000 $t + /tmp/cc4Hkhf7.s:24 .text.HAL_MspInit:0000000000000000 HAL_MspInit + /tmp/cc4Hkhf7.s:76 .text.HAL_MspInit:000000000000002c $d + /tmp/cc4Hkhf7.s:81 .text.HAL_I2C_MspInit:0000000000000000 $t + /tmp/cc4Hkhf7.s:88 .text.HAL_I2C_MspInit:0000000000000000 HAL_I2C_MspInit + /tmp/cc4Hkhf7.s:191 .text.HAL_I2C_MspInit:000000000000005c $d + /tmp/cc4Hkhf7.s:197 .text.HAL_I2C_MspDeInit:0000000000000000 $t + /tmp/cc4Hkhf7.s:204 .text.HAL_I2C_MspDeInit:0000000000000000 HAL_I2C_MspDeInit + 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zUIRocUKaI2eSe0&4h)|Bqjs`O{vE(i^+8n}!=ib$pg~n{m?L*T*5hBO0~aNC9q2;4 zYa7r2CfTL+sO;WtHsfiQdvHH4oDZe%pTM4_Z-o$Uw2?lzkk|JZ>Z%W_;yCoVslr9^ z9symbZwUIxF6pEBQ~o`Ny6S_f_yqdwDme>yPorL_?*R1C{z3Y1rO)d-jyma6WBeby z1iVNSz=e49dxufUJ%{&-!rWJKe_%O)S+KAuhg6|)Q27wQLjP_p7%#o4squb}I@a10 zK$a2cqcx)n*`-2Q5C(Aoa&My%Zpv|!K8hpRRBIPi5k>wbslr9+qj#Y~xufvUP)zVt G^?w0{s*eW% literal 0 HcmV?d00001 diff --git a/squero/build/stm32g0xx_hal_pwr.d b/squero/build/stm32g0xx_hal_pwr.d new file mode 100644 index 0000000..5f0ccd4 --- /dev/null +++ b/squero/build/stm32g0xx_hal_pwr.d @@ -0,0 +1,59 @@ +build/stm32g0xx_hal_pwr.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_pwr.lst b/squero/build/stm32g0xx_hal_pwr.lst new file mode 100644 index 0000000..589e584 --- /dev/null +++ b/squero/build/stm32g0xx_hal_pwr.lst @@ -0,0 +1,1197 @@ +ARM GAS /tmp/ccDIilRR.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_pwr.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_PWR_DeInit,"ax",%progbits + 16 .align 1 + 17 .global HAL_PWR_DeInit + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_PWR_DeInit: + 25 .LFB297: + 26 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @file stm32g0xx_hal_pwr.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief PWR HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + Initialization/de-initialization functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + Peripheral Control functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ****************************************************************************** + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @attention + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *

© Copyright (c) 2018 STMicroelectronics. + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * All rights reserved.

+ 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * This software component is licensed by ST under BSD 3-Clause license, + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * the "License"; You may not use this file except in compliance with the + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * License. You may obtain a copy of the License at: + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * opensource.org/licenses/BSD-3-Clause + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ****************************************************************************** + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #include "stm32g0xx_hal.h" + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup STM32G0xx_HAL_Driver + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR + ARM GAS /tmp/ccDIilRR.s page 2 + + + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @defgroup PWR_Private_Defines PWR Private Defines + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @} + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Exported functions --------------------------------------------------------*/ + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions PWR Exported Functions + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Initialization and de-initialization functions + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @verbatim + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** =============================================================================== + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** =============================================================================== + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @endverbatim + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Deinitialize the HAL PWR peripheral registers to their default reset + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** values. + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DeInit(void) + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 27 .loc 1 75 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); + 32 .loc 1 76 3 view .LVU1 + 33 0000 054B ldr r3, .L2 + 34 0002 D96A ldr r1, [r3, #44] + 35 0004 8022 movs r2, #128 + 36 0006 5205 lsls r2, r2, #21 + 37 0008 0A43 orrs r2, r1 + 38 000a DA62 str r2, [r3, #44] + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); + ARM GAS /tmp/ccDIilRR.s page 3 + + + 39 .loc 1 77 3 view .LVU2 + 40 000c DA6A ldr r2, [r3, #44] + 41 000e 0349 ldr r1, .L2+4 + 42 0010 0A40 ands r2, r1 + 43 0012 DA62 str r2, [r3, #44] + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 44 .loc 1 78 1 is_stmt 0 view .LVU3 + 45 @ sp needed + 46 0014 7047 bx lr + 47 .L3: + 48 0016 C046 .align 2 + 49 .L2: + 50 0018 00100240 .word 1073876992 + 51 001c FFFFFFEF .word -268435457 + 52 .cfi_endproc + 53 .LFE297: + 55 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 56 .align 1 + 57 .global HAL_PWR_EnableBkUpAccess + 58 .syntax unified + 59 .code 16 + 60 .thumb_func + 61 .fpu softvfp + 63 HAL_PWR_EnableBkUpAccess: + 64 .LFB298: + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @} + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Low Power modes configuration functions + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @verbatim + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** =============================================================================== + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ##### Peripheral Control functions ##### + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** =============================================================================== + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** WakeUp pin configuration *** + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ================================ + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) WakeUp pins are used to wakeup the system from Standby mode or + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Shutdown mode. WakeUp pins polarity can be set to configure event + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** detection on high level (rising edge) or low level (falling edge). + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Low Power mode configuration *** + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ===================================== + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** The devices feature 7 low-power modes: + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Low-power run mode: core and peripherals are running at low frequency. + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Regulator is in low power mode. + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running, + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** regulator is main mode. + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** and regulator in low power mode. + ARM GAS /tmp/ccDIilRR.s page 4 + + + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** main mode. + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** off, low power regulator on. + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** disable. + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Shutdown mode: all clocks are stopped except LSE, regulator is + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** disable. + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Low-power run mode *** + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ========================== + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Entry: (from main run mode) + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** having decreased the system clock below 2 MHz. + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Exit: + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) clear LPR bit then wait for REGLPF bit to be reset with + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** HAL_PWREx_DisableLowPowerRunMode() API. Only then can the + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** system clock frequency be increased above 2 MHz. + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Sleep mode / Low-power sleep mode *** + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ========================================= + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Entry: + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** The Sleep & Low-power Sleep modes are entered through + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** is forced to low-power mode and if exit is interrupt or event + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** triggered. + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** power mode). In this case, the system clock frequency must have + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** been decreased below 2 MHz beforehand. + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) WFI Exit: + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Any interrupt enabled in nested vectored interrupt controller (NVIC) + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) WFE Exit: + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Any wakeup event if cortex is configured with SEVONPEND = 0 + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Interrupt even when disabled in NVIC if cortex is configured with + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SEVONPEND = 1 + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event, + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** the MCU is in Low-power Run mode. + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Stop 0 & Stop 1 modes *** + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ============================= + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Entry: + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** The Stop modes are entered through the following APIs: + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) HAL_PWR_EnterSTOPMode() with following settings: + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode. + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode. + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Exit (interrupt or event-triggered, specified when entering STOP mode): + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) WFI Exit: + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Any EXTI line (internal or external) configured in interrupt mode + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** with corresponding interrupt enable in NVIC + ARM GAS /tmp/ccDIilRR.s page 5 + + + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) WFE Exit: + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Any EXTI line (internal or external) configured in event mode if + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** cortex is configured with SEVONPEND = 0 + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) Any EXTI line configured in interrupt mode (even if the + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** corresponding EXTI Interrupt vector is disabled in the NVIC) if + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** cortex is configured with SEVONPEND = 0. The interrupt source can + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** be external interrupts or peripherals with wakeup capability. + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] When exiting Stop, the MCU is either in Run mode or in Low-power Run mode + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** depending on the LPR bit setting. + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Standby mode *** + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ==================== + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] In Standby mode, it is possible to keep backup SRAM content (defined as + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** full SRAM) keeping low power regulator on. This is achievable by setting + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** power consumption. + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Its also possible to define I/O states using APIs: + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown & + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** HAL_PWREx_EnablePullUpPullDownConfig + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Entry: + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** setting SLEEPDEEP in Cortex control register. + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Exit: + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** tamper event (internal & external), LSE CSS detection, reset on + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** NRST pin, IWDG reset & BOR reset. + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] Exiting Standby generates a power reset: Cortex is reset and execute + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Reset handler vector, all registers in the Vcore domain are set to + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** and Standby/Shutdown modes control) are not impacted. + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** *** Shutdown mode *** + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** ====================== + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** In Shutdown mode, + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** voltage regulator is disabled, all clocks are off except LSE, RRS bit is + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** cleared. SRAM and registers contents are lost except for backup domain + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** registers. + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Entry: + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API, + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** by setting SLEEPDEEP in Cortex control register. + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (+) Exit: + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** tamper event (internal & external), LSE CSS detection, reset on + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** NRST pin. + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** Reset handler vector, all registers are set to their reset value but ones + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** in backup domain. + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** @endverbatim + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @{ + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enable access to the backup domain + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * (RTC & TAMP registers, backup registers, RCC BDCR register). + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note After reset, the backup domain is protected against + ARM GAS /tmp/ccDIilRR.s page 6 + + + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * possible unwanted write accesses. All RTC & TAMP registers (backup + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * registers included) and RCC BDCR register are concerned. + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 65 .loc 1 230 1 is_stmt 1 view -0 + 66 .cfi_startproc + 67 @ args = 0, pretend = 0, frame = 0 + 68 @ frame_needed = 0, uses_anonymous_args = 0 + 69 @ link register save eliminated. + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); + 70 .loc 1 231 3 view .LVU5 + 71 0000 034A ldr r2, .L5 + 72 0002 1168 ldr r1, [r2] + 73 0004 8023 movs r3, #128 + 74 0006 5B00 lsls r3, r3, #1 + 75 0008 0B43 orrs r3, r1 + 76 000a 1360 str r3, [r2] + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 77 .loc 1 232 1 is_stmt 0 view .LVU6 + 78 @ sp needed + 79 000c 7047 bx lr + 80 .L6: + 81 000e C046 .align 2 + 82 .L5: + 83 0010 00700040 .word 1073770496 + 84 .cfi_endproc + 85 .LFE298: + 87 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 88 .align 1 + 89 .global HAL_PWR_DisableBkUpAccess + 90 .syntax unified + 91 .code 16 + 92 .thumb_func + 93 .fpu softvfp + 95 HAL_PWR_DisableBkUpAccess: + 96 .LFB299: + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Disable access to the backup domain + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 97 .loc 1 240 1 is_stmt 1 view -0 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 0, uses_anonymous_args = 0 + 101 @ link register save eliminated. + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); + 102 .loc 1 241 3 view .LVU8 + 103 0000 024A ldr r2, .L8 + 104 0002 1368 ldr r3, [r2] + 105 0004 0249 ldr r1, .L8+4 + 106 0006 0B40 ands r3, r1 + ARM GAS /tmp/ccDIilRR.s page 7 + + + 107 0008 1360 str r3, [r2] + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 108 .loc 1 242 1 is_stmt 0 view .LVU9 + 109 @ sp needed + 110 000a 7047 bx lr + 111 .L9: + 112 .align 2 + 113 .L8: + 114 000c 00700040 .word 1073770496 + 115 0010 FFFEFFFF .word -257 + 116 .cfi_endproc + 117 .LFE299: + 119 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 120 .align 1 + 121 .global HAL_PWR_EnableWakeUpPin + 122 .syntax unified + 123 .code 16 + 124 .thumb_func + 125 .fpu softvfp + 127 HAL_PWR_EnableWakeUpPin: + 128 .LVL0: + 129 .LFB300: + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enable the WakeUp PINx functionality. + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * This parameter can be one of the following legacy values which set + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * the default polarity i.e. detection on high level (rising edge): + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * or one of the following value where the user can explicitly specify + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * the enabled pin and the chosen polarity: + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*) + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*) + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note (*) availability depends on devices + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 130 .loc 1 264 1 is_stmt 1 view -0 + 131 .cfi_startproc + 132 @ args = 0, pretend = 0, frame = 0 + 133 @ frame_needed = 0, uses_anonymous_args = 0 + 134 @ link register save eliminated. + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + 135 .loc 1 265 3 view .LVU11 + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Specifies the Wake-Up pin polarity for the event detection + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** (rising or falling edge) */ + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHI + 136 .loc 1 269 3 view .LVU12 + 137 0000 0549 ldr r1, .L11 + ARM GAS /tmp/ccDIilRR.s page 8 + + + 138 0002 CA68 ldr r2, [r1, #12] + 139 0004 2B23 movs r3, #43 + 140 0006 0340 ands r3, r0 + 141 0008 9A43 bics r2, r3 + 142 000a 000A lsrs r0, r0, #8 + 143 .LVL1: + 144 .loc 1 269 3 is_stmt 0 view .LVU13 + 145 000c 1043 orrs r0, r2 + 146 000e C860 str r0, [r1, #12] + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Enable wake-up pin */ + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); + 147 .loc 1 272 3 is_stmt 1 view .LVU14 + 148 0010 8A68 ldr r2, [r1, #8] + 149 0012 1343 orrs r3, r2 + 150 0014 8B60 str r3, [r1, #8] + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 151 .loc 1 273 1 is_stmt 0 view .LVU15 + 152 @ sp needed + 153 0016 7047 bx lr + 154 .L12: + 155 .align 2 + 156 .L11: + 157 0018 00700040 .word 1073770496 + 158 .cfi_endproc + 159 .LFE300: + 161 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 162 .align 1 + 163 .global HAL_PWR_DisableWakeUpPin + 164 .syntax unified + 165 .code 16 + 166 .thumb_func + 167 .fpu softvfp + 169 HAL_PWR_DisableWakeUpPin: + 170 .LVL2: + 171 .LFB301: + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Disable the WakeUp PINx functionality. + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * This parameter can be one of the following values: + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*), + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note (*) availability depends on devices + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 172 .loc 1 286 1 is_stmt 1 view -0 + 173 .cfi_startproc + 174 @ args = 0, pretend = 0, frame = 0 + 175 @ frame_needed = 0, uses_anonymous_args = 0 + 176 @ link register save eliminated. + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 177 .loc 1 287 3 view .LVU17 + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + ARM GAS /tmp/ccDIilRR.s page 9 + + + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); + 178 .loc 1 289 3 view .LVU18 + 179 0000 0349 ldr r1, .L14 + 180 0002 8B68 ldr r3, [r1, #8] + 181 0004 2B22 movs r2, #43 + 182 0006 0240 ands r2, r0 + 183 0008 9343 bics r3, r2 + 184 000a 8B60 str r3, [r1, #8] + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 185 .loc 1 290 1 is_stmt 0 view .LVU19 + 186 @ sp needed + 187 000c 7047 bx lr + 188 .L15: + 189 000e C046 .align 2 + 190 .L14: + 191 0010 00700040 .word 1073770496 + 192 .cfi_endproc + 193 .LFE301: + 195 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 196 .align 1 + 197 .global HAL_PWR_EnterSLEEPMode + 198 .syntax unified + 199 .code 16 + 200 .thumb_func + 201 .fpu softvfp + 203 HAL_PWR_EnterSLEEPMode: + 204 .LVL3: + 205 .LFB302: + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enter Sleep or Low-power Sleep mode. + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * in Run mode. + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * mode. This parameter can be one of the following values: + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * in low-power mode) + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Low-power Sleep mode is entered from Low-power Run mode only. In + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * case Regulator parameter is set to Low Power but MCU is in Run mode, + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * we will first enter in Low-power Run mode. Therefore, user should + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * take care that HCLK frequency is less than 2 MHz. + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * To switch back to Run mode, user must call + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * HAL_PWREx_DisableLowPowerRunMode() API. + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * instruction. This parameter can be one of the following values: + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * mode with WFI instruction + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * mode with WFE instruction + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note When WFI entry is used, tick interrupt have to be disabled if not + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * desired as the interrupt wake up source. + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) + ARM GAS /tmp/ccDIilRR.s page 10 + + + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 206 .loc 1 320 1 is_stmt 1 view -0 + 207 .cfi_startproc + 208 @ args = 0, pretend = 0, frame = 0 + 209 @ frame_needed = 0, uses_anonymous_args = 0 + 210 .loc 1 320 1 is_stmt 0 view .LVU21 + 211 0000 10B5 push {r4, lr} + 212 .LCFI0: + 213 .cfi_def_cfa_offset 8 + 214 .cfi_offset 4, -8 + 215 .cfi_offset 14, -4 + 216 0002 0C00 movs r4, r1 + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Check the parameters */ + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 217 .loc 1 322 3 is_stmt 1 view .LVU22 + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + 218 .loc 1 323 3 view .LVU23 + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set Regulator parameter */ + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if (Regulator != PWR_MAINREGULATOR_ON) + 219 .loc 1 326 3 view .LVU24 + 220 .loc 1 326 6 is_stmt 0 view .LVU25 + 221 0004 0028 cmp r0, #0 + 222 0006 11D0 beq .L17 + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* If in run mode, first move to low-power run mode. + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** The system clock frequency must be below 2 MHz at this point. */ + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u) + 223 .loc 1 330 5 is_stmt 1 view .LVU26 + 224 .loc 1 330 13 is_stmt 0 view .LVU27 + 225 0008 0E4B ldr r3, .L23 + 226 000a 5B69 ldr r3, [r3, #20] + 227 .loc 1 330 8 view .LVU28 + 228 000c 9B05 lsls r3, r3, #22 + 229 000e 0AD5 bpl .L21 + 230 .LVL4: + 231 .L18: + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** HAL_PWREx_EnableLowPowerRunMode(); + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** else + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* If in low-power run mode at this point, exit it */ + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u) + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** return ; + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 232 .loc 1 348 3 is_stmt 1 view .LVU29 + 233 0010 0D4A ldr r2, .L23+4 + ARM GAS /tmp/ccDIilRR.s page 11 + + + 234 0012 1369 ldr r3, [r2, #16] + 235 0014 0421 movs r1, #4 + 236 0016 8B43 bics r3, r1 + 237 0018 1361 str r3, [r2, #16] + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + 238 .loc 1 351 3 view .LVU30 + 239 .loc 1 351 6 is_stmt 0 view .LVU31 + 240 001a 012C cmp r4, #1 + 241 001c 0FD0 beq .L22 + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFI(); + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** else + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Request Wait For Event */ + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __SEV(); + 242 .loc 1 359 5 is_stmt 1 view .LVU32 + 243 .syntax divided + 244 @ 359 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 245 001e 40BF sev + 246 @ 0 "" 2 + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFE(); + 247 .loc 1 360 5 view .LVU33 + 248 @ 360 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 249 0020 20BF wfe + 250 @ 0 "" 2 + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFE(); + 251 .loc 1 361 5 view .LVU34 + 252 @ 361 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 253 0022 20BF wfe + 254 @ 0 "" 2 + 255 .thumb + 256 .syntax unified + 257 .L16: + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 258 .loc 1 363 1 is_stmt 0 view .LVU35 + 259 @ sp needed + 260 0024 10BD pop {r4, pc} + 261 .LVL5: + 262 .L21: + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 263 .loc 1 332 7 is_stmt 1 view .LVU36 + 264 0026 FFF7FEFF bl HAL_PWREx_EnableLowPowerRunMode + 265 .LVL6: + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 266 .loc 1 332 7 is_stmt 0 view .LVU37 + 267 002a F1E7 b .L18 + 268 .LVL7: + 269 .L17: + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 270 .loc 1 338 5 is_stmt 1 view .LVU38 + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 271 .loc 1 338 13 is_stmt 0 view .LVU39 + ARM GAS /tmp/ccDIilRR.s page 12 + + + 272 002c 054B ldr r3, .L23 + 273 002e 5B69 ldr r3, [r3, #20] + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 274 .loc 1 338 8 view .LVU40 + 275 0030 9B05 lsls r3, r3, #22 + 276 0032 EDD5 bpl .L18 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 277 .loc 1 340 7 is_stmt 1 view .LVU41 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 278 .loc 1 340 11 is_stmt 0 view .LVU42 + 279 0034 FFF7FEFF bl HAL_PWREx_DisableLowPowerRunMode + 280 .LVL8: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 281 .loc 1 340 10 view .LVU43 + 282 0038 0028 cmp r0, #0 + 283 003a E9D0 beq .L18 + 284 003c F2E7 b .L16 + 285 .L22: + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 286 .loc 1 354 5 is_stmt 1 view .LVU44 + 287 .syntax divided + 288 @ 354 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 289 003e 30BF wfi + 290 @ 0 "" 2 + 291 .thumb + 292 .syntax unified + 293 0040 F0E7 b .L16 + 294 .L24: + 295 0042 C046 .align 2 + 296 .L23: + 297 0044 00700040 .word 1073770496 + 298 0048 00ED00E0 .word -536810240 + 299 .cfi_endproc + 300 .LFE302: + 302 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 303 .align 1 + 304 .global HAL_PWR_EnterSTOPMode + 305 .syntax unified + 306 .code 16 + 307 .thumb_func + 308 .fpu softvfp + 310 HAL_PWR_EnterSTOPMode: + 311 .LVL9: + 312 .LFB303: + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enter Stop mode + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * legacy code running on devices where only "Stop mode" is mentioned + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * with main or low power regulator ON. + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note All clocks in the VCORE domain are stopped; the PLL, the HSI and the + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * HSE oscillators are disabled. Some peripherals with the wakeup + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * capability can switch on the HSI to receive a frame, and switch off + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * the HSI after receiving the frame if it is not a wakeup frame. + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * SRAM and register contents are preserved. + ARM GAS /tmp/ccDIilRR.s page 13 + + + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * The BOR is available. + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * The voltage regulator can be configured either in normal (Stop 0) or + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * low-power mode (Stop 1). + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * wakeup event, the HSI RC oscillator is selected as system clock + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode (Stop 1), + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * an additional startup delay is incurred when waking up. By keeping + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * the internal regulator ON during Stop mode (Stop 0), the consumption + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * is higher although the startup time is reduced. + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * This parameter can be one of the following values: + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * regulator ON) + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @param STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * WFE instruction. This parameter can be one of the following values: + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * instruction. + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * instruction. + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 313 .loc 1 400 1 view -0 + 314 .cfi_startproc + 315 @ args = 0, pretend = 0, frame = 0 + 316 @ frame_needed = 0, uses_anonymous_args = 0 + 317 @ link register save eliminated. + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Check the parameters */ + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 318 .loc 1 402 3 view .LVU46 + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 319 .loc 1 403 3 view .LVU47 + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if (Regulator != PWR_MAINREGULATOR_ON) + 320 .loc 1 405 3 view .LVU48 + 321 .loc 1 405 6 is_stmt 0 view .LVU49 + 322 0000 0028 cmp r0, #0 + 323 0002 16D0 beq .L26 + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Stop mode with Low-Power Regulator */ + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); + 324 .loc 1 408 5 is_stmt 1 view .LVU50 + 325 0004 0F4A ldr r2, .L31 + 326 0006 1368 ldr r3, [r2] + 327 0008 0720 movs r0, #7 + 328 .LVL10: + 329 .loc 1 408 5 is_stmt 0 view .LVU51 + 330 000a 8343 bics r3, r0 + 331 000c 0638 subs r0, r0, #6 + 332 000e 0343 orrs r3, r0 + 333 0010 1360 str r3, [r2] + 334 .L27: + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** else + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + ARM GAS /tmp/ccDIilRR.s page 14 + + + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Stop mode with Main Regulator */ + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 335 .loc 1 417 3 is_stmt 1 view .LVU52 + 336 0012 0D4A ldr r2, .L31+4 + 337 0014 1369 ldr r3, [r2, #16] + 338 0016 0420 movs r0, #4 + 339 0018 0343 orrs r3, r0 + 340 001a 1361 str r3, [r2, #16] + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** if (STOPEntry == PWR_STOPENTRY_WFI) + 341 .loc 1 420 3 view .LVU53 + 342 .loc 1 420 6 is_stmt 0 view .LVU54 + 343 001c 0129 cmp r1, #1 + 344 001e 0ED0 beq .L30 + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFI(); + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** else + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Request Wait For Event */ + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __SEV(); + 345 .loc 1 428 5 is_stmt 1 view .LVU55 + 346 .syntax divided + 347 @ 428 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 348 0020 40BF sev + 349 @ 0 "" 2 + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFE(); + 350 .loc 1 429 5 view .LVU56 + 351 @ 429 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 352 0022 20BF wfe + 353 @ 0 "" 2 + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFE(); + 354 .loc 1 430 5 view .LVU57 + 355 @ 430 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 356 0024 20BF wfe + 357 @ 0 "" 2 + 358 .thumb + 359 .syntax unified + 360 .L29: + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 361 .loc 1 434 3 view .LVU58 + 362 0026 084A ldr r2, .L31+4 + 363 0028 1369 ldr r3, [r2, #16] + 364 002a 0421 movs r1, #4 + 365 .LVL11: + 366 .loc 1 434 3 is_stmt 0 view .LVU59 + 367 002c 8B43 bics r3, r1 + 368 002e 1361 str r3, [r2, #16] + ARM GAS /tmp/ccDIilRR.s page 15 + + + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 369 .loc 1 435 1 view .LVU60 + 370 @ sp needed + 371 0030 7047 bx lr + 372 .LVL12: + 373 .L26: + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 374 .loc 1 413 5 is_stmt 1 view .LVU61 + 375 0032 044A ldr r2, .L31 + 376 0034 1368 ldr r3, [r2] + 377 0036 0720 movs r0, #7 + 378 .LVL13: + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 379 .loc 1 413 5 is_stmt 0 view .LVU62 + 380 0038 8343 bics r3, r0 + 381 003a 1360 str r3, [r2] + 382 003c E9E7 b .L27 + 383 .L30: + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 384 .loc 1 423 5 is_stmt 1 view .LVU63 + 385 .syntax divided + 386 @ 423 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 387 003e 30BF wfi + 388 @ 0 "" 2 + 389 .thumb + 390 .syntax unified + 391 0040 F1E7 b .L29 + 392 .L32: + 393 0042 C046 .align 2 + 394 .L31: + 395 0044 00700040 .word 1073770496 + 396 0048 00ED00E0 .word -536810240 + 397 .cfi_endproc + 398 .LFE303: + 400 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 401 .align 1 + 402 .global HAL_PWR_EnterSTANDBYMode + 403 .syntax unified + 404 .code 16 + 405 .thumb_func + 406 .fpu softvfp + 408 HAL_PWR_EnterSTANDBYMode: + 409 .LFB304: + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enter Standby mode. + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note In Standby mode, the PLL, the HSI and the HSE oscillators are + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * switched off. The voltage regulator is disabled. SRAM and register + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * contents are lost except for registers in the Backup domain and + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * Standby circuitry. BOR is available. + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note The I/Os can be configured either with a pull-up or pull-down or can + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * be kept in analog state. + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * respectively enable Pull Up and PullDown state. + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * disable the same. These states are effective in Standby mode only if + ARM GAS /tmp/ccDIilRR.s page 16 + + + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention() + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 410 .loc 1 455 1 view -0 + 411 .cfi_startproc + 412 @ args = 0, pretend = 0, frame = 0 + 413 @ frame_needed = 0, uses_anonymous_args = 0 + 414 @ link register save eliminated. + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set Stand-by mode */ + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); + 415 .loc 1 457 3 view .LVU65 + 416 0000 064A ldr r2, .L34 + 417 0002 1368 ldr r3, [r2] + 418 0004 0721 movs r1, #7 + 419 0006 8B43 bics r3, r1 + 420 0008 0439 subs r1, r1, #4 + 421 000a 0B43 orrs r3, r1 + 422 000c 1360 str r3, [r2] + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 423 .loc 1 460 3 view .LVU66 + 424 000e 044A ldr r2, .L34+4 + 425 0010 1369 ldr r3, [r2, #16] + 426 0012 0131 adds r1, r1, #1 + 427 0014 0B43 orrs r3, r1 + 428 0016 1361 str r3, [r2, #16] + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #if defined ( __CC_ARM) + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __force_stores(); + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** #endif /* __CC_ARM */ + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** __WFI(); + 429 .loc 1 468 3 view .LVU67 + 430 .syntax divided + 431 @ 468 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c" 1 + 432 0018 30BF wfi + 433 @ 0 "" 2 + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 434 .loc 1 469 1 is_stmt 0 view .LVU68 + 435 .thumb + 436 .syntax unified + 437 @ sp needed + 438 001a 7047 bx lr + 439 .L35: + 440 .align 2 + 441 .L34: + 442 001c 00700040 .word 1073770496 + 443 0020 00ED00E0 .word -536810240 + 444 .cfi_endproc + 445 .LFE304: + 447 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + ARM GAS /tmp/ccDIilRR.s page 17 + + + 448 .align 1 + 449 .global HAL_PWR_EnableSleepOnExit + 450 .syntax unified + 451 .code 16 + 452 .thumb_func + 453 .fpu softvfp + 455 HAL_PWR_EnableSleepOnExit: + 456 .LFB305: + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enable Sleep-On-Exit Cortex feature + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * processor enters SLEEP or DEEPSLEEP mode when an interruption + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * handling is over returning to thread mode. Setting this bit is + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * useful when the processor is expected to run only on interruptions + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * handling. + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 457 .loc 1 482 1 is_stmt 1 view -0 + 458 .cfi_startproc + 459 @ args = 0, pretend = 0, frame = 0 + 460 @ frame_needed = 0, uses_anonymous_args = 0 + 461 @ link register save eliminated. + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 462 .loc 1 484 3 view .LVU70 + 463 0000 024A ldr r2, .L37 + 464 0002 1369 ldr r3, [r2, #16] + 465 0004 0221 movs r1, #2 + 466 0006 0B43 orrs r3, r1 + 467 0008 1361 str r3, [r2, #16] + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 468 .loc 1 485 1 is_stmt 0 view .LVU71 + 469 @ sp needed + 470 000a 7047 bx lr + 471 .L38: + 472 .align 2 + 473 .L37: + 474 000c 00ED00E0 .word -536810240 + 475 .cfi_endproc + 476 .LFE305: + 478 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 479 .align 1 + 480 .global HAL_PWR_DisableSleepOnExit + 481 .syntax unified + 482 .code 16 + 483 .thumb_func + 484 .fpu softvfp + 486 HAL_PWR_DisableSleepOnExit: + 487 .LFB306: + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Disable Sleep-On-Exit Cortex feature + ARM GAS /tmp/ccDIilRR.s page 18 + + + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * processor enters SLEEP or DEEPSLEEP mode when an interruption + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * handling is over. + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 488 .loc 1 496 1 is_stmt 1 view -0 + 489 .cfi_startproc + 490 @ args = 0, pretend = 0, frame = 0 + 491 @ frame_needed = 0, uses_anonymous_args = 0 + 492 @ link register save eliminated. + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 493 .loc 1 498 3 view .LVU73 + 494 0000 024A ldr r2, .L40 + 495 0002 1369 ldr r3, [r2, #16] + 496 0004 0221 movs r1, #2 + 497 0006 8B43 bics r3, r1 + 498 0008 1361 str r3, [r2, #16] + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 499 .loc 1 499 1 is_stmt 0 view .LVU74 + 500 @ sp needed + 501 000a 7047 bx lr + 502 .L41: + 503 .align 2 + 504 .L40: + 505 000c 00ED00E0 .word -536810240 + 506 .cfi_endproc + 507 .LFE306: + 509 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 510 .align 1 + 511 .global HAL_PWR_EnableSEVOnPend + 512 .syntax unified + 513 .code 16 + 514 .thumb_func + 515 .fpu softvfp + 517 HAL_PWR_EnableSEVOnPend: + 518 .LFB307: + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Enable Cortex Sev On Pending feature. + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * events and all interrupts, including disabled ones can wakeup + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * processor from WFE. + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 519 .loc 1 510 1 is_stmt 1 view -0 + 520 .cfi_startproc + 521 @ args = 0, pretend = 0, frame = 0 + 522 @ frame_needed = 0, uses_anonymous_args = 0 + 523 @ link register save eliminated. + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + ARM GAS /tmp/ccDIilRR.s page 19 + + + 524 .loc 1 512 3 view .LVU76 + 525 0000 024A ldr r2, .L43 + 526 0002 1369 ldr r3, [r2, #16] + 527 0004 1021 movs r1, #16 + 528 0006 0B43 orrs r3, r1 + 529 0008 1361 str r3, [r2, #16] + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 530 .loc 1 513 1 is_stmt 0 view .LVU77 + 531 @ sp needed + 532 000a 7047 bx lr + 533 .L44: + 534 .align 2 + 535 .L43: + 536 000c 00ED00E0 .word -536810240 + 537 .cfi_endproc + 538 .LFE307: + 540 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 541 .align 1 + 542 .global HAL_PWR_DisableSEVOnPend + 543 .syntax unified + 544 .code 16 + 545 .thumb_func + 546 .fpu softvfp + 548 HAL_PWR_DisableSEVOnPend: + 549 .LFB308: + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /** + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @brief Disable Cortex Sev On Pending feature. + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * enable interrupts or events can wakeup processor from WFE + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** * @retval None + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** */ + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** { + 550 .loc 1 523 1 is_stmt 1 view -0 + 551 .cfi_startproc + 552 @ args = 0, pretend = 0, frame = 0 + 553 @ frame_needed = 0, uses_anonymous_args = 0 + 554 @ link register save eliminated. + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 555 .loc 1 525 3 view .LVU79 + 556 0000 024A ldr r2, .L46 + 557 0002 1369 ldr r3, [r2, #16] + 558 0004 1021 movs r1, #16 + 559 0006 8B43 bics r3, r1 + 560 0008 1361 str r3, [r2, #16] + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c **** } + 561 .loc 1 526 1 is_stmt 0 view .LVU80 + 562 @ sp needed + 563 000a 7047 bx lr + 564 .L47: + 565 .align 2 + 566 .L46: + 567 000c 00ED00E0 .word -536810240 + 568 .cfi_endproc + ARM GAS /tmp/ccDIilRR.s page 20 + + + 569 .LFE308: + 571 .text + 572 .Letext0: + 573 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 574 .file 3 "Drivers/CMSIS/Include/core_cm0plus.h" + 575 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 576 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h" + 577 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 578 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccDIilRR.s page 21 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_pwr.c + /tmp/ccDIilRR.s:16 .text.HAL_PWR_DeInit:0000000000000000 $t + /tmp/ccDIilRR.s:24 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit + /tmp/ccDIilRR.s:50 .text.HAL_PWR_DeInit:0000000000000018 $d + /tmp/ccDIilRR.s:56 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t + /tmp/ccDIilRR.s:63 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess + /tmp/ccDIilRR.s:83 .text.HAL_PWR_EnableBkUpAccess:0000000000000010 $d + /tmp/ccDIilRR.s:88 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t + /tmp/ccDIilRR.s:95 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess + /tmp/ccDIilRR.s:114 .text.HAL_PWR_DisableBkUpAccess:000000000000000c $d + /tmp/ccDIilRR.s:120 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t + /tmp/ccDIilRR.s:127 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin + /tmp/ccDIilRR.s:157 .text.HAL_PWR_EnableWakeUpPin:0000000000000018 $d + /tmp/ccDIilRR.s:162 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t + /tmp/ccDIilRR.s:169 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin + /tmp/ccDIilRR.s:191 .text.HAL_PWR_DisableWakeUpPin:0000000000000010 $d + /tmp/ccDIilRR.s:196 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t + /tmp/ccDIilRR.s:203 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode + /tmp/ccDIilRR.s:297 .text.HAL_PWR_EnterSLEEPMode:0000000000000044 $d + /tmp/ccDIilRR.s:303 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t + /tmp/ccDIilRR.s:310 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode + /tmp/ccDIilRR.s:395 .text.HAL_PWR_EnterSTOPMode:0000000000000044 $d + /tmp/ccDIilRR.s:401 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t + /tmp/ccDIilRR.s:408 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode + /tmp/ccDIilRR.s:442 .text.HAL_PWR_EnterSTANDBYMode:000000000000001c $d + /tmp/ccDIilRR.s:448 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t + /tmp/ccDIilRR.s:455 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit + /tmp/ccDIilRR.s:474 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d + /tmp/ccDIilRR.s:479 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t + /tmp/ccDIilRR.s:486 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit + /tmp/ccDIilRR.s:505 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d + /tmp/ccDIilRR.s:510 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t + /tmp/ccDIilRR.s:517 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend + /tmp/ccDIilRR.s:536 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d + /tmp/ccDIilRR.s:541 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t + /tmp/ccDIilRR.s:548 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend + /tmp/ccDIilRR.s:567 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d + +UNDEFINED SYMBOLS +HAL_PWREx_EnableLowPowerRunMode +HAL_PWREx_DisableLowPowerRunMode diff --git a/squero/build/stm32g0xx_hal_pwr.o b/squero/build/stm32g0xx_hal_pwr.o new file mode 100644 index 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Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_pwr_ex.lst b/squero/build/stm32g0xx_hal_pwr_ex.lst new file mode 100644 index 0000000..e909144 --- /dev/null +++ b/squero/build/stm32g0xx_hal_pwr_ex.lst @@ -0,0 +1,2819 @@ +ARM GAS /tmp/ccS0aCke.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_pwr_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_PWREx_EnableBatteryCharging,"ax",%progbits + 16 .align 1 + 17 .global HAL_PWREx_EnableBatteryCharging + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_PWREx_EnableBatteryCharging: + 25 .LVL0: + 26 .LFB297: + 27 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @file stm32g0xx_hal_pwr_ex.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + Extended Initialization and de-initialization functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + Extended Peripheral Control functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ****************************************************************************** + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @attention + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** *

© Copyright (c) 2018 STMicroelectronics. + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * All rights reserved.

+ 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * the "License"; You may not use this file except in compliance with the + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * License. You may obtain a copy of the License at: + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * opensource.org/licenses/BSD-3-Clause + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ****************************************************************************** + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #include "stm32g0xx_hal.h" + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccS0aCke.s page 2 + + + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @addtogroup PWREx + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_PVD_SUPPORT) + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PVD_MODE_IT 0x00010000U /*!< Mask for interruption yielded + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** by PVD threshold crossing */ + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PVD_MODE_EVT 0x00020000U /*!< Mask for event yielded + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** by PVD threshold crossing */ + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PVD_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PVD trigger */ + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PVD_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PVD trigger */ + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @} + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_PVD_SUPPORT */ + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @defgroup PWREx_TimeOut_Value PWREx Flag Setting Time Out Value + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PWR_REGLPF_SETTING_DELAY_6_US 6u /*!< REGLPF should rise in about 5 us plus + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** 2 APB clock. Taking in account max Sysclk at + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** 2 MHz, and rounded to upper value */ + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PWR_VOSF_SETTING_DELAY_6_US 6u /*!< VOSF should rise in about 5 us plus + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** 2 APB clock. Taking in account max Sysclk at + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** 16 MHz, and rounded to upper value */ + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @} + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @defgroup PWREx_Gpio_Pin_Number PWREx Gpio Pin Number + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #define PWR_GPIO_PIN_NB 16u /*!< Number of gpio pin in bank */ + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @} + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @} + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/ + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/ + ARM GAS /tmp/ccS0aCke.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Exported functions --------------------------------------------------------*/ + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Extended Peripheral Control functions + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** @verbatim + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** =============================================================================== + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ##### Extended Peripheral Initialization and de-initialization functions ##### + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** =============================================================================== + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** [..] + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** *** PVD configuration *** + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ========================= + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** [..] + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** threshold selected by the PVD Level (PVDRT[2:0] & PVDFT[2:0] bits in + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR CR2 register). + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** line 16 and can generate an interrupt if enabled. + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby & Shutdown mode. + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** *** PVM configuration *** + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** ========================= + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** [..] + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** @endverbatim + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @{ + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable battery charging. + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When VDD is present, charge the external battery on VBAT through an + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * internal resistor. + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param ResistorSelection specifies the resistor impedance. + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 28 .loc 1 133 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** uint32_t tmpreg; + 33 .loc 1 134 3 view .LVU1 + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); + 34 .loc 1 135 3 view .LVU2 + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Specify resistor selection and enable battery charging */ + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** tmpreg = (PWR->CR4 & ~PWR_CR4_VBRS); + ARM GAS /tmp/ccS0aCke.s page 4 + + + 35 .loc 1 138 3 view .LVU3 + 36 .loc 1 138 16 is_stmt 0 view .LVU4 + 37 0000 044A ldr r2, .L2 + 38 0002 D368 ldr r3, [r2, #12] + 39 .loc 1 138 10 view .LVU5 + 40 0004 0449 ldr r1, .L2+4 + 41 0006 0B40 ands r3, r1 + 42 .LVL1: + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR->CR4 = (tmpreg | ResistorSelection | PWR_CR4_VBE); + 43 .loc 1 139 3 is_stmt 1 view .LVU6 + 44 .loc 1 139 22 is_stmt 0 view .LVU7 + 45 0008 0343 orrs r3, r0 + 46 .LVL2: + 47 .loc 1 139 42 view .LVU8 + 48 000a 8020 movs r0, #128 + 49 .LVL3: + 50 .loc 1 139 42 view .LVU9 + 51 000c 4000 lsls r0, r0, #1 + 52 000e 0343 orrs r3, r0 + 53 .loc 1 139 12 view .LVU10 + 54 0010 D360 str r3, [r2, #12] + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 55 .loc 1 140 1 view .LVU11 + 56 @ sp needed + 57 0012 7047 bx lr + 58 .L3: + 59 .align 2 + 60 .L2: + 61 0014 00700040 .word 1073770496 + 62 0018 FFFDFFFF .word -513 + 63 .cfi_endproc + 64 .LFE297: + 66 .section .text.HAL_PWREx_DisableBatteryCharging,"ax",%progbits + 67 .align 1 + 68 .global HAL_PWREx_DisableBatteryCharging + 69 .syntax unified + 70 .code 16 + 71 .thumb_func + 72 .fpu softvfp + 74 HAL_PWREx_DisableBatteryCharging: + 75 .LFB298: + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable battery charging. + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableBatteryCharging(void) + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 76 .loc 1 148 1 is_stmt 1 view -0 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 0 + 79 @ frame_needed = 0, uses_anonymous_args = 0 + 80 @ link register save eliminated. + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); + 81 .loc 1 149 3 view .LVU13 + 82 0000 024A ldr r2, .L5 + ARM GAS /tmp/ccS0aCke.s page 5 + + + 83 0002 D368 ldr r3, [r2, #12] + 84 0004 0249 ldr r1, .L5+4 + 85 0006 0B40 ands r3, r1 + 86 0008 D360 str r3, [r2, #12] + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 87 .loc 1 150 1 is_stmt 0 view .LVU14 + 88 @ sp needed + 89 000a 7047 bx lr + 90 .L6: + 91 .align 2 + 92 .L5: + 93 000c 00700040 .word 1073770496 + 94 0010 FFFEFFFF .word -257 + 95 .cfi_endproc + 96 .LFE298: + 98 .section .text.HAL_PWREx_EnablePORMonitorSampling,"ax",%progbits + 99 .align 1 + 100 .global HAL_PWREx_EnablePORMonitorSampling + 101 .syntax unified + 102 .code 16 + 103 .thumb_func + 104 .fpu softvfp + 106 HAL_PWREx_EnablePORMonitorSampling: + 107 .LFB299: + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_CR3_ENB_ULP) + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable POR Monitor sampling mode. + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When entering ultra low power modes (standby, shutdown) this feature + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * can be enabled to reduce further consumption: Power On Reset monitor + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * is then set in sampling mode, and no more in always on mode. + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePORMonitorSampling(void) + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 108 .loc 1 161 1 is_stmt 1 view -0 + 109 .cfi_startproc + 110 @ args = 0, pretend = 0, frame = 0 + 111 @ frame_needed = 0, uses_anonymous_args = 0 + 112 @ link register save eliminated. + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR->CR3 |= PWR_CR3_ENB_ULP; + 113 .loc 1 162 3 view .LVU16 + 114 .loc 1 162 12 is_stmt 0 view .LVU17 + 115 0000 034A ldr r2, .L8 + 116 0002 9168 ldr r1, [r2, #8] + 117 0004 8023 movs r3, #128 + 118 0006 9B00 lsls r3, r3, #2 + 119 0008 0B43 orrs r3, r1 + 120 000a 9360 str r3, [r2, #8] + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 121 .loc 1 163 1 view .LVU18 + 122 @ sp needed + 123 000c 7047 bx lr + 124 .L9: + 125 000e C046 .align 2 + 126 .L8: + 127 0010 00700040 .word 1073770496 + ARM GAS /tmp/ccS0aCke.s page 6 + + + 128 .cfi_endproc + 129 .LFE299: + 131 .section .text.HAL_PWREx_DisablePORMonitorSampling,"ax",%progbits + 132 .align 1 + 133 .global HAL_PWREx_DisablePORMonitorSampling + 134 .syntax unified + 135 .code 16 + 136 .thumb_func + 137 .fpu softvfp + 139 HAL_PWREx_DisablePORMonitorSampling: + 140 .LFB300: + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable POR Monitor sampling mode. + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePORMonitorSampling(void) + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 141 .loc 1 171 1 is_stmt 1 view -0 + 142 .cfi_startproc + 143 @ args = 0, pretend = 0, frame = 0 + 144 @ frame_needed = 0, uses_anonymous_args = 0 + 145 @ link register save eliminated. + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR->CR3 &= ~PWR_CR3_ENB_ULP; + 146 .loc 1 172 3 view .LVU20 + 147 .loc 1 172 12 is_stmt 0 view .LVU21 + 148 0000 024A ldr r2, .L11 + 149 0002 9368 ldr r3, [r2, #8] + 150 0004 0249 ldr r1, .L11+4 + 151 0006 0B40 ands r3, r1 + 152 0008 9360 str r3, [r2, #8] + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 153 .loc 1 173 1 view .LVU22 + 154 @ sp needed + 155 000a 7047 bx lr + 156 .L12: + 157 .align 2 + 158 .L11: + 159 000c 00700040 .word 1073770496 + 160 0010 FFFDFFFF .word -513 + 161 .cfi_endproc + 162 .LFE300: + 164 .section .text.HAL_PWREx_ConfigPVD,"ax",%progbits + 165 .align 1 + 166 .global HAL_PWREx_ConfigPVD + 167 .syntax unified + 168 .code 16 + 169 .thumb_func + 170 .fpu softvfp + 172 HAL_PWREx_ConfigPVD: + 173 .LVL4: + 174 .LFB301: + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_CR3_ENB_ULP */ + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_PVD_SUPPORT) + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccS0aCke.s page 7 + + + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Configure the Power Voltage Detector (PVD). + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PVD configuration information: threshold levels, operating mode. + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * more details about the voltage thresholds corresponding to each + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * detection level. + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note User should take care that rising threshold is higher than falling + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * one in order to avoid having always PVDO output set. + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL_OK + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 175 .loc 1 189 1 is_stmt 1 view -0 + 176 .cfi_startproc + 177 @ args = 0, pretend = 0, frame = 0 + 178 @ frame_needed = 0, uses_anonymous_args = 0 + 179 .loc 1 189 1 is_stmt 0 view .LVU24 + 180 0000 10B5 push {r4, lr} + 181 .LCFI0: + 182 .cfi_def_cfa_offset 8 + 183 .cfi_offset 4, -8 + 184 .cfi_offset 14, -4 + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check the parameters */ + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + 185 .loc 1 191 3 is_stmt 1 view .LVU25 + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + 186 .loc 1 192 3 view .LVU26 + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Set PVD level bits only according to PVDLevel value */ + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR2, (PWR_CR2_PVDFT | PWR_CR2_PVDRT), sConfigPVD->PVDLevel); + 187 .loc 1 195 3 view .LVU27 + 188 0002 1F4A ldr r2, .L18 + 189 0004 5368 ldr r3, [r2, #4] + 190 0006 7E21 movs r1, #126 + 191 0008 8B43 bics r3, r1 + 192 000a 0168 ldr r1, [r0] + 193 000c 0B43 orrs r3, r1 + 194 000e 5360 str r3, [r2, #4] + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear any previous config, in case no event or IT mode is selected */ + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + 195 .loc 1 198 3 view .LVU28 + 196 0010 1C4B ldr r3, .L18+4 + 197 0012 8424 movs r4, #132 + 198 0014 1959 ldr r1, [r3, r4] + 199 0016 1C4A ldr r2, .L18+8 + 200 0018 1140 ands r1, r2 + 201 001a 1951 str r1, [r3, r4] + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); + 202 .loc 1 199 3 view .LVU29 + 203 001c 043C subs r4, r4, #4 + 204 001e 1959 ldr r1, [r3, r4] + 205 0020 1140 ands r1, r2 + 206 0022 1951 str r1, [r3, r4] + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + 207 .loc 1 200 3 view .LVU30 + 208 0024 5968 ldr r1, [r3, #4] + ARM GAS /tmp/ccS0aCke.s page 8 + + + 209 0026 1140 ands r1, r2 + 210 0028 5960 str r1, [r3, #4] + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + 211 .loc 1 201 3 view .LVU31 + 212 002a 1968 ldr r1, [r3] + 213 002c 0A40 ands r2, r1 + 214 002e 1A60 str r2, [r3] + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure interrupt mode */ + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 215 .loc 1 204 3 view .LVU32 + 216 .loc 1 204 6 is_stmt 0 view .LVU33 + 217 0030 4368 ldr r3, [r0, #4] + 218 0032 DB03 lsls r3, r3, #15 + 219 0034 06D5 bpl .L14 + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); + 220 .loc 1 206 5 is_stmt 1 view .LVU34 + 221 0036 1349 ldr r1, .L18+4 + 222 0038 8022 movs r2, #128 + 223 003a 8C58 ldr r4, [r1, r2] + 224 003c 8023 movs r3, #128 + 225 003e 5B02 lsls r3, r3, #9 + 226 0040 2343 orrs r3, r4 + 227 0042 8B50 str r3, [r1, r2] + 228 .L14: + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure event mode */ + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 229 .loc 1 210 3 view .LVU35 + 230 .loc 1 210 6 is_stmt 0 view .LVU36 + 231 0044 4368 ldr r3, [r0, #4] + 232 0046 9B03 lsls r3, r3, #14 + 233 0048 06D5 bpl .L15 + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + 234 .loc 1 212 5 is_stmt 1 view .LVU37 + 235 004a 0E49 ldr r1, .L18+4 + 236 004c 8422 movs r2, #132 + 237 004e 8C58 ldr r4, [r1, r2] + 238 0050 8023 movs r3, #128 + 239 0052 5B02 lsls r3, r3, #9 + 240 0054 2343 orrs r3, r4 + 241 0056 8B50 str r3, [r1, r2] + 242 .L15: + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure the edge */ + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 243 .loc 1 216 3 view .LVU38 + 244 .loc 1 216 6 is_stmt 0 view .LVU39 + 245 0058 4368 ldr r3, [r0, #4] + 246 005a DB07 lsls r3, r3, #31 + 247 005c 05D5 bpl .L16 + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + ARM GAS /tmp/ccS0aCke.s page 9 + + + 248 .loc 1 218 5 is_stmt 1 view .LVU40 + 249 005e 094A ldr r2, .L18+4 + 250 0060 1168 ldr r1, [r2] + 251 0062 8023 movs r3, #128 + 252 0064 5B02 lsls r3, r3, #9 + 253 0066 0B43 orrs r3, r1 + 254 0068 1360 str r3, [r2] + 255 .L16: + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 256 .loc 1 221 3 view .LVU41 + 257 .loc 1 221 18 is_stmt 0 view .LVU42 + 258 006a 4368 ldr r3, [r0, #4] + 259 .loc 1 221 6 view .LVU43 + 260 006c 9B07 lsls r3, r3, #30 + 261 006e 05D5 bpl .L17 + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + 262 .loc 1 223 5 is_stmt 1 view .LVU44 + 263 0070 044A ldr r2, .L18+4 + 264 0072 5168 ldr r1, [r2, #4] + 265 0074 8023 movs r3, #128 + 266 0076 5B02 lsls r3, r3, #9 + 267 0078 0B43 orrs r3, r1 + 268 007a 5360 str r3, [r2, #4] + 269 .L17: + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return HAL_OK; + 270 .loc 1 226 3 view .LVU45 + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 271 .loc 1 227 1 is_stmt 0 view .LVU46 + 272 007c 0020 movs r0, #0 + 273 .LVL5: + 274 .loc 1 227 1 view .LVU47 + 275 @ sp needed + 276 007e 10BD pop {r4, pc} + 277 .L19: + 278 .align 2 + 279 .L18: + 280 0080 00700040 .word 1073770496 + 281 0084 00180240 .word 1073879040 + 282 0088 FFFFFEFF .word -65537 + 283 .cfi_endproc + 284 .LFE301: + 286 .section .text.HAL_PWREx_EnablePVD,"ax",%progbits + 287 .align 1 + 288 .global HAL_PWREx_EnablePVD + 289 .syntax unified + 290 .code 16 + 291 .thumb_func + 292 .fpu softvfp + 294 HAL_PWREx_EnablePVD: + 295 .LFB302: + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccS0aCke.s page 10 + + + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable the Power Voltage Detector (PVD). + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVD(void) + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 296 .loc 1 235 1 is_stmt 1 view -0 + 297 .cfi_startproc + 298 @ args = 0, pretend = 0, frame = 0 + 299 @ frame_needed = 0, uses_anonymous_args = 0 + 300 @ link register save eliminated. + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR2, PWR_CR2_PVDE); + 301 .loc 1 236 3 view .LVU49 + 302 0000 024A ldr r2, .L21 + 303 0002 5368 ldr r3, [r2, #4] + 304 0004 0121 movs r1, #1 + 305 0006 0B43 orrs r3, r1 + 306 0008 5360 str r3, [r2, #4] + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 307 .loc 1 237 1 is_stmt 0 view .LVU50 + 308 @ sp needed + 309 000a 7047 bx lr + 310 .L22: + 311 .align 2 + 312 .L21: + 313 000c 00700040 .word 1073770496 + 314 .cfi_endproc + 315 .LFE302: + 317 .section .text.HAL_PWREx_DisablePVD,"ax",%progbits + 318 .align 1 + 319 .global HAL_PWREx_DisablePVD + 320 .syntax unified + 321 .code 16 + 322 .thumb_func + 323 .fpu softvfp + 325 HAL_PWREx_DisablePVD: + 326 .LFB303: + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable the Power Voltage Detector (PVD). + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVD(void) + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 327 .loc 1 245 1 is_stmt 1 view -0 + 328 .cfi_startproc + 329 @ args = 0, pretend = 0, frame = 0 + 330 @ frame_needed = 0, uses_anonymous_args = 0 + 331 @ link register save eliminated. + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); + 332 .loc 1 246 3 view .LVU52 + 333 0000 024A ldr r2, .L24 + 334 0002 5368 ldr r3, [r2, #4] + 335 0004 0121 movs r1, #1 + 336 0006 8B43 bics r3, r1 + 337 0008 5360 str r3, [r2, #4] + ARM GAS /tmp/ccS0aCke.s page 11 + + + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 338 .loc 1 247 1 is_stmt 0 view .LVU53 + 339 @ sp needed + 340 000a 7047 bx lr + 341 .L25: + 342 .align 2 + 343 .L24: + 344 000c 00700040 .word 1073770496 + 345 .cfi_endproc + 346 .LFE303: + 348 .section .text.HAL_PWREx_EnableInternalWakeUpLine,"ax",%progbits + 349 .align 1 + 350 .global HAL_PWREx_EnableInternalWakeUpLine + 351 .syntax unified + 352 .code 16 + 353 .thumb_func + 354 .fpu softvfp + 356 HAL_PWREx_EnableInternalWakeUpLine: + 357 .LFB304: + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_PVD_SUPPORT */ + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_PVM_SUPPORT) + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable VDDUSB supply. + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableVddUSB(void) + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR2, PWR_CR2_USV); + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable VDDUSB supply. + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableVddUSB(void) + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR2, PWR_CR2_USV); + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_PVM_SUPPORT */ + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_CR2_IOSV) + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable VDDIO2 supply. + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableVddIO2(void) + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR2, PWR_CR2_IOSV); + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable VDDIO2 supply. + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + ARM GAS /tmp/ccS0aCke.s page 12 + + + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableVddIO2(void) + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_CR2_IOSV */ + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined (PWR_PVM_SUPPORT) + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePVMUSB(void) + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR2, PWR_PVM_USB); + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePVMUSB(void) + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR2, PWR_PVM_USB); + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_PVM_SUPPORT */ + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_PVM_SUPPORT) + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Configure the Peripheral Voltage Monitoring (PVM). + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PVM configuration information. + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note The API configures a single PVM according to the information contained + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * in the input structure. To configure several PVMs, the API must be singly + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * called for each PVM used. + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * more details about the voltage thresholds corresponding to each + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * detection level and to each monitored supply. + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL status + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check the parameters */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure EXTI 34 interrupts if so required: + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** scan through PVMType to detect which PVMx is set and + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** configure the corresponding EXTI line accordingly. */ + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** switch (sConfigPVM->PVMType) + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_PVM_USB: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_DISABLE_EVENT(); + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_DISABLE_IT(); + ARM GAS /tmp/ccS0aCke.s page 13 + + + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure interrupt mode */ + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_ENABLE_IT(); + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure event mode */ + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_ENABLE_EVENT(); + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Configure the edge */ + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** default: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** status = HAL_ERROR; + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return status; + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_PVM_SUPPORT */ + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable Internal Wake-up Line. + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableInternalWakeUpLine(void) + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 358 .loc 1 383 1 is_stmt 1 view -0 + 359 .cfi_startproc + 360 @ args = 0, pretend = 0, frame = 0 + 361 @ frame_needed = 0, uses_anonymous_args = 0 + 362 @ link register save eliminated. + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR3, PWR_CR3_EIWUL); + 363 .loc 1 384 3 view .LVU55 + 364 0000 034A ldr r2, .L27 + 365 0002 9168 ldr r1, [r2, #8] + 366 0004 8023 movs r3, #128 + 367 0006 1B02 lsls r3, r3, #8 + 368 0008 0B43 orrs r3, r1 + 369 000a 9360 str r3, [r2, #8] + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 370 .loc 1 385 1 is_stmt 0 view .LVU56 + 371 @ sp needed + ARM GAS /tmp/ccS0aCke.s page 14 + + + 372 000c 7047 bx lr + 373 .L28: + 374 000e C046 .align 2 + 375 .L27: + 376 0010 00700040 .word 1073770496 + 377 .cfi_endproc + 378 .LFE304: + 380 .section .text.HAL_PWREx_DisableInternalWakeUpLine,"ax",%progbits + 381 .align 1 + 382 .global HAL_PWREx_DisableInternalWakeUpLine + 383 .syntax unified + 384 .code 16 + 385 .thumb_func + 386 .fpu softvfp + 388 HAL_PWREx_DisableInternalWakeUpLine: + 389 .LFB305: + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable Internal Wake-up Line. + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableInternalWakeUpLine(void) + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 390 .loc 1 392 1 is_stmt 1 view -0 + 391 .cfi_startproc + 392 @ args = 0, pretend = 0, frame = 0 + 393 @ frame_needed = 0, uses_anonymous_args = 0 + 394 @ link register save eliminated. + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); + 395 .loc 1 393 3 view .LVU58 + 396 0000 024A ldr r2, .L30 + 397 0002 9368 ldr r3, [r2, #8] + 398 0004 0249 ldr r1, .L30+4 + 399 0006 0B40 ands r3, r1 + 400 0008 9360 str r3, [r2, #8] + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 401 .loc 1 394 1 is_stmt 0 view .LVU59 + 402 @ sp needed + 403 000a 7047 bx lr + 404 .L31: + 405 .align 2 + 406 .L30: + 407 000c 00700040 .word 1073770496 + 408 0010 FF7FFFFF .word -32769 + 409 .cfi_endproc + 410 .LFE305: + 412 .section .text.HAL_PWREx_EnableGPIOPullUp,"ax",%progbits + 413 .align 1 + 414 .global HAL_PWREx_EnableGPIOPullUp + 415 .syntax unified + 416 .code 16 + 417 .thumb_func + 418 .fpu softvfp + 420 HAL_PWREx_EnableGPIOPullUp: + 421 .LVL6: + 422 .LFB306: + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccS0aCke.s page 15 + + + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * pull-up state in Standby and Shutdown modes. + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This state is effective in Standby and Shutdown modes only if APC bit + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note The configuration is lost when exiting the Shutdown mode due to the + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * power-on reset, maintained when exiting the Standby mode. + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * to select the GPIO peripheral. + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIONumber Specify the I/O pins numbers. + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * I/O pins are available) or the logical OR of several of them to set + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * several bits for a given port in a single API call. + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 423 .loc 1 416 1 is_stmt 1 view -0 + 424 .cfi_startproc + 425 @ args = 0, pretend = 0, frame = 0 + 426 @ frame_needed = 0, uses_anonymous_args = 0 + 427 @ link register save eliminated. + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 428 .loc 1 417 3 view .LVU61 + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO(GPIO)); + 429 .loc 1 419 3 view .LVU62 + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + 430 .loc 1 420 3 view .LVU63 + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** switch (GPIO) + 431 .loc 1 422 3 view .LVU64 + 432 0000 0528 cmp r0, #5 + 433 0002 34D8 bhi .L40 + 434 0004 8000 lsls r0, r0, #2 + 435 .LVL7: + 436 .loc 1 422 3 is_stmt 0 view .LVU65 + 437 0006 1B4B ldr r3, .L41 + 438 0008 1B58 ldr r3, [r3, r0] + 439 000a 9F46 mov pc, r3 + 440 .section .rodata.HAL_PWREx_EnableGPIOPullUp,"a",%progbits + 441 .align 2 + 442 .L35: + 443 0000 0C000000 .word .L39 + 444 0004 26000000 .word .L38 + 445 0008 38000000 .word .L37 + 446 000c 4A000000 .word .L36 + 447 0010 6E000000 .word .L40 + 448 0014 5C000000 .word .L34 + 449 .section .text.HAL_PWREx_EnableGPIOPullUp + 450 .L39: + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_A: + ARM GAS /tmp/ccS0aCke.s page 16 + + + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + 451 .loc 1 425 7 is_stmt 1 view .LVU66 + 452 000c 1A4B ldr r3, .L41+4 + 453 000e 1A6A ldr r2, [r3, #32] + 454 0010 1A48 ldr r0, .L41+8 + 455 0012 0840 ands r0, r1 + 456 0014 0243 orrs r2, r0 + 457 0016 1A62 str r2, [r3, #32] + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + 458 .loc 1 426 7 view .LVU67 + 459 0018 5A6A ldr r2, [r3, #36] + 460 001a 1948 ldr r0, .L41+12 + 461 001c 0140 ands r1, r0 + 462 .LVL8: + 463 .loc 1 426 7 is_stmt 0 view .LVU68 + 464 001e 8A43 bics r2, r1 + 465 0020 5A62 str r2, [r3, #36] + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 466 .loc 1 427 7 is_stmt 1 view .LVU69 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 467 .loc 1 417 21 is_stmt 0 view .LVU70 + 468 0022 0020 movs r0, #0 + 469 .L33: + 470 .LVL9: + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_B: + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRB, GPIONumber); + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRB, GPIONumber); + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_C: + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRC, GPIONumber); + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRC, GPIONumber); + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_D: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRD, GPIONumber); + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRD, GPIONumber); + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(GPI0E) + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_E: + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRE, GPIONumber); + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRE, GPIONumber); + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* GPI0E */ + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_F: + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PUCRF, GPIONumber); + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRF, GPIONumber); + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** default: + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** status = HAL_ERROR; + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return status; + ARM GAS /tmp/ccS0aCke.s page 17 + + + 471 .loc 1 460 3 is_stmt 1 view .LVU71 + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 472 .loc 1 461 1 is_stmt 0 view .LVU72 + 473 @ sp needed + 474 0024 7047 bx lr + 475 .LVL10: + 476 .L38: + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRB, GPIONumber); + 477 .loc 1 430 7 is_stmt 1 view .LVU73 + 478 0026 144B ldr r3, .L41+4 + 479 0028 9A6A ldr r2, [r3, #40] + 480 002a 0A43 orrs r2, r1 + 481 002c 9A62 str r2, [r3, #40] + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 482 .loc 1 431 7 view .LVU74 + 483 002e DA6A ldr r2, [r3, #44] + 484 0030 8A43 bics r2, r1 + 485 0032 DA62 str r2, [r3, #44] + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 486 .loc 1 432 7 view .LVU75 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 487 .loc 1 417 21 is_stmt 0 view .LVU76 + 488 0034 0020 movs r0, #0 + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 489 .loc 1 432 7 view .LVU77 + 490 0036 F5E7 b .L33 + 491 .L37: + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRC, GPIONumber); + 492 .loc 1 435 7 is_stmt 1 view .LVU78 + 493 0038 0F4B ldr r3, .L41+4 + 494 003a 1A6B ldr r2, [r3, #48] + 495 003c 0A43 orrs r2, r1 + 496 003e 1A63 str r2, [r3, #48] + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 497 .loc 1 436 7 view .LVU79 + 498 0040 5A6B ldr r2, [r3, #52] + 499 0042 8A43 bics r2, r1 + 500 0044 5A63 str r2, [r3, #52] + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 501 .loc 1 437 7 view .LVU80 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 502 .loc 1 417 21 is_stmt 0 view .LVU81 + 503 0046 0020 movs r0, #0 + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 504 .loc 1 437 7 view .LVU82 + 505 0048 ECE7 b .L33 + 506 .L36: + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRD, GPIONumber); + 507 .loc 1 440 7 is_stmt 1 view .LVU83 + 508 004a 0B4B ldr r3, .L41+4 + 509 004c 9A6B ldr r2, [r3, #56] + 510 004e 0A43 orrs r2, r1 + 511 0050 9A63 str r2, [r3, #56] + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 512 .loc 1 441 7 view .LVU84 + 513 0052 DA6B ldr r2, [r3, #60] + 514 0054 8A43 bics r2, r1 + ARM GAS /tmp/ccS0aCke.s page 18 + + + 515 0056 DA63 str r2, [r3, #60] + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 516 .loc 1 442 7 view .LVU85 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 517 .loc 1 417 21 is_stmt 0 view .LVU86 + 518 0058 0020 movs r0, #0 + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 519 .loc 1 442 7 view .LVU87 + 520 005a E3E7 b .L33 + 521 .L34: + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRF, GPIONumber); + 522 .loc 1 451 7 is_stmt 1 view .LVU88 + 523 005c 064B ldr r3, .L41+4 + 524 005e 9A6C ldr r2, [r3, #72] + 525 0060 0A43 orrs r2, r1 + 526 0062 9A64 str r2, [r3, #72] + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 527 .loc 1 452 7 view .LVU89 + 528 0064 DA6C ldr r2, [r3, #76] + 529 0066 8A43 bics r2, r1 + 530 0068 DA64 str r2, [r3, #76] + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 531 .loc 1 453 7 view .LVU90 + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 532 .loc 1 417 21 is_stmt 0 view .LVU91 + 533 006a 0020 movs r0, #0 + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 534 .loc 1 453 7 view .LVU92 + 535 006c DAE7 b .L33 + 536 .L40: + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 537 .loc 1 422 3 view .LVU93 + 538 006e 0120 movs r0, #1 + 539 0070 D8E7 b .L33 + 540 .L42: + 541 0072 C046 .align 2 + 542 .L41: + 543 0074 00000000 .word .L35 + 544 0078 00700040 .word 1073770496 + 545 007c FFBFFFFF .word -16385 + 546 0080 FFDFFFFF .word -8193 + 547 .cfi_endproc + 548 .LFE306: + 550 .section .text.HAL_PWREx_DisableGPIOPullUp,"ax",%progbits + 551 .align 1 + 552 .global HAL_PWREx_DisableGPIOPullUp + 553 .syntax unified + 554 .code 16 + 555 .thumb_func + 556 .fpu softvfp + 558 HAL_PWREx_DisableGPIOPullUp: + 559 .LVL11: + 560 .LFB307: + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + ARM GAS /tmp/ccS0aCke.s page 19 + + + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * in pull-up state in Standby and Shutdown modes. + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * to select the GPIO peripheral. + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIONumber Specify the I/O pins numbers. + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * I/O pins are available) or the logical OR of several of them to reset + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * several bits for a given port in a single API call. + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 561 .loc 1 478 1 is_stmt 1 view -0 + 562 .cfi_startproc + 563 @ args = 0, pretend = 0, frame = 0 + 564 @ frame_needed = 0, uses_anonymous_args = 0 + 565 @ link register save eliminated. + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 566 .loc 1 479 3 view .LVU95 + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO(GPIO)); + 567 .loc 1 481 3 view .LVU96 + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + 568 .loc 1 482 3 view .LVU97 + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** switch (GPIO) + 569 .loc 1 484 3 view .LVU98 + 570 0000 0528 cmp r0, #5 + 571 0002 23D8 bhi .L51 + 572 0004 8000 lsls r0, r0, #2 + 573 .LVL12: + 574 .loc 1 484 3 is_stmt 0 view .LVU99 + 575 0006 124B ldr r3, .L52 + 576 0008 1B58 ldr r3, [r3, r0] + 577 000a 9F46 mov pc, r3 + 578 .section .rodata.HAL_PWREx_DisableGPIOPullUp,"a",%progbits + 579 .align 2 + 580 .L46: + 581 0000 0C000000 .word .L50 + 582 0004 1C000000 .word .L49 + 583 0008 28000000 .word .L48 + 584 000c 34000000 .word .L47 + 585 0010 4C000000 .word .L51 + 586 0014 40000000 .word .L45 + 587 .section .text.HAL_PWREx_DisableGPIOPullUp + 588 .L50: + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_A: + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + 589 .loc 1 487 7 is_stmt 1 view .LVU100 + 590 000c 1148 ldr r0, .L52+4 + 591 000e 036A ldr r3, [r0, #32] + 592 0010 114A ldr r2, .L52+8 + 593 0012 1140 ands r1, r2 + 594 .LVL13: + 595 .loc 1 487 7 is_stmt 0 view .LVU101 + ARM GAS /tmp/ccS0aCke.s page 20 + + + 596 0014 8B43 bics r3, r1 + 597 0016 0362 str r3, [r0, #32] + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 598 .loc 1 488 7 is_stmt 1 view .LVU102 + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 599 .loc 1 479 21 is_stmt 0 view .LVU103 + 600 0018 0020 movs r0, #0 + 601 .L44: + 602 .LVL14: + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_B: + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRB, GPIONumber); + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_C: + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRC, GPIONumber); + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_D: + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRD, GPIONumber); + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(GPI0E) + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_E: + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRE, GPIONumber); + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* GPI0E */ + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_F: + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRF, GPIONumber); + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** default: + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** status = HAL_ERROR; + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return status; + 603 .loc 1 516 3 is_stmt 1 view .LVU104 + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 604 .loc 1 517 1 is_stmt 0 view .LVU105 + 605 @ sp needed + 606 001a 7047 bx lr + 607 .LVL15: + 608 .L49: + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 609 .loc 1 491 7 is_stmt 1 view .LVU106 + 610 001c 0D4A ldr r2, .L52+4 + 611 001e 936A ldr r3, [r2, #40] + 612 0020 8B43 bics r3, r1 + 613 0022 9362 str r3, [r2, #40] + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 614 .loc 1 492 7 view .LVU107 + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 615 .loc 1 479 21 is_stmt 0 view .LVU108 + 616 0024 0020 movs r0, #0 + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 617 .loc 1 492 7 view .LVU109 + ARM GAS /tmp/ccS0aCke.s page 21 + + + 618 0026 F8E7 b .L44 + 619 .L48: + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 620 .loc 1 495 7 is_stmt 1 view .LVU110 + 621 0028 0A4A ldr r2, .L52+4 + 622 002a 136B ldr r3, [r2, #48] + 623 002c 8B43 bics r3, r1 + 624 002e 1363 str r3, [r2, #48] + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 625 .loc 1 496 7 view .LVU111 + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 626 .loc 1 479 21 is_stmt 0 view .LVU112 + 627 0030 0020 movs r0, #0 + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 628 .loc 1 496 7 view .LVU113 + 629 0032 F2E7 b .L44 + 630 .L47: + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 631 .loc 1 499 7 is_stmt 1 view .LVU114 + 632 0034 074A ldr r2, .L52+4 + 633 0036 936B ldr r3, [r2, #56] + 634 0038 8B43 bics r3, r1 + 635 003a 9363 str r3, [r2, #56] + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 636 .loc 1 500 7 view .LVU115 + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 637 .loc 1 479 21 is_stmt 0 view .LVU116 + 638 003c 0020 movs r0, #0 + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 639 .loc 1 500 7 view .LVU117 + 640 003e ECE7 b .L44 + 641 .L45: + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 642 .loc 1 508 7 is_stmt 1 view .LVU118 + 643 0040 044A ldr r2, .L52+4 + 644 0042 936C ldr r3, [r2, #72] + 645 0044 8B43 bics r3, r1 + 646 0046 9364 str r3, [r2, #72] + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 647 .loc 1 509 7 view .LVU119 + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 648 .loc 1 479 21 is_stmt 0 view .LVU120 + 649 0048 0020 movs r0, #0 + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 650 .loc 1 509 7 view .LVU121 + 651 004a E6E7 b .L44 + 652 .L51: + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 653 .loc 1 484 3 view .LVU122 + 654 004c 0120 movs r0, #1 + 655 004e E4E7 b .L44 + 656 .L53: + 657 .align 2 + 658 .L52: + 659 0050 00000000 .word .L46 + 660 0054 00700040 .word 1073770496 + 661 0058 FFBFFFFF .word -16385 + ARM GAS /tmp/ccS0aCke.s page 22 + + + 662 .cfi_endproc + 663 .LFE307: + 665 .section .text.HAL_PWREx_EnableGPIOPullDown,"ax",%progbits + 666 .align 1 + 667 .global HAL_PWREx_EnableGPIOPullDown + 668 .syntax unified + 669 .code 16 + 670 .thumb_func + 671 .fpu softvfp + 673 HAL_PWREx_EnableGPIOPullDown: + 674 .LVL16: + 675 .LFB308: + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * pull-down state in Standby and Shutdown modes. + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This state is effective in Standby and Shutdown modes only if APC bit + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note The configuration is lost when exiting the Shutdown mode due to the + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * power-on reset, maintained when exiting the Standby mode. + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * to select the GPIO peripheral. + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIONumber Specify the I/O pins numbers. + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * I/O pins are available) or the logical OR of several of them to set + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * several bits for a given port in a single API call. + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 676 .loc 1 540 1 is_stmt 1 view -0 + 677 .cfi_startproc + 678 @ args = 0, pretend = 0, frame = 0 + 679 @ frame_needed = 0, uses_anonymous_args = 0 + 680 @ link register save eliminated. + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 681 .loc 1 541 3 view .LVU124 + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO(GPIO)); + 682 .loc 1 543 3 view .LVU125 + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + 683 .loc 1 544 3 view .LVU126 + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** switch (GPIO) + 684 .loc 1 546 3 view .LVU127 + 685 0000 0528 cmp r0, #5 + 686 0002 34D8 bhi .L62 + 687 0004 8000 lsls r0, r0, #2 + 688 .LVL17: + 689 .loc 1 546 3 is_stmt 0 view .LVU128 + 690 0006 1B4B ldr r3, .L63 + 691 0008 1B58 ldr r3, [r3, r0] + ARM GAS /tmp/ccS0aCke.s page 23 + + + 692 000a 9F46 mov pc, r3 + 693 .section .rodata.HAL_PWREx_EnableGPIOPullDown,"a",%progbits + 694 .align 2 + 695 .L57: + 696 0000 0C000000 .word .L61 + 697 0004 26000000 .word .L60 + 698 0008 38000000 .word .L59 + 699 000c 4A000000 .word .L58 + 700 0010 6E000000 .word .L62 + 701 0014 5C000000 .word .L56 + 702 .section .text.HAL_PWREx_EnableGPIOPullDown + 703 .L61: + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_A: + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + 704 .loc 1 549 7 is_stmt 1 view .LVU129 + 705 000c 1A4B ldr r3, .L63+4 + 706 000e 5A6A ldr r2, [r3, #36] + 707 0010 1A48 ldr r0, .L63+8 + 708 0012 0840 ands r0, r1 + 709 0014 0243 orrs r2, r0 + 710 0016 5A62 str r2, [r3, #36] + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + 711 .loc 1 550 7 view .LVU130 + 712 0018 1A6A ldr r2, [r3, #32] + 713 001a 1948 ldr r0, .L63+12 + 714 001c 0140 ands r1, r0 + 715 .LVL18: + 716 .loc 1 550 7 is_stmt 0 view .LVU131 + 717 001e 8A43 bics r2, r1 + 718 0020 1A62 str r2, [r3, #32] + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 719 .loc 1 551 7 is_stmt 1 view .LVU132 + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 720 .loc 1 541 21 is_stmt 0 view .LVU133 + 721 0022 0020 movs r0, #0 + 722 .L55: + 723 .LVL19: + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_B: + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRB, GPIONumber); + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRB, GPIONumber); + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_C: + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRC, GPIONumber); + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRC, GPIONumber); + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_D: + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRD, GPIONumber); + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRD, GPIONumber); + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(GPIOE) + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_E: + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRE, GPIONumber); + ARM GAS /tmp/ccS0aCke.s page 24 + + + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRE, GPIONumber); + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* GPI0E */ + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_F: + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->PDCRF, GPIONumber); + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRF, GPIONumber); + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** default: + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** status = HAL_ERROR; + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return status; + 724 .loc 1 584 3 is_stmt 1 view .LVU134 + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 725 .loc 1 585 1 is_stmt 0 view .LVU135 + 726 @ sp needed + 727 0024 7047 bx lr + 728 .LVL20: + 729 .L60: + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRB, GPIONumber); + 730 .loc 1 554 7 is_stmt 1 view .LVU136 + 731 0026 144B ldr r3, .L63+4 + 732 0028 DA6A ldr r2, [r3, #44] + 733 002a 0A43 orrs r2, r1 + 734 002c DA62 str r2, [r3, #44] + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 735 .loc 1 555 7 view .LVU137 + 736 002e 9A6A ldr r2, [r3, #40] + 737 0030 8A43 bics r2, r1 + 738 0032 9A62 str r2, [r3, #40] + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 739 .loc 1 556 7 view .LVU138 + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 740 .loc 1 541 21 is_stmt 0 view .LVU139 + 741 0034 0020 movs r0, #0 + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 742 .loc 1 556 7 view .LVU140 + 743 0036 F5E7 b .L55 + 744 .L59: + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRC, GPIONumber); + 745 .loc 1 559 7 is_stmt 1 view .LVU141 + 746 0038 0F4B ldr r3, .L63+4 + 747 003a 5A6B ldr r2, [r3, #52] + 748 003c 0A43 orrs r2, r1 + 749 003e 5A63 str r2, [r3, #52] + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 750 .loc 1 560 7 view .LVU142 + 751 0040 1A6B ldr r2, [r3, #48] + 752 0042 8A43 bics r2, r1 + 753 0044 1A63 str r2, [r3, #48] + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 754 .loc 1 561 7 view .LVU143 + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 755 .loc 1 541 21 is_stmt 0 view .LVU144 + 756 0046 0020 movs r0, #0 + ARM GAS /tmp/ccS0aCke.s page 25 + + + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 757 .loc 1 561 7 view .LVU145 + 758 0048 ECE7 b .L55 + 759 .L58: + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRD, GPIONumber); + 760 .loc 1 564 7 is_stmt 1 view .LVU146 + 761 004a 0B4B ldr r3, .L63+4 + 762 004c DA6B ldr r2, [r3, #60] + 763 004e 0A43 orrs r2, r1 + 764 0050 DA63 str r2, [r3, #60] + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 765 .loc 1 565 7 view .LVU147 + 766 0052 9A6B ldr r2, [r3, #56] + 767 0054 8A43 bics r2, r1 + 768 0056 9A63 str r2, [r3, #56] + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 769 .loc 1 566 7 view .LVU148 + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 770 .loc 1 541 21 is_stmt 0 view .LVU149 + 771 0058 0020 movs r0, #0 + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 772 .loc 1 566 7 view .LVU150 + 773 005a E3E7 b .L55 + 774 .L56: + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PUCRF, GPIONumber); + 775 .loc 1 575 7 is_stmt 1 view .LVU151 + 776 005c 064B ldr r3, .L63+4 + 777 005e DA6C ldr r2, [r3, #76] + 778 0060 0A43 orrs r2, r1 + 779 0062 DA64 str r2, [r3, #76] + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 780 .loc 1 576 7 view .LVU152 + 781 0064 9A6C ldr r2, [r3, #72] + 782 0066 8A43 bics r2, r1 + 783 0068 9A64 str r2, [r3, #72] + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 784 .loc 1 577 7 view .LVU153 + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 785 .loc 1 541 21 is_stmt 0 view .LVU154 + 786 006a 0020 movs r0, #0 + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 787 .loc 1 577 7 view .LVU155 + 788 006c DAE7 b .L55 + 789 .L62: + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 790 .loc 1 546 3 view .LVU156 + 791 006e 0120 movs r0, #1 + 792 0070 D8E7 b .L55 + 793 .L64: + 794 0072 C046 .align 2 + 795 .L63: + 796 0074 00000000 .word .L57 + 797 0078 00700040 .word 1073770496 + 798 007c FFDFFFFF .word -8193 + 799 0080 FFBFFFFF .word -16385 + 800 .cfi_endproc + 801 .LFE308: + ARM GAS /tmp/ccS0aCke.s page 26 + + + 803 .section .text.HAL_PWREx_DisableGPIOPullDown,"ax",%progbits + 804 .align 1 + 805 .global HAL_PWREx_DisableGPIOPullDown + 806 .syntax unified + 807 .code 16 + 808 .thumb_func + 809 .fpu softvfp + 811 HAL_PWREx_DisableGPIOPullDown: + 812 .LVL21: + 813 .LFB309: + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * in pull-down state in Standby and Shutdown modes. + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * to select the GPIO peripheral. + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param GPIONumber Specify the I/O pins numbers. + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * I/O pins are available) or the logical OR of several of them to reset + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * several bits for a given port in a single API call. + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 814 .loc 1 602 1 is_stmt 1 view -0 + 815 .cfi_startproc + 816 @ args = 0, pretend = 0, frame = 0 + 817 @ frame_needed = 0, uses_anonymous_args = 0 + 818 @ link register save eliminated. + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 819 .loc 1 603 3 view .LVU158 + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO(GPIO)); + 820 .loc 1 605 3 view .LVU159 + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + 821 .loc 1 606 3 view .LVU160 + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** switch (GPIO) + 822 .loc 1 608 3 view .LVU161 + 823 0000 0528 cmp r0, #5 + 824 0002 23D8 bhi .L73 + 825 0004 8000 lsls r0, r0, #2 + 826 .LVL22: + 827 .loc 1 608 3 is_stmt 0 view .LVU162 + 828 0006 124B ldr r3, .L74 + 829 0008 1B58 ldr r3, [r3, r0] + 830 000a 9F46 mov pc, r3 + 831 .section .rodata.HAL_PWREx_DisableGPIOPullDown,"a",%progbits + 832 .align 2 + 833 .L68: + 834 0000 0C000000 .word .L72 + 835 0004 1C000000 .word .L71 + 836 0008 28000000 .word .L70 + 837 000c 34000000 .word .L69 + ARM GAS /tmp/ccS0aCke.s page 27 + + + 838 0010 4C000000 .word .L73 + 839 0014 40000000 .word .L67 + 840 .section .text.HAL_PWREx_DisableGPIOPullDown + 841 .L72: + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_A: + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + 842 .loc 1 611 7 is_stmt 1 view .LVU163 + 843 000c 1148 ldr r0, .L74+4 + 844 000e 436A ldr r3, [r0, #36] + 845 0010 114A ldr r2, .L74+8 + 846 0012 1140 ands r1, r2 + 847 .LVL23: + 848 .loc 1 611 7 is_stmt 0 view .LVU164 + 849 0014 8B43 bics r3, r1 + 850 0016 4362 str r3, [r0, #36] + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 851 .loc 1 612 7 is_stmt 1 view .LVU165 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 852 .loc 1 603 21 is_stmt 0 view .LVU166 + 853 0018 0020 movs r0, #0 + 854 .L66: + 855 .LVL24: + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_B: + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRB, GPIONumber); + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_C: + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRC, GPIONumber); + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_D: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRD, GPIONumber); + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(GPIOE) + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_E: + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRE, GPIONumber); + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* GPI0E */ + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** case PWR_GPIO_F: + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->PDCRF, GPIONumber); + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** default: + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** status = HAL_ERROR; + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return status; + 856 .loc 1 640 3 is_stmt 1 view .LVU167 + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 857 .loc 1 641 1 is_stmt 0 view .LVU168 + 858 @ sp needed + 859 001a 7047 bx lr + 860 .LVL25: + ARM GAS /tmp/ccS0aCke.s page 28 + + + 861 .L71: + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 862 .loc 1 615 7 is_stmt 1 view .LVU169 + 863 001c 0D4A ldr r2, .L74+4 + 864 001e D36A ldr r3, [r2, #44] + 865 0020 8B43 bics r3, r1 + 866 0022 D362 str r3, [r2, #44] + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 867 .loc 1 616 7 view .LVU170 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 868 .loc 1 603 21 is_stmt 0 view .LVU171 + 869 0024 0020 movs r0, #0 + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 870 .loc 1 616 7 view .LVU172 + 871 0026 F8E7 b .L66 + 872 .L70: + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 873 .loc 1 619 7 is_stmt 1 view .LVU173 + 874 0028 0A4A ldr r2, .L74+4 + 875 002a 536B ldr r3, [r2, #52] + 876 002c 8B43 bics r3, r1 + 877 002e 5363 str r3, [r2, #52] + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 878 .loc 1 620 7 view .LVU174 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 879 .loc 1 603 21 is_stmt 0 view .LVU175 + 880 0030 0020 movs r0, #0 + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 881 .loc 1 620 7 view .LVU176 + 882 0032 F2E7 b .L66 + 883 .L69: + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 884 .loc 1 623 7 is_stmt 1 view .LVU177 + 885 0034 074A ldr r2, .L74+4 + 886 0036 D36B ldr r3, [r2, #60] + 887 0038 8B43 bics r3, r1 + 888 003a D363 str r3, [r2, #60] + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 889 .loc 1 624 7 view .LVU178 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 890 .loc 1 603 21 is_stmt 0 view .LVU179 + 891 003c 0020 movs r0, #0 + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 892 .loc 1 624 7 view .LVU180 + 893 003e ECE7 b .L66 + 894 .L67: + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** break; + 895 .loc 1 632 7 is_stmt 1 view .LVU181 + 896 0040 044A ldr r2, .L74+4 + 897 0042 D36C ldr r3, [r2, #76] + 898 0044 8B43 bics r3, r1 + 899 0046 D364 str r3, [r2, #76] + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 900 .loc 1 633 7 view .LVU182 + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 901 .loc 1 603 21 is_stmt 0 view .LVU183 + 902 0048 0020 movs r0, #0 + ARM GAS /tmp/ccS0aCke.s page 29 + + + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 903 .loc 1 633 7 view .LVU184 + 904 004a E6E7 b .L66 + 905 .L73: + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 906 .loc 1 608 3 view .LVU185 + 907 004c 0120 movs r0, #1 + 908 004e E4E7 b .L66 + 909 .L75: + 910 .align 2 + 911 .L74: + 912 0050 00000000 .word .L68 + 913 0054 00700040 .word 1073770496 + 914 0058 FFDFFFFF .word -8193 + 915 .cfi_endproc + 916 .LFE309: + 918 .section .text.HAL_PWREx_EnablePullUpPullDownConfig,"ax",%progbits + 919 .align 1 + 920 .global HAL_PWREx_EnablePullUpPullDownConfig + 921 .syntax unified + 922 .code 16 + 923 .thumb_func + 924 .fpu softvfp + 926 HAL_PWREx_EnablePullUpPullDownConfig: + 927 .LFB310: + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable pull-up and pull-down configuration. + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * is no conflict when setting PUy or PDy bit. + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnablePullUpPullDownConfig(void) + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 928 .loc 1 655 1 is_stmt 1 view -0 + 929 .cfi_startproc + 930 @ args = 0, pretend = 0, frame = 0 + 931 @ frame_needed = 0, uses_anonymous_args = 0 + 932 @ link register save eliminated. + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR3, PWR_CR3_APC); + 933 .loc 1 656 3 view .LVU187 + 934 0000 034A ldr r2, .L77 + 935 0002 9168 ldr r1, [r2, #8] + 936 0004 8023 movs r3, #128 + 937 0006 DB00 lsls r3, r3, #3 + 938 0008 0B43 orrs r3, r1 + 939 000a 9360 str r3, [r2, #8] + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 940 .loc 1 657 1 is_stmt 0 view .LVU188 + 941 @ sp needed + 942 000c 7047 bx lr + 943 .L78: + ARM GAS /tmp/ccS0aCke.s page 30 + + + 944 000e C046 .align 2 + 945 .L77: + 946 0010 00700040 .word 1073770496 + 947 .cfi_endproc + 948 .LFE310: + 950 .section .text.HAL_PWREx_DisablePullUpPullDownConfig,"ax",%progbits + 951 .align 1 + 952 .global HAL_PWREx_DisablePullUpPullDownConfig + 953 .syntax unified + 954 .code 16 + 955 .thumb_func + 956 .fpu softvfp + 958 HAL_PWREx_DisablePullUpPullDownConfig: + 959 .LFB311: + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable pull-up and pull-down configuration. + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisablePullUpPullDownConfig(void) + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 960 .loc 1 666 1 is_stmt 1 view -0 + 961 .cfi_startproc + 962 @ args = 0, pretend = 0, frame = 0 + 963 @ frame_needed = 0, uses_anonymous_args = 0 + 964 @ link register save eliminated. + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR3, PWR_CR3_APC); + 965 .loc 1 667 3 view .LVU190 + 966 0000 024A ldr r2, .L80 + 967 0002 9368 ldr r3, [r2, #8] + 968 0004 0249 ldr r1, .L80+4 + 969 0006 0B40 ands r3, r1 + 970 0008 9360 str r3, [r2, #8] + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 971 .loc 1 668 1 is_stmt 0 view .LVU191 + 972 @ sp needed + 973 000a 7047 bx lr + 974 .L81: + 975 .align 2 + 976 .L80: + 977 000c 00700040 .word 1073770496 + 978 0010 FFFBFFFF .word -1025 + 979 .cfi_endproc + 980 .LFE311: + 982 .section .text.HAL_PWREx_EnableSRAMRetention,"ax",%progbits + 983 .align 1 + 984 .global HAL_PWREx_EnableSRAMRetention + 985 .syntax unified + 986 .code 16 + 987 .thumb_func + 988 .fpu softvfp + 990 HAL_PWREx_EnableSRAMRetention: + 991 .LFB312: + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_CR3_RRS) + ARM GAS /tmp/ccS0aCke.s page 31 + + + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable SRAM content retention in Standby mode. + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When RRS bit is set, SRAM is powered by the low-power regulator in + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * Standby mode and its content is kept. + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableSRAMRetention(void) + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 992 .loc 1 678 1 is_stmt 1 view -0 + 993 .cfi_startproc + 994 @ args = 0, pretend = 0, frame = 0 + 995 @ frame_needed = 0, uses_anonymous_args = 0 + 996 @ link register save eliminated. + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR3, PWR_CR3_RRS); + 997 .loc 1 679 3 view .LVU193 + 998 0000 034A ldr r2, .L83 + 999 0002 9168 ldr r1, [r2, #8] + 1000 0004 8023 movs r3, #128 + 1001 0006 5B00 lsls r3, r3, #1 + 1002 0008 0B43 orrs r3, r1 + 1003 000a 9360 str r3, [r2, #8] + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1004 .loc 1 680 1 is_stmt 0 view .LVU194 + 1005 @ sp needed + 1006 000c 7047 bx lr + 1007 .L84: + 1008 000e C046 .align 2 + 1009 .L83: + 1010 0010 00700040 .word 1073770496 + 1011 .cfi_endproc + 1012 .LFE312: + 1014 .section .text.HAL_PWREx_DisableSRAMRetention,"ax",%progbits + 1015 .align 1 + 1016 .global HAL_PWREx_DisableSRAMRetention + 1017 .syntax unified + 1018 .code 16 + 1019 .thumb_func + 1020 .fpu softvfp + 1022 HAL_PWREx_DisableSRAMRetention: + 1023 .LFB313: + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable SRAM content retention in Standby mode. + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When RRS bit is reset, SRAM is powered off in Standby mode + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * and its content is lost. + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableSRAMRetention(void) + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1024 .loc 1 690 1 is_stmt 1 view -0 + 1025 .cfi_startproc + 1026 @ args = 0, pretend = 0, frame = 0 + 1027 @ frame_needed = 0, uses_anonymous_args = 0 + 1028 @ link register save eliminated. + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); + 1029 .loc 1 691 3 view .LVU196 + ARM GAS /tmp/ccS0aCke.s page 32 + + + 1030 0000 024A ldr r2, .L86 + 1031 0002 9368 ldr r3, [r2, #8] + 1032 0004 0249 ldr r1, .L86+4 + 1033 0006 0B40 ands r3, r1 + 1034 0008 9360 str r3, [r2, #8] + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1035 .loc 1 692 1 is_stmt 0 view .LVU197 + 1036 @ sp needed + 1037 000a 7047 bx lr + 1038 .L87: + 1039 .align 2 + 1040 .L86: + 1041 000c 00700040 .word 1073770496 + 1042 0010 FFFEFFFF .word -257 + 1043 .cfi_endproc + 1044 .LFE313: + 1046 .section .text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits + 1047 .align 1 + 1048 .global HAL_PWREx_EnableFlashPowerDown + 1049 .syntax unified + 1050 .code 16 + 1051 .thumb_func + 1052 .fpu softvfp + 1054 HAL_PWREx_EnableFlashPowerDown: + 1055 .LVL26: + 1056 .LFB314: + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_CR3_RRS */ + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enable Flash Power Down. + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This API allows to enable flash power down capabilities in low power + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * run, low power sleep and stop modes. + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param PowerMode this can be a combination of following values: + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_LPRUN + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_LPSLEEP + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_STOP + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1057 .loc 1 706 1 is_stmt 1 view -0 + 1058 .cfi_startproc + 1059 @ args = 0, pretend = 0, frame = 0 + 1060 @ frame_needed = 0, uses_anonymous_args = 0 + 1061 @ link register save eliminated. + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + 1062 .loc 1 707 3 view .LVU199 + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR->CR1 |= PowerMode; + 1063 .loc 1 709 3 view .LVU200 + 1064 .loc 1 709 12 is_stmt 0 view .LVU201 + 1065 0000 024A ldr r2, .L89 + 1066 0002 1368 ldr r3, [r2] + 1067 0004 0343 orrs r3, r0 + 1068 0006 1360 str r3, [r2] + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1069 .loc 1 710 1 view .LVU202 + ARM GAS /tmp/ccS0aCke.s page 33 + + + 1070 @ sp needed + 1071 0008 7047 bx lr + 1072 .L90: + 1073 000a C046 .align 2 + 1074 .L89: + 1075 000c 00700040 .word 1073770496 + 1076 .cfi_endproc + 1077 .LFE314: + 1079 .section .text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits + 1080 .align 1 + 1081 .global HAL_PWREx_DisableFlashPowerDown + 1082 .syntax unified + 1083 .code 16 + 1084 .thumb_func + 1085 .fpu softvfp + 1087 HAL_PWREx_DisableFlashPowerDown: + 1088 .LVL27: + 1089 .LFB315: + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Disable Flash Power Down. + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This API allows to disable flash power down capabilities in low power + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * run, low power sleep and stop modes. + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param PowerMode this can be a combination of following values: + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_LPRUN + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_LPSLEEP + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_FLASHPD_STOP + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode) + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1090 .loc 1 724 1 is_stmt 1 view -0 + 1091 .cfi_startproc + 1092 @ args = 0, pretend = 0, frame = 0 + 1093 @ frame_needed = 0, uses_anonymous_args = 0 + 1094 @ link register save eliminated. + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + 1095 .loc 1 725 3 view .LVU204 + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** PWR->CR1 &= ~PowerMode; + 1096 .loc 1 727 3 view .LVU205 + 1097 .loc 1 727 12 is_stmt 0 view .LVU206 + 1098 0000 024A ldr r2, .L92 + 1099 0002 1368 ldr r3, [r2] + 1100 0004 8343 bics r3, r0 + 1101 0006 1360 str r3, [r2] + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1102 .loc 1 728 1 view .LVU207 + 1103 @ sp needed + 1104 0008 7047 bx lr + 1105 .L93: + 1106 000a C046 .align 2 + 1107 .L92: + 1108 000c 00700040 .word 1073770496 + 1109 .cfi_endproc + 1110 .LFE315: + ARM GAS /tmp/ccS0aCke.s page 34 + + + 1112 .section .text.HAL_PWREx_GetVoltageRange,"ax",%progbits + 1113 .align 1 + 1114 .global HAL_PWREx_GetVoltageRange + 1115 .syntax unified + 1116 .code 16 + 1117 .thumb_func + 1118 .fpu softvfp + 1120 HAL_PWREx_GetVoltageRange: + 1121 .LFB316: + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Return Voltage Scaling Range. + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval VOS bit field: + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange(void) + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1122 .loc 1 738 1 is_stmt 1 view -0 + 1123 .cfi_startproc + 1124 @ args = 0, pretend = 0, frame = 0 + 1125 @ frame_needed = 0, uses_anonymous_args = 0 + 1126 @ link register save eliminated. + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return (PWR->CR1 & PWR_CR1_VOS); + 1127 .loc 1 739 3 view .LVU209 + 1128 .loc 1 739 14 is_stmt 0 view .LVU210 + 1129 0000 024B ldr r3, .L95 + 1130 0002 1868 ldr r0, [r3] + 1131 .loc 1 739 20 view .LVU211 + 1132 0004 C023 movs r3, #192 + 1133 0006 DB00 lsls r3, r3, #3 + 1134 0008 1840 ands r0, r3 + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1135 .loc 1 740 1 view .LVU212 + 1136 @ sp needed + 1137 000a 7047 bx lr + 1138 .L96: + 1139 .align 2 + 1140 .L95: + 1141 000c 00700040 .word 1073770496 + 1142 .cfi_endproc + 1143 .LFE316: + 1145 .global __aeabi_uidiv + 1146 .section .text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits + 1147 .align 1 + 1148 .global HAL_PWREx_ControlVoltageScaling + 1149 .syntax unified + 1150 .code 16 + 1151 .thumb_func + 1152 .fpu softvfp + 1154 HAL_PWREx_ControlVoltageScaling: + 1155 .LVL28: + 1156 .LFB317: + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccS0aCke.s page 35 + + + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Configure the main regulator output voltage. + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @param VoltageScaling specifies the regulator output voltage to achieve + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * a tradeoff between performance and power consumption. + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * This parameter can be one of the following values: + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * typical output voltage at 1.2 V, + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * system frequency up to 64 MHz. + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * typical output voltage at 1.0 V, + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * system frequency up to 16 MHz. + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * When moving from Range 2 to Range 1, the system frequency can be increased to + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * cleared before returning the status. If the flag is not cleared within + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * 6 microseconds, HAL_TIMEOUT status is reported. + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1157 .loc 1 764 1 is_stmt 1 view -0 + 1158 .cfi_startproc + 1159 @ args = 0, pretend = 0, frame = 0 + 1160 @ frame_needed = 0, uses_anonymous_args = 0 + 1161 .loc 1 764 1 is_stmt 0 view .LVU214 + 1162 0000 10B5 push {r4, lr} + 1163 .LCFI1: + 1164 .cfi_def_cfa_offset 8 + 1165 .cfi_offset 4, -8 + 1166 .cfi_offset 14, -4 + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** uint32_t wait_loop_index; + 1167 .loc 1 765 3 is_stmt 1 view .LVU215 + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + 1168 .loc 1 767 3 view .LVU216 + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Modify voltage scaling range */ + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); + 1169 .loc 1 770 3 view .LVU217 + 1170 0002 104A ldr r2, .L105 + 1171 0004 1368 ldr r3, [r2] + 1172 0006 1049 ldr r1, .L105+4 + 1173 0008 0B40 ands r3, r1 + 1174 000a 0343 orrs r3, r0 + 1175 000c 1360 str r3, [r2] + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + 1176 .loc 1 773 3 view .LVU218 + 1177 .loc 1 773 6 is_stmt 0 view .LVU219 + 1178 000e 8023 movs r3, #128 + 1179 0010 9B00 lsls r3, r3, #2 + 1180 0012 9842 cmp r0, r3 + 1181 0014 01D0 beq .L103 + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Set timeout value */ + ARM GAS /tmp/ccS0aCke.s page 36 + + + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Wait until VOSF is reset */ + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (wait_loop_index != 0U) + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** wait_loop_index--; + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** else + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return HAL_OK; + 1182 .loc 1 792 10 view .LVU220 + 1183 0016 0020 movs r0, #0 + 1184 .LVL29: + 1185 .L98: + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1186 .loc 1 793 1 view .LVU221 + 1187 @ sp needed + 1188 0018 10BD pop {r4, pc} + 1189 .LVL30: + 1190 .L103: + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1191 .loc 1 776 5 is_stmt 1 view .LVU222 + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1192 .loc 1 776 53 is_stmt 0 view .LVU223 + 1193 001a 0C4B ldr r3, .L105+8 + 1194 001c 1B68 ldr r3, [r3] + 1195 001e 5800 lsls r0, r3, #1 + 1196 .LVL31: + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1197 .loc 1 776 53 view .LVU224 + 1198 0020 C018 adds r0, r0, r3 + 1199 0022 4000 lsls r0, r0, #1 + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1200 .loc 1 776 72 view .LVU225 + 1201 0024 0A49 ldr r1, .L105+12 + 1202 0026 FFF7FEFF bl __aeabi_uidiv + 1203 .LVL32: + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1204 .loc 1 776 21 view .LVU226 + 1205 002a 0130 adds r0, r0, #1 + 1206 .LVL33: + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1207 .loc 1 779 5 is_stmt 1 view .LVU227 + 1208 .L99: + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1209 .loc 1 779 11 view .LVU228 + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1210 .loc 1 779 12 is_stmt 0 view .LVU229 + 1211 002c 054B ldr r3, .L105 + 1212 002e 5B69 ldr r3, [r3, #20] + ARM GAS /tmp/ccS0aCke.s page 37 + + + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1213 .loc 1 779 11 view .LVU230 + 1214 0030 5B05 lsls r3, r3, #21 + 1215 0032 03D5 bpl .L104 + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1216 .loc 1 781 7 is_stmt 1 view .LVU231 + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1217 .loc 1 781 10 is_stmt 0 view .LVU232 + 1218 0034 0028 cmp r0, #0 + 1219 0036 03D0 beq .L102 + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1220 .loc 1 783 9 is_stmt 1 view .LVU233 + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1221 .loc 1 783 24 is_stmt 0 view .LVU234 + 1222 0038 0138 subs r0, r0, #1 + 1223 .LVL34: + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1224 .loc 1 783 24 view .LVU235 + 1225 003a F7E7 b .L99 + 1226 .L104: + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1227 .loc 1 792 10 view .LVU236 + 1228 003c 0020 movs r0, #0 + 1229 .LVL35: + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1230 .loc 1 792 10 view .LVU237 + 1231 003e EBE7 b .L98 + 1232 .LVL36: + 1233 .L102: + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1234 .loc 1 787 16 view .LVU238 + 1235 0040 0320 movs r0, #3 + 1236 .LVL37: + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1237 .loc 1 787 16 view .LVU239 + 1238 0042 E9E7 b .L98 + 1239 .L106: + 1240 .align 2 + 1241 .L105: + 1242 0044 00700040 .word 1073770496 + 1243 0048 FFF9FFFF .word -1537 + 1244 004c 00000000 .word SystemCoreClock + 1245 0050 40420F00 .word 1000000 + 1246 .cfi_endproc + 1247 .LFE317: + 1249 .section .text.HAL_PWREx_EnableLowPowerRunMode,"ax",%progbits + 1250 .align 1 + 1251 .global HAL_PWREx_EnableLowPowerRunMode + 1252 .syntax unified + 1253 .code 16 + 1254 .thumb_func + 1255 .fpu softvfp + 1257 HAL_PWREx_EnableLowPowerRunMode: + 1258 .LFB318: + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccS0aCke.s page 38 + + + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enter Low-power Run mode + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note System clock frequency has to be decreased below 2 MHz before entering + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * low power run mode + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnableLowPowerRunMode(void) + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1259 .loc 1 805 1 is_stmt 1 view -0 + 1260 .cfi_startproc + 1261 @ args = 0, pretend = 0, frame = 0 + 1262 @ frame_needed = 0, uses_anonymous_args = 0 + 1263 @ link register save eliminated. + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Set Regulator parameter */ + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(PWR->CR1, PWR_CR1_LPR); + 1264 .loc 1 807 3 view .LVU241 + 1265 0000 034A ldr r2, .L108 + 1266 0002 1168 ldr r1, [r2] + 1267 0004 8023 movs r3, #128 + 1268 0006 DB01 lsls r3, r3, #7 + 1269 0008 0B43 orrs r3, r1 + 1270 000a 1360 str r3, [r2] + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1271 .loc 1 808 1 is_stmt 0 view .LVU242 + 1272 @ sp needed + 1273 000c 7047 bx lr + 1274 .L109: + 1275 000e C046 .align 2 + 1276 .L108: + 1277 0010 00700040 .word 1073770496 + 1278 .cfi_endproc + 1279 .LFE318: + 1281 .section .text.HAL_PWREx_DisableLowPowerRunMode,"ax",%progbits + 1282 .align 1 + 1283 .global HAL_PWREx_DisableLowPowerRunMode + 1284 .syntax unified + 1285 .code 16 + 1286 .thumb_func + 1287 .fpu softvfp + 1289 HAL_PWREx_DisableLowPowerRunMode: + 1290 .LFB319: + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Exit Low-power Run mode. + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * returns HAL_TIMEOUT status). The system clock frequency can then be + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * increased above 2 MHz. + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval HAL Status + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1291 .loc 1 820 1 is_stmt 1 view -0 + 1292 .cfi_startproc + 1293 @ args = 0, pretend = 0, frame = 0 + ARM GAS /tmp/ccS0aCke.s page 39 + + + 1294 @ frame_needed = 0, uses_anonymous_args = 0 + 1295 0000 10B5 push {r4, lr} + 1296 .LCFI2: + 1297 .cfi_def_cfa_offset 8 + 1298 .cfi_offset 4, -8 + 1299 .cfi_offset 14, -4 + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; + 1300 .loc 1 821 3 view .LVU244 + 1301 .loc 1 821 62 is_stmt 0 view .LVU245 + 1302 0002 0D4B ldr r3, .L117 + 1303 0004 1B68 ldr r3, [r3] + 1304 0006 5800 lsls r0, r3, #1 + 1305 0008 C018 adds r0, r0, r3 + 1306 000a 4000 lsls r0, r0, #1 + 1307 .loc 1 821 81 view .LVU246 + 1308 000c 0B49 ldr r1, .L117+4 + 1309 000e FFF7FEFF bl __aeabi_uidiv + 1310 .LVL38: + 1311 .loc 1 821 12 view .LVU247 + 1312 0012 0130 adds r0, r0, #1 + 1313 .LVL39: + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear LPR bit */ + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + 1314 .loc 1 824 3 is_stmt 1 view .LVU248 + 1315 0014 0A4A ldr r2, .L117+8 + 1316 0016 1368 ldr r3, [r2] + 1317 0018 0A49 ldr r1, .L117+12 + 1318 001a 0B40 ands r3, r1 + 1319 001c 1360 str r3, [r2] + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Wait until REGLPF is reset */ + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) + 1320 .loc 1 827 3 view .LVU249 + 1321 .loc 1 827 9 is_stmt 0 view .LVU250 + 1322 001e 00E0 b .L111 + 1323 .L116: + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (wait_loop_index != 0U) + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** wait_loop_index--; + 1324 .loc 1 831 7 is_stmt 1 view .LVU251 + 1325 .loc 1 831 22 is_stmt 0 view .LVU252 + 1326 0020 0138 subs r0, r0, #1 + 1327 .LVL40: + 1328 .L111: + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1329 .loc 1 827 9 is_stmt 1 view .LVU253 + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1330 .loc 1 827 10 is_stmt 0 view .LVU254 + 1331 0022 074B ldr r3, .L117+8 + 1332 0024 5B69 ldr r3, [r3, #20] + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1333 .loc 1 827 9 view .LVU255 + 1334 0026 9B05 lsls r3, r3, #22 + 1335 0028 03D5 bpl .L115 + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + ARM GAS /tmp/ccS0aCke.s page 40 + + + 1336 .loc 1 829 5 is_stmt 1 view .LVU256 + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1337 .loc 1 829 8 is_stmt 0 view .LVU257 + 1338 002a 0028 cmp r0, #0 + 1339 002c F8D1 bne .L116 + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** else + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return HAL_TIMEOUT; + 1340 .loc 1 835 14 view .LVU258 + 1341 002e 0320 movs r0, #3 + 1342 .LVL41: + 1343 .loc 1 835 14 view .LVU259 + 1344 0030 00E0 b .L112 + 1345 .LVL42: + 1346 .L115: + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** return HAL_OK; + 1347 .loc 1 839 10 view .LVU260 + 1348 0032 0020 movs r0, #0 + 1349 .LVL43: + 1350 .L112: + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1351 .loc 1 840 1 view .LVU261 + 1352 @ sp needed + 1353 0034 10BD pop {r4, pc} + 1354 .L118: + 1355 0036 C046 .align 2 + 1356 .L117: + 1357 0038 00000000 .word SystemCoreClock + 1358 003c 40420F00 .word 1000000 + 1359 0040 00700040 .word 1073770496 + 1360 0044 FFBFFFFF .word -16385 + 1361 .cfi_endproc + 1362 .LFE319: + 1364 .section .text.HAL_PWREx_EnterSHUTDOWNMode,"ax",%progbits + 1365 .align 1 + 1366 .global HAL_PWREx_EnterSHUTDOWNMode + 1367 .syntax unified + 1368 .code 16 + 1369 .thumb_func + 1370 .fpu softvfp + 1372 HAL_PWREx_EnterSHUTDOWNMode: + 1373 .LFB320: + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_SHDW_SUPPORT) + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief Enter Shutdown mode. + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * off. The voltage regulator is disabled and Vcore domain is powered off. + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * SRAM and registers contents are lost except for registers in the Backup domain. + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * The BOR is not available. + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note The I/Os can be configured either with a pull-up or pull-down or can + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * be kept in analog state. + ARM GAS /tmp/ccS0aCke.s page 41 + + + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * respectively enable Pull Up and PullDown state. + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * disable the same. These states are effective in Standby mode only if + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSHUTDOWNMode(void) + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1374 .loc 1 862 1 is_stmt 1 view -0 + 1375 .cfi_startproc + 1376 @ args = 0, pretend = 0, frame = 0 + 1377 @ frame_needed = 0, uses_anonymous_args = 0 + 1378 @ link register save eliminated. + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Set Shutdown mode */ + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); + 1379 .loc 1 864 3 view .LVU263 + 1380 0000 064A ldr r2, .L120 + 1381 0002 1368 ldr r3, [r2] + 1382 0004 0721 movs r1, #7 + 1383 0006 8B43 bics r3, r1 + 1384 0008 0339 subs r1, r1, #3 + 1385 000a 0B43 orrs r3, r1 + 1386 000c 1360 str r3, [r2] + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 1387 .loc 1 867 3 view .LVU264 + 1388 000e 044A ldr r2, .L120+4 + 1389 0010 1369 ldr r3, [r2, #16] + 1390 0012 0B43 orrs r3, r1 + 1391 0014 1361 str r3, [r2, #16] + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* This option is used to ensure that store operations are completed */ + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined ( __CC_ARM) + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __force_stores(); + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* __CC_ARM */ + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Request Wait For Interrupt */ + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __WFI(); + 1392 .loc 1 875 3 view .LVU265 + 1393 .syntax divided + 1394 @ 875 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c" 1 + 1395 0016 30BF wfi + 1396 @ 0 "" 2 + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1397 .loc 1 876 1 is_stmt 0 view .LVU266 + 1398 .thumb + 1399 .syntax unified + 1400 @ sp needed + 1401 0018 7047 bx lr + 1402 .L121: + 1403 001a C046 .align 2 + 1404 .L120: + 1405 001c 00700040 .word 1073770496 + ARM GAS /tmp/ccS0aCke.s page 42 + + + 1406 0020 00ED00E0 .word -536810240 + 1407 .cfi_endproc + 1408 .LFE320: + 1410 .section .text.HAL_PWREx_PVD_Rising_Callback,"ax",%progbits + 1411 .align 1 + 1412 .weak HAL_PWREx_PVD_Rising_Callback + 1413 .syntax unified + 1414 .code 16 + 1415 .thumb_func + 1416 .fpu softvfp + 1418 HAL_PWREx_PVD_Rising_Callback: + 1419 .LFB322: + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #endif /* PWR_SHDW_SUPPORT */ + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD interrupt request. + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_IRQHandler(). + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_PVM_IRQHandler(void) + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR PVD exti Rising flag */ + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVD exti pending bit */ + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVD interrupt rising user callback */ + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_PVM_Rising_Callback(); + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR exti fallling flag */ + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVD exti pending bit */ + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVD interrupt falling user callback */ + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_PVM_Falling_Callback(); + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR PVM exti Rising flag */ + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U) + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVM exti pending bit */ + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG(); + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVD PVM interrupt rising user callback */ + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_PVM_Rising_Callback(); + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR PVM exti fallling flag */ + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U) + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVM exti pending bit */ + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG(); + ARM GAS /tmp/ccS0aCke.s page 43 + + + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVM interrupt falling user callback */ + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_PVM_Falling_Callback(); + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt rising callback + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVD_PVM_Rising_Callback(void) + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified; when the callback is needed, + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt Falling callback + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVD_PVM_Falling_Callback(void) + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified; when the callback is needed, + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** #elif defined(PWR_PVD_SUPPORT) + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD interrupt request. + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_IRQHandler(). + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_IRQHandler(void) + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR exti Rising flag */ + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVD exti pending bit */ + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVD interrupt rising user callback */ + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_Rising_Callback(); + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR exti fallling flag */ + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Clear PVD exti pending bit */ + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* PWR PVD interrupt falling user callback */ + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** HAL_PWREx_PVD_Falling_Callback(); + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + ARM GAS /tmp/ccS0aCke.s page 44 + + + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt rising callback + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVD_Rising_Callback(void) + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1420 .loc 1 983 1 is_stmt 1 view -0 + 1421 .cfi_startproc + 1422 @ args = 0, pretend = 0, frame = 0 + 1423 @ frame_needed = 0, uses_anonymous_args = 0 + 1424 @ link register save eliminated. + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified; when the callback is needed, + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1425 .loc 1 987 1 view .LVU268 + 1426 @ sp needed + 1427 0000 7047 bx lr + 1428 .cfi_endproc + 1429 .LFE322: + 1431 .section .text.HAL_PWREx_PVD_Falling_Callback,"ax",%progbits + 1432 .align 1 + 1433 .weak HAL_PWREx_PVD_Falling_Callback + 1434 .syntax unified + 1435 .code 16 + 1436 .thumb_func + 1437 .fpu softvfp + 1439 HAL_PWREx_PVD_Falling_Callback: + 1440 .LFB323: + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /** + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt Falling callback + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** * @retval None + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** __weak void HAL_PWREx_PVD_Falling_Callback(void) + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1441 .loc 1 994 1 view -0 + 1442 .cfi_startproc + 1443 @ args = 0, pretend = 0, frame = 0 + 1444 @ frame_needed = 0, uses_anonymous_args = 0 + 1445 @ link register save eliminated. + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* NOTE : This function should not be modified; when the callback is needed, + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** */ + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1446 .loc 1 998 1 view .LVU270 + 1447 @ sp needed + 1448 0000 7047 bx lr + 1449 .cfi_endproc + 1450 .LFE323: + 1452 .section .text.HAL_PWREx_PVD_IRQHandler,"ax",%progbits + 1453 .align 1 + 1454 .global HAL_PWREx_PVD_IRQHandler + 1455 .syntax unified + 1456 .code 16 + 1457 .thumb_func + 1458 .fpu softvfp + 1460 HAL_PWREx_PVD_IRQHandler: + ARM GAS /tmp/ccS0aCke.s page 45 + + + 1461 .LFB321: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** /* Check PWR exti Rising flag */ + 1462 .loc 1 956 1 view -0 + 1463 .cfi_startproc + 1464 @ args = 0, pretend = 0, frame = 0 + 1465 @ frame_needed = 0, uses_anonymous_args = 0 + 1466 0000 10B5 push {r4, lr} + 1467 .LCFI3: + 1468 .cfi_def_cfa_offset 8 + 1469 .cfi_offset 4, -8 + 1470 .cfi_offset 14, -4 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1471 .loc 1 958 3 view .LVU272 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1472 .loc 1 958 7 is_stmt 0 view .LVU273 + 1473 0002 0B4B ldr r3, .L129 + 1474 0004 DB68 ldr r3, [r3, #12] + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1475 .loc 1 958 6 view .LVU274 + 1476 0006 DB03 lsls r3, r3, #15 + 1477 0008 04D4 bmi .L127 + 1478 .L125: + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1479 .loc 1 968 3 is_stmt 1 view .LVU275 + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1480 .loc 1 968 7 is_stmt 0 view .LVU276 + 1481 000a 094B ldr r3, .L129 + 1482 000c 1B69 ldr r3, [r3, #16] + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** { + 1483 .loc 1 968 6 view .LVU277 + 1484 000e DB03 lsls r3, r3, #15 + 1485 0010 07D4 bmi .L128 + 1486 .L124: + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1487 .loc 1 976 1 view .LVU278 + 1488 @ sp needed + 1489 0012 10BD pop {r4, pc} + 1490 .L127: + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1491 .loc 1 961 5 is_stmt 1 view .LVU279 + 1492 0014 064B ldr r3, .L129 + 1493 0016 8022 movs r2, #128 + 1494 0018 5202 lsls r2, r2, #9 + 1495 001a DA60 str r2, [r3, #12] + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + 1496 .loc 1 964 5 view .LVU280 + 1497 001c FFF7FEFF bl HAL_PWREx_PVD_Rising_Callback + 1498 .LVL44: + 1499 0020 F3E7 b .L125 + 1500 .L128: + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1501 .loc 1 971 5 view .LVU281 + 1502 0022 034B ldr r3, .L129 + 1503 0024 8022 movs r2, #128 + 1504 0026 5202 lsls r2, r2, #9 + 1505 0028 1A61 str r2, [r3, #16] + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** } + ARM GAS /tmp/ccS0aCke.s page 46 + + + 1506 .loc 1 974 5 view .LVU282 + 1507 002a FFF7FEFF bl HAL_PWREx_PVD_Falling_Callback + 1508 .LVL45: + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c **** + 1509 .loc 1 976 1 is_stmt 0 view .LVU283 + 1510 002e F0E7 b .L124 + 1511 .L130: + 1512 .align 2 + 1513 .L129: + 1514 0030 00180240 .word 1073879040 + 1515 .cfi_endproc + 1516 .LFE321: + 1518 .text + 1519 .Letext0: + 1520 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1521 .file 3 "Drivers/CMSIS/Include/core_cm0plus.h" + 1522 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1523 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1524 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h" + 1525 .file 7 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h" + 1526 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccS0aCke.s page 47 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_pwr_ex.c + /tmp/ccS0aCke.s:16 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 $t + /tmp/ccS0aCke.s:24 .text.HAL_PWREx_EnableBatteryCharging:0000000000000000 HAL_PWREx_EnableBatteryCharging + /tmp/ccS0aCke.s:61 .text.HAL_PWREx_EnableBatteryCharging:0000000000000014 $d + /tmp/ccS0aCke.s:67 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 $t + /tmp/ccS0aCke.s:74 .text.HAL_PWREx_DisableBatteryCharging:0000000000000000 HAL_PWREx_DisableBatteryCharging + /tmp/ccS0aCke.s:93 .text.HAL_PWREx_DisableBatteryCharging:000000000000000c $d + /tmp/ccS0aCke.s:99 .text.HAL_PWREx_EnablePORMonitorSampling:0000000000000000 $t + /tmp/ccS0aCke.s:106 .text.HAL_PWREx_EnablePORMonitorSampling:0000000000000000 HAL_PWREx_EnablePORMonitorSampling + /tmp/ccS0aCke.s:127 .text.HAL_PWREx_EnablePORMonitorSampling:0000000000000010 $d + /tmp/ccS0aCke.s:132 .text.HAL_PWREx_DisablePORMonitorSampling:0000000000000000 $t + /tmp/ccS0aCke.s:139 .text.HAL_PWREx_DisablePORMonitorSampling:0000000000000000 HAL_PWREx_DisablePORMonitorSampling + /tmp/ccS0aCke.s:159 .text.HAL_PWREx_DisablePORMonitorSampling:000000000000000c $d + /tmp/ccS0aCke.s:165 .text.HAL_PWREx_ConfigPVD:0000000000000000 $t + /tmp/ccS0aCke.s:172 .text.HAL_PWREx_ConfigPVD:0000000000000000 HAL_PWREx_ConfigPVD + /tmp/ccS0aCke.s:280 .text.HAL_PWREx_ConfigPVD:0000000000000080 $d + /tmp/ccS0aCke.s:287 .text.HAL_PWREx_EnablePVD:0000000000000000 $t + /tmp/ccS0aCke.s:294 .text.HAL_PWREx_EnablePVD:0000000000000000 HAL_PWREx_EnablePVD + /tmp/ccS0aCke.s:313 .text.HAL_PWREx_EnablePVD:000000000000000c $d + /tmp/ccS0aCke.s:318 .text.HAL_PWREx_DisablePVD:0000000000000000 $t + /tmp/ccS0aCke.s:325 .text.HAL_PWREx_DisablePVD:0000000000000000 HAL_PWREx_DisablePVD + /tmp/ccS0aCke.s:344 .text.HAL_PWREx_DisablePVD:000000000000000c $d + /tmp/ccS0aCke.s:349 .text.HAL_PWREx_EnableInternalWakeUpLine:0000000000000000 $t + /tmp/ccS0aCke.s:356 .text.HAL_PWREx_EnableInternalWakeUpLine:0000000000000000 HAL_PWREx_EnableInternalWakeUpLine + /tmp/ccS0aCke.s:376 .text.HAL_PWREx_EnableInternalWakeUpLine:0000000000000010 $d + /tmp/ccS0aCke.s:381 .text.HAL_PWREx_DisableInternalWakeUpLine:0000000000000000 $t + /tmp/ccS0aCke.s:388 .text.HAL_PWREx_DisableInternalWakeUpLine:0000000000000000 HAL_PWREx_DisableInternalWakeUpLine + /tmp/ccS0aCke.s:407 .text.HAL_PWREx_DisableInternalWakeUpLine:000000000000000c $d + /tmp/ccS0aCke.s:413 .text.HAL_PWREx_EnableGPIOPullUp:0000000000000000 $t + /tmp/ccS0aCke.s:420 .text.HAL_PWREx_EnableGPIOPullUp:0000000000000000 HAL_PWREx_EnableGPIOPullUp + /tmp/ccS0aCke.s:441 .rodata.HAL_PWREx_EnableGPIOPullUp:0000000000000000 $d + /tmp/ccS0aCke.s:543 .text.HAL_PWREx_EnableGPIOPullUp:0000000000000074 $d + /tmp/ccS0aCke.s:551 .text.HAL_PWREx_DisableGPIOPullUp:0000000000000000 $t + /tmp/ccS0aCke.s:558 .text.HAL_PWREx_DisableGPIOPullUp:0000000000000000 HAL_PWREx_DisableGPIOPullUp + /tmp/ccS0aCke.s:579 .rodata.HAL_PWREx_DisableGPIOPullUp:0000000000000000 $d + /tmp/ccS0aCke.s:659 .text.HAL_PWREx_DisableGPIOPullUp:0000000000000050 $d + /tmp/ccS0aCke.s:666 .text.HAL_PWREx_EnableGPIOPullDown:0000000000000000 $t + /tmp/ccS0aCke.s:673 .text.HAL_PWREx_EnableGPIOPullDown:0000000000000000 HAL_PWREx_EnableGPIOPullDown + /tmp/ccS0aCke.s:694 .rodata.HAL_PWREx_EnableGPIOPullDown:0000000000000000 $d + /tmp/ccS0aCke.s:796 .text.HAL_PWREx_EnableGPIOPullDown:0000000000000074 $d + /tmp/ccS0aCke.s:804 .text.HAL_PWREx_DisableGPIOPullDown:0000000000000000 $t + /tmp/ccS0aCke.s:811 .text.HAL_PWREx_DisableGPIOPullDown:0000000000000000 HAL_PWREx_DisableGPIOPullDown + /tmp/ccS0aCke.s:832 .rodata.HAL_PWREx_DisableGPIOPullDown:0000000000000000 $d + /tmp/ccS0aCke.s:912 .text.HAL_PWREx_DisableGPIOPullDown:0000000000000050 $d + /tmp/ccS0aCke.s:919 .text.HAL_PWREx_EnablePullUpPullDownConfig:0000000000000000 $t + /tmp/ccS0aCke.s:926 .text.HAL_PWREx_EnablePullUpPullDownConfig:0000000000000000 HAL_PWREx_EnablePullUpPullDownConfig + /tmp/ccS0aCke.s:946 .text.HAL_PWREx_EnablePullUpPullDownConfig:0000000000000010 $d + /tmp/ccS0aCke.s:951 .text.HAL_PWREx_DisablePullUpPullDownConfig:0000000000000000 $t + /tmp/ccS0aCke.s:958 .text.HAL_PWREx_DisablePullUpPullDownConfig:0000000000000000 HAL_PWREx_DisablePullUpPullDownConfig + /tmp/ccS0aCke.s:977 .text.HAL_PWREx_DisablePullUpPullDownConfig:000000000000000c $d + /tmp/ccS0aCke.s:983 .text.HAL_PWREx_EnableSRAMRetention:0000000000000000 $t + /tmp/ccS0aCke.s:990 .text.HAL_PWREx_EnableSRAMRetention:0000000000000000 HAL_PWREx_EnableSRAMRetention + /tmp/ccS0aCke.s:1010 .text.HAL_PWREx_EnableSRAMRetention:0000000000000010 $d + /tmp/ccS0aCke.s:1015 .text.HAL_PWREx_DisableSRAMRetention:0000000000000000 $t + /tmp/ccS0aCke.s:1022 .text.HAL_PWREx_DisableSRAMRetention:0000000000000000 HAL_PWREx_DisableSRAMRetention + /tmp/ccS0aCke.s:1041 .text.HAL_PWREx_DisableSRAMRetention:000000000000000c $d + ARM GAS /tmp/ccS0aCke.s page 48 + + + /tmp/ccS0aCke.s:1047 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 $t + /tmp/ccS0aCke.s:1054 .text.HAL_PWREx_EnableFlashPowerDown:0000000000000000 HAL_PWREx_EnableFlashPowerDown + /tmp/ccS0aCke.s:1075 .text.HAL_PWREx_EnableFlashPowerDown:000000000000000c $d + /tmp/ccS0aCke.s:1080 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 $t + /tmp/ccS0aCke.s:1087 .text.HAL_PWREx_DisableFlashPowerDown:0000000000000000 HAL_PWREx_DisableFlashPowerDown + /tmp/ccS0aCke.s:1108 .text.HAL_PWREx_DisableFlashPowerDown:000000000000000c $d + /tmp/ccS0aCke.s:1113 .text.HAL_PWREx_GetVoltageRange:0000000000000000 $t + /tmp/ccS0aCke.s:1120 .text.HAL_PWREx_GetVoltageRange:0000000000000000 HAL_PWREx_GetVoltageRange + /tmp/ccS0aCke.s:1141 .text.HAL_PWREx_GetVoltageRange:000000000000000c $d + /tmp/ccS0aCke.s:1147 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 $t + /tmp/ccS0aCke.s:1154 .text.HAL_PWREx_ControlVoltageScaling:0000000000000000 HAL_PWREx_ControlVoltageScaling + /tmp/ccS0aCke.s:1242 .text.HAL_PWREx_ControlVoltageScaling:0000000000000044 $d + /tmp/ccS0aCke.s:1250 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000000 $t + /tmp/ccS0aCke.s:1257 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000000 HAL_PWREx_EnableLowPowerRunMode + /tmp/ccS0aCke.s:1277 .text.HAL_PWREx_EnableLowPowerRunMode:0000000000000010 $d + /tmp/ccS0aCke.s:1282 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000000 $t + /tmp/ccS0aCke.s:1289 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000000 HAL_PWREx_DisableLowPowerRunMode + /tmp/ccS0aCke.s:1357 .text.HAL_PWREx_DisableLowPowerRunMode:0000000000000038 $d + /tmp/ccS0aCke.s:1365 .text.HAL_PWREx_EnterSHUTDOWNMode:0000000000000000 $t + /tmp/ccS0aCke.s:1372 .text.HAL_PWREx_EnterSHUTDOWNMode:0000000000000000 HAL_PWREx_EnterSHUTDOWNMode + /tmp/ccS0aCke.s:1405 .text.HAL_PWREx_EnterSHUTDOWNMode:000000000000001c $d + /tmp/ccS0aCke.s:1411 .text.HAL_PWREx_PVD_Rising_Callback:0000000000000000 $t + /tmp/ccS0aCke.s:1418 .text.HAL_PWREx_PVD_Rising_Callback:0000000000000000 HAL_PWREx_PVD_Rising_Callback + /tmp/ccS0aCke.s:1432 .text.HAL_PWREx_PVD_Falling_Callback:0000000000000000 $t + /tmp/ccS0aCke.s:1439 .text.HAL_PWREx_PVD_Falling_Callback:0000000000000000 HAL_PWREx_PVD_Falling_Callback + /tmp/ccS0aCke.s:1453 .text.HAL_PWREx_PVD_IRQHandler:0000000000000000 $t + /tmp/ccS0aCke.s:1460 .text.HAL_PWREx_PVD_IRQHandler:0000000000000000 HAL_PWREx_PVD_IRQHandler + /tmp/ccS0aCke.s:1514 .text.HAL_PWREx_PVD_IRQHandler:0000000000000030 $d + +UNDEFINED SYMBOLS +__aeabi_uidiv +SystemCoreClock diff --git a/squero/build/stm32g0xx_hal_pwr_ex.o b/squero/build/stm32g0xx_hal_pwr_ex.o new file mode 100644 index 0000000000000000000000000000000000000000..b4ef98d8013499dba276ca109bfdab5e76cd9a37 GIT binary patch literal 20560 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© Copyright (c) 2018 STMicroelectronics. + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * All rights reserved.
+ 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * This software component is licensed by ST under BSD 3-Clause license, + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * the "License"; You may not use this file except in compliance with the + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * License. You may obtain a copy of the License at: + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * opensource.org/licenses/BSD-3-Clause + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** ****************************************************************************** + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #include "stm32g0xx_hal.h" + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @addtogroup STM32G0xx_HAL_Driver + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC RCC + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief RCC HAL module driver + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define PLLSOURCE_NONE (0U) + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @} + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + ARM GAS /tmp/ccBwposX.s page 3 + + + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_MCO2_SUPPORT) + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO2_GPIO_PORT GPIOA + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define MCO2_PIN GPIO_PIN_10 + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_MCO2_SUPPORT */ + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @} + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @} + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Exported functions --------------------------------------------------------*/ + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** @verbatim + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** =============================================================================== + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** =============================================================================== + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** [..] + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** This section provides functions allowing to configure the internal and external oscillators + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB) + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** the PLL as System clock source. + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** clock source. + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** through the PLL as System clock source. Can be used also optionally as RTC clock sourc + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) The first output (R) is used to generate the high speed system clock (up to 64MHz). + ARM GAS /tmp/ccBwposX.s page 4 + + + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) The second output(Q) is used to generate the clock for the random analog generator + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) The Third output (P) is used to generate the clock for the Analog to Digital Conver + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (HSE used directly or through PLL as System clock source), the System clock + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** is automatically switched respectively to HSI or LSI and an interrupt is generated + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** exception vector. + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) MCOx (microcontroller clock output): + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) MCO1 used to output LSI, HSI48(*), HSI, LSE, HSE or main PLL clock (through a con + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) MCO2(*) used to output LSI, HSI48(*), HSI, LSE, HSE, main PLLR clock, PLLQ clock, + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (*) available on certain devices only + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HSE, LSI, LSE and main PLL. + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** the peripherals mapped on these buses. You can use + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** divided by 2 to 31. + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() fu + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** to configure this clock. + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+@) RNG(*) requires a frequency equal or lower than 48 MHz. + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** This clock is derived from the main PLL or HSI or System clock. + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (*) available on certain devices only + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+@) IWDG clock which is always the LSI clock. + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 64 MHz. + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** Depending on the device voltage range, the maximum frequency should be + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** adapted accordingly. + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** @endverbatim + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) Table 1. HCLK clock frequency. + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) +-------------------------------------------------------+ + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) | Latency | HCLK clock frequency (MHz) | + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) | |-------------------------------------| + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) | | voltage range 1 | voltage range 2 | + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) | | 1.2 V | 1.0 V | + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |-----------------|------------------|------------------| + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |-----------------|------------------|------------------| + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |-----------------|------------------|------------------| + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |2WS(3 CPU cycles)| HCLK <= 64 | - | + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (++) |-----------------|------------------|------------------| + ARM GAS /tmp/ccBwposX.s page 5 + + + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Reset the RCC clock configuration to the default reset state. + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - HSI ON and used as system clock source + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - HSE, PLL OFF + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - AHB and APB prescaler set to 1. + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - CSS, MCO1 OFF + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - All interrupts disabled + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note This function does not modify the configuration of the + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - Peripheral clocks + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval HAL status + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 27 .loc 1 221 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 0000 70B5 push {r4, r5, r6, lr} + 32 .LCFI0: + 33 .cfi_def_cfa_offset 16 + 34 .cfi_offset 4, -16 + 35 .cfi_offset 5, -12 + 36 .cfi_offset 6, -8 + 37 .cfi_offset 14, -4 + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t tickstart; + 38 .loc 1 222 3 view .LVU1 + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 39 .loc 1 225 3 view .LVU2 + 40 .loc 1 225 15 is_stmt 0 view .LVU3 + 41 0002 FFF7FEFF bl HAL_GetTick + 42 .LVL0: + 43 0006 0400 movs r4, r0 + 44 .LVL1: + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set HSION bit to the reset value */ + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); + 45 .loc 1 228 3 is_stmt 1 view .LVU4 + 46 0008 254A ldr r2, .L15 + 47 000a 1168 ldr r1, [r2] + 48 000c 8023 movs r3, #128 + 49 000e 5B00 lsls r3, r3, #1 + 50 0010 0B43 orrs r3, r1 + 51 0012 1360 str r3, [r2] + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI is ready */ + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 52 .loc 1 231 3 view .LVU5 + 53 .LVL2: + 54 .L2: + 55 .loc 1 231 9 view .LVU6 + ARM GAS /tmp/ccBwposX.s page 6 + + + 56 .loc 1 231 10 is_stmt 0 view .LVU7 + 57 0014 224B ldr r3, .L15 + 58 0016 1B68 ldr r3, [r3] + 59 .loc 1 231 9 view .LVU8 + 60 0018 5B05 lsls r3, r3, #21 + 61 001a 06D4 bmi .L12 + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 62 .loc 1 233 5 is_stmt 1 view .LVU9 + 63 .loc 1 233 10 is_stmt 0 view .LVU10 + 64 001c FFF7FEFF bl HAL_GetTick + 65 .LVL3: + 66 .loc 1 233 24 view .LVU11 + 67 0020 001B subs r0, r0, r4 + 68 .loc 1 233 8 view .LVU12 + 69 0022 0228 cmp r0, #2 + 70 0024 F6D9 bls .L2 + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 71 .loc 1 235 14 view .LVU13 + 72 0026 0320 movs r0, #3 + 73 .L3: + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set HSITRIM[6:0] bits to the reset value */ + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->ICSCR = RCC_ICSCR_HSITRIM_6; + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Reset CFGR register (HSI is selected as system clock source) */ + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CFGR = 0x00000000u; + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI is ready */ + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CR = RCC_CR_HSION; + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Then again to HSEBYP in case bypass was enabled */ + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CR = RCC_CR_HSION; + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till PLL is ready */ + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 7 + + + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* once PLL is OFF, reset PLLCFGR register to default value */ + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable all interrupts */ + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CIER = 0x00000000u; + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Clear all flags */ + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CICR = 0xFFFFFFFFu; + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Adapt Systick interrupt period */ + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (HAL_InitTick(uwTickPrio) != HAL_OK) + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_OK; + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 74 .loc 1 296 1 view .LVU14 + 75 @ sp needed + 76 .LVL4: + 77 .loc 1 296 1 view .LVU15 + 78 0028 70BD pop {r4, r5, r6, pc} + 79 .LVL5: + 80 .L12: + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 81 .loc 1 240 3 is_stmt 1 view .LVU16 + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 82 .loc 1 240 14 is_stmt 0 view .LVU17 + 83 002a 1D4D ldr r5, .L15 + 84 002c 8023 movs r3, #128 + 85 002e DB01 lsls r3, r3, #7 + 86 0030 6B60 str r3, [r5, #4] + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 87 .loc 1 243 3 is_stmt 1 view .LVU18 + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 88 .loc 1 243 15 is_stmt 0 view .LVU19 + 89 0032 FFF7FEFF bl HAL_GetTick + 90 .LVL6: + 91 0036 0400 movs r4, r0 + 92 .LVL7: + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 93 .loc 1 246 3 is_stmt 1 view .LVU20 + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 94 .loc 1 246 13 is_stmt 0 view .LVU21 + 95 0038 0023 movs r3, #0 + 96 003a AB60 str r3, [r5, #8] + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 97 .loc 1 249 3 is_stmt 1 view .LVU22 + ARM GAS /tmp/ccBwposX.s page 8 + + + 98 .LVL8: + 99 .L5: + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 100 .loc 1 249 9 view .LVU23 + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 101 .loc 1 249 10 is_stmt 0 view .LVU24 + 102 003c 184B ldr r3, .L15 + 103 003e 9B68 ldr r3, [r3, #8] + 104 0040 3822 movs r2, #56 + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 105 .loc 1 249 9 view .LVU25 + 106 0042 1A42 tst r2, r3 + 107 0044 07D0 beq .L13 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 108 .loc 1 251 5 is_stmt 1 view .LVU26 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 109 .loc 1 251 10 is_stmt 0 view .LVU27 + 110 0046 FFF7FEFF bl HAL_GetTick + 111 .LVL9: + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 112 .loc 1 251 24 view .LVU28 + 113 004a 001B subs r0, r0, r4 + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 114 .loc 1 251 8 view .LVU29 + 115 004c 154B ldr r3, .L15+4 + 116 004e 9842 cmp r0, r3 + 117 0050 F4D9 bls .L5 + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 118 .loc 1 253 14 view .LVU30 + 119 0052 0320 movs r0, #3 + 120 0054 E8E7 b .L3 + 121 .L13: + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 122 .loc 1 258 3 is_stmt 1 view .LVU31 + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 123 .loc 1 258 11 is_stmt 0 view .LVU32 + 124 0056 124B ldr r3, .L15 + 125 0058 C832 adds r2, r2, #200 + 126 005a 1A60 str r2, [r3] + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 127 .loc 1 261 3 is_stmt 1 view .LVU33 + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 128 .loc 1 261 11 is_stmt 0 view .LVU34 + 129 005c 1A60 str r2, [r3] + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 130 .loc 1 264 3 is_stmt 1 view .LVU35 + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 131 .loc 1 264 15 is_stmt 0 view .LVU36 + 132 005e FFF7FEFF bl HAL_GetTick + 133 .LVL10: + 134 0062 0400 movs r4, r0 + 135 .LVL11: + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 136 .loc 1 267 3 is_stmt 1 view .LVU37 + 137 .L7: + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 138 .loc 1 267 9 view .LVU38 + ARM GAS /tmp/ccBwposX.s page 9 + + + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 139 .loc 1 267 10 is_stmt 0 view .LVU39 + 140 0064 0E4B ldr r3, .L15 + 141 0066 1B68 ldr r3, [r3] + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 142 .loc 1 267 9 view .LVU40 + 143 0068 9B01 lsls r3, r3, #6 + 144 006a 06D5 bpl .L14 + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 145 .loc 1 269 5 is_stmt 1 view .LVU41 + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 146 .loc 1 269 10 is_stmt 0 view .LVU42 + 147 006c FFF7FEFF bl HAL_GetTick + 148 .LVL12: + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 149 .loc 1 269 24 view .LVU43 + 150 0070 001B subs r0, r0, r4 + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 151 .loc 1 269 8 view .LVU44 + 152 0072 0228 cmp r0, #2 + 153 0074 F6D9 bls .L7 + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 154 .loc 1 271 14 view .LVU45 + 155 0076 0320 movs r0, #3 + 156 0078 D6E7 b .L3 + 157 .L14: + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 158 .loc 1 276 3 is_stmt 1 view .LVU46 + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 159 .loc 1 276 16 is_stmt 0 view .LVU47 + 160 007a 094B ldr r3, .L15 + 161 007c 8022 movs r2, #128 + 162 007e 5201 lsls r2, r2, #5 + 163 0080 DA60 str r2, [r3, #12] + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 164 .loc 1 279 3 is_stmt 1 view .LVU48 + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 165 .loc 1 279 13 is_stmt 0 view .LVU49 + 166 0082 0022 movs r2, #0 + 167 0084 9A61 str r2, [r3, #24] + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 168 .loc 1 282 3 is_stmt 1 view .LVU50 + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 169 .loc 1 282 13 is_stmt 0 view .LVU51 + 170 0086 013A subs r2, r2, #1 + 171 0088 1A62 str r2, [r3, #32] + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 172 .loc 1 285 3 is_stmt 1 view .LVU52 + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 173 .loc 1 285 19 is_stmt 0 view .LVU53 + 174 008a 074B ldr r3, .L15+8 + 175 008c 074A ldr r2, .L15+12 + 176 008e 1A60 str r2, [r3] + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 177 .loc 1 288 3 is_stmt 1 view .LVU54 + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 178 .loc 1 288 7 is_stmt 0 view .LVU55 + ARM GAS /tmp/ccBwposX.s page 10 + + + 179 0090 074B ldr r3, .L15+16 + 180 0092 1868 ldr r0, [r3] + 181 0094 FFF7FEFF bl HAL_InitTick + 182 .LVL13: + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 183 .loc 1 288 6 view .LVU56 + 184 0098 0028 cmp r0, #0 + 185 009a C5D0 beq .L3 + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 186 .loc 1 290 12 view .LVU57 + 187 009c 0120 movs r0, #1 + 188 009e C3E7 b .L3 + 189 .L16: + 190 .align 2 + 191 .L15: + 192 00a0 00100240 .word 1073876992 + 193 00a4 88130000 .word 5000 + 194 00a8 00000000 .word SystemCoreClock + 195 00ac 0024F400 .word 16000000 + 196 00b0 00000000 .word uwTickPrio + 197 .cfi_endproc + 198 .LFE297: + 200 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 201 .align 1 + 202 .global HAL_RCC_OscConfig + 203 .syntax unified + 204 .code 16 + 205 .thumb_func + 206 .fpu softvfp + 208 HAL_RCC_OscConfig: + 209 .LVL14: + 210 .LFB298: + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Initialize the RCC Oscillators according to the specified parameters in the + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @ref RCC_OscInitTypeDef. + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * supported by this function. User should request a transition to HSE Off + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * first and then to HSE On or HSE Bypass. + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * supported by this function. User should request a transition to LSE Off + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * first and then to LSE On or LSE Bypass. + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval HAL status + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 211 .loc 1 313 1 is_stmt 1 view -0 + 212 .cfi_startproc + 213 @ args = 0, pretend = 0, frame = 8 + 214 @ frame_needed = 0, uses_anonymous_args = 0 + 215 .loc 1 313 1 is_stmt 0 view .LVU59 + 216 0000 70B5 push {r4, r5, r6, lr} + 217 .LCFI1: + 218 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccBwposX.s page 11 + + + 219 .cfi_offset 4, -16 + 220 .cfi_offset 5, -12 + 221 .cfi_offset 6, -8 + 222 .cfi_offset 14, -4 + 223 0002 82B0 sub sp, sp, #8 + 224 .LCFI2: + 225 .cfi_def_cfa_offset 24 + 226 0004 041E subs r4, r0, #0 + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t tickstart; + 227 .loc 1 314 3 is_stmt 1 view .LVU60 + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t temp_sysclksrc; + 228 .loc 1 315 3 view .LVU61 + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t temp_pllckcfg; + 229 .loc 1 316 3 view .LVU62 + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check Null pointer */ + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct == NULL) + 230 .loc 1 319 3 view .LVU63 + 231 .loc 1 319 6 is_stmt 0 view .LVU64 + 232 0006 00D1 bne .LCB183 + 233 0008 34E2 b .L72 @long jump + 234 .LCB183: + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 235 .loc 1 325 3 is_stmt 1 view .LVU65 + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 236 .loc 1 328 3 view .LVU66 + 237 .loc 1 328 6 is_stmt 0 view .LVU67 + 238 000a 0368 ldr r3, [r0] + 239 000c DB07 lsls r3, r3, #31 + 240 000e 39D5 bpl .L19 + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 241 .loc 1 331 5 is_stmt 1 view .LVU68 + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 242 .loc 1 333 5 view .LVU69 + 243 .loc 1 333 22 is_stmt 0 view .LVU70 + 244 0010 C14A ldr r2, .L117 + 245 0012 9168 ldr r1, [r2, #8] + 246 .loc 1 333 20 view .LVU71 + 247 0014 3823 movs r3, #56 + 248 0016 0B40 ands r3, r1 + 249 .LVL15: + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + 250 .loc 1 334 5 is_stmt 1 view .LVU72 + 251 .loc 1 334 21 is_stmt 0 view .LVU73 + 252 0018 D168 ldr r1, [r2, #12] + 253 .loc 1 334 19 view .LVU74 + 254 001a 0322 movs r2, #3 + ARM GAS /tmp/ccBwposX.s page 12 + + + 255 001c 0A40 ands r2, r1 + 256 .LVL16: + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE) + 257 .loc 1 337 5 is_stmt 1 view .LVU75 + 258 .loc 1 337 8 is_stmt 0 view .LVU76 + 259 001e 102B cmp r3, #16 + 260 0020 26D0 beq .L99 + 261 .L20: + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + 262 .loc 1 338 9 view .LVU77 + 263 0022 082B cmp r3, #8 + 264 0024 26D0 beq .L21 + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 265 .loc 1 348 7 is_stmt 1 view .LVU78 + 266 .loc 1 348 7 view .LVU79 + 267 0026 6368 ldr r3, [r4, #4] + 268 .LVL17: + 269 .loc 1 348 7 is_stmt 0 view .LVU80 + 270 0028 8022 movs r2, #128 + 271 .LVL18: + 272 .loc 1 348 7 view .LVU81 + 273 002a 5202 lsls r2, r2, #9 + 274 002c 9342 cmp r3, r2 + 275 002e 7FD0 beq .L100 + 276 .loc 1 348 7 is_stmt 1 discriminator 2 view .LVU82 + 277 0030 A022 movs r2, #160 + 278 0032 D202 lsls r2, r2, #11 + 279 0034 9342 cmp r3, r2 + 280 0036 00D1 bne .LCB223 + 281 0038 81E0 b .L101 @long jump + 282 .LCB223: + 283 .loc 1 348 7 discriminator 5 view .LVU83 + 284 003a B74B ldr r3, .L117 + 285 003c 1A68 ldr r2, [r3] + 286 003e B749 ldr r1, .L117+4 + 287 .LVL19: + 288 .loc 1 348 7 is_stmt 0 discriminator 5 view .LVU84 + 289 0040 0A40 ands r2, r1 + 290 0042 1A60 str r2, [r3] + 291 .loc 1 348 7 is_stmt 1 discriminator 5 view .LVU85 + 292 0044 1A68 ldr r2, [r3] + 293 0046 B649 ldr r1, .L117+8 + 294 0048 0A40 ands r2, r1 + 295 004a 1A60 str r2, [r3] + 296 .L24: + 297 .loc 1 348 7 discriminator 7 view .LVU86 + ARM GAS /tmp/ccBwposX.s page 13 + + + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the HSE State */ + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 298 .loc 1 351 7 discriminator 7 view .LVU87 + 299 .loc 1 351 10 is_stmt 0 discriminator 7 view .LVU88 + 300 004c 6368 ldr r3, [r4, #4] + 301 004e 002B cmp r3, #0 + 302 0050 00D1 bne .LCB243 + 303 0052 80E0 b .L26 @long jump + 304 .LCB243: + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 305 .loc 1 354 9 is_stmt 1 view .LVU89 + 306 .loc 1 354 21 is_stmt 0 view .LVU90 + 307 0054 FFF7FEFF bl HAL_GetTick + 308 .LVL20: + 309 .loc 1 354 21 view .LVU91 + 310 0058 0500 movs r5, r0 + 311 .LVL21: + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSE is ready */ + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 312 .loc 1 357 9 is_stmt 1 view .LVU92 + 313 .L27: + 314 .loc 1 357 15 view .LVU93 + 315 .loc 1 357 16 is_stmt 0 view .LVU94 + 316 005a AF4B ldr r3, .L117 + 317 005c 1B68 ldr r3, [r3] + 318 .loc 1 357 15 view .LVU95 + 319 005e 9B03 lsls r3, r3, #14 + 320 0060 10D4 bmi .L19 + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 321 .loc 1 359 11 is_stmt 1 view .LVU96 + 322 .loc 1 359 16 is_stmt 0 view .LVU97 + 323 0062 FFF7FEFF bl HAL_GetTick + 324 .LVL22: + 325 .loc 1 359 30 view .LVU98 + 326 0066 401B subs r0, r0, r5 + 327 .loc 1 359 14 view .LVU99 + 328 0068 6428 cmp r0, #100 + 329 006a F6D9 bls .L27 + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 330 .loc 1 361 20 view .LVU100 + 331 006c 0320 movs r0, #3 + 332 .loc 1 361 20 view .LVU101 + 333 006e 02E2 b .L18 + 334 .LVL23: + 335 .L99: + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + 336 .loc 1 337 61 discriminator 1 view .LVU102 + 337 0070 032A cmp r2, #3 + 338 0072 D6D1 bne .L20 + 339 .L21: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 14 + + + 340 .loc 1 340 7 is_stmt 1 view .LVU103 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 341 .loc 1 340 12 is_stmt 0 view .LVU104 + 342 0074 A84B ldr r3, .L117 + 343 .LVL24: + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 344 .loc 1 340 12 view .LVU105 + 345 0076 1B68 ldr r3, [r3] + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 346 .loc 1 340 10 view .LVU106 + 347 0078 9B03 lsls r3, r3, #14 + 348 007a 03D5 bpl .L19 + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 349 .loc 1 340 52 discriminator 1 view .LVU107 + 350 007c 6368 ldr r3, [r4, #4] + 351 007e 002B cmp r3, #0 + 352 0080 00D1 bne .LCB290 + 353 0082 FAE1 b .L102 @long jump + 354 .LCB290: + 355 .LVL25: + 356 .L19: + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 357 .loc 1 382 3 is_stmt 1 view .LVU108 + 358 .loc 1 382 6 is_stmt 0 view .LVU109 + 359 0084 2368 ldr r3, [r4] + 360 0086 9B07 lsls r3, r3, #30 + 361 0088 31D5 bpl .L31 + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 362 .loc 1 385 5 is_stmt 1 view .LVU110 + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 363 .loc 1 386 5 view .LVU111 + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + 364 .loc 1 387 5 view .LVU112 + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock + ARM GAS /tmp/ccBwposX.s page 15 + + + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 365 .loc 1 390 5 view .LVU113 + 366 .loc 1 390 22 is_stmt 0 view .LVU114 + 367 008a A34A ldr r2, .L117 + 368 008c 9368 ldr r3, [r2, #8] + 369 .loc 1 390 20 view .LVU115 + 370 008e 3821 movs r1, #56 + 371 0090 0B40 ands r3, r1 + 372 .LVL26: + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + 373 .loc 1 391 5 is_stmt 1 view .LVU116 + 374 .loc 1 391 21 is_stmt 0 view .LVU117 + 375 0092 D168 ldr r1, [r2, #12] + 376 .loc 1 391 19 view .LVU118 + 377 0094 0322 movs r2, #3 + 378 0096 0A40 ands r2, r1 + 379 .LVL27: + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI) + 380 .loc 1 392 5 is_stmt 1 view .LVU119 + 381 .loc 1 392 8 is_stmt 0 view .LVU120 + 382 0098 102B cmp r3, #16 + 383 009a 6AD0 beq .L103 + 384 .L32: + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + 385 .loc 1 393 9 view .LVU121 + 386 009c 002B cmp r3, #0 + 387 009e 6BD1 bne .L34 + 388 .L33: + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* When HSI is used as system clock or as PLL input clock it can not be disabled */ + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 389 .loc 1 396 7 is_stmt 1 view .LVU122 + 390 .loc 1 396 12 is_stmt 0 view .LVU123 + 391 00a0 9D4A ldr r2, .L117 + 392 .LVL28: + 393 .loc 1 396 12 view .LVU124 + 394 00a2 1268 ldr r2, [r2] + 395 .loc 1 396 10 view .LVU125 + 396 00a4 5205 lsls r2, r2, #21 + 397 00a6 03D5 bpl .L35 + 398 .loc 1 396 52 discriminator 1 view .LVU126 + 399 00a8 E268 ldr r2, [r4, #12] + 400 00aa 002A cmp r2, #0 + 401 00ac 00D1 bne .LCB334 + 402 00ae E6E1 b .L76 @long jump + 403 .LCB334: + 404 .L35: + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 405 .loc 1 404 9 is_stmt 1 view .LVU127 + 406 00b0 9948 ldr r0, .L117 + ARM GAS /tmp/ccBwposX.s page 16 + + + 407 00b2 4268 ldr r2, [r0, #4] + 408 00b4 9B49 ldr r1, .L117+12 + 409 .LVL29: + 410 .loc 1 404 9 is_stmt 0 view .LVU128 + 411 00b6 0A40 ands r2, r1 + 412 00b8 6169 ldr r1, [r4, #20] + 413 00ba 0902 lsls r1, r1, #8 + 414 00bc 0A43 orrs r2, r1 + 415 00be 4260 str r2, [r0, #4] + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + 416 .loc 1 406 9 is_stmt 1 view .LVU129 + 417 .loc 1 406 12 is_stmt 0 view .LVU130 + 418 00c0 002B cmp r3, #0 + 419 00c2 0DD1 bne .L36 + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Adjust the HSI16 division factor */ + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 420 .loc 1 409 11 is_stmt 1 view .LVU131 + 421 00c4 0368 ldr r3, [r0] + 422 .LVL30: + 423 .loc 1 409 11 is_stmt 0 view .LVU132 + 424 00c6 9849 ldr r1, .L117+16 + 425 00c8 0B40 ands r3, r1 + 426 00ca 2169 ldr r1, [r4, #16] + 427 00cc 0B43 orrs r3, r1 + 428 00ce 0360 str r3, [r0] + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable with HSISYS value */ + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSID + 429 .loc 1 412 11 is_stmt 1 view .LVU133 + 430 .loc 1 412 52 is_stmt 0 view .LVU134 + 431 00d0 0368 ldr r3, [r0] + 432 .loc 1 412 86 view .LVU135 + 433 00d2 DB0A lsrs r3, r3, #11 + 434 00d4 0722 movs r2, #7 + 435 00d6 1A40 ands r2, r3 + 436 .loc 1 412 40 view .LVU136 + 437 00d8 944B ldr r3, .L117+20 + 438 00da D340 lsrs r3, r3, r2 + 439 .loc 1 412 27 view .LVU137 + 440 00dc 944A ldr r2, .L117+24 + 441 00de 1360 str r3, [r2] + 442 .L36: + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Adapt Systick interrupt period */ + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (HAL_InitTick(uwTickPrio) != HAL_OK) + 443 .loc 1 416 9 is_stmt 1 view .LVU138 + 444 .loc 1 416 13 is_stmt 0 view .LVU139 + 445 00e0 944B ldr r3, .L117+28 + 446 00e2 1868 ldr r0, [r3] + 447 00e4 FFF7FEFF bl HAL_InitTick + 448 .LVL31: + 449 .loc 1 416 12 view .LVU140 + 450 00e8 0028 cmp r0, #0 + 451 00ea 00D0 beq .LCB377 + ARM GAS /tmp/ccBwposX.s page 17 + + + 452 00ec C9E1 b .L104 @long jump + 453 .LCB377: + 454 .L31: + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the HSI State */ + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the HSI16 division factor */ + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI16). */ + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI is ready */ + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI16). */ + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI is disabled */ + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 455 .loc 1 468 3 is_stmt 1 view .LVU141 + 456 .loc 1 468 6 is_stmt 0 view .LVU142 + ARM GAS /tmp/ccBwposX.s page 18 + + + 457 00ee 2368 ldr r3, [r4] + 458 00f0 1B07 lsls r3, r3, #28 + 459 00f2 00D4 bmi .LCB388 + 460 00f4 81E0 b .L42 @long jump + 461 .LCB388: + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 462 .loc 1 471 5 is_stmt 1 view .LVU143 + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check if LSI is used as system clock */ + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + 463 .loc 1 474 5 view .LVU144 + 464 .loc 1 474 9 is_stmt 0 view .LVU145 + 465 00f6 884B ldr r3, .L117 + 466 00f8 9A68 ldr r2, [r3, #8] + 467 00fa 3823 movs r3, #56 + 468 00fc 1340 ands r3, r2 + 469 .loc 1 474 8 view .LVU146 + 470 00fe 182B cmp r3, #24 + 471 0100 73D0 beq .L105 + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* When LSI is used as system clock it will not be disabled */ + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the LSI State */ + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 472 .loc 1 485 7 is_stmt 1 view .LVU147 + 473 .loc 1 485 10 is_stmt 0 view .LVU148 + 474 0102 A369 ldr r3, [r4, #24] + 475 0104 002B cmp r3, #0 + 476 0106 00D1 bne .LCB401 + 477 0108 B4E0 b .L44 @long jump + 478 .LCB401: + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 479 .loc 1 488 9 is_stmt 1 view .LVU149 + 480 010a 834A ldr r2, .L117 + 481 010c 136E ldr r3, [r2, #96] + 482 010e 0121 movs r1, #1 + 483 0110 0B43 orrs r3, r1 + 484 0112 1366 str r3, [r2, #96] + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 485 .loc 1 491 9 view .LVU150 + 486 .loc 1 491 21 is_stmt 0 view .LVU151 + 487 0114 FFF7FEFF bl HAL_GetTick + 488 .LVL32: + 489 0118 0500 movs r5, r0 + 490 .LVL33: + ARM GAS /tmp/ccBwposX.s page 19 + + + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till LSI is ready */ + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 491 .loc 1 494 9 is_stmt 1 view .LVU152 + 492 .L45: + 493 .loc 1 494 15 view .LVU153 + 494 .loc 1 494 16 is_stmt 0 view .LVU154 + 495 011a 7F4B ldr r3, .L117 + 496 011c 1B6E ldr r3, [r3, #96] + 497 .loc 1 494 15 view .LVU155 + 498 011e 9B07 lsls r3, r3, #30 + 499 0120 6BD4 bmi .L42 + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 500 .loc 1 496 11 is_stmt 1 view .LVU156 + 501 .loc 1 496 16 is_stmt 0 view .LVU157 + 502 0122 FFF7FEFF bl HAL_GetTick + 503 .LVL34: + 504 .loc 1 496 30 view .LVU158 + 505 0126 401B subs r0, r0, r5 + 506 .loc 1 496 14 view .LVU159 + 507 0128 0228 cmp r0, #2 + 508 012a F6D9 bls .L45 + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 509 .loc 1 498 20 view .LVU160 + 510 012c 0320 movs r0, #3 + 511 012e A2E1 b .L18 + 512 .LVL35: + 513 .L100: + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 514 .loc 1 348 7 is_stmt 1 discriminator 1 view .LVU161 + 515 0130 794A ldr r2, .L117 + 516 0132 1168 ldr r1, [r2] + 517 .LVL36: + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 518 .loc 1 348 7 is_stmt 0 discriminator 1 view .LVU162 + 519 0134 8023 movs r3, #128 + 520 0136 5B02 lsls r3, r3, #9 + 521 0138 0B43 orrs r3, r1 + 522 013a 1360 str r3, [r2] + 523 013c 86E7 b .L24 + 524 .LVL37: + 525 .L101: + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 526 .loc 1 348 7 is_stmt 1 discriminator 4 view .LVU163 + 527 013e 764B ldr r3, .L117 + 528 0140 1968 ldr r1, [r3] + 529 .LVL38: + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 530 .loc 1 348 7 is_stmt 0 discriminator 4 view .LVU164 + 531 0142 8022 movs r2, #128 + 532 0144 D202 lsls r2, r2, #11 + 533 0146 0A43 orrs r2, r1 + 534 0148 1A60 str r2, [r3] + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 535 .loc 1 348 7 is_stmt 1 discriminator 4 view .LVU165 + ARM GAS /tmp/ccBwposX.s page 20 + + + 536 014a 1968 ldr r1, [r3] + 537 014c 8022 movs r2, #128 + 538 014e 5202 lsls r2, r2, #9 + 539 0150 0A43 orrs r2, r1 + 540 0152 1A60 str r2, [r3] + 541 0154 7AE7 b .L24 + 542 .L26: + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 543 .loc 1 368 9 view .LVU166 + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 544 .loc 1 368 21 is_stmt 0 view .LVU167 + 545 0156 FFF7FEFF bl HAL_GetTick + 546 .LVL39: + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 547 .loc 1 368 21 view .LVU168 + 548 015a 0500 movs r5, r0 + 549 .LVL40: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 550 .loc 1 371 9 is_stmt 1 view .LVU169 + 551 .L29: + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 552 .loc 1 371 15 view .LVU170 + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 553 .loc 1 371 16 is_stmt 0 view .LVU171 + 554 015c 6E4B ldr r3, .L117 + 555 015e 1B68 ldr r3, [r3] + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 556 .loc 1 371 15 view .LVU172 + 557 0160 9B03 lsls r3, r3, #14 + 558 0162 8FD5 bpl .L19 + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 559 .loc 1 373 11 is_stmt 1 view .LVU173 + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 560 .loc 1 373 16 is_stmt 0 view .LVU174 + 561 0164 FFF7FEFF bl HAL_GetTick + 562 .LVL41: + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 563 .loc 1 373 30 view .LVU175 + 564 0168 401B subs r0, r0, r5 + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 565 .loc 1 373 14 view .LVU176 + 566 016a 6428 cmp r0, #100 + 567 016c F6D9 bls .L29 + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 568 .loc 1 375 20 view .LVU177 + 569 016e 0320 movs r0, #3 + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 570 .loc 1 375 20 view .LVU178 + 571 0170 81E1 b .L18 + 572 .LVL42: + 573 .L103: + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + 574 .loc 1 392 61 discriminator 1 view .LVU179 + 575 0172 022A cmp r2, #2 + 576 0174 92D1 bne .L32 + 577 0176 93E7 b .L33 + 578 .L34: + ARM GAS /tmp/ccBwposX.s page 21 + + + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 579 .loc 1 425 7 is_stmt 1 view .LVU180 + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 580 .loc 1 425 10 is_stmt 0 view .LVU181 + 581 0178 E368 ldr r3, [r4, #12] + 582 .LVL43: + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 583 .loc 1 425 10 view .LVU182 + 584 017a 002B cmp r3, #0 + 585 017c 22D0 beq .L37 + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 586 .loc 1 428 9 is_stmt 1 view .LVU183 + 587 017e 664A ldr r2, .L117 + 588 .LVL44: + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 589 .loc 1 428 9 is_stmt 0 view .LVU184 + 590 0180 1368 ldr r3, [r2] + 591 0182 6949 ldr r1, .L117+16 + 592 .LVL45: + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 593 .loc 1 428 9 view .LVU185 + 594 0184 0B40 ands r3, r1 + 595 0186 2169 ldr r1, [r4, #16] + 596 0188 0B43 orrs r3, r1 + 597 018a 1360 str r3, [r2] + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 598 .loc 1 431 9 is_stmt 1 view .LVU186 + 599 018c 1168 ldr r1, [r2] + 600 018e 8023 movs r3, #128 + 601 0190 5B00 lsls r3, r3, #1 + 602 0192 0B43 orrs r3, r1 + 603 0194 1360 str r3, [r2] + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 604 .loc 1 434 9 view .LVU187 + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 605 .loc 1 434 21 is_stmt 0 view .LVU188 + 606 0196 FFF7FEFF bl HAL_GetTick + 607 .LVL46: + 608 019a 0500 movs r5, r0 + 609 .LVL47: + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 610 .loc 1 437 9 is_stmt 1 view .LVU189 + 611 .L38: + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 612 .loc 1 437 15 view .LVU190 + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 613 .loc 1 437 16 is_stmt 0 view .LVU191 + 614 019c 5E4B ldr r3, .L117 + 615 019e 1B68 ldr r3, [r3] + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 616 .loc 1 437 15 view .LVU192 + 617 01a0 5B05 lsls r3, r3, #21 + 618 01a2 06D4 bmi .L106 + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 619 .loc 1 439 11 is_stmt 1 view .LVU193 + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 620 .loc 1 439 16 is_stmt 0 view .LVU194 + ARM GAS /tmp/ccBwposX.s page 22 + + + 621 01a4 FFF7FEFF bl HAL_GetTick + 622 .LVL48: + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 623 .loc 1 439 30 view .LVU195 + 624 01a8 401B subs r0, r0, r5 + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 625 .loc 1 439 14 view .LVU196 + 626 01aa 0228 cmp r0, #2 + 627 01ac F6D9 bls .L38 + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 628 .loc 1 441 20 view .LVU197 + 629 01ae 0320 movs r0, #3 + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 630 .loc 1 441 20 view .LVU198 + 631 01b0 61E1 b .L18 + 632 .L106: + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 633 .loc 1 446 9 is_stmt 1 view .LVU199 + 634 01b2 5949 ldr r1, .L117 + 635 01b4 4B68 ldr r3, [r1, #4] + 636 01b6 5B4A ldr r2, .L117+12 + 637 01b8 1340 ands r3, r2 + 638 01ba 6269 ldr r2, [r4, #20] + 639 01bc 1202 lsls r2, r2, #8 + 640 01be 1343 orrs r3, r2 + 641 01c0 4B60 str r3, [r1, #4] + 642 01c2 94E7 b .L31 + 643 .LVL49: + 644 .L37: + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 645 .loc 1 451 9 view .LVU200 + 646 01c4 544A ldr r2, .L117 + 647 .LVL50: + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 648 .loc 1 451 9 is_stmt 0 view .LVU201 + 649 01c6 1368 ldr r3, [r2] + 650 01c8 5B49 ldr r1, .L117+32 + 651 .LVL51: + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 652 .loc 1 451 9 view .LVU202 + 653 01ca 0B40 ands r3, r1 + 654 01cc 1360 str r3, [r2] + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 655 .loc 1 454 9 is_stmt 1 view .LVU203 + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 656 .loc 1 454 21 is_stmt 0 view .LVU204 + 657 01ce FFF7FEFF bl HAL_GetTick + 658 .LVL52: + 659 01d2 0500 movs r5, r0 + 660 .LVL53: + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 661 .loc 1 457 9 is_stmt 1 view .LVU205 + 662 .L40: + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 663 .loc 1 457 15 view .LVU206 + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 664 .loc 1 457 16 is_stmt 0 view .LVU207 + ARM GAS /tmp/ccBwposX.s page 23 + + + 665 01d4 504B ldr r3, .L117 + 666 01d6 1B68 ldr r3, [r3] + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 667 .loc 1 457 15 view .LVU208 + 668 01d8 5B05 lsls r3, r3, #21 + 669 01da 88D5 bpl .L31 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 670 .loc 1 459 11 is_stmt 1 view .LVU209 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 671 .loc 1 459 16 is_stmt 0 view .LVU210 + 672 01dc FFF7FEFF bl HAL_GetTick + 673 .LVL54: + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 674 .loc 1 459 30 view .LVU211 + 675 01e0 401B subs r0, r0, r5 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 676 .loc 1 459 14 view .LVU212 + 677 01e2 0228 cmp r0, #2 + 678 01e4 F6D9 bls .L40 + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 679 .loc 1 461 20 view .LVU213 + 680 01e6 0320 movs r0, #3 + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 681 .loc 1 461 20 view .LVU214 + 682 01e8 45E1 b .L18 + 683 .LVL55: + 684 .L105: + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 685 .loc 1 477 7 is_stmt 1 view .LVU215 + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 686 .loc 1 477 17 is_stmt 0 view .LVU216 + 687 01ea 4B4B ldr r3, .L117 + 688 01ec 1B6E ldr r3, [r3, #96] + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 689 .loc 1 477 10 view .LVU217 + 690 01ee 9B07 lsls r3, r3, #30 + 691 01f0 03D5 bpl .L42 + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 692 .loc 1 477 49 discriminator 1 view .LVU218 + 693 01f2 A369 ldr r3, [r4, #24] + 694 01f4 002B cmp r3, #0 + 695 01f6 00D1 bne .LCB626 + 696 01f8 45E1 b .L107 @long jump + 697 .LCB626: + 698 .L42: + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till LSI is disabled */ + ARM GAS /tmp/ccBwposX.s page 24 + + + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 699 .loc 1 522 3 is_stmt 1 view .LVU219 + 700 .loc 1 522 6 is_stmt 0 view .LVU220 + 701 01fa 2368 ldr r3, [r4] + 702 01fc 5B07 lsls r3, r3, #29 + 703 01fe 00D4 bmi .LCB635 + 704 0200 A2E0 b .L49 @long jump + 705 .LCB635: + 706 .LBB4: + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; + 707 .loc 1 524 5 is_stmt 1 view .LVU221 + 708 .LVL56: + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 709 .loc 1 527 5 view .LVU222 + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* When the LSE is used as system clock, it is not allowed disable it */ + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + 710 .loc 1 530 5 view .LVU223 + 711 .loc 1 530 9 is_stmt 0 view .LVU224 + 712 0202 454B ldr r3, .L117 + 713 0204 9A68 ldr r2, [r3, #8] + 714 0206 3823 movs r3, #56 + 715 0208 1340 ands r3, r2 + 716 .loc 1 530 8 view .LVU225 + 717 020a 202B cmp r3, #32 + 718 020c 45D0 beq .L108 + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + 719 .loc 1 541 7 is_stmt 1 view .LVU226 + 720 .loc 1 541 11 is_stmt 0 view .LVU227 + 721 020e 424B ldr r3, .L117 + 722 0210 DB6B ldr r3, [r3, #60] + 723 .loc 1 541 43 view .LVU228 + 724 0212 DB00 lsls r3, r3, #3 + ARM GAS /tmp/ccBwposX.s page 25 + + + 725 0214 4AD4 bmi .L84 + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 726 .loc 1 543 9 is_stmt 1 view .LVU229 + 727 .LBB5: + 728 .loc 1 543 9 view .LVU230 + 729 .loc 1 543 9 view .LVU231 + 730 0216 404A ldr r2, .L117 + 731 0218 D16B ldr r1, [r2, #60] + 732 021a 8020 movs r0, #128 + 733 021c 4005 lsls r0, r0, #21 + 734 021e 0143 orrs r1, r0 + 735 0220 D163 str r1, [r2, #60] + 736 .loc 1 543 9 view .LVU232 + 737 0222 D36B ldr r3, [r2, #60] + 738 0224 0340 ands r3, r0 + 739 0226 0193 str r3, [sp, #4] + 740 .loc 1 543 9 view .LVU233 + 741 0228 019B ldr r3, [sp, #4] + 742 .LBE5: + 743 .loc 1 543 9 view .LVU234 + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pwrclkchanged = SET; + 744 .loc 1 544 9 view .LVU235 + 745 .LVL57: + 746 .loc 1 544 23 is_stmt 0 view .LVU236 + 747 022a 0125 movs r5, #1 + 748 .LVL58: + 749 .L51: + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 750 .loc 1 547 7 is_stmt 1 view .LVU237 + 751 .loc 1 547 11 is_stmt 0 view .LVU238 + 752 022c 434B ldr r3, .L117+36 + 753 022e 1B68 ldr r3, [r3] + 754 .loc 1 547 10 view .LVU239 + 755 0230 DB05 lsls r3, r3, #23 + 756 0232 3DD5 bpl .L109 + 757 .L52: + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + ARM GAS /tmp/ccBwposX.s page 26 + + + 758 .loc 1 565 7 is_stmt 1 view .LVU240 + 759 .loc 1 565 7 view .LVU241 + 760 0234 A368 ldr r3, [r4, #8] + 761 0236 012B cmp r3, #1 + 762 0238 4ED0 beq .L110 + 763 .loc 1 565 7 discriminator 2 view .LVU242 + 764 023a 052B cmp r3, #5 + 765 023c 52D0 beq .L111 + 766 .loc 1 565 7 discriminator 5 view .LVU243 + 767 023e 364B ldr r3, .L117 + 768 0240 DA6D ldr r2, [r3, #92] + 769 0242 0121 movs r1, #1 + 770 0244 8A43 bics r2, r1 + 771 0246 DA65 str r2, [r3, #92] + 772 .loc 1 565 7 discriminator 5 view .LVU244 + 773 0248 DA6D ldr r2, [r3, #92] + 774 024a 0331 adds r1, r1, #3 + 775 024c 8A43 bics r2, r1 + 776 024e DA65 str r2, [r3, #92] + 777 .L56: + 778 .loc 1 565 7 discriminator 7 view .LVU245 + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the LSE State */ + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 779 .loc 1 568 7 discriminator 7 view .LVU246 + 780 .loc 1 568 10 is_stmt 0 discriminator 7 view .LVU247 + 781 0250 A368 ldr r3, [r4, #8] + 782 0252 002B cmp r3, #0 + 783 0254 50D0 beq .L58 + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 784 .loc 1 571 9 is_stmt 1 view .LVU248 + 785 .loc 1 571 21 is_stmt 0 view .LVU249 + 786 0256 FFF7FEFF bl HAL_GetTick + 787 .LVL59: + 788 025a 0600 movs r6, r0 + 789 .LVL60: + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till LSE is ready */ + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 790 .loc 1 574 9 is_stmt 1 view .LVU250 + 791 .L59: + 792 .loc 1 574 15 view .LVU251 + 793 .loc 1 574 16 is_stmt 0 view .LVU252 + 794 025c 2E4B ldr r3, .L117 + 795 025e DB6D ldr r3, [r3, #92] + 796 .loc 1 574 15 view .LVU253 + 797 0260 9B07 lsls r3, r3, #30 + 798 0262 6FD4 bmi .L61 + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 799 .loc 1 576 11 is_stmt 1 view .LVU254 + 800 .loc 1 576 16 is_stmt 0 view .LVU255 + 801 0264 FFF7FEFF bl HAL_GetTick + 802 .LVL61: + 803 .loc 1 576 30 view .LVU256 + ARM GAS /tmp/ccBwposX.s page 27 + + + 804 0268 801B subs r0, r0, r6 + 805 .loc 1 576 14 view .LVU257 + 806 026a 354B ldr r3, .L117+40 + 807 026c 9842 cmp r0, r3 + 808 026e F5D9 bls .L59 + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 809 .loc 1 578 20 view .LVU258 + 810 0270 0320 movs r0, #3 + 811 0272 00E1 b .L18 + 812 .LVL62: + 813 .L44: + 814 .loc 1 578 20 view .LVU259 + 815 .LBE4: + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 816 .loc 1 505 9 is_stmt 1 view .LVU260 + 817 0274 284A ldr r2, .L117 + 818 0276 136E ldr r3, [r2, #96] + 819 0278 0121 movs r1, #1 + 820 027a 8B43 bics r3, r1 + 821 027c 1366 str r3, [r2, #96] + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 822 .loc 1 508 9 view .LVU261 + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 823 .loc 1 508 21 is_stmt 0 view .LVU262 + 824 027e FFF7FEFF bl HAL_GetTick + 825 .LVL63: + 826 0282 0500 movs r5, r0 + 827 .LVL64: + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 828 .loc 1 511 9 is_stmt 1 view .LVU263 + 829 .L47: + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 830 .loc 1 511 15 view .LVU264 + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 831 .loc 1 511 16 is_stmt 0 view .LVU265 + 832 0284 244B ldr r3, .L117 + 833 0286 1B6E ldr r3, [r3, #96] + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 834 .loc 1 511 15 view .LVU266 + 835 0288 9B07 lsls r3, r3, #30 + 836 028a B6D5 bpl .L42 + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 837 .loc 1 513 11 is_stmt 1 view .LVU267 + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 838 .loc 1 513 16 is_stmt 0 view .LVU268 + 839 028c FFF7FEFF bl HAL_GetTick + 840 .LVL65: + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 841 .loc 1 513 30 view .LVU269 + 842 0290 401B subs r0, r0, r5 + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 843 .loc 1 513 14 view .LVU270 + 844 0292 0228 cmp r0, #2 + 845 0294 F6D9 bls .L47 + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 846 .loc 1 515 20 view .LVU271 + ARM GAS /tmp/ccBwposX.s page 28 + + + 847 0296 0320 movs r0, #3 + 848 0298 EDE0 b .L18 + 849 .LVL66: + 850 .L108: + 851 .LBB6: + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 852 .loc 1 532 7 is_stmt 1 view .LVU272 + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 853 .loc 1 532 17 is_stmt 0 view .LVU273 + 854 029a 1F4B ldr r3, .L117 + 855 029c DB6D ldr r3, [r3, #92] + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 856 .loc 1 532 10 view .LVU274 + 857 029e 9B07 lsls r3, r3, #30 + 858 02a0 52D5 bpl .L49 + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 859 .loc 1 532 51 discriminator 1 view .LVU275 + 860 02a2 A368 ldr r3, [r4, #8] + 861 02a4 002B cmp r3, #0 + 862 02a6 4FD1 bne .L49 + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 863 .loc 1 534 16 view .LVU276 + 864 02a8 0120 movs r0, #1 + 865 02aa E4E0 b .L18 + 866 .L84: + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 867 .loc 1 524 22 view .LVU277 + 868 02ac 0025 movs r5, #0 + 869 02ae BDE7 b .L51 + 870 .LVL67: + 871 .L109: + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 872 .loc 1 550 9 is_stmt 1 view .LVU278 + 873 02b0 224A ldr r2, .L117+36 + 874 02b2 1168 ldr r1, [r2] + 875 02b4 8023 movs r3, #128 + 876 02b6 5B00 lsls r3, r3, #1 + 877 02b8 0B43 orrs r3, r1 + 878 02ba 1360 str r3, [r2] + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 879 .loc 1 553 9 view .LVU279 + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 880 .loc 1 553 21 is_stmt 0 view .LVU280 + 881 02bc FFF7FEFF bl HAL_GetTick + 882 .LVL68: + 883 02c0 0600 movs r6, r0 + 884 .LVL69: + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 885 .loc 1 555 9 is_stmt 1 view .LVU281 + 886 .L53: + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 887 .loc 1 555 15 view .LVU282 + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 888 .loc 1 555 16 is_stmt 0 view .LVU283 + 889 02c2 1E4B ldr r3, .L117+36 + 890 02c4 1B68 ldr r3, [r3] + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 29 + + + 891 .loc 1 555 15 view .LVU284 + 892 02c6 DB05 lsls r3, r3, #23 + 893 02c8 B4D4 bmi .L52 + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 894 .loc 1 557 11 is_stmt 1 view .LVU285 + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 895 .loc 1 557 16 is_stmt 0 view .LVU286 + 896 02ca FFF7FEFF bl HAL_GetTick + 897 .LVL70: + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 898 .loc 1 557 30 view .LVU287 + 899 02ce 801B subs r0, r0, r6 + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 900 .loc 1 557 14 view .LVU288 + 901 02d0 0228 cmp r0, #2 + 902 02d2 F6D9 bls .L53 + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 903 .loc 1 559 20 view .LVU289 + 904 02d4 0320 movs r0, #3 + 905 02d6 CEE0 b .L18 + 906 .LVL71: + 907 .L110: + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 908 .loc 1 565 7 is_stmt 1 discriminator 1 view .LVU290 + 909 02d8 0F4A ldr r2, .L117 + 910 02da D36D ldr r3, [r2, #92] + 911 02dc 0121 movs r1, #1 + 912 02de 0B43 orrs r3, r1 + 913 02e0 D365 str r3, [r2, #92] + 914 02e2 B5E7 b .L56 + 915 .L111: + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 916 .loc 1 565 7 discriminator 4 view .LVU291 + 917 02e4 0C4B ldr r3, .L117 + 918 02e6 DA6D ldr r2, [r3, #92] + 919 02e8 0421 movs r1, #4 + 920 02ea 0A43 orrs r2, r1 + 921 02ec DA65 str r2, [r3, #92] + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 922 .loc 1 565 7 discriminator 4 view .LVU292 + 923 02ee DA6D ldr r2, [r3, #92] + 924 02f0 0339 subs r1, r1, #3 + 925 02f2 0A43 orrs r2, r1 + 926 02f4 DA65 str r2, [r3, #92] + 927 02f6 ABE7 b .L56 + 928 .L58: + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 929 .loc 1 585 9 view .LVU293 + 930 .loc 1 585 21 is_stmt 0 view .LVU294 + 931 02f8 FFF7FEFF bl HAL_GetTick + 932 .LVL72: + ARM GAS /tmp/ccBwposX.s page 30 + + + 933 02fc 0600 movs r6, r0 + 934 .LVL73: + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till LSE is disabled */ + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + 935 .loc 1 588 9 is_stmt 1 view .LVU295 + 936 .L62: + 937 .loc 1 588 15 view .LVU296 + 938 .loc 1 588 16 is_stmt 0 view .LVU297 + 939 02fe 064B ldr r3, .L117 + 940 0300 DB6D ldr r3, [r3, #92] + 941 .loc 1 588 15 view .LVU298 + 942 0302 9B07 lsls r3, r3, #30 + 943 0304 1ED5 bpl .L61 + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 944 .loc 1 590 11 is_stmt 1 view .LVU299 + 945 .loc 1 590 16 is_stmt 0 view .LVU300 + 946 0306 FFF7FEFF bl HAL_GetTick + 947 .LVL74: + 948 .loc 1 590 30 view .LVU301 + 949 030a 801B subs r0, r0, r6 + 950 .loc 1 590 14 view .LVU302 + 951 030c 0C4B ldr r3, .L117+40 + 952 030e 9842 cmp r0, r3 + 953 0310 F5D9 bls .L62 + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 954 .loc 1 592 20 view .LVU303 + 955 0312 0320 movs r0, #3 + 956 0314 AFE0 b .L18 + 957 .L118: + 958 0316 C046 .align 2 + 959 .L117: + 960 0318 00100240 .word 1073876992 + 961 031c FFFFFEFF .word -65537 + 962 0320 FFFFFBFF .word -262145 + 963 0324 FF80FFFF .word -32513 + 964 0328 FFC7FFFF .word -14337 + 965 032c 0024F400 .word 16000000 + 966 0330 00000000 .word SystemCoreClock + 967 0334 00000000 .word uwTickPrio + 968 0338 FFFEFFFF .word -257 + 969 033c 00700040 .word 1073770496 + 970 0340 88130000 .word 5000 + 971 .L61: + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Restore clock configuration if changed */ + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (pwrclkchanged == SET) + 972 .loc 1 598 7 is_stmt 1 view .LVU304 + 973 .loc 1 598 10 is_stmt 0 view .LVU305 + 974 0344 012D cmp r5, #1 + 975 0346 26D0 beq .L112 + 976 .LVL75: + ARM GAS /tmp/ccBwposX.s page 31 + + + 977 .L49: + 978 .loc 1 598 10 view .LVU306 + 979 .LBE6: + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*------------------------------ HSI48 Configuration -----------------------*/ + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the LSI State */ + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (HSI48). */ + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI48_ENABLE(); + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI48 is ready */ + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (HSI48). */ + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_HSI48_DISABLE(); + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till HSI48 is disabled */ + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 980 .loc 1 650 3 is_stmt 1 view .LVU307 + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + ARM GAS /tmp/ccBwposX.s page 32 + + + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 981 .loc 1 652 3 view .LVU308 + 982 .loc 1 652 29 is_stmt 0 view .LVU309 + 983 0348 E369 ldr r3, [r4, #28] + 984 .loc 1 652 6 view .LVU310 + 985 034a 002B cmp r3, #0 + 986 034c 00D1 bne .LCB921 + 987 034e 9CE0 b .L88 @long jump + 988 .LCB921: + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 989 .loc 1 655 5 is_stmt 1 view .LVU311 + 990 .loc 1 655 9 is_stmt 0 view .LVU312 + 991 0350 564A ldr r2, .L119 + 992 0352 9168 ldr r1, [r2, #8] + 993 0354 3822 movs r2, #56 + 994 0356 0A40 ands r2, r1 + 995 .loc 1 655 8 view .LVU313 + 996 0358 102A cmp r2, #16 + 997 035a 63D0 beq .L64 + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 998 .loc 1 657 7 is_stmt 1 view .LVU314 + 999 .loc 1 657 10 is_stmt 0 view .LVU315 + 1000 035c 022B cmp r3, #2 + 1001 035e 20D0 beq .L113 + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_PLLQ_SUPPORT) + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable the main PLL. */ + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till PLL is ready */ + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the main PLL clock source, multiplication and division factors. */ + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN, + ARM GAS /tmp/ccBwposX.s page 33 + + + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP, + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_PLLQ_SUPPORT) + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ, + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR); + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable the main PLL. */ + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Enable PLLR Clock output. */ + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till PLL is ready */ + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable the main PLL. */ + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 1002 .loc 1 715 9 is_stmt 1 view .LVU316 + 1003 0360 524B ldr r3, .L119 + 1004 0362 1A68 ldr r2, [r3] + 1005 0364 5249 ldr r1, .L119+4 + 1006 0366 0A40 ands r2, r1 + 1007 0368 1A60 str r2, [r3] + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Disable all PLL outputs to save power */ + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); + 1008 .loc 1 718 9 view .LVU317 + 1009 036a DA68 ldr r2, [r3, #12] + 1010 036c 0321 movs r1, #3 + 1011 036e 8A43 bics r2, r1 + 1012 0370 DA60 str r2, [r3, #12] + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_PLLQ_SUPPORT) + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); + 1013 .loc 1 721 9 view .LVU318 + 1014 0372 DA68 ldr r2, [r3, #12] + 1015 0374 4F49 ldr r1, .L119+8 + 1016 0376 0A40 ands r2, r1 + 1017 0378 DA60 str r2, [r3, #12] + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #else + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1018 .loc 1 727 9 view .LVU319 + ARM GAS /tmp/ccBwposX.s page 34 + + + 1019 .loc 1 727 21 is_stmt 0 view .LVU320 + 1020 037a FFF7FEFF bl HAL_GetTick + 1021 .LVL76: + 1022 037e 0400 movs r4, r0 + 1023 .LVL77: + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 1024 .loc 1 730 9 is_stmt 1 view .LVU321 + 1025 .L70: + 1026 .loc 1 730 15 view .LVU322 + 1027 .loc 1 730 16 is_stmt 0 view .LVU323 + 1028 0380 4A4B ldr r3, .L119 + 1029 0382 1B68 ldr r3, [r3] + 1030 .loc 1 730 15 view .LVU324 + 1031 0384 9B01 lsls r3, r3, #6 + 1032 0386 4BD5 bpl .L114 + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 1033 .loc 1 732 11 is_stmt 1 view .LVU325 + 1034 .loc 1 732 16 is_stmt 0 view .LVU326 + 1035 0388 FFF7FEFF bl HAL_GetTick + 1036 .LVL78: + 1037 .loc 1 732 30 view .LVU327 + 1038 038c 001B subs r0, r0, r4 + 1039 .loc 1 732 14 view .LVU328 + 1040 038e 0228 cmp r0, #2 + 1041 0390 F6D9 bls .L70 + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 1042 .loc 1 734 20 view .LVU329 + 1043 0392 0320 movs r0, #3 + 1044 0394 6FE0 b .L18 + 1045 .LVL79: + 1046 .L112: + 1047 .LBB7: + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1048 .loc 1 600 9 is_stmt 1 view .LVU330 + 1049 0396 454A ldr r2, .L119 + 1050 0398 D36B ldr r3, [r2, #60] + 1051 039a 4749 ldr r1, .L119+12 + 1052 039c 0B40 ands r3, r1 + 1053 039e D363 str r3, [r2, #60] + 1054 03a0 D2E7 b .L49 + 1055 .LVL80: + 1056 .L113: + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1057 .loc 1 600 9 is_stmt 0 view .LVU331 + 1058 .LBE7: + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + 1059 .loc 1 660 9 is_stmt 1 view .LVU332 + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + 1060 .loc 1 661 9 view .LVU333 + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + 1061 .loc 1 662 9 view .LVU334 + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_PLLQ_SUPPORT) + 1062 .loc 1 663 9 view .LVU335 + ARM GAS /tmp/ccBwposX.s page 35 + + + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 1063 .loc 1 665 9 view .LVU336 + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1064 .loc 1 667 9 view .LVU337 + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1065 .loc 1 670 9 view .LVU338 + 1066 03a2 424A ldr r2, .L119 + 1067 03a4 1368 ldr r3, [r2] + 1068 03a6 4249 ldr r1, .L119+4 + 1069 03a8 0B40 ands r3, r1 + 1070 03aa 1360 str r3, [r2] + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1071 .loc 1 673 9 view .LVU339 + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1072 .loc 1 673 21 is_stmt 0 view .LVU340 + 1073 03ac FFF7FEFF bl HAL_GetTick + 1074 .LVL81: + 1075 03b0 0500 movs r5, r0 + 1076 .LVL82: + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1077 .loc 1 676 9 is_stmt 1 view .LVU341 + 1078 .L66: + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1079 .loc 1 676 15 view .LVU342 + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1080 .loc 1 676 16 is_stmt 0 view .LVU343 + 1081 03b2 3E4B ldr r3, .L119 + 1082 03b4 1B68 ldr r3, [r3] + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1083 .loc 1 676 15 view .LVU344 + 1084 03b6 9B01 lsls r3, r3, #6 + 1085 03b8 06D5 bpl .L115 + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1086 .loc 1 678 11 is_stmt 1 view .LVU345 + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1087 .loc 1 678 16 is_stmt 0 view .LVU346 + 1088 03ba FFF7FEFF bl HAL_GetTick + 1089 .LVL83: + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1090 .loc 1 678 30 view .LVU347 + 1091 03be 401B subs r0, r0, r5 + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1092 .loc 1 678 14 view .LVU348 + 1093 03c0 0228 cmp r0, #2 + 1094 03c2 F6D9 bls .L66 + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1095 .loc 1 680 20 view .LVU349 + 1096 03c4 0320 movs r0, #3 + 1097 03c6 56E0 b .L18 + 1098 .L115: + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM, + 1099 .loc 1 685 9 is_stmt 1 view .LVU350 + 1100 03c8 384A ldr r2, .L119 + 1101 03ca D368 ldr r3, [r2, #12] + 1102 03cc 3B49 ldr r1, .L119+16 + 1103 03ce 1940 ands r1, r3 + 1104 03d0 236A ldr r3, [r4, #32] + ARM GAS /tmp/ccBwposX.s page 36 + + + 1105 03d2 606A ldr r0, [r4, #36] + 1106 03d4 0343 orrs r3, r0 + 1107 03d6 A06A ldr r0, [r4, #40] + 1108 03d8 0002 lsls r0, r0, #8 + 1109 03da 0343 orrs r3, r0 + 1110 03dc E06A ldr r0, [r4, #44] + 1111 03de 0343 orrs r3, r0 + 1112 03e0 206B ldr r0, [r4, #48] + 1113 03e2 0343 orrs r3, r0 + 1114 03e4 606B ldr r0, [r4, #52] + 1115 03e6 0343 orrs r3, r0 + 1116 03e8 0B43 orrs r3, r1 + 1117 03ea D360 str r3, [r2, #12] + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1118 .loc 1 695 9 view .LVU351 + 1119 03ec 1168 ldr r1, [r2] + 1120 03ee 8023 movs r3, #128 + 1121 03f0 5B04 lsls r3, r3, #17 + 1122 03f2 0B43 orrs r3, r1 + 1123 03f4 1360 str r3, [r2] + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1124 .loc 1 698 9 view .LVU352 + 1125 03f6 D168 ldr r1, [r2, #12] + 1126 03f8 8023 movs r3, #128 + 1127 03fa 5B05 lsls r3, r3, #21 + 1128 03fc 0B43 orrs r3, r1 + 1129 03fe D360 str r3, [r2, #12] + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1130 .loc 1 701 9 view .LVU353 + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1131 .loc 1 701 21 is_stmt 0 view .LVU354 + 1132 0400 FFF7FEFF bl HAL_GetTick + 1133 .LVL84: + 1134 0404 0400 movs r4, r0 + 1135 .LVL85: + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1136 .loc 1 704 9 is_stmt 1 view .LVU355 + 1137 .L68: + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1138 .loc 1 704 15 view .LVU356 + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1139 .loc 1 704 16 is_stmt 0 view .LVU357 + 1140 0406 294B ldr r3, .L119 + 1141 0408 1B68 ldr r3, [r3] + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1142 .loc 1 704 15 view .LVU358 + 1143 040a 9B01 lsls r3, r3, #6 + 1144 040c 06D4 bmi .L116 + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1145 .loc 1 706 11 is_stmt 1 view .LVU359 + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1146 .loc 1 706 16 is_stmt 0 view .LVU360 + 1147 040e FFF7FEFF bl HAL_GetTick + 1148 .LVL86: + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1149 .loc 1 706 30 view .LVU361 + 1150 0412 001B subs r0, r0, r4 + ARM GAS /tmp/ccBwposX.s page 37 + + + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1151 .loc 1 706 14 view .LVU362 + 1152 0414 0228 cmp r0, #2 + 1153 0416 F6D9 bls .L68 + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1154 .loc 1 708 20 view .LVU363 + 1155 0418 0320 movs r0, #3 + 1156 041a 2CE0 b .L18 + 1157 .L116: + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check if there is a request to disable the PLL used as System clock source */ + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** temp_pllckcfg = RCC->PLLCFGR; + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCF + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined (RCC_PLLQ_SUPPORT) + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_OK; + 1158 .loc 1 764 10 view .LVU364 + 1159 041c 0020 movs r0, #0 + 1160 041e 2AE0 b .L18 + 1161 .L114: + 1162 .loc 1 764 10 view .LVU365 + 1163 0420 0020 movs r0, #0 + 1164 0422 28E0 b .L18 + 1165 .LVL87: + 1166 .L64: + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1167 .loc 1 742 7 is_stmt 1 view .LVU366 + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1168 .loc 1 742 10 is_stmt 0 view .LVU367 + 1169 0424 012B cmp r3, #1 + 1170 0426 32D0 beq .L92 + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 1171 .loc 1 749 9 is_stmt 1 view .LVU368 + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ARM GAS /tmp/ccBwposX.s page 38 + + + 1172 .loc 1 749 23 is_stmt 0 view .LVU369 + 1173 0428 204B ldr r3, .L119 + 1174 042a DA68 ldr r2, [r3, #12] + 1175 .LVL88: + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1176 .loc 1 750 9 is_stmt 1 view .LVU370 + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1177 .loc 1 750 14 is_stmt 0 view .LVU371 + 1178 042c 0323 movs r3, #3 + 1179 042e 1340 ands r3, r2 + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1180 .loc 1 750 12 view .LVU372 + 1181 0430 216A ldr r1, [r4, #32] + 1182 0432 8B42 cmp r3, r1 + 1183 0434 2DD1 bne .L93 + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCF + 1184 .loc 1 751 14 discriminator 1 view .LVU373 + 1185 0436 7023 movs r3, #112 + 1186 0438 1340 ands r3, r2 + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 1187 .loc 1 750 95 discriminator 1 view .LVU374 + 1188 043a 616A ldr r1, [r4, #36] + 1189 043c 8B42 cmp r3, r1 + 1190 043e 2AD1 bne .L94 + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 1191 .loc 1 752 14 view .LVU375 + 1192 0440 FE21 movs r1, #254 + 1193 0442 C901 lsls r1, r1, #7 + 1194 0444 1140 ands r1, r2 + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 1195 .loc 1 752 88 view .LVU376 + 1196 0446 A36A ldr r3, [r4, #40] + 1197 0448 1B02 lsls r3, r3, #8 + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCF + 1198 .loc 1 751 88 view .LVU377 + 1199 044a 9942 cmp r1, r3 + 1200 044c 25D1 bne .L95 + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined (RCC_PLLQ_SUPPORT) + 1201 .loc 1 753 14 view .LVU378 + 1202 044e F823 movs r3, #248 + 1203 0450 9B03 lsls r3, r3, #14 + 1204 0452 1340 ands r3, r2 + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 1205 .loc 1 752 114 view .LVU379 + 1206 0454 E16A ldr r1, [r4, #44] + 1207 0456 8B42 cmp r3, r1 + 1208 0458 21D1 bne .L96 + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 1209 .loc 1 755 14 view .LVU380 + 1210 045a E023 movs r3, #224 + 1211 045c 1B05 lsls r3, r3, #20 + 1212 045e 1340 ands r3, r2 + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined (RCC_PLLQ_SUPPORT) + 1213 .loc 1 753 88 view .LVU381 + 1214 0460 216B ldr r1, [r4, #48] + 1215 0462 8B42 cmp r3, r1 + 1216 0464 1DD1 bne .L97 + ARM GAS /tmp/ccBwposX.s page 39 + + + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1217 .loc 1 757 14 view .LVU382 + 1218 0466 520F lsrs r2, r2, #29 + 1219 .LVL89: + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1220 .loc 1 757 14 view .LVU383 + 1221 0468 5207 lsls r2, r2, #29 + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1222 .loc 1 757 81 view .LVU384 + 1223 046a 636B ldr r3, [r4, #52] + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ + 1224 .loc 1 755 88 view .LVU385 + 1225 046c 9A42 cmp r2, r3 + 1226 046e 1AD1 bne .L98 + 1227 .loc 1 764 10 view .LVU386 + 1228 0470 0020 movs r0, #0 + 1229 0472 00E0 b .L18 + 1230 .LVL90: + 1231 .L72: + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1232 .loc 1 321 12 view .LVU387 + 1233 0474 0120 movs r0, #1 + 1234 .LVL91: + 1235 .L18: + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1236 .loc 1 765 1 view .LVU388 + 1237 0476 02B0 add sp, sp, #8 + 1238 @ sp needed + 1239 0478 70BD pop {r4, r5, r6, pc} + 1240 .LVL92: + 1241 .L102: + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1242 .loc 1 342 16 view .LVU389 + 1243 047a 0120 movs r0, #1 + 1244 .LVL93: + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1245 .loc 1 342 16 view .LVU390 + 1246 047c FBE7 b .L18 + 1247 .LVL94: + 1248 .L76: + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1249 .loc 1 398 16 view .LVU391 + 1250 047e 0120 movs r0, #1 + 1251 0480 F9E7 b .L18 + 1252 .LVL95: + 1253 .L104: + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1254 .loc 1 418 18 view .LVU392 + 1255 0482 0120 movs r0, #1 + 1256 0484 F7E7 b .L18 + 1257 .L107: + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1258 .loc 1 479 16 view .LVU393 + 1259 0486 0120 movs r0, #1 + 1260 0488 F5E7 b .L18 + 1261 .L88: + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + ARM GAS /tmp/ccBwposX.s page 40 + + + 1262 .loc 1 764 10 view .LVU394 + 1263 048a 0020 movs r0, #0 + 1264 048c F3E7 b .L18 + 1265 .L92: + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1266 .loc 1 744 16 view .LVU395 + 1267 048e 0120 movs r0, #1 + 1268 0490 F1E7 b .L18 + 1269 .LVL96: + 1270 .L93: + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1271 .loc 1 759 18 view .LVU396 + 1272 0492 0120 movs r0, #1 + 1273 0494 EFE7 b .L18 + 1274 .L94: + 1275 0496 0120 movs r0, #1 + 1276 0498 EDE7 b .L18 + 1277 .L95: + 1278 049a 0120 movs r0, #1 + 1279 049c EBE7 b .L18 + 1280 .L96: + 1281 049e 0120 movs r0, #1 + 1282 04a0 E9E7 b .L18 + 1283 .L97: + 1284 04a2 0120 movs r0, #1 + 1285 04a4 E7E7 b .L18 + 1286 .LVL97: + 1287 .L98: + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1288 .loc 1 759 18 view .LVU397 + 1289 04a6 0120 movs r0, #1 + 1290 04a8 E5E7 b .L18 + 1291 .L120: + 1292 04aa C046 .align 2 + 1293 .L119: + 1294 04ac 00100240 .word 1073876992 + 1295 04b0 FFFFFFFE .word -16777217 + 1296 04b4 FFFFFEEE .word -285278209 + 1297 04b8 FFFFFFEF .word -268435457 + 1298 04bc 8C80C111 .word 297894028 + 1299 .cfi_endproc + 1300 .LFE298: + 1302 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 1303 .align 1 + 1304 .global HAL_RCC_MCOConfig + 1305 .syntax unified + 1306 .code 16 + 1307 .thumb_func + 1308 .fpu softvfp + 1310 HAL_RCC_MCOConfig: + 1311 .LVL98: + 1312 .LFB300: + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Initialize the CPU, AHB and APB buses clocks according to the specified + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that + ARM GAS /tmp/ccBwposX.s page 41 + + + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param FLatency FLASH Latency + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * This parameter can be one of the following values: + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The HSI is used by default as system clock source after + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * the HSI frequency is set to 8 Mhz, then it reaches its default value 16 MHz. + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The HSI can be selected as system clock source after + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * from STOP modes or in case of failure of the HSE used directly or indirectly + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * as system clock (if the Clock Security System CSS is enabled). + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The LSI can be selected as system clock source after + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * in case of failure of the LSE used directly or indirectly + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * as system clock (if the Clock Security System LSECSS is enabled). + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * clock source is ready (clock stable after startup delay or PLL locked). + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * occur when the clock source is ready. + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * currently used as system clock source. + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Depending on the device voltage range, the software has to set correctly + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * (for more details refer to section above "Initialization/de-initialization functions") + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t tickstart; + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check Null pointer */ + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_ClkInitStruct == NULL) + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** must be correctly programmed according to the frequency of the FLASH clock + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (HCLK) and the supply voltage of the device. */ + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (FLatency > __HAL_FLASH_GET_LATENCY()) + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + ARM GAS /tmp/ccBwposX.s page 42 + + + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** memory by polling the FLASH_ACR register */ + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set the highest APB divider in order to ensure that we do not go through + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** a non-spec phase whatever we decrease or increase HCLK. */ + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set the new HCLK clock divider */ + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the HSE ready flag */ + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the PLL ready flag */ + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the HSI ready flag */ + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + ARM GAS /tmp/ccBwposX.s page 43 + + + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* LSI is selected as System Clock Source */ + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the LSI ready flag */ + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* LSE is selected as System Clock Source */ + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the LSE ready flag */ + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_ERROR; + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get Start Tick*/ + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (FLatency < __HAL_FLASH_GET_LATENCY()) + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** memory by polling the FLASH_ACR register */ + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_TIMEOUT; + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + ARM GAS /tmp/ccBwposX.s page 44 + + + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RC + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return HAL_InitTick(uwTickPrio); + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @} + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief RCC clocks control functions + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** @verbatim + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** =============================================================================== + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** ##### Peripheral Control functions ##### + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** =============================================================================== + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** [..] + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** This subsection provides a set of functions allowing to: + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) Output clock to MCO pin. + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) Retrieve current clock frequencies. + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** (+) Enable the Clock Security System. + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** @endverbatim + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @{ + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*). + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note PA8, PA10(*) should be configured in alternate function mode. + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * For STM32G0xx family this parameter can have only one value: + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA10)(*). + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * This parameter can be one of the following values: + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices wit + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*) + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*) + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*) + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*) + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*) + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*) + ARM GAS /tmp/ccBwposX.s page 45 + + + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices wi +1000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source(*) +1001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source(*) +1002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_PLLCLK main PLLR clock selected as MCO2 source(*) +1003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source(*) +1004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source(*) +1005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP clock selected as MCO2 source(*) +1006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ clock selected as MCO2 source(*) +1007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source(*) +1008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_Wakeup selected as MCO2 source(*) +1009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO prescaler. +1010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * This parameter can be one of the following values: +1011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock +1012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock +1013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock +1014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock +1015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock +1017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock +1018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock +1019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_1 no division applied to MCO2 clock(*) +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_2 division by 2 applied to MCO2 clock(*) +1021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_4 division by 4 applied to MCO2 clock(*) +1022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_8 division by 8 applied to MCO2 clock(*) +1023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_16 division by 16 applied to MCO2 clock(*) +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_32 division by 32 applied to MCO2 clock(*) +1025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_64 division by 64 applied to MCO2 clock(*) +1026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_128 division by 128 applied to MCO2 clock(*) +1027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_256 division by 256 applied to MCO2 clock(*) +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_512 division by 512 applied to MCO2 clock(*) +1029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @arg @ref RCC_MCO2DIV_1024 division by 1024 applied to MCO2 clock(*) +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * (*) Feature not available on all devices of the family +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +1035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1313 .loc 1 1035 1 is_stmt 1 view -0 + 1314 .cfi_startproc + 1315 @ args = 0, pretend = 0, frame = 24 + 1316 @ frame_needed = 0, uses_anonymous_args = 0 + 1317 .loc 1 1035 1 is_stmt 0 view .LVU399 + 1318 0000 70B5 push {r4, r5, r6, lr} + 1319 .LCFI3: + 1320 .cfi_def_cfa_offset 16 + 1321 .cfi_offset 4, -16 + 1322 .cfi_offset 5, -12 + 1323 .cfi_offset 6, -8 + 1324 .cfi_offset 14, -4 + 1325 0002 86B0 sub sp, sp, #24 + 1326 .LCFI4: + 1327 .cfi_def_cfa_offset 40 + 1328 0004 0C00 movs r4, r1 + 1329 0006 1500 movs r5, r2 +1036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitTypeDef GPIO_InitStruct; + 1330 .loc 1 1036 3 is_stmt 1 view .LVU400 +1037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + ARM GAS /tmp/ccBwposX.s page 46 + + +1038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ +1039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); + 1331 .loc 1 1039 3 view .LVU401 +1040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Common GPIO init parameters */ +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1332 .loc 1 1042 3 view .LVU402 + 1333 .loc 1 1042 29 is_stmt 0 view .LVU403 + 1334 0008 0223 movs r3, #2 + 1335 000a 0293 str r3, [sp, #8] +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1336 .loc 1 1043 3 is_stmt 1 view .LVU404 + 1337 .loc 1 1043 29 is_stmt 0 view .LVU405 + 1338 000c 0133 adds r3, r3, #1 + 1339 000e 0493 str r3, [sp, #16] +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1340 .loc 1 1044 3 is_stmt 1 view .LVU406 + 1341 .loc 1 1044 29 is_stmt 0 view .LVU407 + 1342 0010 0023 movs r3, #0 + 1343 0012 0393 str r3, [sp, #12] +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (RCC_MCOx == RCC_MCO1) + 1344 .loc 1 1046 3 is_stmt 1 view .LVU408 + 1345 .loc 1 1046 6 is_stmt 0 view .LVU409 + 1346 0014 0028 cmp r0, #0 + 1347 0016 01D0 beq .L123 + 1348 .LVL99: + 1349 .L121: +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); +1050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* MCO1 Clock Enable */ +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MCO1_CLK_ENABLE(); +1052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO1_PIN; +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); +1056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); +1058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_MCO2_SUPPORT) +1060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (RCC_MCOx == RCC_MCO2) +1061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCO2DIV(RCC_MCODiv)); +1063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); +1064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* MCO2 Clock Enable */ +1065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MCO2_CLK_ENABLE(); +1066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO2 pin in alternate function mode */ +1067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Pin = MCO2_PIN; +1068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF3_MCO2; +1069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ +1071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv)); +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_MCO2_SUPPORT */ +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1350 .loc 1 1074 1 view .LVU410 + ARM GAS /tmp/ccBwposX.s page 47 + + + 1351 0018 06B0 add sp, sp, #24 + 1352 @ sp needed + 1353 .LVL100: + 1354 .loc 1 1074 1 view .LVU411 + 1355 001a 70BD pop {r4, r5, r6, pc} + 1356 .LVL101: + 1357 .L123: +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + 1358 .loc 1 1048 5 is_stmt 1 view .LVU412 +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* MCO1 Clock Enable */ + 1359 .loc 1 1049 5 view .LVU413 +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1360 .loc 1 1051 5 view .LVU414 + 1361 .LBB8: +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1362 .loc 1 1051 5 view .LVU415 +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1363 .loc 1 1051 5 view .LVU416 + 1364 001c 0C4E ldr r6, .L124 + 1365 001e 726B ldr r2, [r6, #52] + 1366 .LVL102: +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1367 .loc 1 1051 5 is_stmt 0 view .LVU417 + 1368 0020 0133 adds r3, r3, #1 + 1369 0022 1A43 orrs r2, r3 + 1370 0024 7263 str r2, [r6, #52] +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1371 .loc 1 1051 5 is_stmt 1 view .LVU418 + 1372 0026 726B ldr r2, [r6, #52] + 1373 0028 1340 ands r3, r2 + 1374 002a 0093 str r3, [sp] +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1375 .loc 1 1051 5 view .LVU419 + 1376 002c 009B ldr r3, [sp] + 1377 .LBE8: +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 1378 .loc 1 1051 5 view .LVU420 +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1379 .loc 1 1053 5 view .LVU421 +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + 1380 .loc 1 1053 25 is_stmt 0 view .LVU422 + 1381 002e 8023 movs r3, #128 + 1382 0030 5B00 lsls r3, r3, #1 + 1383 0032 0193 str r3, [sp, #4] +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + 1384 .loc 1 1054 5 is_stmt 1 view .LVU423 +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + 1385 .loc 1 1054 31 is_stmt 0 view .LVU424 + 1386 0034 0023 movs r3, #0 + 1387 0036 0593 str r3, [sp, #20] +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + 1388 .loc 1 1055 5 is_stmt 1 view .LVU425 + 1389 0038 A030 adds r0, r0, #160 + 1390 .LVL103: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + 1391 .loc 1 1055 5 is_stmt 0 view .LVU426 + 1392 003a 01A9 add r1, sp, #4 + ARM GAS /tmp/ccBwposX.s page 48 + + + 1393 .LVL104: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + 1394 .loc 1 1055 5 view .LVU427 + 1395 003c C005 lsls r0, r0, #23 + 1396 .LVL105: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + 1397 .loc 1 1055 5 view .LVU428 + 1398 003e FFF7FEFF bl HAL_GPIO_Init + 1399 .LVL106: +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1400 .loc 1 1057 5 is_stmt 1 view .LVU429 + 1401 0042 B268 ldr r2, [r6, #8] + 1402 0044 0349 ldr r1, .L124+4 + 1403 0046 0A40 ands r2, r1 + 1404 0048 2C43 orrs r4, r5 + 1405 .LVL107: +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1406 .loc 1 1057 5 is_stmt 0 view .LVU430 + 1407 004a 1443 orrs r4, r2 + 1408 004c B460 str r4, [r6, #8] + 1409 .loc 1 1074 1 view .LVU431 + 1410 004e E3E7 b .L121 + 1411 .L125: + 1412 .align 2 + 1413 .L124: + 1414 0050 00100240 .word 1073876992 + 1415 0054 FFFFFF88 .word -1996488705 + 1416 .cfi_endproc + 1417 .LFE300: + 1419 .global __aeabi_uidiv + 1420 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 1421 .align 1 + 1422 .global HAL_RCC_GetSysClockFreq + 1423 .syntax unified + 1424 .code 16 + 1425 .thumb_func + 1426 .fpu softvfp + 1428 HAL_RCC_GetSysClockFreq: + 1429 .LFB301: +1075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Return the SYSCLK frequency. +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real +1080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * constant and the selected clock source: +1082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*) +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) +1084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), +1085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. +1086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(***) +1087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(****) +1088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value +1089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * 16 MHz) but the real value may vary depending on the variations +1090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * in voltage and temperature. +1091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value +1092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + ARM GAS /tmp/ccBwposX.s page 49 + + +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may +1094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * have wrong result. +1095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note (***) LSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * 32768 Hz). +1097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note (****) LSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value +1098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * 32000 Hz). +1099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional +1101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * value for HSE crystal. +1102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note This function can be used by the user application to compute the +1104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * baudrate for the communication peripherals or configure other parameters. +1105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the +1107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre +1108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval SYSCLK frequency +1111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) +1113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1430 .loc 1 1113 1 is_stmt 1 view -0 + 1431 .cfi_startproc + 1432 @ args = 0, pretend = 0, frame = 0 + 1433 @ frame_needed = 0, uses_anonymous_args = 0 + 1434 0000 10B5 push {r4, lr} + 1435 .LCFI5: + 1436 .cfi_def_cfa_offset 8 + 1437 .cfi_offset 4, -8 + 1438 .cfi_offset 14, -4 +1114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t pllvco, pllsource, pllr, pllm, hsidiv; + 1439 .loc 1 1114 3 view .LVU433 +1115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t sysclockfreq; + 1440 .loc 1 1115 3 view .LVU434 +1116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 1441 .loc 1 1117 3 view .LVU435 + 1442 .loc 1 1117 7 is_stmt 0 view .LVU436 + 1443 0002 2A4B ldr r3, .L138 + 1444 0004 9B68 ldr r3, [r3, #8] + 1445 0006 3822 movs r2, #56 + 1446 .loc 1 1117 6 view .LVU437 + 1447 0008 1A42 tst r2, r3 + 1448 000a 07D1 bne .L127 +1118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* HSISYS can be derived for HSI16 */ +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + 1449 .loc 1 1120 5 is_stmt 1 view .LVU438 + 1450 .loc 1 1120 24 is_stmt 0 view .LVU439 + 1451 000c 274B ldr r3, .L138 + 1452 000e 1A68 ldr r2, [r3] + 1453 .loc 1 1120 58 view .LVU440 + 1454 0010 D20A lsrs r2, r2, #11 + 1455 0012 0723 movs r3, #7 + 1456 0014 1340 ands r3, r2 + 1457 .LVL108: +1121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + ARM GAS /tmp/ccBwposX.s page 50 + + +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* HSI used as system clock source */ +1123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = (HSI_VALUE / hsidiv); + 1458 .loc 1 1123 5 is_stmt 1 view .LVU441 + 1459 .loc 1 1123 18 is_stmt 0 view .LVU442 + 1460 0016 2648 ldr r0, .L138+4 + 1461 0018 D840 lsrs r0, r0, r3 + 1462 .LVL109: + 1463 .L126: +1124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) +1126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* HSE used as system clock source */ +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; +1129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) +1131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* PLL used as system clock source */ +1133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SYSCLK = PLL_VCO / PLLR +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; +1139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** switch (pllsource) +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; +1145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ +1147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** default: /* HSI16 used as PLL clock source */ +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; +1150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = pllvco / pllr; +1153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* LSE used as system clock source */ +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = LSE_VALUE; +1158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) +1160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* LSI used as system clock source */ +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = LSI_VALUE; +1163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = 0U; +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return sysclockfreq; +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1464 .loc 1 1170 1 view .LVU443 + 1465 @ sp needed + ARM GAS /tmp/ccBwposX.s page 51 + + + 1466 001a 10BD pop {r4, pc} + 1467 .L127: +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1468 .loc 1 1125 8 is_stmt 1 view .LVU444 +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1469 .loc 1 1125 12 is_stmt 0 view .LVU445 + 1470 001c 234B ldr r3, .L138 + 1471 001e 9A68 ldr r2, [r3, #8] + 1472 0020 3823 movs r3, #56 + 1473 0022 1340 ands r3, r2 +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1474 .loc 1 1125 11 view .LVU446 + 1475 0024 082B cmp r3, #8 + 1476 0026 3BD0 beq .L132 +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1477 .loc 1 1130 8 is_stmt 1 view .LVU447 +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1478 .loc 1 1130 12 is_stmt 0 view .LVU448 + 1479 0028 204B ldr r3, .L138 + 1480 002a 9A68 ldr r2, [r3, #8] + 1481 002c 3823 movs r3, #56 + 1482 002e 1340 ands r3, r2 +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1483 .loc 1 1130 11 view .LVU449 + 1484 0030 102B cmp r3, #16 + 1485 0032 0DD0 beq .L135 +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1486 .loc 1 1154 8 is_stmt 1 view .LVU450 +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1487 .loc 1 1154 12 is_stmt 0 view .LVU451 + 1488 0034 1D4B ldr r3, .L138 + 1489 0036 9A68 ldr r2, [r3, #8] + 1490 0038 3823 movs r3, #56 + 1491 003a 1340 ands r3, r2 +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1492 .loc 1 1154 11 view .LVU452 + 1493 003c 202B cmp r3, #32 + 1494 003e 31D0 beq .L133 +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1495 .loc 1 1159 8 is_stmt 1 view .LVU453 +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1496 .loc 1 1159 12 is_stmt 0 view .LVU454 + 1497 0040 1A4B ldr r3, .L138 + 1498 0042 9A68 ldr r2, [r3, #8] + 1499 0044 3823 movs r3, #56 + 1500 0046 1340 ands r3, r2 +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1501 .loc 1 1159 11 view .LVU455 + 1502 0048 182B cmp r3, #24 + 1503 004a 26D0 beq .L136 +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1504 .loc 1 1166 18 view .LVU456 + 1505 004c 0020 movs r0, #0 + 1506 .LVL110: +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1507 .loc 1 1169 3 is_stmt 1 view .LVU457 +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + ARM GAS /tmp/ccBwposX.s page 52 + + + 1508 .loc 1 1169 10 is_stmt 0 view .LVU458 + 1509 004e E4E7 b .L126 + 1510 .LVL111: + 1511 .L135: +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + 1512 .loc 1 1137 5 is_stmt 1 view .LVU459 +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + 1513 .loc 1 1137 21 is_stmt 0 view .LVU460 + 1514 0050 164A ldr r2, .L138 + 1515 0052 D168 ldr r1, [r2, #12] +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + 1516 .loc 1 1137 15 view .LVU461 + 1517 0054 0D3B subs r3, r3, #13 + 1518 0056 0B40 ands r3, r1 + 1519 .LVL112: +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1520 .loc 1 1138 5 is_stmt 1 view .LVU462 +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1521 .loc 1 1138 17 is_stmt 0 view .LVU463 + 1522 0058 D268 ldr r2, [r2, #12] +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1523 .loc 1 1138 47 view .LVU464 + 1524 005a 1209 lsrs r2, r2, #4 + 1525 005c 0721 movs r1, #7 + 1526 005e 1140 ands r1, r2 +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1527 .loc 1 1138 10 view .LVU465 + 1528 0060 0131 adds r1, r1, #1 + 1529 .LVL113: +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1530 .loc 1 1140 5 is_stmt 1 view .LVU466 + 1531 0062 032B cmp r3, #3 + 1532 0064 0FD0 beq .L137 +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1533 .loc 1 1148 9 view .LVU467 +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1534 .loc 1 1148 29 is_stmt 0 view .LVU468 + 1535 0066 1248 ldr r0, .L138+4 + 1536 0068 FFF7FEFF bl __aeabi_uidiv + 1537 .LVL114: +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1538 .loc 1 1148 44 view .LVU469 + 1539 006c 0F4B ldr r3, .L138 + 1540 006e DA68 ldr r2, [r3, #12] +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1541 .loc 1 1148 74 view .LVU470 + 1542 0070 120A lsrs r2, r2, #8 + 1543 0072 7F23 movs r3, #127 + 1544 0074 1340 ands r3, r2 +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1545 .loc 1 1148 16 view .LVU471 + 1546 0076 5843 muls r0, r3 + 1547 .LVL115: +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1548 .loc 1 1149 9 is_stmt 1 view .LVU472 + 1549 .L131: +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = pllvco / pllr; + ARM GAS /tmp/ccBwposX.s page 53 + + + 1550 .loc 1 1151 5 view .LVU473 +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = pllvco / pllr; + 1551 .loc 1 1151 18 is_stmt 0 view .LVU474 + 1552 0078 0C4B ldr r3, .L138 + 1553 007a D968 ldr r1, [r3, #12] +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = pllvco / pllr; + 1554 .loc 1 1151 48 view .LVU475 + 1555 007c 490F lsrs r1, r1, #29 +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** sysclockfreq = pllvco / pllr; + 1556 .loc 1 1151 10 view .LVU476 + 1557 007e 0131 adds r1, r1, #1 + 1558 .LVL116: +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1559 .loc 1 1152 5 is_stmt 1 view .LVU477 +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1560 .loc 1 1152 18 is_stmt 0 view .LVU478 + 1561 0080 FFF7FEFF bl __aeabi_uidiv + 1562 .LVL117: +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1563 .loc 1 1152 18 view .LVU479 + 1564 0084 C9E7 b .L126 + 1565 .LVL118: + 1566 .L137: +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1567 .loc 1 1143 9 is_stmt 1 view .LVU480 +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1568 .loc 1 1143 29 is_stmt 0 view .LVU481 + 1569 0086 0B48 ldr r0, .L138+8 + 1570 0088 FFF7FEFF bl __aeabi_uidiv + 1571 .LVL119: +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1572 .loc 1 1143 44 view .LVU482 + 1573 008c 074B ldr r3, .L138 + 1574 008e DA68 ldr r2, [r3, #12] +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1575 .loc 1 1143 74 view .LVU483 + 1576 0090 120A lsrs r2, r2, #8 + 1577 0092 7F23 movs r3, #127 + 1578 0094 1340 ands r3, r2 +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** break; + 1579 .loc 1 1143 16 view .LVU484 + 1580 0096 5843 muls r0, r3 + 1581 .LVL120: +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1582 .loc 1 1144 9 is_stmt 1 view .LVU485 + 1583 0098 EEE7 b .L131 + 1584 .LVL121: + 1585 .L136: +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1586 .loc 1 1162 18 is_stmt 0 view .LVU486 + 1587 009a FA20 movs r0, #250 + 1588 009c C001 lsls r0, r0, #7 + 1589 009e BCE7 b .L126 + 1590 .L132: +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1591 .loc 1 1128 18 view .LVU487 + 1592 00a0 0448 ldr r0, .L138+8 + ARM GAS /tmp/ccBwposX.s page 54 + + + 1593 00a2 BAE7 b .L126 + 1594 .L133: +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1595 .loc 1 1157 18 view .LVU488 + 1596 00a4 8020 movs r0, #128 + 1597 00a6 0002 lsls r0, r0, #8 + 1598 00a8 B7E7 b .L126 + 1599 .L139: + 1600 00aa C046 .align 2 + 1601 .L138: + 1602 00ac 00100240 .word 1073876992 + 1603 00b0 0024F400 .word 16000000 + 1604 00b4 00127A00 .word 8000000 + 1605 .cfi_endproc + 1606 .LFE301: + 1608 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 1609 .align 1 + 1610 .global HAL_RCC_ClockConfig + 1611 .syntax unified + 1612 .code 16 + 1613 .thumb_func + 1614 .fpu softvfp + 1616 HAL_RCC_ClockConfig: + 1617 .LVL122: + 1618 .LFB299: + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t tickstart; + 1619 .loc 1 806 1 is_stmt 1 view -0 + 1620 .cfi_startproc + 1621 @ args = 0, pretend = 0, frame = 0 + 1622 @ frame_needed = 0, uses_anonymous_args = 0 + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t tickstart; + 1623 .loc 1 806 1 is_stmt 0 view .LVU490 + 1624 0000 70B5 push {r4, r5, r6, lr} + 1625 .LCFI6: + 1626 .cfi_def_cfa_offset 16 + 1627 .cfi_offset 4, -16 + 1628 .cfi_offset 5, -12 + 1629 .cfi_offset 6, -8 + 1630 .cfi_offset 14, -4 + 1631 0002 0400 movs r4, r0 + 1632 0004 0D00 movs r5, r1 + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1633 .loc 1 807 3 is_stmt 1 view .LVU491 + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1634 .loc 1 810 3 view .LVU492 + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1635 .loc 1 810 6 is_stmt 0 view .LVU493 + 1636 0006 0028 cmp r0, #0 + 1637 0008 00D1 bne .LCB1569 + 1638 000a AAE0 b .L159 @long jump + 1639 .LCB1569: + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 1640 .loc 1 816 3 is_stmt 1 view .LVU494 + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1641 .loc 1 817 3 view .LVU495 + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1642 .loc 1 824 3 view .LVU496 + ARM GAS /tmp/ccBwposX.s page 55 + + + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1643 .loc 1 824 18 is_stmt 0 view .LVU497 + 1644 000c 574B ldr r3, .L174 + 1645 000e 1A68 ldr r2, [r3] + 1646 0010 0723 movs r3, #7 + 1647 0012 1340 ands r3, r2 + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1648 .loc 1 824 6 view .LVU498 + 1649 0014 8B42 cmp r3, r1 + 1650 0016 21D3 bcc .L168 + 1651 .LVL123: + 1652 .L142: + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1653 .loc 1 843 3 is_stmt 1 view .LVU499 + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1654 .loc 1 843 26 is_stmt 0 view .LVU500 + 1655 0018 2368 ldr r3, [r4] + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1656 .loc 1 843 6 view .LVU501 + 1657 001a 9A07 lsls r2, r3, #30 + 1658 001c 0ED5 bpl .L145 + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1659 .loc 1 847 5 is_stmt 1 view .LVU502 + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1660 .loc 1 847 8 is_stmt 0 view .LVU503 + 1661 001e 5B07 lsls r3, r3, #29 + 1662 0020 05D5 bpl .L146 + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1663 .loc 1 849 7 is_stmt 1 view .LVU504 + 1664 0022 534A ldr r2, .L174+4 + 1665 0024 9168 ldr r1, [r2, #8] + 1666 0026 E023 movs r3, #224 + 1667 0028 DB01 lsls r3, r3, #7 + 1668 002a 0B43 orrs r3, r1 + 1669 002c 9360 str r3, [r2, #8] + 1670 .L146: + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 1671 .loc 1 853 5 view .LVU505 + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1672 .loc 1 854 5 view .LVU506 + 1673 002e 504A ldr r2, .L174+4 + 1674 0030 9368 ldr r3, [r2, #8] + 1675 0032 5049 ldr r1, .L174+8 + 1676 0034 0B40 ands r3, r1 + 1677 0036 A168 ldr r1, [r4, #8] + 1678 0038 0B43 orrs r3, r1 + 1679 003a 9360 str r3, [r2, #8] + 1680 .L145: + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1681 .loc 1 858 3 view .LVU507 + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1682 .loc 1 858 6 is_stmt 0 view .LVU508 + 1683 003c 2368 ldr r3, [r4] + 1684 003e DB07 lsls r3, r3, #31 + 1685 0040 54D5 bpl .L147 + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1686 .loc 1 860 5 is_stmt 1 view .LVU509 + ARM GAS /tmp/ccBwposX.s page 56 + + + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1687 .loc 1 863 5 view .LVU510 + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1688 .loc 1 863 26 is_stmt 0 view .LVU511 + 1689 0042 6368 ldr r3, [r4, #4] + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1690 .loc 1 863 8 view .LVU512 + 1691 0044 012B cmp r3, #1 + 1692 0046 20D0 beq .L169 + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1693 .loc 1 872 10 is_stmt 1 view .LVU513 + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1694 .loc 1 872 13 is_stmt 0 view .LVU514 + 1695 0048 022B cmp r3, #2 + 1696 004a 3BD0 beq .L170 + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1697 .loc 1 881 10 is_stmt 1 view .LVU515 + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1698 .loc 1 881 13 is_stmt 0 view .LVU516 + 1699 004c 002B cmp r3, #0 + 1700 004e 3FD1 bne .L151 + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1701 .loc 1 884 7 is_stmt 1 view .LVU517 + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1702 .loc 1 884 11 is_stmt 0 view .LVU518 + 1703 0050 474A ldr r2, .L174+4 + 1704 0052 1268 ldr r2, [r2] + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1705 .loc 1 884 10 view .LVU519 + 1706 0054 5205 lsls r2, r2, #21 + 1707 0056 1CD4 bmi .L149 + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1708 .loc 1 886 16 view .LVU520 + 1709 0058 0120 movs r0, #1 + 1710 005a 6AE0 b .L141 + 1711 .LVL124: + 1712 .L168: + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1713 .loc 1 827 5 is_stmt 1 view .LVU521 + 1714 005c 434A ldr r2, .L174 + 1715 005e 1368 ldr r3, [r2] + 1716 0060 0721 movs r1, #7 + 1717 .LVL125: + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1718 .loc 1 827 5 is_stmt 0 view .LVU522 + 1719 0062 8B43 bics r3, r1 + 1720 0064 2B43 orrs r3, r5 + 1721 0066 1360 str r3, [r2] + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1722 .loc 1 831 5 is_stmt 1 view .LVU523 + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1723 .loc 1 831 17 is_stmt 0 view .LVU524 + 1724 0068 FFF7FEFF bl HAL_GetTick + 1725 .LVL126: + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1726 .loc 1 831 17 view .LVU525 + 1727 006c 0600 movs r6, r0 + ARM GAS /tmp/ccBwposX.s page 57 + + + 1728 .LVL127: + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1729 .loc 1 833 5 is_stmt 1 view .LVU526 + 1730 .L143: + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1731 .loc 1 833 11 view .LVU527 + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1732 .loc 1 833 18 is_stmt 0 view .LVU528 + 1733 006e 3F4B ldr r3, .L174 + 1734 0070 1A68 ldr r2, [r3] + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1735 .loc 1 833 24 view .LVU529 + 1736 0072 0723 movs r3, #7 + 1737 0074 1340 ands r3, r2 + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1738 .loc 1 833 11 view .LVU530 + 1739 0076 AB42 cmp r3, r5 + 1740 0078 CED0 beq .L142 + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1741 .loc 1 835 7 is_stmt 1 view .LVU531 + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1742 .loc 1 835 12 is_stmt 0 view .LVU532 + 1743 007a FFF7FEFF bl HAL_GetTick + 1744 .LVL128: + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1745 .loc 1 835 26 view .LVU533 + 1746 007e 801B subs r0, r0, r6 + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1747 .loc 1 835 10 view .LVU534 + 1748 0080 3D4A ldr r2, .L174+12 + 1749 0082 9042 cmp r0, r2 + 1750 0084 F3D9 bls .L143 + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1751 .loc 1 837 16 view .LVU535 + 1752 0086 0320 movs r0, #3 + 1753 0088 53E0 b .L141 + 1754 .LVL129: + 1755 .L169: + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1756 .loc 1 866 7 is_stmt 1 view .LVU536 + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1757 .loc 1 866 11 is_stmt 0 view .LVU537 + 1758 008a 394A ldr r2, .L174+4 + 1759 008c 1268 ldr r2, [r2] + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1760 .loc 1 866 10 view .LVU538 + 1761 008e 9203 lsls r2, r2, #14 + 1762 0090 69D5 bpl .L171 + 1763 .L149: + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1764 .loc 1 907 5 is_stmt 1 view .LVU539 + 1765 0092 3749 ldr r1, .L174+4 + 1766 0094 8A68 ldr r2, [r1, #8] + 1767 0096 0720 movs r0, #7 + 1768 0098 8243 bics r2, r0 + 1769 009a 1343 orrs r3, r2 + 1770 009c 8B60 str r3, [r1, #8] + ARM GAS /tmp/ccBwposX.s page 58 + + + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1771 .loc 1 910 5 view .LVU540 + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1772 .loc 1 910 17 is_stmt 0 view .LVU541 + 1773 009e FFF7FEFF bl HAL_GetTick + 1774 .LVL130: + 1775 00a2 0600 movs r6, r0 + 1776 .LVL131: + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1777 .loc 1 912 5 is_stmt 1 view .LVU542 + 1778 .L153: + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1779 .loc 1 912 11 view .LVU543 + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1780 .loc 1 912 12 is_stmt 0 view .LVU544 + 1781 00a4 324B ldr r3, .L174+4 + 1782 00a6 9B68 ldr r3, [r3, #8] + 1783 00a8 3822 movs r2, #56 + 1784 00aa 1A40 ands r2, r3 + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1785 .loc 1 912 78 view .LVU545 + 1786 00ac 6368 ldr r3, [r4, #4] + 1787 00ae DB00 lsls r3, r3, #3 + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1788 .loc 1 912 11 view .LVU546 + 1789 00b0 9A42 cmp r2, r3 + 1790 00b2 1BD0 beq .L147 + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1791 .loc 1 914 7 is_stmt 1 view .LVU547 + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1792 .loc 1 914 12 is_stmt 0 view .LVU548 + 1793 00b4 FFF7FEFF bl HAL_GetTick + 1794 .LVL132: + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1795 .loc 1 914 26 view .LVU549 + 1796 00b8 801B subs r0, r0, r6 + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1797 .loc 1 914 10 view .LVU550 + 1798 00ba 2F4B ldr r3, .L174+12 + 1799 00bc 9842 cmp r0, r3 + 1800 00be F1D9 bls .L153 + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1801 .loc 1 916 16 view .LVU551 + 1802 00c0 0320 movs r0, #3 + 1803 00c2 36E0 b .L141 + 1804 .LVL133: + 1805 .L170: + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1806 .loc 1 875 7 is_stmt 1 view .LVU552 + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1807 .loc 1 875 11 is_stmt 0 view .LVU553 + 1808 00c4 2A4A ldr r2, .L174+4 + 1809 00c6 1268 ldr r2, [r2] + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1810 .loc 1 875 10 view .LVU554 + 1811 00c8 9201 lsls r2, r2, #6 + 1812 00ca E2D4 bmi .L149 + ARM GAS /tmp/ccBwposX.s page 59 + + + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1813 .loc 1 877 16 view .LVU555 + 1814 00cc 0120 movs r0, #1 + 1815 00ce 30E0 b .L141 + 1816 .L151: + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1817 .loc 1 890 10 is_stmt 1 view .LVU556 + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1818 .loc 1 890 13 is_stmt 0 view .LVU557 + 1819 00d0 032B cmp r3, #3 + 1820 00d2 05D0 beq .L172 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1821 .loc 1 902 7 is_stmt 1 view .LVU558 + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1822 .loc 1 902 11 is_stmt 0 view .LVU559 + 1823 00d4 264A ldr r2, .L174+4 + 1824 00d6 D26D ldr r2, [r2, #92] + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1825 .loc 1 902 10 view .LVU560 + 1826 00d8 9207 lsls r2, r2, #30 + 1827 00da DAD4 bmi .L149 + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1828 .loc 1 904 16 view .LVU561 + 1829 00dc 0120 movs r0, #1 + 1830 00de 28E0 b .L141 + 1831 .L172: + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1832 .loc 1 893 7 is_stmt 1 view .LVU562 + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1833 .loc 1 893 11 is_stmt 0 view .LVU563 + 1834 00e0 234A ldr r2, .L174+4 + 1835 00e2 126E ldr r2, [r2, #96] + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1836 .loc 1 893 10 view .LVU564 + 1837 00e4 9207 lsls r2, r2, #30 + 1838 00e6 D4D4 bmi .L149 + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1839 .loc 1 895 16 view .LVU565 + 1840 00e8 0120 movs r0, #1 + 1841 00ea 22E0 b .L141 + 1842 .L147: + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1843 .loc 1 922 3 is_stmt 1 view .LVU566 + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1844 .loc 1 922 18 is_stmt 0 view .LVU567 + 1845 00ec 1F4B ldr r3, .L174 + 1846 00ee 1A68 ldr r2, [r3] + 1847 00f0 0723 movs r3, #7 + 1848 00f2 1340 ands r3, r2 + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1849 .loc 1 922 6 view .LVU568 + 1850 00f4 AB42 cmp r3, r5 + 1851 00f6 1DD8 bhi .L173 + 1852 .L155: + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1853 .loc 1 941 3 is_stmt 1 view .LVU569 + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 60 + + + 1854 .loc 1 941 6 is_stmt 0 view .LVU570 + 1855 00f8 2368 ldr r3, [r4] + 1856 00fa 5B07 lsls r3, r3, #29 + 1857 00fc 06D5 bpl .L158 + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + 1858 .loc 1 943 5 is_stmt 1 view .LVU571 + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1859 .loc 1 944 5 view .LVU572 + 1860 00fe 1C4A ldr r2, .L174+4 + 1861 0100 9368 ldr r3, [r2, #8] + 1862 0102 1E49 ldr r1, .L174+16 + 1863 0104 0B40 ands r3, r1 + 1864 0106 E168 ldr r1, [r4, #12] + 1865 0108 0B43 orrs r3, r1 + 1866 010a 9360 str r3, [r2, #8] + 1867 .L158: + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1868 .loc 1 948 3 view .LVU573 + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1869 .loc 1 948 22 is_stmt 0 view .LVU574 + 1870 010c FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1871 .LVL134: + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1872 .loc 1 948 71 view .LVU575 + 1873 0110 174B ldr r3, .L174+4 + 1874 0112 9A68 ldr r2, [r3, #8] + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1875 .loc 1 948 95 view .LVU576 + 1876 0114 120A lsrs r2, r2, #8 + 1877 0116 0F23 movs r3, #15 + 1878 0118 1340 ands r3, r2 + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1879 .loc 1 948 66 view .LVU577 + 1880 011a 9B00 lsls r3, r3, #2 + 1881 011c 184A ldr r2, .L174+20 + 1882 011e 9A58 ldr r2, [r3, r2] + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1883 .loc 1 948 118 view .LVU578 + 1884 0120 1F23 movs r3, #31 + 1885 0122 1340 ands r3, r2 + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1886 .loc 1 948 48 view .LVU579 + 1887 0124 D840 lsrs r0, r0, r3 + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1888 .loc 1 948 19 view .LVU580 + 1889 0126 174B ldr r3, .L174+24 + 1890 0128 1860 str r0, [r3] + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1891 .loc 1 951 3 is_stmt 1 view .LVU581 + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1892 .loc 1 951 10 is_stmt 0 view .LVU582 + 1893 012a 174B ldr r3, .L174+28 + 1894 012c 1868 ldr r0, [r3] + 1895 012e FFF7FEFF bl HAL_InitTick + 1896 .LVL135: + 1897 .L141: + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + ARM GAS /tmp/ccBwposX.s page 61 + + + 1898 .loc 1 952 1 view .LVU583 + 1899 @ sp needed + 1900 .LVL136: + 1901 .LVL137: + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1902 .loc 1 952 1 view .LVU584 + 1903 0132 70BD pop {r4, r5, r6, pc} + 1904 .LVL138: + 1905 .L173: + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1906 .loc 1 925 5 is_stmt 1 view .LVU585 + 1907 0134 0D4A ldr r2, .L174 + 1908 0136 1368 ldr r3, [r2] + 1909 0138 0721 movs r1, #7 + 1910 013a 8B43 bics r3, r1 + 1911 013c 2B43 orrs r3, r5 + 1912 013e 1360 str r3, [r2] + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1913 .loc 1 929 5 view .LVU586 + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 1914 .loc 1 929 17 is_stmt 0 view .LVU587 + 1915 0140 FFF7FEFF bl HAL_GetTick + 1916 .LVL139: + 1917 0144 0600 movs r6, r0 + 1918 .LVL140: + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1919 .loc 1 931 5 is_stmt 1 view .LVU588 + 1920 .L156: + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1921 .loc 1 931 11 view .LVU589 + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1922 .loc 1 931 18 is_stmt 0 view .LVU590 + 1923 0146 094B ldr r3, .L174 + 1924 0148 1A68 ldr r2, [r3] + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1925 .loc 1 931 24 view .LVU591 + 1926 014a 0723 movs r3, #7 + 1927 014c 1340 ands r3, r2 + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1928 .loc 1 931 11 view .LVU592 + 1929 014e AB42 cmp r3, r5 + 1930 0150 D2D0 beq .L155 + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1931 .loc 1 933 7 is_stmt 1 view .LVU593 + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1932 .loc 1 933 12 is_stmt 0 view .LVU594 + 1933 0152 FFF7FEFF bl HAL_GetTick + 1934 .LVL141: + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1935 .loc 1 933 26 view .LVU595 + 1936 0156 801B subs r0, r0, r6 + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1937 .loc 1 933 10 view .LVU596 + 1938 0158 074B ldr r3, .L174+12 + 1939 015a 9842 cmp r0, r3 + 1940 015c F3D9 bls .L156 + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + ARM GAS /tmp/ccBwposX.s page 62 + + + 1941 .loc 1 935 16 view .LVU597 + 1942 015e 0320 movs r0, #3 + 1943 0160 E7E7 b .L141 + 1944 .LVL142: + 1945 .L159: + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1946 .loc 1 812 12 view .LVU598 + 1947 0162 0120 movs r0, #1 + 1948 .LVL143: + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1949 .loc 1 812 12 view .LVU599 + 1950 0164 E5E7 b .L141 + 1951 .LVL144: + 1952 .L171: + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1953 .loc 1 868 16 view .LVU600 + 1954 0166 0120 movs r0, #1 + 1955 0168 E3E7 b .L141 + 1956 .L175: + 1957 016a C046 .align 2 + 1958 .L174: + 1959 016c 00200240 .word 1073881088 + 1960 0170 00100240 .word 1073876992 + 1961 0174 FFF0FFFF .word -3841 + 1962 0178 88130000 .word 5000 + 1963 017c FF8FFFFF .word -28673 + 1964 0180 00000000 .word AHBPrescTable + 1965 0184 00000000 .word SystemCoreClock + 1966 0188 00000000 .word uwTickPrio + 1967 .cfi_endproc + 1968 .LFE299: + 1970 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 1971 .align 1 + 1972 .global HAL_RCC_GetHCLKFreq + 1973 .syntax unified + 1974 .code 16 + 1975 .thumb_func + 1976 .fpu softvfp + 1978 HAL_RCC_GetHCLKFreq: + 1979 .LFB302: +1171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Return the HCLK frequency. +1174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * +1177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval HCLK frequency in Hz +1179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 1980 .loc 1 1181 1 is_stmt 1 view -0 + 1981 .cfi_startproc + 1982 @ args = 0, pretend = 0, frame = 0 + 1983 @ frame_needed = 0, uses_anonymous_args = 0 + 1984 @ link register save eliminated. +1182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return SystemCoreClock; + ARM GAS /tmp/ccBwposX.s page 63 + + + 1985 .loc 1 1182 3 view .LVU602 + 1986 .loc 1 1182 10 is_stmt 0 view .LVU603 + 1987 0000 014B ldr r3, .L177 + 1988 0002 1868 ldr r0, [r3] +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 1989 .loc 1 1183 1 view .LVU604 + 1990 @ sp needed + 1991 0004 7047 bx lr + 1992 .L178: + 1993 0006 C046 .align 2 + 1994 .L177: + 1995 0008 00000000 .word SystemCoreClock + 1996 .cfi_endproc + 1997 .LFE302: + 1999 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 2000 .align 1 + 2001 .global HAL_RCC_GetPCLK1Freq + 2002 .syntax unified + 2003 .code 16 + 2004 .thumb_func + 2005 .fpu softvfp + 2007 HAL_RCC_GetPCLK1Freq: + 2008 .LFB303: +1184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Return the PCLK1 frequency. +1187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval PCLK1 frequency in Hz +1190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2009 .loc 1 1192 1 is_stmt 1 view -0 + 2010 .cfi_startproc + 2011 @ args = 0, pretend = 0, frame = 0 + 2012 @ frame_needed = 0, uses_anonymous_args = 0 + 2013 0000 10B5 push {r4, lr} + 2014 .LCFI7: + 2015 .cfi_def_cfa_offset 8 + 2016 .cfi_offset 4, -8 + 2017 .cfi_offset 14, -4 +1193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); + 2018 .loc 1 1194 3 view .LVU606 + 2019 .loc 1 1194 22 is_stmt 0 view .LVU607 + 2020 0002 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 2021 .LVL145: + 2022 .LBB9: + 2023 .LBI9: + 2024 .file 2 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h" + 1:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @file stm32g0xx_ll_rcc.h + 4:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Header file of RCC LL module. + 6:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ****************************************************************************** + 7:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @attention + ARM GAS /tmp/ccBwposX.s page 64 + + + 8:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * + 9:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** *

© Copyright (c) 2018 STMicroelectronics. + 10:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * All rights reserved.

+ 11:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * + 12:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * This software component is licensed by ST under BSD 3-Clause license, + 13:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * the "License"; You may not use this file except in compliance with the + 14:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * License. You may obtain a copy of the License at: + 15:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * opensource.org/licenses/BSD-3-Clause + 16:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * + 17:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ****************************************************************************** + 18:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 19:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 20:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Define to prevent recursive inclusion -------------------------------------*/ + 21:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #ifndef STM32G0xx_LL_RCC_H + 22:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define STM32G0xx_LL_RCC_H + 23:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 24:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #ifdef __cplusplus + 25:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** extern "C" { + 26:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif + 27:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 28:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Includes ------------------------------------------------------------------*/ + 29:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #include "stm32g0xx.h" + 30:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 31:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @addtogroup STM32G0xx_LL_Driver + 32:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 33:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 34:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 35:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC) + 36:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 37:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL RCC + 38:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 39:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 40:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 41:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Private types -------------------------------------------------------------*/ + 42:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Private variables ---------------------------------------------------------*/ + 43:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Variables RCC Private Variables + 44:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 45:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 46:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 47:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 48:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 49:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 50:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 51:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 52:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Private constants ---------------------------------------------------------*/ + 53:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Private macros ------------------------------------------------------------*/ + 54:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 55:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Private_Macros RCC Private Macros + 56:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 57:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 58:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 59:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 60:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 61:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /*USE_FULL_LL_DRIVER*/ + 62:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 63:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Exported types ------------------------------------------------------------*/ + 64:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + ARM GAS /tmp/ccBwposX.s page 65 + + + 65:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Types RCC Exported Types + 66:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 67:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 68:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 69:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + 70:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 71:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 72:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 73:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 74:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief RCC Clocks Frequency Structure + 75:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 76:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** typedef struct + 77:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { + 78:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + 79:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + 80:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + 81:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } LL_RCC_ClocksTypeDef; + 82:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 83:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 84:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 85:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 86:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 87:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 88:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 89:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 90:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 91:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 92:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Exported constants --------------------------------------------------------*/ + 93:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + 94:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 95:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 96:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 97:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + 98:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Defines used to adapt values of different oscillators + 99:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note These values could be modified in the user environment according to + 100:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * HW set-up. + 101:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 102:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 103:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (HSE_VALUE) + 104:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ + 105:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* HSE_VALUE */ + 106:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 107:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (HSI_VALUE) + 108:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ + 109:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* HSI_VALUE */ + 110:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 111:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (LSE_VALUE) + 112:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ + 113:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LSE_VALUE */ + 114:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 115:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (LSI_VALUE) + 116:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ + 117:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LSI_VALUE */ + 118:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (EXTERNAL_CLOCK_VALUE) + 119:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */ + 120:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* EXTERNAL_CLOCK_VALUE */ + 121:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + ARM GAS /tmp/ccBwposX.s page 66 + + + 122:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 123:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if !defined (HSI48_VALUE) + 124:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ + 125:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* HSI48_VALUE */ + 126:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 127:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 128:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 129:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 130:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 131:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + 132:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_WriteReg function + 133:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 134:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 135:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ + 136:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ + 137:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ + 138:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ + 139:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ + 140:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Inte + 141:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrup + 142:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 143:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ + 144:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 145:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 146:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 147:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 148:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 149:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + 150:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Flags defines which can be used with LL_RCC_ReadReg function + 151:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 152:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 153:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ + 154:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ + 155:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ + 156:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 157:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ + 158:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 159:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ + 160:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ + 161:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Inte + 162:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrup + 163:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ + 164:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ + 165:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ + 166:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ + 167:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag + 168:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ + 169:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ + 170:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 171:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 172:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 173:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 174:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_IT IT Defines + 175:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + 176:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 177:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 178:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable * + ARM GAS /tmp/ccBwposX.s page 67 + + + 179:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable * + 180:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable * + 181:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable * + 182:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable * + 183:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 184:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable + 185:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 186:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 187:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 188:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 189:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 190:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + 191:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 192:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 193:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving cap + 194:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low drivin + 195:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high drivi + 196:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving ca + 197:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 198:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 199:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 200:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 201:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + 202:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 203:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 204:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low s + 205:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low s + 206:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 207:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 208:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 209:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 210:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + 211:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 212:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 213:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as + 214:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as + 215:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as + 216:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection us + 217:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection us + 218:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 219:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 220:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 221:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 222:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + 223:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 224:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 225:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as sys + 226:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as sys + 227:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as sys + 228:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as sys + 229:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as sys + 230:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 231:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 232:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 233:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 234:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + 235:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + ARM GAS /tmp/ccBwposX.s page 68 + + + 236:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 237:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_1 0x00000000U + 238:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 + 239:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) + 240:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) + 241:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) + 242:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) + 243:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) + 244:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) + 245:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | R + 246:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 247:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 248:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 249:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 250:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + 251:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 252:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 253:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_1 0x00000000U /* + 254:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /* + 255:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /* + 256:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /* + 257:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /* + 258:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 259:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 260:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 261:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 262:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_HSI_DIV HSI division factor + 263:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 264:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 265:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not d + 266:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divid + 267:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divid + 268:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divid + 269:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divid + 270:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divid + 271:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divid + 272:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divid + 273:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 274:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 275:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 276:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 277:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + 278:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 279:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 280:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output d + 281:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selec + 282:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 283:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 select + 284:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 285:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 select + 286:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selectio + 287:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL sel + 288:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selectio + 289:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) + 290:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOSEL_3) + 291:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK sele + 292:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK sele + ARM GAS /tmp/ccBwposX.s page 69 + + + 293:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selec + 294:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) / + 295:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOSEL_3 */ + 296:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 297:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 298:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 299:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 300:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + 301:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 302:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 303:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1 0x00000000U + 304:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 + 305:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 + 306:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) + 307:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 + 308:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) + 309:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) + 310:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE + 311:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CFGR_MCOPRE_3) + 312:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 + 313:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) + 314:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) + 315:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CFGR_MCOPRE_3 */ + 316:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 317:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 318:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 319:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 320:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_MCO2_SUPPORT) + 321:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection + 322:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 323:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 324:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U + 325:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 + 326:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 327:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 + 328:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 329:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) + 330:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 + 331:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) + 332:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1) + 333:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2 + 334:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 + 335:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0) + 336:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1) + 337:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2 + 338:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 339:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 340:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 341:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 342:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler + 343:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 344:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 345:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1 0x00000000U + 346:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 + 347:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 + 348:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) + 349:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 + ARM GAS /tmp/ccBwposX.s page 70 + + + 350:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) + 351:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) + 352:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2 + 353:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 + 354:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) + 355:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) + 356:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 357:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 358:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 359:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_MCO2_SUPPORT */ + 360:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 361:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(USE_FULL_LL_DRIVER) + 362:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + 363:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 364:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 365:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the + 366:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be prov + 367:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 368:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 369:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 370:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* USE_FULL_LL_DRIVER */ + 371:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 372:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + 373:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 374:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 375:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) + 376:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) + 377:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) + 378:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) + 379:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) + 380:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) + 381:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) + 382:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) + 383:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART3SEL) + 384:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) / + 385:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) / + 386:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) / + 387:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) / + 388:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART3SEL */ + 389:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 390:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 391:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 392:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 393:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPUART1) || defined(LPUART2) + 394:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + 395:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 396:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 397:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPUART2) + 398:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) + 399:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) + 400:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) + 401:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) + 402:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPUART2 */ + 403:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) + 404:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) + 405:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) + 406:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) + ARM GAS /tmp/ccBwposX.s page 71 + + + 407:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 408:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 409:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 410:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPUART1 || LPUART2 */ + 411:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 412:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + 413:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 414:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 415:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U) /*!< + 416:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0) /*!< + 417:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1) /*!< + 418:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C2SEL) + 419:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U) /*!< + 420:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0) /*!< + 421:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1) /*!< + 422:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_I2C2SEL */ + 423:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 424:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 425:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 426:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 427:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection + 428:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 429:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 430:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + 431:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U) /*!< + 432:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0) /*! + 433:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1) /*! + 434:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL) /*! + 435:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U) /*!< + 436:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0) /*! + 437:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1) /*! + 438:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL) /*! + 439:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #else + 440:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2 + 441:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL clock used as I2S1 + 442:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock used as I2S1 + 443:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as + 444:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + 445:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 446:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 447:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 448:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 449:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 450:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_TIM1SEL) + 451:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection + 452:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 453:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 454:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /* + 455:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /* + 456:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 457:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 458:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 459:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_TIM1SEL */ + 460:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 461:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_TIM15SEL) + 462:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE + 463:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + ARM GAS /tmp/ccBwposX.s page 72 + + + 464:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 465:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /* + 466:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /* + 467:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 468:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 469:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 470:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_TIM15SEL */ + 471:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 472:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPTIM1) && defined(LPTIM2) + 473:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + 474:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 475:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 476:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) / + 477:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) / + 478:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) / + 479:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) / + 480:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) / + 481:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) / + 482:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) / + 483:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) / + 484:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 485:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 486:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 487:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPTIM1 && LPTIM2*/ + 488:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 489:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(CEC) + 490:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection + 491:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 492:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 493:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock + 494:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock + 495:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 496:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 497:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 498:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 499:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* CEC */ + 500:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 501:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(FDCAN1) || defined(FDCAN2) + 502:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection + 503:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 504:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 505:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 oscillator cl + 506:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" oscillato + 507:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clo + 508:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 509:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 510:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 511:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 512:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* FDCAN1 || FDCAN2 */ + 513:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 514:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RNG) + 515:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + 516:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 517:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 518:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG + 519:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator clock + 520:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK divided by 1 u + ARM GAS /tmp/ccBwposX.s page 73 + + + 521:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL /*!< PLL used as RNG clock + 522:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 523:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 524:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 525:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RNG */ + 526:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 527:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RNG) + 528:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor + 529:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 530:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 531:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLK_DIV1 0x00000000U /*!< RNG clock not divide + 532:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by + 533:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by + 534:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV /*!< RNG clock divided by + 535:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 536:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 537:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 538:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RNG */ + 539:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 540:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + 541:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + 542:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 543:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 544:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) + 545:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB cloc + 546:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ + 547:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< PLL clock used as USB clock so + 548:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL clock used as USB clock so + 549:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 550:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 551:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 552:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + 553:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 554:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + 555:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 556:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 557:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC cl + 558:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0 /*!< PLL used as ADC clock + 559:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock + 560:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 561:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 562:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 563:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 564:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source + 565:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 566:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 567:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection * + 568:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection * + 569:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_USART3SEL) + 570:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection * + 571:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_USART3SEL */ + 572:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 573:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 574:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 575:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 576:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPUART1) + 577:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + ARM GAS /tmp/ccBwposX.s page 74 + + + 578:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 579:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 580:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection + 581:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPUART2) + 582:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection + 583:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPUART2 */ + 584:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 585:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 586:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 587:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPUART1 */ + 588:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 589:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + 590:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 591:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 592:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */ + 593:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_I2C2SEL) + 594:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */ + 595:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_I2C2SEL */ + 596:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 597:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 598:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 599:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 600:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + 601:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 602:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 603:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + 604:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */ + 605:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */ + 606:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #else + 607:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */ + 608:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + 609:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 610:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 611:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 612:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 613:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_TIM1SEL) + 614:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source + 615:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 616:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 617:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */ + 618:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR_TIM15SEL) + 619:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */ + 620:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_TIM15SEL */ + 621:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 622:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 623:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 624:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR_TIM1SEL */ + 625:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 626:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(LPTIM1) && defined(LPTIM2) + 627:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + 628:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 629:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 630:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection * + 631:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection * + 632:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 633:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 634:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccBwposX.s page 75 + + + 635:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* LPTIM1 && LPTIM2 */ + 636:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 637:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(CEC) + 638:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + 639:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 640:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 641:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL /*!< CEC Clock source selection + 642:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 643:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 644:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 645:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* CEC */ + 646:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 647:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(FDCAN1) || defined(FDCAN2) + 648:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + 649:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 650:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 651:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL /*!< FDCAN Clock source sel + 652:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 653:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 654:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 655:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* FDCAN1 */ + 656:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 657:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + 658:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + 659:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 660:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 661:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */ + 662:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 663:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 664:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 665:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + 666:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 667:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RNG) + 668:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + 669:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 670:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 671:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG Clock source selection + 672:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 673:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 674:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 675:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 676:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor + 677:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 678:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 679:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV /*!< RNG Clock division factor * + 680:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 681:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 682:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 683:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RNG */ + 684:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 685:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + 686:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 687:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 688:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection + 689:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 690:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 691:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccBwposX.s page 76 + + + 692:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 693:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + 694:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 695:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 696:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC + 697:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used a + 698:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used a + 699:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divide + 700:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 701:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 702:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 703:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 704:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 705:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source + 706:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 707:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 708:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ + 709:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL + 710:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL e + 711:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 712:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 713:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 714:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 715:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor (PLLM) + 716:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 717:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 718:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL div + 719:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL div + 720:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL div + 721:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL div + 722:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL div + 723:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL div + 724:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL div + 725:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL div + 726:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 727:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 728:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 729:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 730:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + 731:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 732:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 733:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 734:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 735:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 736:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL d + 737:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL d + 738:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL d + 739:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL d + 740:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 741:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 742:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 743:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 744:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + 745:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 746:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 747:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) + 748:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) + ARM GAS /tmp/ccBwposX.s page 77 + + + 749:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) + 750:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) + 751:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) + 752:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) + 753:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 754:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) + 755:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) + 756:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) + 757:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 758:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) + 759:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 760:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 761:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 762:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) + 763:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) + 764:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) + 765:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 766:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) + 767:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 768:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 769:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 770:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) + 771:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_ + 772:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_ + 773:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 774:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_ + 775:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 776:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_ + 777:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_ + 778:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 779:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 780:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 781:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 782:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_PLLQ_SUPPORT) + 783:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + 784:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 785:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 786:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 787:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 788:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 789:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL di + 790:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL di + 791:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL di + 792:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL di + 793:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 794:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 795:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 796:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_PLLQ_SUPPORT */ + 797:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 798:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 799:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 800:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 801:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 802:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Exported macro ------------------------------------------------------------*/ + 803:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + 804:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 805:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + ARM GAS /tmp/ccBwposX.s page 78 + + + 806:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 807:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + 808:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 809:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 810:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 811:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 812:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Write a value in RCC register + 813:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __REG__ Register to be written + 814:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __VALUE__ Value to be written in the register + 815:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None + 816:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 817:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) + 818:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 819:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 820:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Read a value in RCC register + 821:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __REG__ Register to be read + 822:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Register value + 823:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 824:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) + 825:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 826:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} + 827:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 828:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 829:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + 830:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ + 831:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 832:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 833:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 834:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLCLK frequency on system domain + 835:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + 836:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + 837:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + 838:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: + 839:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 + 840:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 + 841:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 + 842:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + 843:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 + 844:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 + 845:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 + 846:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 + 847:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + 848:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLR__ This parameter can be one of the following values: + 849:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_2 + 850:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_3 + 851:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_4 + 852:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_5 + 853:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_6 + 854:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_7 + 855:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLR_DIV_8 + 856:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 857:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 858:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ + 859:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + 860:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) + 861:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 862:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + ARM GAS /tmp/ccBwposX.s page 79 + + + 863:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain + 864:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + 865:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + 866:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + 867:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: + 868:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 + 869:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 + 870:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 + 871:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + 872:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 + 873:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 + 874:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 + 875:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 + 876:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + 877:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLP__ This parameter can be one of the following values: + 878:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 + 879:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_3 + 880:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 + 881:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_5 + 882:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 + 883:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_7 + 884:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 + 885:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_9 + 886:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_10 + 887:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_11 + 888:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_12 + 889:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_13 + 890:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_14 + 891:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_15 + 892:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_16 + 893:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_17 + 894:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_18 + 895:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_19 + 896:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_20 + 897:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_21 + 898:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_22 + 899:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_23 + 900:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_24 + 901:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_25 + 902:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_26 + 903:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_27 + 904:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_28 + 905:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_29 + 906:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_30 + 907:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_31 + 908:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_32 + 909:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 910:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 911:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + 912:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + 913:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + 914:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 915:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_CCIPR2_I2S2SEL) + 916:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 917:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLPCLK frequency used on I2S2 domain + 918:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + 919:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + ARM GAS /tmp/ccBwposX.s page 80 + + + 920:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + 921:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: + 922:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 + 923:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 + 924:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 + 925:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + 926:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 + 927:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 + 928:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 + 929:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 + 930:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + 931:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLP__ This parameter can be one of the following values: + 932:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 + 933:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_3 + 934:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 + 935:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_5 + 936:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 + 937:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_7 + 938:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 + 939:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_9 + 940:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_10 + 941:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_11 + 942:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_12 + 943:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_13 + 944:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_14 + 945:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_15 + 946:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_16 + 947:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_17 + 948:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_18 + 949:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_19 + 950:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_20 + 951:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_21 + 952:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_22 + 953:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_23 + 954:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_24 + 955:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_25 + 956:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_26 + 957:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_27 + 958:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_28 + 959:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_29 + 960:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_30 + 961:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_31 + 962:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_32 + 963:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) + 964:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ + 965:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + 966:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + 967:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + 968:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_CCIPR2_I2S2SEL */ + 969:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + 970:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + 971:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain + 972:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + 973:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + 974:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + 975:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: + 976:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 + ARM GAS /tmp/ccBwposX.s page 81 + + + 977:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 + 978:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 + 979:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + 980:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 + 981:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 + 982:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 + 983:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 + 984:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + 985:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLP__ This parameter can be one of the following values: + 986:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_2 + 987:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_3 + 988:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_4 + 989:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_5 + 990:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_6 + 991:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_7 + 992:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_8 + 993:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_9 + 994:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_10 + 995:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_11 + 996:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_12 + 997:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_13 + 998:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_14 + 999:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_15 +1000:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_16 +1001:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_17 +1002:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_18 +1003:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_19 +1004:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_20 +1005:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_21 +1006:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_22 +1007:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_23 +1008:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_24 +1009:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_25 +1010:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_26 +1011:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_27 +1012:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_28 +1013:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_29 +1014:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_30 +1015:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_31 +1016:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLP_DIV_32 +1017:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1018:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1019:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ +1020:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1021:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +1022:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1023:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RNG) +1024:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1025:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain +1026:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1027:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1028:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1029:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1030:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 +1031:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1032:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1033:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 + ARM GAS /tmp/ccBwposX.s page 82 + + +1034:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1035:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1036:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1037:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1038:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 +1039:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1040:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1041:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1042:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1043:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1044:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1045:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1046:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1047:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1048:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1049:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ +1050:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1051:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +1052:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RNG */ +1053:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1054:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_PLLQ_SUPPORT) +1055:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1056:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLQCLK frequency used on TIM1 domain +1057:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1058:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1059:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1060:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1061:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 +1062:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1063:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1064:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1065:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1066:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1067:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1068:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1069:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 +1070:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1071:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1072:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1073:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1074:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1075:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1076:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1077:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1078:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1079:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1080:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ +1081:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1082:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +1083:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(TIM15) +1084:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1085:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain +1086:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1087:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1088:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1089:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1090:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 + ARM GAS /tmp/ccBwposX.s page 83 + + +1091:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1092:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1093:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1094:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1095:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1096:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1097:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1098:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 +1099:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1100:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1101:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1102:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1103:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1104:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1105:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1106:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1107:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1108:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1109:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ +1110:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1111:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +1112:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* TIM15 */ +1113:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_PLLQ_SUPPORT */ +1114:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1115:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(FDCAN1) || defined(FDCAN2) +1116:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1117:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLQCLK frequency used on FDCAN domain +1118:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1119:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1120:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1121:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1122:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 +1123:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1124:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1125:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1126:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1127:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1128:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1129:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1130:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 +1131:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1132:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1133:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1134:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1135:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1136:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1137:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1138:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1139:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1140:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1141:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ +1142:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1143:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +1144:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* FDCAN1 || FDCAN2 */ +1145:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1146:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +1147:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + ARM GAS /tmp/ccBwposX.s page 84 + + +1148:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PLLQCLK frequency used on USB domain +1149:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), +1150:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); +1151:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) +1152:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLM__ This parameter can be one of the following values: +1153:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_1 +1154:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_2 +1155:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_3 +1156:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_4 +1157:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_5 +1158:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_6 +1159:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_7 +1160:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLM_DIV_8 +1161:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 +1162:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __PLLQ__ This parameter can be one of the following values: +1163:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_2 +1164:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_3 +1165:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_4 +1166:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_5 +1167:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_6 +1168:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_7 +1169:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_PLLQ_DIV_8 +1170:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PLL clock frequency (in Hz) +1171:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1172:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ +1173:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ +1174:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +1175:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +1176:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1177:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1178:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the HCLK frequency +1179:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) +1180:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __AHBPRESCALER__ This parameter can be one of the following values: +1181:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1182:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1183:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1184:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1185:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1186:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1187:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1188:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1189:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1190:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval HCLK clock frequency (in Hz) +1191:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1192:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ +1193:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & +1194:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1195:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1196:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) +1197:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __HCLKFREQ__ HCLK frequency +1198:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __APB1PRESCALER__ This parameter can be one of the following values: +1199:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1200:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1201:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1202:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1203:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1204:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval PCLK1 clock frequency (in Hz) + ARM GAS /tmp/ccBwposX.s page 85 + + +1205:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1206:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ +1207:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU)) +1208:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1209:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1210:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Helper macro to calculate the HSISYS frequency +1211:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param __HSIDIV__ This parameter can be one of the following values: +1212:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_1 +1213:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_2 +1214:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_4 +1215:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_8 +1216:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_16 +1217:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_32 +1218:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_64 +1219:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_128 +1220:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval HSISYS clock frequency (in Hz) +1221:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1222:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) +1223:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1224:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1225:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1226:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1227:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1228:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1229:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1230:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1231:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1232:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /* Exported functions --------------------------------------------------------*/ +1233:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions +1234:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1235:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1236:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1237:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSE HSE +1238:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1239:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1240:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1241:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1242:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable the Clock Security System. +1243:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS +1244:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1245:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1246:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +1247:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1248:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_CSSON); +1249:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1250:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1251:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1252:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable HSE external oscillator (HSE Bypass) +1253:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass +1254:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1255:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1256:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +1257:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1258:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEBYP); +1259:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1260:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1261:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** + ARM GAS /tmp/ccBwposX.s page 86 + + +1262:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable HSE external oscillator (HSE Bypass) +1263:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass +1264:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1265:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1266:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +1267:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1268:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +1269:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1270:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1271:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1272:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable HSE crystal oscillator (HSE ON) +1273:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Enable +1274:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1275:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1276:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Enable(void) +1277:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1278:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSEON); +1279:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1280:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1281:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1282:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable HSE crystal oscillator (HSE ON) +1283:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSEON LL_RCC_HSE_Disable +1284:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1285:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1286:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSE_Disable(void) +1287:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1288:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +1289:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1290:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1291:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1292:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if HSE oscillator Ready +1293:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSERDY LL_RCC_HSE_IsReady +1294:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1295:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1296:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +1297:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1298:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +1299:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1300:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1301:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1302:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1303:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1304:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1305:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI HSI +1306:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1307:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1308:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1309:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1310:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable HSI even in stop mode +1311:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note HSI oscillator is forced ON even in Stop mode +1312:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode +1313:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1314:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1315:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +1316:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1317:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSIKERON); +1318:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } + ARM GAS /tmp/ccBwposX.s page 87 + + +1319:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1320:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1321:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable HSI in stop mode +1322:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode +1323:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1324:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1325:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +1326:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1327:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +1328:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1329:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1330:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1331:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if HSI in stop mode is enabled +1332:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode +1333:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1334:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1335:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +1336:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1337:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +1338:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1339:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1340:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1341:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable HSI oscillator +1342:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Enable +1343:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1344:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1345:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Enable(void) +1346:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1347:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSION); +1348:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1349:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1350:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1351:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable HSI oscillator +1352:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSION LL_RCC_HSI_Disable +1353:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1354:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1355:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_Disable(void) +1356:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1357:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSION); +1358:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1359:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1360:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1361:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if HSI clock is ready +1362:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady +1363:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1364:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1365:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +1366:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1367:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +1368:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1369:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1370:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1371:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get HSI Calibration value +1372:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note When HSITRIM is written, HSICAL is updated with the sum of +1373:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * HSITRIM and the factory trim value +1374:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration +1375:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + ARM GAS /tmp/ccBwposX.s page 88 + + +1376:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1377:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +1378:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1379:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +1380:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1381:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1382:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1383:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Set HSI Calibration trimming +1384:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note user-programmable trimming value that is added to the HSICAL +1385:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note Default value is 64, which, when added to the HSICAL value, +1386:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * should trim the HSI to 16 MHz +/- 1 % +1387:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming +1388:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param Value Between Min_Data = 0 and Max_Data = 127 +1389:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1390:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1391:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +1392:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1393:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +1394:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1395:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1396:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1397:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get HSI Calibration trimming +1398:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming +1399:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Between Min_Data = 0 and Max_Data = 127 +1400:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1401:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +1402:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1403:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +1404:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1405:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1406:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1407:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1408:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1409:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1410:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #if defined(RCC_HSI48_SUPPORT) +1411:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_HSI48 HSI48 +1412:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1413:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1414:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1415:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1416:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable HSI48 +1417:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable +1418:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1419:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1420:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Enable(void) +1421:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1422:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CR, RCC_CR_HSI48ON); +1423:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1424:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1425:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1426:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable HSI48 +1427:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable +1428:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1429:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1430:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_HSI48_Disable(void) +1431:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1432:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); + ARM GAS /tmp/ccBwposX.s page 89 + + +1433:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1434:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1435:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1436:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if HSI48 oscillator Ready +1437:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady +1438:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1439:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1440:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +1441:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1442:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +1443:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1444:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1445:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1446:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get HSI48 Calibration value +1447:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration +1448:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF +1449:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1450:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +1451:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1452:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +1453:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1454:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1455:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1456:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1457:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1458:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** #endif /* RCC_HSI48_SUPPORT */ +1459:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1460:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSE LSE +1461:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1462:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1463:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1464:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1465:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable Low Speed External (LSE) crystal. +1466:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Enable +1467:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1468:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1469:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Enable(void) +1470:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1471:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +1472:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1473:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1474:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1475:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable Low Speed External (LSE) crystal. +1476:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEON LL_RCC_LSE_Disable +1477:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1478:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1479:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_Disable(void) +1480:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1481:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +1482:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1483:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1484:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1485:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable external clock source (LSE bypass). +1486:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass +1487:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1488:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1489:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) + ARM GAS /tmp/ccBwposX.s page 90 + + +1490:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1491:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +1492:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1493:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1494:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1495:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable external clock source (LSE bypass). +1496:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass +1497:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1498:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1499:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +1500:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1501:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +1502:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1503:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1504:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1505:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Set LSE oscillator drive capability +1506:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note The oscillator is in Xtal mode when it is not in bypass mode. +1507:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability +1508:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param LSEDrive This parameter can be one of the following values: +1509:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1510:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1511:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1512:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1513:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1514:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1515:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +1516:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1517:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +1518:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1519:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1520:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1521:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get LSE oscillator drive capability +1522:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability +1523:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1524:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_LOW +1525:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW +1526:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH +1527:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSEDRIVE_HIGH +1528:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1529:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +1530:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1531:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +1532:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1533:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1534:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1535:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable Clock security system on LSE. +1536:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS +1537:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1538:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1539:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +1540:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1541:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +1542:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1543:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1544:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1545:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable Clock security system on LSE. +1546:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note Clock security system can be disabled only after a LSE + ARM GAS /tmp/ccBwposX.s page 91 + + +1547:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * failure detection. In that case it MUST be disabled by software. +1548:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS +1549:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1550:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1551:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +1552:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1553:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +1554:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1555:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1556:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1557:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if LSE oscillator Ready +1558:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady +1559:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1560:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1561:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +1562:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1563:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +1564:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1565:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1566:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1567:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if CSS on LSE failure Detection +1568:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected +1569:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1570:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1571:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +1572:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1573:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +1574:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1575:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1576:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1577:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1578:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1579:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1580:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSI LSI +1581:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1582:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1583:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1584:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1585:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable LSI Oscillator +1586:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Enable +1587:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1588:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1589:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Enable(void) +1590:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1591:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->CSR, RCC_CSR_LSION); +1592:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1593:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1594:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1595:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable LSI Oscillator +1596:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CSR LSION LL_RCC_LSI_Disable +1597:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1598:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1599:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSI_Disable(void) +1600:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1601:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +1602:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1603:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** + ARM GAS /tmp/ccBwposX.s page 92 + + +1604:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1605:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Check if LSI is Ready +1606:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady +1607:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval State of bit (1 or 0). +1608:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1609:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +1610:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1611:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +1612:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1613:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1614:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1615:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1616:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1617:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1618:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_LSCO LSCO +1619:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1620:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1621:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1622:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1623:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Enable Low speed clock +1624:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable +1625:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1626:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1627:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSCO_Enable(void) +1628:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1629:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +1630:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1631:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1632:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1633:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Disable Low speed clock +1634:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable +1635:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1636:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1637:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSCO_Disable(void) +1638:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1639:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +1640:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1641:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1642:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1643:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Configure Low speed clock selection +1644:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource +1645:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1646:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI +1647:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE +1648:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1649:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1650:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +1651:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1652:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +1653:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1654:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1655:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1656:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get Low speed clock selection +1657:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource +1658:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1659:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI +1660:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + ARM GAS /tmp/ccBwposX.s page 93 + + +1661:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1662:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +1663:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1664:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +1665:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1666:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1667:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1668:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @} +1669:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1670:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1671:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** @defgroup RCC_LL_EF_System System +1672:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @{ +1673:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1674:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1675:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1676:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Configure the system clock source +1677:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR SW LL_RCC_SetSysClkSource +1678:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param Source This parameter can be one of the following values: +1679:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI +1680:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE +1681:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL +1682:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI +1683:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE +1684:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1685:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1686:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +1687:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1688:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +1689:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1690:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1691:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1692:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get the system clock source +1693:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR SWS LL_RCC_GetSysClkSource +1694:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1695:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI +1696:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE +1697:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL +1698:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI +1699:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE +1700:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1701:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +1702:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1703:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +1704:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1705:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1706:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1707:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Set AHB prescaler +1708:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler +1709:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1710:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1711:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1712:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1713:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1714:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1715:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1716:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1717:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 + ARM GAS /tmp/ccBwposX.s page 94 + + +1718:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 +1719:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1720:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1721:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +1722:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1723:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +1724:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1725:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1726:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1727:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Set APB1 prescaler +1728:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler +1729:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param Prescaler This parameter can be one of the following values: +1730:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1731:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1732:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1733:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1734:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1735:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1736:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1737:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +1738:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1739:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +1740:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1741:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1742:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1743:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Set HSI16 division factor +1744:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv +1745:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as +1746:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * system clock source. +1747:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @param HSIDiv This parameter can be one of the following values: +1748:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_1 +1749:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_2 +1750:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_4 +1751:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_8 +1752:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_16 +1753:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_32 +1754:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_64 +1755:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_HSI_DIV_128 +1756:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval None +1757:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1758:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) +1759:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1760:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); +1761:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1762:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1763:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get AHB prescaler +1764:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler +1765:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1766:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_1 +1767:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_2 +1768:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_4 +1769:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_8 +1770:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_16 +1771:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_64 +1772:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_128 +1773:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_256 +1774:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_SYSCLK_DIV_512 + ARM GAS /tmp/ccBwposX.s page 95 + + +1775:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1776:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +1777:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1778:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +1779:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** } +1780:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** +1781:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** /** +1782:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @brief Get APB1 prescaler +1783:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler +1784:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @retval Returned value can be one of the following values: +1785:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_1 +1786:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_2 +1787:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_4 +1788:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_8 +1789:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** * @arg @ref LL_RCC_APB1_DIV_16 +1790:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** */ +1791:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) + 2025 .loc 2 1791 26 is_stmt 1 view .LVU608 + 2026 .LBB10: +1792:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** { +1793:Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h **** return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); + 2027 .loc 2 1793 3 view .LVU609 + 2028 .loc 2 1793 21 is_stmt 0 view .LVU610 + 2029 0006 064B ldr r3, .L180 + 2030 0008 9A68 ldr r2, [r3, #8] + 2031 .LBE10: + 2032 .LBE9: + 2033 .loc 1 1194 22 view .LVU611 + 2034 000a 120B lsrs r2, r2, #12 + 2035 000c 0723 movs r3, #7 + 2036 000e 1340 ands r3, r2 + 2037 0010 9B00 lsls r3, r3, #2 + 2038 0012 044A ldr r2, .L180+4 + 2039 0014 9A58 ldr r2, [r3, r2] + 2040 0016 1F23 movs r3, #31 + 2041 0018 1340 ands r3, r2 + 2042 .loc 1 1194 11 view .LVU612 + 2043 001a D840 lsrs r0, r0, r3 +1195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2044 .loc 1 1195 1 view .LVU613 + 2045 @ sp needed + 2046 001c 10BD pop {r4, pc} + 2047 .L181: + 2048 001e C046 .align 2 + 2049 .L180: + 2050 0020 00100240 .word 1073876992 + 2051 0024 00000000 .word APBPrescTable + 2052 .cfi_endproc + 2053 .LFE303: + 2055 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 2056 .align 1 + 2057 .global HAL_RCC_GetOscConfig + 2058 .syntax unified + 2059 .code 16 + 2060 .thumb_func + 2061 .fpu softvfp + 2063 HAL_RCC_GetOscConfig: + ARM GAS /tmp/ccBwposX.s page 96 + + + 2064 .LVL146: + 2065 .LFB304: +1196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Configure the RCC_OscInitStruct according to the internal +1199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * RCC configuration registers. +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that +1201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * will be configured. +1202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +1205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2066 .loc 1 1205 1 is_stmt 1 view -0 + 2067 .cfi_startproc + 2068 @ args = 0, pretend = 0, frame = 0 + 2069 @ frame_needed = 0, uses_anonymous_args = 0 + 2070 @ link register save eliminated. +1206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ +1207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != (void *)NULL); + 2071 .loc 1 1207 3 view .LVU615 +1208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLA +1213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #else +1214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + 2072 .loc 1 1214 3 view .LVU616 + 2073 .loc 1 1214 37 is_stmt 0 view .LVU617 + 2074 0000 0F23 movs r3, #15 + 2075 0002 0360 str r3, [r0] +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +1216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + 2076 .loc 1 1219 3 is_stmt 1 view .LVU618 + 2077 .loc 1 1219 11 is_stmt 0 view .LVU619 + 2078 0004 324B ldr r3, .L195 + 2079 0006 1B68 ldr r3, [r3] + 2080 .loc 1 1219 6 view .LVU620 + 2081 0008 5B03 lsls r3, r3, #13 + 2082 000a 42D5 bpl .L183 +1220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + 2083 .loc 1 1221 5 is_stmt 1 view .LVU621 + 2084 .loc 1 1221 33 is_stmt 0 view .LVU622 + 2085 000c A023 movs r3, #160 + 2086 000e DB02 lsls r3, r3, #11 + 2087 0010 4360 str r3, [r0, #4] + 2088 .L184: +1222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) +1224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; +1226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else + ARM GAS /tmp/ccBwposX.s page 97 + + +1228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; +1230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + 2089 .loc 1 1233 3 is_stmt 1 view .LVU623 + 2090 .loc 1 1233 11 is_stmt 0 view .LVU624 + 2091 0012 2F4B ldr r3, .L195 + 2092 0014 1B68 ldr r3, [r3] + 2093 .loc 1 1233 6 view .LVU625 + 2094 0016 DB05 lsls r3, r3, #23 + 2095 0018 46D5 bpl .L186 +1234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; + 2096 .loc 1 1235 5 is_stmt 1 view .LVU626 + 2097 .loc 1 1235 33 is_stmt 0 view .LVU627 + 2098 001a 8023 movs r3, #128 + 2099 001c 5B00 lsls r3, r3, #1 + 2100 001e C360 str r3, [r0, #12] + 2101 .L187: +1236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; +1240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_P + 2102 .loc 1 1241 3 is_stmt 1 view .LVU628 + 2103 .loc 1 1241 49 is_stmt 0 view .LVU629 + 2104 0020 2B4B ldr r3, .L195 + 2105 0022 5968 ldr r1, [r3, #4] + 2106 .loc 1 1241 78 view .LVU630 + 2107 0024 090A lsrs r1, r1, #8 + 2108 0026 7F22 movs r2, #127 + 2109 0028 0A40 ands r2, r1 + 2110 .loc 1 1241 42 view .LVU631 + 2111 002a 4261 str r2, [r0, #20] +1242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSIDiv = (RCC->CR & RCC_CR_HSIDIV); + 2112 .loc 1 1242 3 is_stmt 1 view .LVU632 + 2113 .loc 1 1242 35 is_stmt 0 view .LVU633 + 2114 002c 1A68 ldr r2, [r3] + 2115 .loc 1 1242 40 view .LVU634 + 2116 002e E021 movs r1, #224 + 2117 0030 8901 lsls r1, r1, #6 + 2118 0032 0A40 ands r2, r1 + 2119 .loc 1 1242 29 view .LVU635 + 2120 0034 0261 str r2, [r0, #16] +1243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + 2121 .loc 1 1245 3 is_stmt 1 view .LVU636 + 2122 .loc 1 1245 11 is_stmt 0 view .LVU637 + 2123 0036 DB6D ldr r3, [r3, #92] + 2124 .loc 1 1245 6 view .LVU638 + 2125 0038 5B07 lsls r3, r3, #29 + 2126 003a 38D5 bpl .L188 +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 98 + + +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + 2127 .loc 1 1247 5 is_stmt 1 view .LVU639 + 2128 .loc 1 1247 33 is_stmt 0 view .LVU640 + 2129 003c 0523 movs r3, #5 + 2130 003e 8360 str r3, [r0, #8] + 2131 .L189: +1248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) +1250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; +1252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + 2132 .loc 1 1259 3 is_stmt 1 view .LVU641 + 2133 .loc 1 1259 11 is_stmt 0 view .LVU642 + 2134 0040 234B ldr r3, .L195 + 2135 0042 1B6E ldr r3, [r3, #96] + 2136 .loc 1 1259 6 view .LVU643 + 2137 0044 DB07 lsls r3, r3, #31 + 2138 0046 3CD5 bpl .L191 +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; + 2139 .loc 1 1261 5 is_stmt 1 view .LVU644 + 2140 .loc 1 1261 33 is_stmt 0 view .LVU645 + 2141 0048 0123 movs r3, #1 + 2142 004a 8361 str r3, [r0, #24] + 2143 .L192: +1262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; +1266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_HSI48_SUPPORT) +1269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the HSI48 configuration ---------------------------------------------*/ +1270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if (READ_BIT(RCC->CR, RCC_CR_HSI48ON) == RCC_CR_HSI48ON) +1271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; +1277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_HSI48_SUPPORT */ +1279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + 2144 .loc 1 1281 3 is_stmt 1 view .LVU646 + 2145 .loc 1 1281 11 is_stmt 0 view .LVU647 + 2146 004c 204B ldr r3, .L195 + 2147 004e 1B68 ldr r3, [r3] + 2148 .loc 1 1281 6 view .LVU648 + ARM GAS /tmp/ccBwposX.s page 99 + + + 2149 0050 DB01 lsls r3, r3, #7 + 2150 0052 39D5 bpl .L193 +1282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + 2151 .loc 1 1283 5 is_stmt 1 view .LVU649 + 2152 .loc 1 1283 37 is_stmt 0 view .LVU650 + 2153 0054 0223 movs r3, #2 + 2154 0056 C361 str r3, [r0, #28] + 2155 .L194: +1284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** else +1286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; +1288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + 2156 .loc 1 1289 3 is_stmt 1 view .LVU651 + 2157 .loc 1 1289 42 is_stmt 0 view .LVU652 + 2158 0058 1D4B ldr r3, .L195 + 2159 005a D968 ldr r1, [r3, #12] + 2160 .loc 1 1289 52 view .LVU653 + 2161 005c 0322 movs r2, #3 + 2162 005e 0A40 ands r2, r1 + 2163 .loc 1 1289 36 view .LVU654 + 2164 0060 0262 str r2, [r0, #32] +1290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLM = (RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + 2165 .loc 1 1290 3 is_stmt 1 view .LVU655 + 2166 .loc 1 1290 37 is_stmt 0 view .LVU656 + 2167 0062 D968 ldr r1, [r3, #12] + 2168 .loc 1 1290 47 view .LVU657 + 2169 0064 7022 movs r2, #112 + 2170 0066 0A40 ands r2, r1 + 2171 .loc 1 1290 31 view .LVU658 + 2172 0068 4262 str r2, [r0, #36] +1291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLN = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 2173 .loc 1 1291 3 is_stmt 1 view .LVU659 + 2174 .loc 1 1291 38 is_stmt 0 view .LVU660 + 2175 006a D968 ldr r1, [r3, #12] + 2176 .loc 1 1291 68 view .LVU661 + 2177 006c 090A lsrs r1, r1, #8 + 2178 006e 7F22 movs r2, #127 + 2179 0070 0A40 ands r2, r1 + 2180 .loc 1 1291 31 view .LVU662 + 2181 0072 8262 str r2, [r0, #40] +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLP = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP); + 2182 .loc 1 1292 3 is_stmt 1 view .LVU663 + 2183 .loc 1 1292 37 is_stmt 0 view .LVU664 + 2184 0074 DA68 ldr r2, [r3, #12] + 2185 .loc 1 1292 47 view .LVU665 + 2186 0076 F821 movs r1, #248 + 2187 0078 8903 lsls r1, r1, #14 + 2188 007a 0A40 ands r2, r1 + 2189 .loc 1 1292 31 view .LVU666 + 2190 007c C262 str r2, [r0, #44] +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #if defined(RCC_PLLQ_SUPPORT) +1294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLQ = (RCC->PLLCFGR & RCC_PLLCFGR_PLLQ); + 2191 .loc 1 1294 3 is_stmt 1 view .LVU667 + 2192 .loc 1 1294 37 is_stmt 0 view .LVU668 + ARM GAS /tmp/ccBwposX.s page 100 + + + 2193 007e DA68 ldr r2, [r3, #12] + 2194 .loc 1 1294 47 view .LVU669 + 2195 0080 E021 movs r1, #224 + 2196 0082 0905 lsls r1, r1, #20 + 2197 0084 0A40 ands r2, r1 + 2198 .loc 1 1294 31 view .LVU670 + 2199 0086 0263 str r2, [r0, #48] +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** #endif /* RCC_PLLQ_SUPPORT */ +1296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLR = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR); + 2200 .loc 1 1296 3 is_stmt 1 view .LVU671 + 2201 .loc 1 1296 37 is_stmt 0 view .LVU672 + 2202 0088 DB68 ldr r3, [r3, #12] + 2203 .loc 1 1296 47 view .LVU673 + 2204 008a 5B0F lsrs r3, r3, #29 + 2205 008c 5B07 lsls r3, r3, #29 + 2206 .loc 1 1296 31 view .LVU674 + 2207 008e 4363 str r3, [r0, #52] +1297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2208 .loc 1 1297 1 view .LVU675 + 2209 @ sp needed + 2210 0090 7047 bx lr + 2211 .L183: +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2212 .loc 1 1223 8 is_stmt 1 view .LVU676 +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2213 .loc 1 1223 16 is_stmt 0 view .LVU677 + 2214 0092 0F4B ldr r3, .L195 + 2215 0094 1B68 ldr r3, [r3] +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2216 .loc 1 1223 11 view .LVU678 + 2217 0096 DB03 lsls r3, r3, #15 + 2218 0098 03D5 bpl .L185 +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2219 .loc 1 1225 5 is_stmt 1 view .LVU679 +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2220 .loc 1 1225 33 is_stmt 0 view .LVU680 + 2221 009a 8023 movs r3, #128 + 2222 009c 5B02 lsls r3, r3, #9 + 2223 009e 4360 str r3, [r0, #4] + 2224 00a0 B7E7 b .L184 + 2225 .L185: +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2226 .loc 1 1229 5 is_stmt 1 view .LVU681 +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2227 .loc 1 1229 33 is_stmt 0 view .LVU682 + 2228 00a2 0023 movs r3, #0 + 2229 00a4 4360 str r3, [r0, #4] + 2230 00a6 B4E7 b .L184 + 2231 .L186: +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2232 .loc 1 1239 5 is_stmt 1 view .LVU683 +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2233 .loc 1 1239 33 is_stmt 0 view .LVU684 + 2234 00a8 0023 movs r3, #0 + 2235 00aa C360 str r3, [r0, #12] + 2236 00ac B8E7 b .L187 + 2237 .L188: + ARM GAS /tmp/ccBwposX.s page 101 + + +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2238 .loc 1 1249 8 is_stmt 1 view .LVU685 +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2239 .loc 1 1249 16 is_stmt 0 view .LVU686 + 2240 00ae 084B ldr r3, .L195 + 2241 00b0 DB6D ldr r3, [r3, #92] +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2242 .loc 1 1249 11 view .LVU687 + 2243 00b2 DB07 lsls r3, r3, #31 + 2244 00b4 02D5 bpl .L190 +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2245 .loc 1 1251 5 is_stmt 1 view .LVU688 +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2246 .loc 1 1251 33 is_stmt 0 view .LVU689 + 2247 00b6 0123 movs r3, #1 + 2248 00b8 8360 str r3, [r0, #8] + 2249 00ba C1E7 b .L189 + 2250 .L190: +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2251 .loc 1 1255 5 is_stmt 1 view .LVU690 +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2252 .loc 1 1255 33 is_stmt 0 view .LVU691 + 2253 00bc 0023 movs r3, #0 + 2254 00be 8360 str r3, [r0, #8] + 2255 00c0 BEE7 b .L189 + 2256 .L191: +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2257 .loc 1 1265 5 is_stmt 1 view .LVU692 +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2258 .loc 1 1265 33 is_stmt 0 view .LVU693 + 2259 00c2 0023 movs r3, #0 + 2260 00c4 8361 str r3, [r0, #24] + 2261 00c6 C1E7 b .L192 + 2262 .L193: +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2263 .loc 1 1287 5 is_stmt 1 view .LVU694 +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2264 .loc 1 1287 37 is_stmt 0 view .LVU695 + 2265 00c8 0123 movs r3, #1 + 2266 00ca C361 str r3, [r0, #28] + 2267 00cc C4E7 b .L194 + 2268 .L196: + 2269 00ce C046 .align 2 + 2270 .L195: + 2271 00d0 00100240 .word 1073876992 + 2272 .cfi_endproc + 2273 .LFE304: + 2275 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 2276 .align 1 + 2277 .global HAL_RCC_GetClockConfig + 2278 .syntax unified + 2279 .code 16 + 2280 .thumb_func + 2281 .fpu softvfp + 2283 HAL_RCC_GetClockConfig: + 2284 .LVL147: + 2285 .LFB305: + ARM GAS /tmp/ccBwposX.s page 102 + + +1298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Configure the RCC_ClkInitStruct according to the internal +1301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * RCC configuration registers. +1302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that +1303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * will be configured. +1304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. +1305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2286 .loc 1 1308 1 is_stmt 1 view -0 + 2287 .cfi_startproc + 2288 @ args = 0, pretend = 0, frame = 0 + 2289 @ frame_needed = 0, uses_anonymous_args = 0 + 2290 .loc 1 1308 1 is_stmt 0 view .LVU697 + 2291 0000 30B5 push {r4, r5, lr} + 2292 .LCFI8: + 2293 .cfi_def_cfa_offset 12 + 2294 .cfi_offset 4, -12 + 2295 .cfi_offset 5, -8 + 2296 .cfi_offset 14, -4 +1309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check the parameters */ +1310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != (void *)NULL); + 2297 .loc 1 1310 3 is_stmt 1 view .LVU698 +1311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** assert_param(pFLatency != (void *)NULL); + 2298 .loc 1 1311 3 view .LVU699 +1312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + 2299 .loc 1 1314 3 view .LVU700 + 2300 .loc 1 1314 32 is_stmt 0 view .LVU701 + 2301 0002 0723 movs r3, #7 + 2302 0004 0360 str r3, [r0] +1315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ +1317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 2303 .loc 1 1317 3 is_stmt 1 view .LVU702 + 2304 .loc 1 1317 51 is_stmt 0 view .LVU703 + 2305 0006 094A ldr r2, .L198 + 2306 0008 9468 ldr r4, [r2, #8] + 2307 .loc 1 1317 37 view .LVU704 + 2308 000a 1C40 ands r4, r3 + 2309 .loc 1 1317 35 view .LVU705 + 2310 000c 4460 str r4, [r0, #4] +1318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ +1320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 2311 .loc 1 1320 3 is_stmt 1 view .LVU706 + 2312 .loc 1 1320 52 is_stmt 0 view .LVU707 + 2313 000e 9468 ldr r4, [r2, #8] + 2314 .loc 1 1320 38 view .LVU708 + 2315 0010 F025 movs r5, #240 + 2316 0012 2D01 lsls r5, r5, #4 + 2317 0014 2C40 ands r4, r5 + 2318 .loc 1 1320 36 view .LVU709 + 2319 0016 8460 str r4, [r0, #8] + ARM GAS /tmp/ccBwposX.s page 103 + + +1321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + 2320 .loc 1 1323 3 is_stmt 1 view .LVU710 + 2321 .loc 1 1323 53 is_stmt 0 view .LVU711 + 2322 0018 9268 ldr r2, [r2, #8] + 2323 .loc 1 1323 39 view .LVU712 + 2324 001a E024 movs r4, #224 + 2325 001c E401 lsls r4, r4, #7 + 2326 001e 2240 ands r2, r4 + 2327 .loc 1 1323 37 view .LVU713 + 2328 0020 C260 str r2, [r0, #12] +1324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 2329 .loc 1 1327 3 is_stmt 1 view .LVU714 + 2330 .loc 1 1327 32 is_stmt 0 view .LVU715 + 2331 0022 034A ldr r2, .L198+4 + 2332 0024 1268 ldr r2, [r2] + 2333 .loc 1 1327 16 view .LVU716 + 2334 0026 1340 ands r3, r2 + 2335 .loc 1 1327 14 view .LVU717 + 2336 0028 0B60 str r3, [r1] +1328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2337 .loc 1 1328 1 view .LVU718 + 2338 @ sp needed + 2339 002a 30BD pop {r4, r5, pc} + 2340 .L199: + 2341 .align 2 + 2342 .L198: + 2343 002c 00100240 .word 1073876992 + 2344 0030 00200240 .word 1073881088 + 2345 .cfi_endproc + 2346 .LFE305: + 2348 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 2349 .align 1 + 2350 .global HAL_RCC_EnableCSS + 2351 .syntax unified + 2352 .code 16 + 2353 .thumb_func + 2354 .fpu softvfp + 2356 HAL_RCC_EnableCSS: + 2357 .LFB306: +1329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Enable the Clock Security System. +1332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator +1333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the +1334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), +1335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to +1336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. +1337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The Clock Security System can only be cleared by reset. +1338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) +1341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + ARM GAS /tmp/ccBwposX.s page 104 + + + 2358 .loc 1 1341 1 is_stmt 1 view -0 + 2359 .cfi_startproc + 2360 @ args = 0, pretend = 0, frame = 0 + 2361 @ frame_needed = 0, uses_anonymous_args = 0 + 2362 @ link register save eliminated. +1342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_CSSON) ; + 2363 .loc 1 1342 3 view .LVU720 + 2364 0000 034A ldr r2, .L201 + 2365 0002 1168 ldr r1, [r2] + 2366 0004 8023 movs r3, #128 + 2367 0006 1B03 lsls r3, r3, #12 + 2368 0008 0B43 orrs r3, r1 + 2369 000a 1360 str r3, [r2] +1343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2370 .loc 1 1343 1 is_stmt 0 view .LVU721 + 2371 @ sp needed + 2372 000c 7047 bx lr + 2373 .L202: + 2374 000e C046 .align 2 + 2375 .L201: + 2376 0010 00100240 .word 1073876992 + 2377 .cfi_endproc + 2378 .LFE306: + 2380 .section .text.HAL_RCC_EnableLSECSS,"ax",%progbits + 2381 .align 1 + 2382 .global HAL_RCC_EnableLSECSS + 2383 .syntax unified + 2384 .code 16 + 2385 .thumb_func + 2386 .fpu softvfp + 2388 HAL_RCC_EnableLSECSS: + 2389 .LFB307: +1344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Enable the LSE Clock Security System. +1347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note If a failure is detected on the LSE oscillator clock, this oscillator +1348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the +1349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), +1350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to +1351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. +1352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The LSE Clock Security System Detection bit (LSECSSD in BDCR) can only be +1353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * cleared by a backup domain reset. +1354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_EnableLSECSS(void) +1357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2390 .loc 1 1357 1 is_stmt 1 view -0 + 2391 .cfi_startproc + 2392 @ args = 0, pretend = 0, frame = 0 + 2393 @ frame_needed = 0, uses_anonymous_args = 0 + 2394 @ link register save eliminated. +1358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + 2395 .loc 1 1358 3 view .LVU723 + 2396 0000 024A ldr r2, .L204 + 2397 0002 D36D ldr r3, [r2, #92] + 2398 0004 2021 movs r1, #32 + 2399 0006 0B43 orrs r3, r1 + ARM GAS /tmp/ccBwposX.s page 105 + + + 2400 0008 D365 str r3, [r2, #92] +1359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2401 .loc 1 1359 1 is_stmt 0 view .LVU724 + 2402 @ sp needed + 2403 000a 7047 bx lr + 2404 .L205: + 2405 .align 2 + 2406 .L204: + 2407 000c 00100240 .word 1073876992 + 2408 .cfi_endproc + 2409 .LFE307: + 2411 .section .text.HAL_RCC_DisableLSECSS,"ax",%progbits + 2412 .align 1 + 2413 .global HAL_RCC_DisableLSECSS + 2414 .syntax unified + 2415 .code 16 + 2416 .thumb_func + 2417 .fpu softvfp + 2419 HAL_RCC_DisableLSECSS: + 2420 .LFB308: +1360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Disable the LSE Clock Security System. +1363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note After LSE failure detection, the software must disable LSECSSON +1364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note The Clock Security System can only be cleared by reset otherwise. +1365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_DisableLSECSS(void) +1368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2421 .loc 1 1368 1 is_stmt 1 view -0 + 2422 .cfi_startproc + 2423 @ args = 0, pretend = 0, frame = 0 + 2424 @ frame_needed = 0, uses_anonymous_args = 0 + 2425 @ link register save eliminated. +1369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + 2426 .loc 1 1369 3 view .LVU726 + 2427 0000 024A ldr r2, .L207 + 2428 0002 D36D ldr r3, [r2, #92] + 2429 0004 2021 movs r1, #32 + 2430 0006 8B43 bics r3, r1 + 2431 0008 D365 str r3, [r2, #92] +1370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2432 .loc 1 1370 1 is_stmt 0 view .LVU727 + 2433 @ sp needed + 2434 000a 7047 bx lr + 2435 .L208: + 2436 .align 2 + 2437 .L207: + 2438 000c 00100240 .word 1073876992 + 2439 .cfi_endproc + 2440 .LFE308: + 2442 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 2443 .align 1 + 2444 .weak HAL_RCC_CSSCallback + 2445 .syntax unified + 2446 .code 16 + 2447 .thumb_func + ARM GAS /tmp/ccBwposX.s page 106 + + + 2448 .fpu softvfp + 2450 HAL_RCC_CSSCallback: + 2451 .LFB310: +1371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Handle the RCC Clock Security System interrupt request. +1374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval None +1376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t itflag = RCC->CIFR; +1380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Clear interrupt flags related to CSS */ +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF)); +1383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check RCC CSSF interrupt flag */ +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((itflag & RCC_CIFR_CSSF) != 0x00u) +1386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_RCC_CSSCallback(); +1389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Check RCC LSECSSF interrupt flag */ +1392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** if ((itflag & RCC_CIFR_LSECSSF) != 0x00u) +1393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { +1394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** HAL_RCC_LSECSSCallback(); +1396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } +1398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Handle the RCC HSE Clock Security System interrupt callback. +1401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval none +1402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) +1404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2452 .loc 1 1404 1 is_stmt 1 view -0 + 2453 .cfi_startproc + 2454 @ args = 0, pretend = 0, frame = 0 + 2455 @ frame_needed = 0, uses_anonymous_args = 0 + 2456 @ link register save eliminated. +1405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* NOTE : This function should not be modified, when the callback is needed, +1406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** the @ref HAL_RCC_CSSCallback should be implemented in the user file +1407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2457 .loc 1 1408 1 view .LVU729 + 2458 @ sp needed + 2459 0000 7047 bx lr + 2460 .cfi_endproc + 2461 .LFE310: + 2463 .section .text.HAL_RCC_LSECSSCallback,"ax",%progbits + 2464 .align 1 + 2465 .weak HAL_RCC_LSECSSCallback + 2466 .syntax unified + 2467 .code 16 + 2468 .thumb_func + ARM GAS /tmp/ccBwposX.s page 107 + + + 2469 .fpu softvfp + 2471 HAL_RCC_LSECSSCallback: + 2472 .LFB311: +1409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief RCC LSE Clock Security System interrupt callback. +1412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval none +1413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** __weak void HAL_RCC_LSECSSCallback(void) +1415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2473 .loc 1 1415 1 view -0 + 2474 .cfi_startproc + 2475 @ args = 0, pretend = 0, frame = 0 + 2476 @ frame_needed = 0, uses_anonymous_args = 0 + 2477 @ link register save eliminated. +1416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* NOTE : This function should not be modified, when the callback is needed, +1417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** the HAL_RCC_LSECSSCallback should be implemented in the user file +1418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2478 .loc 1 1419 1 view .LVU731 + 2479 @ sp needed + 2480 0000 7047 bx lr + 2481 .cfi_endproc + 2482 .LFE311: + 2484 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 2485 .align 1 + 2486 .global HAL_RCC_NMI_IRQHandler + 2487 .syntax unified + 2488 .code 16 + 2489 .thumb_func + 2490 .fpu softvfp + 2492 HAL_RCC_NMI_IRQHandler: + 2493 .LFB309: +1378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t itflag = RCC->CIFR; + 2494 .loc 1 1378 1 view -0 + 2495 .cfi_startproc + 2496 @ args = 0, pretend = 0, frame = 0 + 2497 @ frame_needed = 0, uses_anonymous_args = 0 + 2498 0000 10B5 push {r4, lr} + 2499 .LCFI9: + 2500 .cfi_def_cfa_offset 8 + 2501 .cfi_offset 4, -8 + 2502 .cfi_offset 14, -4 +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2503 .loc 1 1379 3 view .LVU733 +1379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2504 .loc 1 1379 12 is_stmt 0 view .LVU734 + 2505 0002 084A ldr r2, .L216 + 2506 0004 D469 ldr r4, [r2, #28] + 2507 .LVL148: +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2508 .loc 1 1382 3 is_stmt 1 view .LVU735 +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2509 .loc 1 1382 23 is_stmt 0 view .LVU736 + 2510 0006 C023 movs r3, #192 + 2511 0008 9B00 lsls r3, r3, #2 + 2512 000a 2340 ands r3, r4 + ARM GAS /tmp/ccBwposX.s page 108 + + +1382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2513 .loc 1 1382 13 view .LVU737 + 2514 000c 1362 str r3, [r2, #32] +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2515 .loc 1 1385 3 is_stmt 1 view .LVU738 +1385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2516 .loc 1 1385 6 is_stmt 0 view .LVU739 + 2517 000e E305 lsls r3, r4, #23 + 2518 0010 02D4 bmi .L214 + 2519 .L212: +1392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2520 .loc 1 1392 3 is_stmt 1 view .LVU740 +1392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2521 .loc 1 1392 6 is_stmt 0 view .LVU741 + 2522 0012 A305 lsls r3, r4, #22 + 2523 0014 03D4 bmi .L215 + 2524 .L211: +1397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2525 .loc 1 1397 1 view .LVU742 + 2526 @ sp needed + 2527 .LVL149: +1397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2528 .loc 1 1397 1 view .LVU743 + 2529 0016 10BD pop {r4, pc} + 2530 .LVL150: + 2531 .L214: +1388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2532 .loc 1 1388 5 is_stmt 1 view .LVU744 + 2533 0018 FFF7FEFF bl HAL_RCC_CSSCallback + 2534 .LVL151: + 2535 001c F9E7 b .L212 + 2536 .L215: +1395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2537 .loc 1 1395 5 view .LVU745 + 2538 001e FFF7FEFF bl HAL_RCC_LSECSSCallback + 2539 .LVL152: +1397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** + 2540 .loc 1 1397 1 is_stmt 0 view .LVU746 + 2541 0022 F8E7 b .L211 + 2542 .L217: + 2543 .align 2 + 2544 .L216: + 2545 0024 00100240 .word 1073876992 + 2546 .cfi_endproc + 2547 .LFE309: + 2549 .section .text.HAL_RCC_GetResetSource,"ax",%progbits + 2550 .align 1 + 2551 .global HAL_RCC_GetResetSource + 2552 .syntax unified + 2553 .code 16 + 2554 .thumb_func + 2555 .fpu softvfp + 2557 HAL_RCC_GetResetSource: + 2558 .LFB312: +1420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /** +1422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @brief Get and clear reset flags + ARM GAS /tmp/ccBwposX.s page 109 + + +1423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @note Once reset flags are retrieved, this API is clearing them in order +1424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * to isolate next reset reason. +1425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** * @retval can be a combination of @ref RCC_Reset_Flag +1426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** */ +1427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t HAL_RCC_GetResetSource(void) +1428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** { + 2559 .loc 1 1428 1 is_stmt 1 view -0 + 2560 .cfi_startproc + 2561 @ args = 0, pretend = 0, frame = 0 + 2562 @ frame_needed = 0, uses_anonymous_args = 0 + 2563 @ link register save eliminated. +1429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** uint32_t reset; + 2564 .loc 1 1429 3 view .LVU748 +1430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Get all reset flags */ +1432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** reset = RCC->CSR & RCC_RESET_FLAG_ALL; + 2565 .loc 1 1432 3 view .LVU749 + 2566 .loc 1 1432 14 is_stmt 0 view .LVU750 + 2567 0000 044B ldr r3, .L219 + 2568 0002 186E ldr r0, [r3, #96] + 2569 .loc 1 1432 9 view .LVU751 + 2570 0004 400E lsrs r0, r0, #25 + 2571 0006 4006 lsls r0, r0, #25 + 2572 .LVL153: +1433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** /* Clear Reset flags */ +1435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** RCC->CSR |= RCC_CSR_RMVF; + 2573 .loc 1 1435 3 is_stmt 1 view .LVU752 + 2574 .loc 1 1435 12 is_stmt 0 view .LVU753 + 2575 0008 196E ldr r1, [r3, #96] + 2576 000a 8022 movs r2, #128 + 2577 000c 1204 lsls r2, r2, #16 + 2578 000e 0A43 orrs r2, r1 + 2579 0010 1A66 str r2, [r3, #96] +1436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** +1437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** return reset; + 2580 .loc 1 1437 3 is_stmt 1 view .LVU754 +1438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c **** } + 2581 .loc 1 1438 1 is_stmt 0 view .LVU755 + 2582 @ sp needed + 2583 0012 7047 bx lr + 2584 .L220: + 2585 .align 2 + 2586 .L219: + 2587 0014 00100240 .word 1073876992 + 2588 .cfi_endproc + 2589 .LFE312: + 2591 .text + 2592 .Letext0: + 2593 .file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 2594 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h" + 2595 .file 5 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 2596 .file 6 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h" + 2597 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 2598 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h" + 2599 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h" + 2600 .file 10 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + ARM GAS /tmp/ccBwposX.s page 110 + + + 2601 .file 11 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/ccBwposX.s page 111 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_rcc.c + /tmp/ccBwposX.s:16 .text.HAL_RCC_DeInit:0000000000000000 $t + /tmp/ccBwposX.s:24 .text.HAL_RCC_DeInit:0000000000000000 HAL_RCC_DeInit + /tmp/ccBwposX.s:192 .text.HAL_RCC_DeInit:00000000000000a0 $d + /tmp/ccBwposX.s:201 .text.HAL_RCC_OscConfig:0000000000000000 $t + /tmp/ccBwposX.s:208 .text.HAL_RCC_OscConfig:0000000000000000 HAL_RCC_OscConfig + /tmp/ccBwposX.s:960 .text.HAL_RCC_OscConfig:0000000000000318 $d + /tmp/ccBwposX.s:974 .text.HAL_RCC_OscConfig:0000000000000344 $t + /tmp/ccBwposX.s:1294 .text.HAL_RCC_OscConfig:00000000000004ac $d + /tmp/ccBwposX.s:1303 .text.HAL_RCC_MCOConfig:0000000000000000 $t + /tmp/ccBwposX.s:1310 .text.HAL_RCC_MCOConfig:0000000000000000 HAL_RCC_MCOConfig + /tmp/ccBwposX.s:1414 .text.HAL_RCC_MCOConfig:0000000000000050 $d + /tmp/ccBwposX.s:1421 .text.HAL_RCC_GetSysClockFreq:0000000000000000 $t + /tmp/ccBwposX.s:1428 .text.HAL_RCC_GetSysClockFreq:0000000000000000 HAL_RCC_GetSysClockFreq + /tmp/ccBwposX.s:1602 .text.HAL_RCC_GetSysClockFreq:00000000000000ac $d + /tmp/ccBwposX.s:1609 .text.HAL_RCC_ClockConfig:0000000000000000 $t + /tmp/ccBwposX.s:1616 .text.HAL_RCC_ClockConfig:0000000000000000 HAL_RCC_ClockConfig + /tmp/ccBwposX.s:1959 .text.HAL_RCC_ClockConfig:000000000000016c $d + /tmp/ccBwposX.s:1971 .text.HAL_RCC_GetHCLKFreq:0000000000000000 $t + /tmp/ccBwposX.s:1978 .text.HAL_RCC_GetHCLKFreq:0000000000000000 HAL_RCC_GetHCLKFreq + /tmp/ccBwposX.s:1995 .text.HAL_RCC_GetHCLKFreq:0000000000000008 $d + /tmp/ccBwposX.s:2000 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 $t + /tmp/ccBwposX.s:2007 .text.HAL_RCC_GetPCLK1Freq:0000000000000000 HAL_RCC_GetPCLK1Freq + /tmp/ccBwposX.s:2050 .text.HAL_RCC_GetPCLK1Freq:0000000000000020 $d + /tmp/ccBwposX.s:2056 .text.HAL_RCC_GetOscConfig:0000000000000000 $t + /tmp/ccBwposX.s:2063 .text.HAL_RCC_GetOscConfig:0000000000000000 HAL_RCC_GetOscConfig + /tmp/ccBwposX.s:2271 .text.HAL_RCC_GetOscConfig:00000000000000d0 $d + /tmp/ccBwposX.s:2276 .text.HAL_RCC_GetClockConfig:0000000000000000 $t + /tmp/ccBwposX.s:2283 .text.HAL_RCC_GetClockConfig:0000000000000000 HAL_RCC_GetClockConfig + /tmp/ccBwposX.s:2343 .text.HAL_RCC_GetClockConfig:000000000000002c $d + /tmp/ccBwposX.s:2349 .text.HAL_RCC_EnableCSS:0000000000000000 $t + /tmp/ccBwposX.s:2356 .text.HAL_RCC_EnableCSS:0000000000000000 HAL_RCC_EnableCSS + /tmp/ccBwposX.s:2376 .text.HAL_RCC_EnableCSS:0000000000000010 $d + /tmp/ccBwposX.s:2381 .text.HAL_RCC_EnableLSECSS:0000000000000000 $t + /tmp/ccBwposX.s:2388 .text.HAL_RCC_EnableLSECSS:0000000000000000 HAL_RCC_EnableLSECSS + /tmp/ccBwposX.s:2407 .text.HAL_RCC_EnableLSECSS:000000000000000c $d + /tmp/ccBwposX.s:2412 .text.HAL_RCC_DisableLSECSS:0000000000000000 $t + /tmp/ccBwposX.s:2419 .text.HAL_RCC_DisableLSECSS:0000000000000000 HAL_RCC_DisableLSECSS + /tmp/ccBwposX.s:2438 .text.HAL_RCC_DisableLSECSS:000000000000000c $d + /tmp/ccBwposX.s:2443 .text.HAL_RCC_CSSCallback:0000000000000000 $t + /tmp/ccBwposX.s:2450 .text.HAL_RCC_CSSCallback:0000000000000000 HAL_RCC_CSSCallback + /tmp/ccBwposX.s:2464 .text.HAL_RCC_LSECSSCallback:0000000000000000 $t + /tmp/ccBwposX.s:2471 .text.HAL_RCC_LSECSSCallback:0000000000000000 HAL_RCC_LSECSSCallback + /tmp/ccBwposX.s:2485 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 $t + /tmp/ccBwposX.s:2492 .text.HAL_RCC_NMI_IRQHandler:0000000000000000 HAL_RCC_NMI_IRQHandler + /tmp/ccBwposX.s:2545 .text.HAL_RCC_NMI_IRQHandler:0000000000000024 $d + /tmp/ccBwposX.s:2550 .text.HAL_RCC_GetResetSource:0000000000000000 $t + /tmp/ccBwposX.s:2557 .text.HAL_RCC_GetResetSource:0000000000000000 HAL_RCC_GetResetSource + /tmp/ccBwposX.s:2587 .text.HAL_RCC_GetResetSource:0000000000000014 $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_InitTick +SystemCoreClock +uwTickPrio +HAL_GPIO_Init + ARM GAS /tmp/ccBwposX.s page 112 + + +__aeabi_uidiv +AHBPrescTable +APBPrescTable diff --git a/squero/build/stm32g0xx_hal_rcc.o b/squero/build/stm32g0xx_hal_rcc.o new file mode 100644 index 0000000000000000000000000000000000000000..2d5741597c38404a2df9aadc4106b3f83143cb78 GIT binary patch literal 25404 zcmc(ndtj8+ng7o_@4S;qG7~})AS8g31TYdZNgyCXfFYAWE?hzqFn}!yAz>mRiAg|I z6ui{p<=3jvt%_Y-bz6JcwcBE4TkUGAz5QC3D6}eWH&nZEw-?*B7pt!PzTfjcXEGUV z>;Cn7;hoQUp7WgNJm>PB_cHI~VC~w~mSrikS*lo#OG>@IP3Jh38pWzih1J00=l}Tr zd9Rw&FgbRpXq!rpX15nM=Et@MaDSZd>;!e;B0c2#(PhqW|s zM@nN#LtcAIV{S~_6+d^%3VnM_WqKlqv!z9|f2R`zkKgoV?<_S^`7=9qHs!K2&otZ} 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zqd%VejK40V6a77kHLVRgvl)LKP$c@RiMsL7ALBCqZbUlKA1mWpW;WyRdMFb8t%bi_ z=;#kib==>>NGJN^bMHH;kj?lz4mr`^PWWRx=r4fX#P~2i5I{`a$jM1k_A4{_P+Mls| zGRf{F>^`WUPr?paD#A*zolfXyoKEBY{Bn}NQ553*Gn;8IpNHUoeB<-fH|o=idzM^oOBTJ~Z5vfvB!TrF<4)Hj|f|WLJ#^tc(t1Gj=(!ORV>bbyyEz z$9i#j5U=;*B!5>G;k!KJ3^e|VlKjos>|V3bUqOPurAhu$XS?5t8<)o4;v|2Mz#o5% zPk#s@9^cv|fByu3Zv>3D@%ZYJ{GG;w!$UBmKV0s_{k4fduD{&wt5E71Tq~N5@p11= zvdg+`;&Ei`_pF literal 0 HcmV?d00001 diff --git a/squero/build/stm32g0xx_hal_rcc_ex.d b/squero/build/stm32g0xx_hal_rcc_ex.d new file mode 100644 index 0000000..54088d3 --- /dev/null +++ b/squero/build/stm32g0xx_hal_rcc_ex.d @@ -0,0 +1,59 @@ +build/stm32g0xx_hal_rcc_ex.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h \ + Core/Inc/stm32g0xx_hal_conf.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/stm32g0xx_hal_rcc_ex.lst b/squero/build/stm32g0xx_hal_rcc_ex.lst new file mode 100644 index 0000000..7eb3ae2 --- /dev/null +++ b/squero/build/stm32g0xx_hal_rcc_ex.lst @@ -0,0 +1,3625 @@ +ARM GAS /tmp/ccW75d03.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_hal_rcc_ex.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 16 .align 1 + 17 .global HAL_RCCEx_PeriphCLKConfig + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 HAL_RCCEx_PeriphCLKConfig: + 25 .LVL0: + 26 .LFB297: + 27 .file 1 "Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c" + 1:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** + 2:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ****************************************************************************** + 3:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @file stm32g0xx_hal_rcc_ex.c + 4:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver. + 6:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * functionalities RCC extended peripheral: + 8:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + Extended Clock management functions + 10:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + Extended Clock Recovery System Control functions + 11:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 12:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ****************************************************************************** + 13:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @attention + 14:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 15:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** *

© Copyright (c) 2018 STMicroelectronics. + 16:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * All rights reserved.

+ 17:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 18:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * This software component is licensed by ST under BSD 3-Clause license, + 19:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * the "License"; You may not use this file except in compliance with the + 20:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * License. You may obtain a copy of the License at: + 21:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * opensource.org/licenses/BSD-3-Clause + 22:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 23:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ****************************************************************************** + 24:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 25:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 26:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 27:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #include "stm32g0xx_hal.h" + 28:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 29:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @addtogroup STM32G0xx_HAL_Driver + 30:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ + 31:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + ARM GAS /tmp/ccW75d03.s page 2 + + + 32:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 33:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + 34:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief RCC Extended HAL module driver + 35:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ + 36:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 37:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 38:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + 39:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 40:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 41:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Private defines -----------------------------------------------------------*/ + 42:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Constants RCCEx Private Constants + 43:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ + 44:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 45:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */ + 46:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 47:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 48:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #define LSCO_GPIO_PORT GPIOA + 49:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #define LSCO_PIN GPIO_PIN_2 + 50:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** + 51:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @} + 52:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 53:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 54:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Private macros ------------------------------------------------------------*/ + 55:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 56:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 57:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Exported functions --------------------------------------------------------*/ + 58:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 59:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 60:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ + 61:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 62:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 63:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + 64:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 65:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 66:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** @verbatim + 67:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** =============================================================================== + 68:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 69:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** =============================================================================== + 70:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** [..] + 71:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 72:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequencies. + 73:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** [..] + 74:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + 75:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 76:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 77:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** the backup registers) and RCC_BDCR register are set to their reset values. + 78:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 79:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** @endverbatim + 80:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ + 81:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 82:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** + 83:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Initialize the RCC extended peripherals clocks according to the specified + 84:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * parameters in the @ref RCC_PeriphCLKInitTypeDef. + 85:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that + 86:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * contains a field PeriphClockSelection which can be a combination of the following value + 87:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + 88:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + ARM GAS /tmp/ccW75d03.s page 3 + + + 89:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + 90:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (2) + 91:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + 92:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + 93:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + 94:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + 95:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + 96:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + 97:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1) + 98:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock (1) + 99:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + 100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + 101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + 102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (2) + 103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (2) + 104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + 105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + 106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (1) Peripherals are not available on all devices + 108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (2) Peripherals clock selection is not available on all devices + 109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + 110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * the RTC clock source: in this case the access to Backup domain is enabled. + 111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * + 112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @retval HAL status + 113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 28 .loc 1 115 1 view -0 + 29 .cfi_startproc + 30 @ args = 0, pretend = 0, frame = 8 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 .loc 1 115 1 is_stmt 0 view .LVU1 + 33 0000 F0B5 push {r4, r5, r6, r7, lr} + 34 .LCFI0: + 35 .cfi_def_cfa_offset 20 + 36 .cfi_offset 4, -20 + 37 .cfi_offset 5, -16 + 38 .cfi_offset 6, -12 + 39 .cfi_offset 7, -8 + 40 .cfi_offset 14, -4 + 41 0002 83B0 sub sp, sp, #12 + 42 .LCFI1: + 43 .cfi_def_cfa_offset 32 + 44 0004 0400 movs r4, r0 + 116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t tmpregister; + 45 .loc 1 116 3 is_stmt 1 view .LVU2 + 117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t tickstart; + 46 .loc 1 117 3 view .LVU3 + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 47 .loc 1 118 3 view .LVU4 + 48 .LVL1: + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 49 .loc 1 119 3 view .LVU5 + 120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 50 .loc 1 122 3 view .LVU6 + ARM GAS /tmp/ccW75d03.s page 4 + + + 123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- RTC clock source configuration ----------------------*/ + 125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 51 .loc 1 125 3 view .LVU7 + 52 .loc 1 125 6 is_stmt 0 view .LVU8 + 53 0006 0368 ldr r3, [r0] + 54 0008 9B03 lsls r3, r3, #14 + 55 000a 62D5 bpl .L20 + 56 .LBB2: + 126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 57 .loc 1 127 5 is_stmt 1 view .LVU9 + 58 .LVL2: + 128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check for RTC Parameters used to output RTCCLK */ + 130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 59 .loc 1 130 5 view .LVU10 + 131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable Power Clock */ + 133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 60 .loc 1 133 5 view .LVU11 + 61 .loc 1 133 9 is_stmt 0 view .LVU12 + 62 000c 6D4B ldr r3, .L29 + 63 000e DB6B ldr r3, [r3, #60] + 64 .loc 1 133 8 view .LVU13 + 65 0010 DB00 lsls r3, r3, #3 + 66 0012 1ED4 bmi .L21 + 134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 67 .loc 1 135 7 is_stmt 1 view .LVU14 + 68 .LBB3: + 69 .loc 1 135 7 view .LVU15 + 70 .loc 1 135 7 view .LVU16 + 71 0014 6B4A ldr r2, .L29 + 72 0016 D16B ldr r1, [r2, #60] + 73 0018 8020 movs r0, #128 + 74 .LVL3: + 75 .loc 1 135 7 is_stmt 0 view .LVU17 + 76 001a 4005 lsls r0, r0, #21 + 77 001c 0143 orrs r1, r0 + 78 001e D163 str r1, [r2, #60] + 79 .loc 1 135 7 is_stmt 1 view .LVU18 + 80 0020 D36B ldr r3, [r2, #60] + 81 0022 0340 ands r3, r0 + 82 0024 0193 str r3, [sp, #4] + 83 .loc 1 135 7 view .LVU19 + 84 0026 019B ldr r3, [sp, #4] + 85 .LBE3: + 86 .loc 1 135 7 view .LVU20 + 136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 87 .loc 1 136 7 view .LVU21 + 88 .LVL4: + 89 .loc 1 136 21 is_stmt 0 view .LVU22 + 90 0028 0126 movs r6, #1 + 91 .LVL5: + 92 .L3: + 137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccW75d03.s page 5 + + + 138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** SET_BIT(PWR->CR1, PWR_CR1_DBP); + 93 .loc 1 140 5 is_stmt 1 view .LVU23 + 94 002a 674A ldr r2, .L29+4 + 95 002c 1168 ldr r1, [r2] + 96 002e 8023 movs r3, #128 + 97 0030 5B00 lsls r3, r3, #1 + 98 0032 0B43 orrs r3, r1 + 99 0034 1360 str r3, [r2] + 141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 100 .loc 1 143 5 view .LVU24 + 101 .loc 1 143 17 is_stmt 0 view .LVU25 + 102 0036 FFF7FEFF bl HAL_GetTick + 103 .LVL6: + 104 003a 0500 movs r5, r0 + 105 .LVL7: + 144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + 106 .loc 1 145 5 is_stmt 1 view .LVU26 + 107 .L4: + 108 .loc 1 145 11 view .LVU27 + 109 .loc 1 145 16 is_stmt 0 view .LVU28 + 110 003c 624B ldr r3, .L29+4 + 111 003e 1B68 ldr r3, [r3] + 112 .loc 1 145 11 view .LVU29 + 113 0040 DB05 lsls r3, r3, #23 + 114 0042 08D4 bmi .L24 + 146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 115 .loc 1 147 7 is_stmt 1 view .LVU30 + 116 .loc 1 147 12 is_stmt 0 view .LVU31 + 117 0044 FFF7FEFF bl HAL_GetTick + 118 .LVL8: + 119 .loc 1 147 26 view .LVU32 + 120 0048 401B subs r0, r0, r5 + 121 .loc 1 147 10 view .LVU33 + 122 004a 0228 cmp r0, #2 + 123 004c F6D9 bls .L4 + 148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT; + 124 .loc 1 149 13 view .LVU34 + 125 004e 0325 movs r5, #3 + 126 .LVL9: + 127 .loc 1 149 13 view .LVU35 + 128 0050 02E0 b .L5 + 129 .LVL10: + 130 .L21: + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 131 .loc 1 127 22 view .LVU36 + 132 0052 0026 movs r6, #0 + 133 0054 E9E7 b .L3 + 134 .LVL11: + 135 .L24: + 127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccW75d03.s page 6 + + + 136 .loc 1 127 22 view .LVU37 + 137 .LBE2: + 118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 138 .loc 1 118 21 view .LVU38 + 139 0056 0025 movs r5, #0 + 140 .LVL12: + 141 .L5: + 142 .LBB4: + 150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (ret == HAL_OK) + 143 .loc 1 154 5 is_stmt 1 view .LVU39 + 144 .loc 1 154 8 is_stmt 0 view .LVU40 + 145 0058 002D cmp r5, #0 + 146 005a 23D1 bne .L7 + 155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + 157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + 147 .loc 1 157 7 is_stmt 1 view .LVU41 + 148 .loc 1 157 21 is_stmt 0 view .LVU42 + 149 005c 594B ldr r3, .L29 + 150 005e D96D ldr r1, [r3, #92] + 151 .loc 1 157 19 view .LVU43 + 152 0060 C022 movs r2, #192 + 153 0062 9200 lsls r2, r2, #2 + 154 0064 0B00 movs r3, r1 + 155 0066 1340 ands r3, r2 + 156 .LVL13: + 158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified */ + 160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelectio + 157 .loc 1 160 7 is_stmt 1 view .LVU44 + 158 .loc 1 160 10 is_stmt 0 view .LVU45 + 159 0068 1142 tst r1, r2 + 160 006a 10D0 beq .L8 + 161 .loc 1 160 50 discriminator 1 view .LVU46 + 162 006c 626A ldr r2, [r4, #36] + 163 006e 9A42 cmp r2, r3 + 164 0070 0DD0 beq .L8 + 161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 165 .loc 1 163 9 is_stmt 1 view .LVU47 + 166 .loc 1 163 23 is_stmt 0 view .LVU48 + 167 0072 544A ldr r2, .L29 + 168 0074 D36D ldr r3, [r2, #92] + 169 .LVL14: + 170 .loc 1 163 21 view .LVU49 + 171 0076 5549 ldr r1, .L29+8 + 172 .LVL15: + 173 .loc 1 163 21 view .LVU50 + 174 0078 0B40 ands r3, r1 + 175 .LVL16: + 164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + ARM GAS /tmp/ccW75d03.s page 7 + + + 176 .loc 1 165 9 is_stmt 1 view .LVU51 + 177 007a D06D ldr r0, [r2, #92] + 178 007c 8021 movs r1, #128 + 179 007e 4902 lsls r1, r1, #9 + 180 0080 0143 orrs r1, r0 + 181 0082 D165 str r1, [r2, #92] + 166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 182 .loc 1 166 9 view .LVU52 + 183 0084 D16D ldr r1, [r2, #92] + 184 0086 5248 ldr r0, .L29+12 + 185 0088 0140 ands r1, r0 + 186 008a D165 str r1, [r2, #92] + 167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** RCC->BDCR = tmpregister; + 187 .loc 1 168 9 view .LVU53 + 188 .loc 1 168 19 is_stmt 0 view .LVU54 + 189 008c D365 str r3, [r2, #92] + 190 .L8: + 169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + 172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + 191 .loc 1 172 7 is_stmt 1 view .LVU55 + 192 .loc 1 172 10 is_stmt 0 view .LVU56 + 193 008e DB07 lsls r3, r3, #31 + 194 0090 10D4 bmi .L25 + 195 .LVL17: + 196 .L9: + 173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get Start Tick*/ + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + 179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ret = HAL_TIMEOUT; + 183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (ret == HAL_OK) + 197 .loc 1 188 7 is_stmt 1 view .LVU57 + 198 .loc 1 188 10 is_stmt 0 view .LVU58 + 199 0092 002D cmp r5, #0 + 200 0094 06D1 bne .L7 + 189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Apply new RTC clock source selection */ + 191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 201 .loc 1 191 9 is_stmt 1 view .LVU59 + 202 0096 4B4A ldr r2, .L29 + 203 0098 D36D ldr r3, [r2, #92] + 204 009a 4C49 ldr r1, .L29+8 + 205 009c 0B40 ands r3, r1 + 206 009e 616A ldr r1, [r4, #36] + ARM GAS /tmp/ccW75d03.s page 8 + + + 207 00a0 0B43 orrs r3, r1 + 208 00a2 D365 str r3, [r2, #92] + 209 .L7: + 210 .LVL18: + 192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* set overall return value */ + 196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** status = ret; + 197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* set overall return value */ + 202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** status = ret; + 203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Restore clock configuration if changed */ + 206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (pwrclkchanged == SET) + 211 .loc 1 206 5 view .LVU60 + 212 .loc 1 206 8 is_stmt 0 view .LVU61 + 213 00a4 012E cmp r6, #1 + 214 00a6 15D1 bne .L2 + 207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 215 .loc 1 208 7 is_stmt 1 view .LVU62 + 216 00a8 464A ldr r2, .L29 + 217 00aa D36B ldr r3, [r2, #60] + 218 00ac 4949 ldr r1, .L29+16 + 219 00ae 0B40 ands r3, r1 + 220 00b0 D363 str r3, [r2, #60] + 221 00b2 0FE0 b .L2 + 222 .LVL19: + 223 .L25: + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 224 .loc 1 175 9 view .LVU63 + 175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 225 .loc 1 175 21 is_stmt 0 view .LVU64 + 226 00b4 FFF7FEFF bl HAL_GetTick + 227 .LVL20: + 228 00b8 0700 movs r7, r0 + 229 .LVL21: + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 230 .loc 1 178 9 is_stmt 1 view .LVU65 + 231 .L10: + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 232 .loc 1 178 15 view .LVU66 + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 233 .loc 1 178 16 is_stmt 0 view .LVU67 + 234 00ba 424B ldr r3, .L29 + 235 00bc DB6D ldr r3, [r3, #92] + 178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 236 .loc 1 178 15 view .LVU68 + 237 00be 9B07 lsls r3, r3, #30 + 238 00c0 E7D4 bmi .L9 + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 239 .loc 1 180 11 is_stmt 1 view .LVU69 + ARM GAS /tmp/ccW75d03.s page 9 + + + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 240 .loc 1 180 16 is_stmt 0 view .LVU70 + 241 00c2 FFF7FEFF bl HAL_GetTick + 242 .LVL22: + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 243 .loc 1 180 30 view .LVU71 + 244 00c6 C01B subs r0, r0, r7 + 180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 245 .loc 1 180 14 view .LVU72 + 246 00c8 434B ldr r3, .L29+20 + 247 00ca 9842 cmp r0, r3 + 248 00cc F5D9 bls .L10 + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 249 .loc 1 182 17 view .LVU73 + 250 00ce 0325 movs r5, #3 + 251 .LVL23: + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 252 .loc 1 182 17 view .LVU74 + 253 00d0 DFE7 b .L9 + 254 .LVL24: + 255 .L20: + 182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 256 .loc 1 182 17 view .LVU75 + 257 .LBE4: + 119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 258 .loc 1 119 21 view .LVU76 + 259 00d2 0025 movs r5, #0 + 260 .LVL25: + 261 .L2: + 209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- USART1 clock source configuration -------------------*/ + 213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 262 .loc 1 213 3 is_stmt 1 view .LVU77 + 263 .loc 1 213 6 is_stmt 0 view .LVU78 + 264 00d4 2368 ldr r3, [r4] + 265 00d6 DB07 lsls r3, r3, #31 + 266 00d8 06D5 bpl .L12 + 214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 267 .loc 1 216 5 is_stmt 1 view .LVU79 + 217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 268 .loc 1 219 5 view .LVU80 + 269 00da 3A4A ldr r2, .L29 + 270 00dc 536D ldr r3, [r2, #84] + 271 00de 0321 movs r1, #3 + 272 00e0 8B43 bics r3, r1 + 273 00e2 6168 ldr r1, [r4, #4] + 274 00e4 0B43 orrs r3, r1 + 275 00e6 5365 str r3, [r2, #84] + 276 .L12: + 220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccW75d03.s page 10 + + + 222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART2SEL) + 223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- USART2 clock source configuration -------------------*/ + 224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART2SEL */ + 233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART3SEL) + 235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- USART3 clock source configuration -------------------*/ + 236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + 240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */ + 242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART3SEL */ + 245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(LPUART1) + 247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- LPUART1 clock source configuration ------------------*/ + 248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 277 .loc 1 248 3 view .LVU81 + 278 .loc 1 248 6 is_stmt 0 view .LVU82 + 279 00e8 2368 ldr r3, [r4] + 280 00ea DB06 lsls r3, r3, #27 + 281 00ec 06D5 bpl .L13 + 249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + 282 .loc 1 251 5 is_stmt 1 view .LVU83 + 252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the LPUART1 clock source */ + 254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 283 .loc 1 254 5 view .LVU84 + 284 00ee 354A ldr r2, .L29 + 285 00f0 536D ldr r3, [r2, #84] + 286 00f2 3A49 ldr r1, .L29+24 + 287 00f4 0B40 ands r3, r1 + 288 00f6 A168 ldr r1, [r4, #8] + 289 00f8 0B43 orrs r3, r1 + 290 00fa 5365 str r3, [r2, #84] + 291 .L13: + 255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* LPUART1 */ + 257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(LPUART2) + 259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- LPUART2 clock source configuration ------------------*/ + 260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) + 261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPUART2CLKSOURCE(PeriphClkInit->Lpuart2ClockSelection)); + ARM GAS /tmp/ccW75d03.s page 11 + + + 264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the LPUART clock source */ + 266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_LPUART2_CONFIG(PeriphClkInit->Lpuart2ClockSelection); + 267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* LPUART2 */ + 269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM1SEL) + 271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- LPTIM1 clock source configuration -------------------*/ + 272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 292 .loc 1 272 3 view .LVU85 + 293 .loc 1 272 6 is_stmt 0 view .LVU86 + 294 00fc 2368 ldr r3, [r4] + 295 00fe 9B05 lsls r3, r3, #22 + 296 0100 06D5 bpl .L14 + 273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + 297 .loc 1 274 5 is_stmt 1 view .LVU87 + 275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 298 .loc 1 275 5 view .LVU88 + 299 0102 304A ldr r2, .L29 + 300 0104 536D ldr r3, [r2, #84] + 301 0106 3649 ldr r1, .L29+28 + 302 0108 0B40 ands r3, r1 + 303 010a 6169 ldr r1, [r4, #20] + 304 010c 0B43 orrs r3, r1 + 305 010e 5365 str r3, [r2, #84] + 306 .L14: + 276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM1SEL */ + 278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM2SEL) + 280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- LPTIM2 clock source configuration -------------------*/ + 281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 307 .loc 1 281 3 view .LVU89 + 308 .loc 1 281 6 is_stmt 0 view .LVU90 + 309 0110 2368 ldr r3, [r4] + 310 0112 5B05 lsls r3, r3, #21 + 311 0114 06D5 bpl .L15 + 282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + 312 .loc 1 283 5 is_stmt 1 view .LVU91 + 284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 313 .loc 1 284 5 view .LVU92 + 314 0116 2B4A ldr r2, .L29 + 315 0118 536D ldr r3, [r2, #84] + 316 011a 3249 ldr r1, .L29+32 + 317 011c 0B40 ands r3, r1 + 318 011e A169 ldr r1, [r4, #24] + 319 0120 0B43 orrs r3, r1 + 320 0122 5365 str r3, [r2, #84] + 321 .L15: + 285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM2SEL */ + 287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- I2C1 clock source configuration ---------------------*/ + 289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 322 .loc 1 289 3 view .LVU93 + ARM GAS /tmp/ccW75d03.s page 12 + + + 323 .loc 1 289 6 is_stmt 0 view .LVU94 + 324 0124 2368 ldr r3, [r4] + 325 0126 9B06 lsls r3, r3, #26 + 326 0128 06D5 bpl .L16 + 290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 327 .loc 1 292 5 is_stmt 1 view .LVU95 + 293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 328 .loc 1 295 5 view .LVU96 + 329 012a 264A ldr r2, .L29 + 330 012c 536D ldr r3, [r2, #84] + 331 012e 2E49 ldr r1, .L29+36 + 332 0130 0B40 ands r3, r1 + 333 0132 E168 ldr r1, [r4, #12] + 334 0134 0B43 orrs r3, r1 + 335 0136 5365 str r3, [r2, #84] + 336 .L16: + 296:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 297:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 298:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C2SEL) + 299:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- I2C2 clock source configuration ---------------------*/ + 300:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 301:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 302:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 303:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + 304:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 305:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */ + 306:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 307:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 308:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* (RCC_CCIPR_I2C2SEL */ + 309:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 310:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RNG) + 311:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- RNG clock source configuration ----------------------*/ + 312:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 313:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 314:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + 315:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 316:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 317:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 318:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 319:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLQCLK output */ + 320:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 321:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 322:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 323:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RNG */ + 324:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- ADC clock source configuration ----------------------*/ + 325:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 337 .loc 1 325 3 view .LVU97 + 338 .loc 1 325 6 is_stmt 0 view .LVU98 + 339 0138 2368 ldr r3, [r4] + 340 013a 5B04 lsls r3, r3, #17 + 341 013c 0BD5 bpl .L17 + 326:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 327:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + ARM GAS /tmp/ccW75d03.s page 13 + + + 328:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + 342 .loc 1 328 5 is_stmt 1 view .LVU99 + 329:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 330:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the ADC interface clock source */ + 331:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 343 .loc 1 331 5 view .LVU100 + 344 013e 214A ldr r2, .L29 + 345 0140 536D ldr r3, [r2, #84] + 346 0142 9B00 lsls r3, r3, #2 + 347 0144 9B08 lsrs r3, r3, #2 + 348 0146 E169 ldr r1, [r4, #28] + 349 0148 0B43 orrs r3, r1 + 350 014a 5365 str r3, [r2, #84] + 332:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 333:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) + 351 .loc 1 333 5 view .LVU101 + 352 .loc 1 333 8 is_stmt 0 view .LVU102 + 353 014c 8023 movs r3, #128 + 354 014e DB05 lsls r3, r3, #23 + 355 0150 E269 ldr r2, [r4, #28] + 356 0152 9A42 cmp r2, r3 + 357 0154 20D0 beq .L26 + 358 .L17: + 334:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 335:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLPCLK output */ + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 337:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 338:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 339:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 340:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(CEC) + 341:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- CEC clock source configuration ---------------------*/ + 342:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 343:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 344:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 345:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + 346:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 347:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 348:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 349:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 350:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* CEC */ + 351:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 352:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM1SEL) + 353:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- TIM1 clock source configuration ---------------------*/ + 354:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + 359 .loc 1 354 3 is_stmt 1 view .LVU103 + 360 .loc 1 354 6 is_stmt 0 view .LVU104 + 361 0156 2368 ldr r3, [r4] + 362 0158 9B02 lsls r3, r3, #10 + 363 015a 0BD5 bpl .L18 + 355:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 356:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 357:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + 364 .loc 1 357 5 is_stmt 1 view .LVU105 + 358:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 359:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the TIM1 clock source */ + 360:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + 365 .loc 1 360 5 view .LVU106 + ARM GAS /tmp/ccW75d03.s page 14 + + + 366 015c 194A ldr r2, .L29 + 367 015e 536D ldr r3, [r2, #84] + 368 0160 2249 ldr r1, .L29+40 + 369 0162 0B40 ands r3, r1 + 370 0164 216A ldr r1, [r4, #32] + 371 0166 0B43 orrs r3, r1 + 372 0168 5365 str r3, [r2, #84] + 361:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 362:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL) + 373 .loc 1 362 5 view .LVU107 + 374 .loc 1 362 8 is_stmt 0 view .LVU108 + 375 016a 8023 movs r3, #128 + 376 016c DB03 lsls r3, r3, #15 + 377 016e 226A ldr r2, [r4, #32] + 378 0170 9A42 cmp r2, r3 + 379 0172 18D0 beq .L27 + 380 .L18: + 363:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 364:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLQCLK output */ + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 366:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 367:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 368:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM1SEL */ + 369:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 370:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM15SEL) + 371:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- TIM15 clock source configuration ---------------------*/ + 372:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 373:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 374:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 375:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + 376:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 377:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the TIM15 clock source */ + 378:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 379:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 380:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL) + 381:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 382:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLQCLK output */ + 383:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 384:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 385:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 386:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM15SEL */ + 387:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 388:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- I2S1 clock source configuration ---------------------*/ + 389:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) + 381 .loc 1 389 3 is_stmt 1 view .LVU109 + 382 .loc 1 389 6 is_stmt 0 view .LVU110 + 383 0174 2368 ldr r3, [r4] + 384 0176 1B05 lsls r3, r3, #20 + 385 0178 0BD5 bpl .L19 + 390:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 391:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 392:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); + 386 .loc 1 392 5 is_stmt 1 view .LVU111 + 393:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 394:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the I2S1 clock source */ + 395:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); + 387 .loc 1 395 5 view .LVU112 + ARM GAS /tmp/ccW75d03.s page 15 + + + 388 017a 124A ldr r2, .L29 + 389 017c 536D ldr r3, [r2, #84] + 390 017e 1C49 ldr r1, .L29+44 + 391 0180 0B40 ands r3, r1 + 392 0182 2169 ldr r1, [r4, #16] + 393 0184 0B43 orrs r3, r1 + 394 0186 5365 str r3, [r2, #84] + 396:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 397:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) + 395 .loc 1 397 5 view .LVU113 + 396 .loc 1 397 22 is_stmt 0 view .LVU114 + 397 0188 2269 ldr r2, [r4, #16] + 398 .loc 1 397 8 view .LVU115 + 399 018a 8023 movs r3, #128 + 400 018c DB01 lsls r3, r3, #7 + 401 018e 9A42 cmp r2, r3 + 402 0190 10D0 beq .L28 + 403 .L19: + 398:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 399:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLPCLK output */ + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 401:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 402:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 403:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 404:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_I2S2SEL) + 405:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- I2S2 clock source configuration ---------------------*/ + 406:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + 407:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 408:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 409:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + 410:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 411:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the I2S2 clock source */ + 412:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 413:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 414:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + 415:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 416:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLPCLK output */ + 417:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + 418:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 419:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 420:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_I2S2SEL */ + 421:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 422:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + 423:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- USB clock source configuration ---------------------*/ + 424:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 425:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 426:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 427:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + 428:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 429:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the USB clock source */ + 430:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + 431:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 432:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + 433:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 434:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLQCLK output */ + 435:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 436:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccW75d03.s page 16 + + + 437:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 438:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + 439:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 440:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(FDCAN1) || defined(FDCAN2) + 441:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /*-------------------------- FDCAN clock source configuration ---------------------*/ + 442:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + 443:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 444:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 445:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + 446:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 447:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the FDCAN clock source */ + 448:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + 449:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 450:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) + 451:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 452:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable PLLQCLK output */ + 453:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + 454:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 455:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 456:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* FDCAN1 || FDCAN2 */ + 457:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 458:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** return status; + 404 .loc 1 458 3 is_stmt 1 view .LVU116 + 459:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 405 .loc 1 459 1 is_stmt 0 view .LVU117 + 406 0192 2800 movs r0, r5 + 407 0194 03B0 add sp, sp, #12 + 408 @ sp needed + 409 .LVL26: + 410 .LVL27: + 411 .loc 1 459 1 view .LVU118 + 412 0196 F0BD pop {r4, r5, r6, r7, pc} + 413 .LVL28: + 414 .L26: + 336:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 415 .loc 1 336 7 is_stmt 1 view .LVU119 + 416 0198 0A4A ldr r2, .L29 + 417 019a D168 ldr r1, [r2, #12] + 418 019c 8023 movs r3, #128 + 419 019e 5B02 lsls r3, r3, #9 + 420 01a0 0B43 orrs r3, r1 + 421 01a2 D360 str r3, [r2, #12] + 422 01a4 D7E7 b .L17 + 423 .L27: + 365:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 424 .loc 1 365 7 view .LVU120 + 425 01a6 074A ldr r2, .L29 + 426 01a8 D168 ldr r1, [r2, #12] + 427 01aa 8023 movs r3, #128 + 428 01ac 5B04 lsls r3, r3, #17 + 429 01ae 0B43 orrs r3, r1 + 430 01b0 D360 str r3, [r2, #12] + 431 01b2 DFE7 b .L18 + 432 .L28: + 400:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 433 .loc 1 400 7 view .LVU121 + 434 01b4 034A ldr r2, .L29 + ARM GAS /tmp/ccW75d03.s page 17 + + + 435 01b6 D168 ldr r1, [r2, #12] + 436 01b8 8023 movs r3, #128 + 437 01ba 5B02 lsls r3, r3, #9 + 438 01bc 0B43 orrs r3, r1 + 439 01be D360 str r3, [r2, #12] + 440 01c0 E7E7 b .L19 + 441 .L30: + 442 01c2 C046 .align 2 + 443 .L29: + 444 01c4 00100240 .word 1073876992 + 445 01c8 00700040 .word 1073770496 + 446 01cc FFFCFFFF .word -769 + 447 01d0 FFFFFEFF .word -65537 + 448 01d4 FFFFFFEF .word -268435457 + 449 01d8 88130000 .word 5000 + 450 01dc FFF3FFFF .word -3073 + 451 01e0 FFFFF3FF .word -786433 + 452 01e4 FFFFCFFF .word -3145729 + 453 01e8 FFCFFFFF .word -12289 + 454 01ec FFFFBFFF .word -4194305 + 455 01f0 FF3FFFFF .word -49153 + 456 .cfi_endproc + 457 .LFE297: + 459 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + 460 .align 1 + 461 .global HAL_RCCEx_GetPeriphCLKConfig + 462 .syntax unified + 463 .code 16 + 464 .thumb_func + 465 .fpu softvfp + 467 HAL_RCCEx_GetPeriphCLKConfig: + 468 .LVL29: + 469 .LFB298: + 460:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 461:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** + 462:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + 463:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 464:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals + 465:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * clocks: I2C1, I2S1, USART1, RTC, ADC, + 466:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RN + 467:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (1) Peripheral is not available on all devices + 468:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (2) Peripheral clock selection is not available on all devices + 469:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @retval None + 470:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 471:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 472:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 470 .loc 1 472 1 view -0 + 471 .cfi_startproc + 472 @ args = 0, pretend = 0, frame = 0 + 473 @ frame_needed = 0, uses_anonymous_args = 0 + 474 @ link register save eliminated. + 473:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 474:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I + 475 .loc 1 474 3 view .LVU123 + 476 .loc 1 474 39 is_stmt 0 view .LVU124 + 477 0000 1A4B ldr r3, .L32 + 478 0002 0360 str r3, [r0] + ARM GAS /tmp/ccW75d03.s page 18 + + + 475:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC ; + 476:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 477:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM1SEL) && defined(RCC_CCIPR_LPTIM2SEL) + 478:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM1; + 479 .loc 1 478 3 is_stmt 1 view .LVU125 + 480 .loc 1 478 39 is_stmt 0 view .LVU126 + 481 0004 1A4B ldr r3, .L32+4 + 482 0006 0360 str r3, [r0] + 479:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM1SEL && RCC_CCIPR_LPTIM2SEL */ + 480:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_RNGSEL) + 481:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_RNG; + 482:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_RNGSEL */ + 483:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART1SEL) + 484:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1; + 483 .loc 1 484 3 is_stmt 1 view .LVU127 + 484 .loc 1 484 39 is_stmt 0 view .LVU128 + 485 0008 1A4B ldr r3, .L32+8 + 486 000a 0360 str r3, [r0] + 485:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART1SEL */ + 486:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART2SEL) + 487:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART2; + 488:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART2SEL */ + 489:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_CECSEL) + 490:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + 491:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_CECSEL */ + 492:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM1SEL) + 493:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; + 487 .loc 1 493 3 is_stmt 1 view .LVU129 + 488 .loc 1 493 39 is_stmt 0 view .LVU130 + 489 000c 1A4B ldr r3, .L32+12 + 490 000e 0360 str r3, [r0] + 494:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM1SEL */ + 495:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM15SEL) + 496:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; + 497:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM15SEL */ + 498:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART2SEL) + 499:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; + 500:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART2SEL */ + 501:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART3SEL) + 502:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; + 503:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART3SEL */ + 504:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C2SEL) + 505:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; + 506:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C2SEL */ + 507:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_I2S2SEL) + 508:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; + 509:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_I2S2SEL */ + 510:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_USBSEL) + 511:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + 512:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_USBSEL */ + 513:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_FDCANSEL) + 514:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN; + 515:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_FDCANSEL */ + 516:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the USART1 clock source ---------------------------------------------*/ + 517:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + 491 .loc 1 517 3 is_stmt 1 view .LVU131 + 492 .loc 1 517 42 is_stmt 0 view .LVU132 + ARM GAS /tmp/ccW75d03.s page 19 + + + 493 0010 1A4B ldr r3, .L32+16 + 494 0012 596D ldr r1, [r3, #84] + 495 0014 0322 movs r2, #3 + 496 0016 0A40 ands r2, r1 + 497 .loc 1 517 40 view .LVU133 + 498 0018 4260 str r2, [r0, #4] + 518:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART2SEL) + 519:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the USART2 clock source ---------------------------------------------*/ + 520:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + 521:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART2SEL */ + 522:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART3SEL) + 523:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the USART3 clock source ---------------------------------------------*/ + 524:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + 525:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART3SEL */ + 526:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART1SEL) + 527:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the LPUART1 clock source --------------------------------------------*/ + 528:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); + 499 .loc 1 528 3 is_stmt 1 view .LVU134 + 500 .loc 1 528 42 is_stmt 0 view .LVU135 + 501 001a 5A6D ldr r2, [r3, #84] + 502 001c C021 movs r1, #192 + 503 001e 0901 lsls r1, r1, #4 + 504 0020 0A40 ands r2, r1 + 505 .loc 1 528 40 view .LVU136 + 506 0022 8260 str r2, [r0, #8] + 529:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART1SEL */ + 530:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART2SEL) + 531:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the LPUART2 clock source --------------------------------------------*/ + 532:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Lpuart2ClockSelection = __HAL_RCC_GET_LPUART2_SOURCE(); + 533:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART2SEL */ + 534:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the I2C1 clock source -----------------------------------------------*/ + 535:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + 507 .loc 1 535 3 is_stmt 1 view .LVU137 + 508 .loc 1 535 42 is_stmt 0 view .LVU138 + 509 0024 5A6D ldr r2, [r3, #84] + 510 0026 C021 movs r1, #192 + 511 0028 8901 lsls r1, r1, #6 + 512 002a 0A40 ands r2, r1 + 513 .loc 1 535 40 view .LVU139 + 514 002c C260 str r2, [r0, #12] + 536:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C2SEL) + 537:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the I2C2 clock source -----------------------------------------------*/ + 538:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + 539:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C2SEL */ + 540:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM1SEL) + 541:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the LPTIM1 clock source ---------------------------------------------*/ + 542:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + 515 .loc 1 542 3 is_stmt 1 view .LVU140 + 516 .loc 1 542 42 is_stmt 0 view .LVU141 + 517 002e 5A6D ldr r2, [r3, #84] + 518 0030 C021 movs r1, #192 + 519 0032 0903 lsls r1, r1, #12 + 520 0034 0A40 ands r2, r1 + 521 .loc 1 542 40 view .LVU142 + 522 0036 4261 str r2, [r0, #20] + 543:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM1SEL */ + 544:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM2SEL) + ARM GAS /tmp/ccW75d03.s page 20 + + + 545:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the LPTIM2 clock source ---------------------------------------------*/ + 546:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + 523 .loc 1 546 3 is_stmt 1 view .LVU143 + 524 .loc 1 546 42 is_stmt 0 view .LVU144 + 525 0038 5A6D ldr r2, [r3, #84] + 526 003a C021 movs r1, #192 + 527 003c 8903 lsls r1, r1, #14 + 528 003e 0A40 ands r2, r1 + 529 .loc 1 546 40 view .LVU145 + 530 0040 8261 str r2, [r0, #24] + 547:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM2SEL */ + 548:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM1SEL) + 549:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the TIM1 clock source ---------------------------------------------*/ + 550:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); + 531 .loc 1 550 3 is_stmt 1 view .LVU146 + 532 .loc 1 550 40 is_stmt 0 view .LVU147 + 533 0042 5A6D ldr r2, [r3, #84] + 534 0044 8021 movs r1, #128 + 535 0046 C903 lsls r1, r1, #15 + 536 0048 0A40 ands r2, r1 + 537 .loc 1 550 38 view .LVU148 + 538 004a 0262 str r2, [r0, #32] + 551:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM1SEL */ + 552:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM15SEL) + 553:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the TIM15 clock source ---------------------------------------------*/ + 554:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + 555:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM15SEL */ + 556:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the RTC clock source ------------------------------------------------*/ + 557:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + 539 .loc 1 557 3 is_stmt 1 view .LVU149 + 540 .loc 1 557 42 is_stmt 0 view .LVU150 + 541 004c DA6D ldr r2, [r3, #92] + 542 004e C021 movs r1, #192 + 543 0050 8900 lsls r1, r1, #2 + 544 0052 0A40 ands r2, r1 + 545 .loc 1 557 40 view .LVU151 + 546 0054 4262 str r2, [r0, #36] + 558:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_RNGSEL) + 559:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the RNG clock source ------------------------------------------------*/ + 560:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); + 561:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_RNGSEL */ + 562:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the ADC clock source -----------------------------------------------*/ + 563:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + 547 .loc 1 563 3 is_stmt 1 view .LVU152 + 548 .loc 1 563 42 is_stmt 0 view .LVU153 + 549 0056 5A6D ldr r2, [r3, #84] + 550 0058 920F lsrs r2, r2, #30 + 551 005a 9207 lsls r2, r2, #30 + 552 .loc 1 563 40 view .LVU154 + 553 005c C261 str r2, [r0, #28] + 564:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_CECSEL) + 565:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the CEC clock source -----------------------------------------------*/ + 566:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + 567:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_CECSEL */ + 568:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_USBSEL) + 569:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the USB clock source -----------------------------------------------*/ + 570:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + ARM GAS /tmp/ccW75d03.s page 21 + + + 571:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_USBSEL */ + 572:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_FDCANSEL) + 573:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the FDCAN clock source -----------------------------------------------*/ + 574:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + 575:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_FDCANSEL */ + 576:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the I2S1 clock source -----------------------------------------------*/ + 577:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE(); + 554 .loc 1 577 3 is_stmt 1 view .LVU155 + 555 .loc 1 577 42 is_stmt 0 view .LVU156 + 556 005e 5B6D ldr r3, [r3, #84] + 557 0060 C022 movs r2, #192 + 558 0062 1202 lsls r2, r2, #8 + 559 0064 1340 ands r3, r2 + 560 .loc 1 577 40 view .LVU157 + 561 0066 0361 str r3, [r0, #16] + 578:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_I2S2SEL) + 579:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the I2S2 clock source -----------------------------------------------*/ + 580:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); + 581:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_I2S2SEL */ + 582:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 562 .loc 1 582 1 view .LVU158 + 563 @ sp needed + 564 0068 7047 bx lr + 565 .L33: + 566 006a C046 .align 2 + 567 .L32: + 568 006c 21480200 .word 149537 + 569 0070 214E0200 .word 151073 + 570 0074 314E0200 .word 151089 + 571 0078 314E2200 .word 2248241 + 572 007c 00100240 .word 1073876992 + 573 .cfi_endproc + 574 .LFE298: + 576 .global __aeabi_uidiv + 577 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 578 .align 1 + 579 .global HAL_RCCEx_GetPeriphCLKFreq + 580 .syntax unified + 581 .code 16 + 582 .thumb_func + 583 .fpu softvfp + 585 HAL_RCCEx_GetPeriphCLKFreq: + 586 .LVL30: + 587 .LFB299: + 583:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 584:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** + 585:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Return the peripheral clock frequency for peripherals with clock source from PLL + 586:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note Return 0 if peripheral clock identifier not managed by this API + 587:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier + 588:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * This parameter can be one of the following values: + 589:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + 590:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + 591:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + 592:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (1) + 593:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + 594:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + 595:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + ARM GAS /tmp/ccW75d03.s page 22 + + + 596:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (1)(2) + 597:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (1) + 598:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + 599:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + 600:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + 601:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + 602:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + 603:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1) + 604:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock(1) + 605:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + 606:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + 607:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + 608:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (1) Peripheral not available on all devices + 609:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @note (2) Peripheral Clock configuration not available on all devices + 610:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @retval Frequency in Hz + 611:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ + 612:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + 613:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 588 .loc 1 613 1 is_stmt 1 view -0 + 589 .cfi_startproc + 590 @ args = 0, pretend = 0, frame = 0 + 591 @ frame_needed = 0, uses_anonymous_args = 0 + 592 .loc 1 613 1 is_stmt 0 view .LVU160 + 593 0000 10B5 push {r4, lr} + 594 .LCFI2: + 595 .cfi_def_cfa_offset 8 + 596 .cfi_offset 4, -8 + 597 .cfi_offset 14, -4 + 598 0002 0400 movs r4, r0 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t frequency = 0U; + 599 .loc 1 614 3 is_stmt 1 view .LVU161 + 600 .LVL31: + 615:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 601 .loc 1 615 3 view .LVU162 + 616:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t pllvco; + 602 .loc 1 616 3 view .LVU163 + 617:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t plln; + 603 .loc 1 617 3 view .LVU164 + 618:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_RNGSEL) + 619:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t rngclk; + 620:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t rngdiv; + 621:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_RNGSEL */ + 622:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ + 623:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + 604 .loc 1 623 3 view .LVU165 + 624:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 625:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (PeriphClk == RCC_PERIPHCLK_RTC) + 605 .loc 1 625 3 view .LVU166 + 606 .loc 1 625 6 is_stmt 0 view .LVU167 + 607 0004 8023 movs r3, #128 + 608 0006 9B02 lsls r3, r3, #10 + 609 0008 9842 cmp r0, r3 + 610 000a 4DD0 beq .L89 + 626:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 627:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current RTC source */ + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE(); + 629:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccW75d03.s page 23 + + + 630:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check if LSE is ready and if RTC clock selection is LSE */ + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + 632:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 634:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 635:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check if LSI is ready and if RTC clock selection is LSI */ + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + 637:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSI_VALUE; + 639:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 640:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) + 642:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 32U; + 644:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 645:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for RTC*/ + 646:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 647:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 648:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 649:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 650:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 651:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 652:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 653:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Other external peripheral clock source than RTC */ + 654:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 655:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Compute PLL clock input */ + 656:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ + 611 .loc 1 656 5 is_stmt 1 view .LVU168 + 612 .loc 1 656 9 is_stmt 0 view .LVU169 + 613 000c BD4B ldr r3, .L108 + 614 000e DA68 ldr r2, [r3, #12] + 615 0010 0323 movs r3, #3 + 616 0012 1340 ands r3, r2 + 617 .loc 1 656 8 view .LVU170 + 618 0014 022B cmp r3, #2 + 619 0016 6ED0 beq .L72 + 657:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pllvco = HSI_VALUE; + 659:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 660:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ + 620 .loc 1 660 10 is_stmt 1 view .LVU171 + 621 .loc 1 660 14 is_stmt 0 view .LVU172 + 622 0018 BA4B ldr r3, .L108 + 623 001a DA68 ldr r2, [r3, #12] + 624 001c 0323 movs r3, #3 + 625 001e 1340 ands r3, r2 + 626 .loc 1 660 13 view .LVU173 + 627 0020 032B cmp r3, #3 + 628 0022 66D0 beq .L90 + 661:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pllvco = HSE_VALUE; + 663:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 664:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No source */ + 665:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 666:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pllvco = 0U; + 629 .loc 1 666 14 view .LVU174 + 630 0024 0020 movs r0, #0 + ARM GAS /tmp/ccW75d03.s page 24 + + + 631 .LVL32: + 632 .L39: + 667:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 668:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 669:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLL Source) / PLLM */ + 670:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + 633 .loc 1 670 5 is_stmt 1 view .LVU175 + 634 .loc 1 670 26 is_stmt 0 view .LVU176 + 635 0026 B74B ldr r3, .L108 + 636 0028 DB68 ldr r3, [r3, #12] + 637 .loc 1 670 67 view .LVU177 + 638 002a 1B09 lsrs r3, r3, #4 + 639 002c 0721 movs r1, #7 + 640 002e 1940 ands r1, r3 + 641 .loc 1 670 92 view .LVU178 + 642 0030 0131 adds r1, r1, #1 + 643 .loc 1 670 12 view .LVU179 + 644 0032 FFF7FEFF bl __aeabi_uidiv + 645 .LVL33: + 646 .loc 1 670 12 view .LVU180 + 647 0036 0200 movs r2, r0 + 648 .LVL34: + 671:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** switch (PeriphClk) + 649 .loc 1 672 5 is_stmt 1 view .LVU181 + 650 0038 8023 movs r3, #128 + 651 003a DB00 lsls r3, r3, #3 + 652 003c 9C42 cmp r4, r3 + 653 003e 00D1 bne .LCB633 + 654 0040 66E1 b .L40 @long jump + 655 .LCB633: + 656 0042 00D9 bls .LCB635 + 657 0044 87E0 b .L41 @long jump + 658 .LCB635: + 659 0046 202C cmp r4, #32 + 660 0048 00D1 bne .LCB637 + 661 004a 1DE1 b .L42 @long jump + 662 .LCB637: + 663 004c 55D9 bls .L91 + 664 004e 8023 movs r3, #128 + 665 0050 9B00 lsls r3, r3, #2 + 666 0052 9C42 cmp r4, r3 + 667 0054 7DD1 bne .L92 + 673:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 674:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_RNGSEL) + 675:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_RNG: + 676:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 677:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL); + 678:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_RNGCLKSOURCE_HSI_DIV8) /* HSI_DIV8 ? */ + 679:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 680:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** rngclk = HSI_VALUE / 8U; + 681:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 682:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */ + 683:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 684:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + 685:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + 686:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** rngclk = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ + ARM GAS /tmp/ccW75d03.s page 25 + + + 687:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 688:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_RNGCLKSOURCE_SYSCLK) /* SYSCLK ? */ + 689:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 690:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** rngclk = HAL_RCC_GetSysClockFreq(); + 691:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 692:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No clock source */ + 693:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 694:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** rngclk = 0U; + 695:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 696:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 697:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + 698:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (rngclk / rngdiv); + 699:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 700:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 701:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_RNGSEL */ + 702:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART1: + 703:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current USART1 source */ + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART1_SOURCE(); + 705:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 ? */ + 707:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 709:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK ? */ + 711:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 713:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + 715:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 717:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE + 719:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 721:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 722:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for USART1 */ + 723:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 724:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 725:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 726:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 727:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 728:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART2SEL) + 729:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART2: + 730:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current USART2 source */ + 731:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART2_SOURCE(); + 732:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 733:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + 734:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 735:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 736:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 737:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + 738:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 739:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 740:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 741:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + 742:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 743:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + ARM GAS /tmp/ccW75d03.s page 26 + + + 744:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 745:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE + 746:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 747:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 748:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 749:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for USART2 */ + 750:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 751:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 752:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 753:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 754:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 755:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART2SEL */ + 756:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 757:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_USART3SEL) + 758:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART3: + 759:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current USART3 source */ + 760:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART3_SOURCE(); + 761:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 762:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + 763:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 764:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 765:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 766:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + 767:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 768:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 769:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 770:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + 771:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 772:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 773:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 774:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE + 775:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 776:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 777:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 778:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for USART3 */ + 779:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 780:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 781:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 782:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 783:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 784:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_USART3SEL */ + 785:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 786:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_CECSEL) + 787:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_CEC: + 788:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current CEC source */ + 789:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_CEC_SOURCE(); + 790:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 791:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_CECCLKSOURCE_HSI_DIV488)) + 792:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 793:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (HSI_VALUE / 488U); + 794:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 795:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE)) + 796:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 797:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 798:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 799:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for CEC */ + 800:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + ARM GAS /tmp/ccW75d03.s page 27 + + + 801:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 802:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 803:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 804:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 805:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_CECSEL */ + 806:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 807:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART1SEL) + 808:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPUART1: + 809:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current LPUART1 source */ + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + 811:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) + 813:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 815:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + 817:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 819:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + 821:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 823:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LS + 825:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 827:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 828:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for LPUART1 */ + 829:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 830:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 831:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 832:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 833:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 834:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART1SEL */ + 835:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 836:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPUART2SEL) + 837:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPUART2: + 838:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current LPUART2 source */ + 839:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPUART2_SOURCE(); + 840:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 841:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_LPUART2CLKSOURCE_PCLK1) + 842:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 843:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 844:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 845:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_LPUART2CLKSOURCE_SYSCLK) + 846:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 847:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 848:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 849:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART2CLKSOURCE_HSI)) + 850:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 851:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 852:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 853:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART2CLKSOURCE_LS + 854:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 855:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 856:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 857:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for LPUART2 */ + ARM GAS /tmp/ccW75d03.s page 28 + + + 858:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 859:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 860:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 861:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 862:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 863:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPUART2SEL */ + 864:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 865:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC: + 866:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC_SOURCE(); + 868:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_ADCCLKSOURCE_SYSCLK) + 870:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 872:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_ADCCLKSOURCE_HSI) + 874:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 876:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_ADCCLKSOURCE_PLLADC) + 878:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + 880:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 881:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 884:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 885:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 886:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for ADC */ + 887:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 888:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 889:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 890:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 891:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 892:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 893:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C1: + 894:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current I2C1 source */ + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + 896:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + 898:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 900:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + 902:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 904:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + 906:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 908:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 909:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for I2C1 */ + 910:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 911:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 912:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 913:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 914:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + ARM GAS /tmp/ccW75d03.s page 29 + + + 915:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 916:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_I2C2SEL) + 917:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C2: + 918:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current I2C2 source */ + 919:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + 920:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 921:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + 922:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 923:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 924:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 925:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + 926:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 927:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 928:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 929:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + 930:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 931:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 932:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 933:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for I2C2 */ + 934:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 935:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 936:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 937:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 938:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 939:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_I2C2SEL */ + 940:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 941:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2S1: + 942:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current I2S1 source */ + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2S1_SOURCE(); + 944:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2S1CLKSOURCE_PLL) + 946:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + 948:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 949:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 952:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 953:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK) + 955:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 957:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSI)) + 959:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 961:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2S1CLKSOURCE_EXT) + 963:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 964:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* External clock used.*/ + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = EXTERNAL_I2S1_CLOCK_VALUE; + 966:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 967:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for I2S1 */ + 968:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else + 969:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 970:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ + 971:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccW75d03.s page 30 + + + 972:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; + 973:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 974:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_I2S2SEL) + 975:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2S2: + 976:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current I2S2 source */ + 977:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2S2_SOURCE(); + 978:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 979:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_I2S2CLKSOURCE_PLL) + 980:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 981:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + 982:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 983:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + 984:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + 985:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 986:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 987:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 988:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2S2CLKSOURCE_SYSCLK) + 989:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 990:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); + 991:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 992:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S2CLKSOURCE_HSI)) + 993:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 994:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; + 995:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 996:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2S2CLKSOURCE_EXT) + 997:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 998:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* External clock used.*/ + 999:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = EXTERNAL_I2S2_CLOCK_VALUE; +1000:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1001:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for I2S2 */ +1002:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else +1003:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1004:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1005:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1006:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1007:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_I2S2SEL */ +1008:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1009:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM1SEL) +1010:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPTIM1: +1011:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current LPTIM1 source */ +1012:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + 668 .loc 1 1012 9 view .LVU182 + 669 .loc 1 1012 18 is_stmt 0 view .LVU183 + 670 0056 AB4B ldr r3, .L108 + 671 0058 5A6D ldr r2, [r3, #84] + 672 .loc 1 1012 16 view .LVU184 + 673 005a C023 movs r3, #192 + 674 005c 1B03 lsls r3, r3, #12 + 675 005e 1100 movs r1, r2 + 676 0060 1940 ands r1, r3 + 677 .LVL35: +1013:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1014:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) + 678 .loc 1 1014 9 is_stmt 1 view .LVU185 + 679 .loc 1 1014 12 is_stmt 0 view .LVU186 + 680 0062 1A42 tst r2, r3 + 681 0064 00D1 bne .LCB654 + ARM GAS /tmp/ccW75d03.s page 31 + + + 682 0066 4AE1 b .L93 @long jump + 683 .LCB654: +1015:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1017:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1018:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + 684 .loc 1 1018 14 is_stmt 1 view .LVU187 + 685 .loc 1 1018 19 is_stmt 0 view .LVU188 + 686 0068 A64B ldr r3, .L108 + 687 006a 1B6E ldr r3, [r3, #96] + 688 .loc 1 1018 17 view .LVU189 + 689 006c 9B07 lsls r3, r3, #30 + 690 006e 04D5 bpl .L63 + 691 .loc 1 1018 61 discriminator 1 view .LVU190 + 692 0070 8023 movs r3, #128 + 693 0072 DB02 lsls r3, r3, #11 + 694 0074 9942 cmp r1, r3 + 695 0076 00D1 bne .LCB665 + 696 0078 90E1 b .L83 @long jump + 697 .LCB665: + 698 .L63: +1019:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSI_VALUE; +1021:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1022:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + 699 .loc 1 1022 14 is_stmt 1 view .LVU191 + 700 .loc 1 1022 19 is_stmt 0 view .LVU192 + 701 007a A24B ldr r3, .L108 + 702 007c 1B68 ldr r3, [r3] + 703 .loc 1 1022 17 view .LVU193 + 704 007e 5B05 lsls r3, r3, #21 + 705 0080 04D5 bpl .L64 + 706 .loc 1 1022 59 discriminator 1 view .LVU194 + 707 0082 8023 movs r3, #128 + 708 0084 1B03 lsls r3, r3, #12 + 709 0086 9942 cmp r1, r3 + 710 0088 00D1 bne .LCB677 + 711 008a 8AE1 b .L84 @long jump + 712 .LCB677: + 713 .L64: +1023:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1025:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1026:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE + 714 .loc 1 1026 14 is_stmt 1 view .LVU195 + 715 .loc 1 1026 19 is_stmt 0 view .LVU196 + 716 008c 9D4B ldr r3, .L108 + 717 008e DB6D ldr r3, [r3, #92] + 718 0090 0222 movs r2, #2 + 719 0092 1000 movs r0, r2 + 720 .LVL36: + 721 .loc 1 1026 19 view .LVU197 + 722 0094 1840 ands r0, r3 + 723 .loc 1 1026 17 view .LVU198 + 724 0096 1A42 tst r2, r3 + 725 0098 5CD0 beq .L34 + 726 .loc 1 1026 63 discriminator 1 view .LVU199 + ARM GAS /tmp/ccW75d03.s page 32 + + + 727 009a C023 movs r3, #192 + 728 009c 1B03 lsls r3, r3, #12 + 729 009e 9942 cmp r1, r3 + 730 00a0 00D1 bne .LCB691 + 731 00a2 80E1 b .L85 @long jump + 732 .LCB691: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 733 .loc 1 614 12 view .LVU200 + 734 00a4 0020 movs r0, #0 + 735 00a6 55E0 b .L34 + 736 .LVL37: + 737 .L89: + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 738 .loc 1 628 5 is_stmt 1 view .LVU201 + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 739 .loc 1 628 14 is_stmt 0 view .LVU202 + 740 00a8 964A ldr r2, .L108 + 741 00aa D36D ldr r3, [r2, #92] + 628:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 742 .loc 1 628 12 view .LVU203 + 743 00ac C021 movs r1, #192 + 744 00ae 8900 lsls r1, r1, #2 + 745 00b0 0B40 ands r3, r1 + 746 .LVL38: + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 747 .loc 1 631 5 is_stmt 1 view .LVU204 + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 748 .loc 1 631 10 is_stmt 0 view .LVU205 + 749 00b2 D26D ldr r2, [r2, #92] + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 750 .loc 1 631 8 view .LVU206 + 751 00b4 9207 lsls r2, r2, #30 + 752 00b6 04D5 bpl .L36 + 631:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 753 .loc 1 631 54 discriminator 1 view .LVU207 + 754 00b8 8022 movs r2, #128 + 755 00ba 5200 lsls r2, r2, #1 + 756 00bc 9342 cmp r3, r2 + 757 00be 00D1 bne .LCB716 + 758 00c0 52E1 b .L69 @long jump + 759 .LCB716: + 760 .L36: + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 761 .loc 1 636 10 is_stmt 1 view .LVU208 + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 762 .loc 1 636 15 is_stmt 0 view .LVU209 + 763 00c2 904A ldr r2, .L108 + 764 00c4 126E ldr r2, [r2, #96] + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 765 .loc 1 636 13 view .LVU210 + 766 00c6 9207 lsls r2, r2, #30 + 767 00c8 04D5 bpl .L38 + 636:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 768 .loc 1 636 57 discriminator 1 view .LVU211 + 769 00ca 8022 movs r2, #128 + 770 00cc 9200 lsls r2, r2, #2 + 771 00ce 9342 cmp r3, r2 + ARM GAS /tmp/ccW75d03.s page 33 + + + 772 00d0 00D1 bne .LCB728 + 773 00d2 4CE1 b .L70 @long jump + 774 .LCB728: + 775 .L38: + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 776 .loc 1 641 10 is_stmt 1 view .LVU212 + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 777 .loc 1 641 15 is_stmt 0 view .LVU213 + 778 00d4 8B4A ldr r2, .L108 + 779 00d6 1168 ldr r1, [r2] + 780 00d8 8022 movs r2, #128 + 781 00da 9202 lsls r2, r2, #10 + 782 00dc 0800 movs r0, r1 + 783 .LVL39: + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 784 .loc 1 641 15 view .LVU214 + 785 00de 1040 ands r0, r2 + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 786 .loc 1 641 13 view .LVU215 + 787 00e0 1142 tst r1, r2 + 788 00e2 37D0 beq .L34 + 641:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 789 .loc 1 641 55 discriminator 1 view .LVU216 + 790 00e4 C022 movs r2, #192 + 791 00e6 9200 lsls r2, r2, #2 + 792 00e8 9342 cmp r3, r2 + 793 00ea 00D1 bne .LCB743 + 794 00ec 42E1 b .L71 @long jump + 795 .LCB743: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 796 .loc 1 614 12 view .LVU217 + 797 00ee 0020 movs r0, #0 + 798 00f0 30E0 b .L34 + 799 .LVL40: + 800 .L90: + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 801 .loc 1 662 14 view .LVU218 + 802 00f2 8548 ldr r0, .L108+4 + 803 .LVL41: + 662:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 804 .loc 1 662 14 view .LVU219 + 805 00f4 97E7 b .L39 + 806 .LVL42: + 807 .L72: + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 808 .loc 1 658 14 view .LVU220 + 809 00f6 8548 ldr r0, .L108+8 + 810 .LVL43: + 658:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 811 .loc 1 658 14 view .LVU221 + 812 00f8 95E7 b .L39 + 813 .LVL44: + 814 .L91: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 815 .loc 1 672 5 view .LVU222 + 816 00fa 012C cmp r4, #1 + 817 00fc 00D1 bne .LCB766 + ARM GAS /tmp/ccW75d03.s page 34 + + + 818 00fe 70E0 b .L44 @long jump + 819 .LCB766: + 820 0100 102C cmp r4, #16 + 821 0102 24D1 bne .L94 + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 822 .loc 1 810 9 is_stmt 1 view .LVU223 + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 823 .loc 1 810 18 is_stmt 0 view .LVU224 + 824 0104 7F4B ldr r3, .L108 + 825 0106 5A6D ldr r2, [r3, #84] + 810:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 826 .loc 1 810 16 view .LVU225 + 827 0108 C023 movs r3, #192 + 828 010a 1B01 lsls r3, r3, #4 + 829 010c 1100 movs r1, r2 + 830 010e 1940 ands r1, r3 + 831 .LVL45: + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 832 .loc 1 812 9 is_stmt 1 view .LVU226 + 812:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 833 .loc 1 812 12 is_stmt 0 view .LVU227 + 834 0110 1A42 tst r2, r3 + 835 0112 00D1 bne .LCB779 + 836 0114 87E0 b .L95 @long jump + 837 .LCB779: + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 838 .loc 1 816 14 is_stmt 1 view .LVU228 + 816:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 839 .loc 1 816 17 is_stmt 0 view .LVU229 + 840 0116 8023 movs r3, #128 + 841 0118 DB00 lsls r3, r3, #3 + 842 011a 9942 cmp r1, r3 + 843 011c 00D1 bne .LCB784 + 844 011e 85E0 b .L96 @long jump + 845 .LCB784: + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 846 .loc 1 820 14 is_stmt 1 view .LVU230 + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 847 .loc 1 820 19 is_stmt 0 view .LVU231 + 848 0120 784B ldr r3, .L108 + 849 0122 1B68 ldr r3, [r3] + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 850 .loc 1 820 17 view .LVU232 + 851 0124 5B05 lsls r3, r3, #21 + 852 0126 04D5 bpl .L55 + 820:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 853 .loc 1 820 59 discriminator 1 view .LVU233 + 854 0128 8023 movs r3, #128 + 855 012a 1B01 lsls r3, r3, #4 + 856 012c 9942 cmp r1, r3 + 857 012e 00D1 bne .LCB795 + 858 0130 27E1 b .L76 @long jump + 859 .LCB795: + 860 .L55: + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 861 .loc 1 824 14 is_stmt 1 view .LVU234 + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccW75d03.s page 35 + + + 862 .loc 1 824 19 is_stmt 0 view .LVU235 + 863 0132 744B ldr r3, .L108 + 864 0134 DB6D ldr r3, [r3, #92] + 865 0136 0222 movs r2, #2 + 866 0138 1000 movs r0, r2 + 867 .LVL46: + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 868 .loc 1 824 19 view .LVU236 + 869 013a 1840 ands r0, r3 + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 870 .loc 1 824 17 view .LVU237 + 871 013c 1A42 tst r2, r3 + 872 013e 09D0 beq .L34 + 824:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 873 .loc 1 824 63 discriminator 1 view .LVU238 + 874 0140 C023 movs r3, #192 + 875 0142 1B01 lsls r3, r3, #4 + 876 0144 9942 cmp r1, r3 + 877 0146 00D1 bne .LCB809 + 878 0148 1DE1 b .L77 @long jump + 879 .LCB809: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 880 .loc 1 614 12 view .LVU239 + 881 014a 0020 movs r0, #0 + 882 014c 02E0 b .L34 + 883 .LVL47: + 884 .L94: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 885 .loc 1 672 5 view .LVU240 + 886 014e 0020 movs r0, #0 + 887 .LVL48: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 888 .loc 1 672 5 view .LVU241 + 889 0150 00E0 b .L34 + 890 .LVL49: + 891 .L92: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 892 .loc 1 672 5 view .LVU242 + 893 0152 0020 movs r0, #0 + 894 .LVL50: + 895 .L34: +1027:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1029:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1030:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for LPTIM1 */ +1031:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else +1032:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1033:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1034:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1035:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1036:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM1SEL */ +1037:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1038:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_LPTIM2SEL) +1039:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_LPTIM2: +1040:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Get the current LPTIM2 source */ +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); +1042:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccW75d03.s page 36 + + +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) +1044:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1046:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) +1048:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSI_VALUE; +1050:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) +1052:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1054:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE +1056:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1058:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1059:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Clock not enabled for LPTIM2 */ +1060:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else +1061:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1062:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1063:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1064:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1065:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_LPTIM2SEL */ +1066:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1067:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM1SEL) +1068:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM1: +1069:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL); +1071:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_TIM1CLKSOURCE_PLL) /* PLL ? */ +1073:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) +1075:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1076:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR +1079:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1080:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM1CLKSOURCE_PCLK1) /* PCLK1 ? */ +1082:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1084:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1085:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No clock source */ +1086:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1087:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1088:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1089:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1090:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM1SEL */ +1091:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1092:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR_TIM15SEL) +1093:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM15: +1094:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1095:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL); +1096:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1097:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_TIM15CLKSOURCE_PLL) /* PLL ? */ +1098:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1099:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + ARM GAS /tmp/ccW75d03.s page 37 + + +1100:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1101:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ +1102:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +1103:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR +1104:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1105:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1106:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM15CLKSOURCE_PCLK1) /* PCLK1 ? */ +1107:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1108:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1109:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1110:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No clock source */ +1111:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1112:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1113:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1114:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1115:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR_TIM15SEL */ +1116:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1117:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_USBSEL) +1118:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USB: +1119:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1120:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL); +1121:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1122:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */ +1123:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1124:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) +1125:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1126:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ +1127:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +1128:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR +1129:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1130:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1131:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_HSI48_SUPPORT) +1132:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USBCLKSOURCE_HSI48) /* HSI48 ? */ +1133:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1134:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) +1135:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1136:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSI48_VALUE; +1137:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1138:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1139:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_HSI48_SUPPORT */ +1140:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_USBCLKSOURCE_HSE) +1141:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1142:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBCLKSOURCE_HSE)) +1143:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1144:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1145:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1146:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1147:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No clock source */ +1148:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1149:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1150:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1151:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1152:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_USBSEL */ +1153:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1154:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #if defined(RCC_CCIPR2_FDCANSEL) +1155:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_FDCAN: +1156:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccW75d03.s page 38 + + +1157:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL); +1158:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1159:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (srcclk == RCC_FDCANCLKSOURCE_PLL) /* PLL ? */ +1160:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1161:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) +1162:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1163:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ +1164:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; +1165:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR +1166:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1167:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1168:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) /* PCLK1 ? */ +1169:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1170:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1171:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1172:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE)) +1173:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1174:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = HSE_VALUE; +1175:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1176:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** else /* No clock source */ +1177:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1178:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Nothing to do as frequency already initialized to 0U */ +1179:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1180:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1181:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** #endif /* RCC_CCIPR2_FDCANSEL */ +1182:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1183:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** default: +1184:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** break; +1185:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1186:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1187:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** return (frequency); +1189:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 896 .loc 1 1189 1 view .LVU243 + 897 @ sp needed + 898 .LVL51: + 899 .loc 1 1189 1 view .LVU244 + 900 0154 10BD pop {r4, pc} + 901 .LVL52: + 902 .L41: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 903 .loc 1 672 5 view .LVU245 + 904 0156 8023 movs r3, #128 + 905 0158 DB01 lsls r3, r3, #7 + 906 015a 9C42 cmp r4, r3 + 907 015c 69D0 beq .L47 + 908 015e 8023 movs r3, #128 + 909 0160 9B03 lsls r3, r3, #14 + 910 0162 9C42 cmp r4, r3 + 911 0164 1AD1 bne .L97 +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 912 .loc 1 1070 9 is_stmt 1 view .LVU246 +1070:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 913 .loc 1 1070 18 is_stmt 0 view .LVU247 + 914 0166 674B ldr r3, .L108 + 915 0168 5B6D ldr r3, [r3, #84] + 916 .LVL53: + ARM GAS /tmp/ccW75d03.s page 39 + + +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 917 .loc 1 1072 9 is_stmt 1 view .LVU248 +1072:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 918 .loc 1 1072 12 is_stmt 0 view .LVU249 + 919 016a 5B02 lsls r3, r3, #9 + 920 016c 00D4 bmi .LCB858 + 921 016e F8E0 b .L68 @long jump + 922 .LCB858: + 923 .LVL54: +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 924 .loc 1 1074 11 is_stmt 1 view .LVU250 +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 925 .loc 1 1074 15 is_stmt 0 view .LVU251 + 926 0170 644B ldr r3, .L108 + 927 0172 D968 ldr r1, [r3, #12] + 928 0174 8023 movs r3, #128 + 929 0176 5B04 lsls r3, r3, #17 + 930 0178 0800 movs r0, r1 + 931 .LVL55: +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 932 .loc 1 1074 15 view .LVU252 + 933 017a 1840 ands r0, r3 +1074:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 934 .loc 1 1074 14 view .LVU253 + 935 017c 1942 tst r1, r3 + 936 017e E9D0 beq .L34 +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR + 937 .loc 1 1077 13 is_stmt 1 view .LVU254 +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR + 938 .loc 1 1077 20 is_stmt 0 view .LVU255 + 939 0180 6049 ldr r1, .L108 + 940 0182 CB68 ldr r3, [r1, #12] +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR + 941 .loc 1 1077 61 view .LVU256 + 942 0184 1B0A lsrs r3, r3, #8 +1077:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR + 943 .loc 1 1077 18 view .LVU257 + 944 0186 7F20 movs r0, #127 + 945 0188 1840 ands r0, r3 + 946 .LVL56: +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 947 .loc 1 1078 13 is_stmt 1 view .LVU258 +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 948 .loc 1 1078 33 is_stmt 0 view .LVU259 + 949 018a 5043 muls r0, r2 + 950 .LVL57: +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 951 .loc 1 1078 45 view .LVU260 + 952 018c CB68 ldr r3, [r1, #12] + 953 .LVL58: +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 954 .loc 1 1078 86 view .LVU261 + 955 018e 5B0E lsrs r3, r3, #25 + 956 0190 0721 movs r1, #7 + 957 0192 1940 ands r1, r3 +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 958 .loc 1 1078 111 view .LVU262 + ARM GAS /tmp/ccW75d03.s page 40 + + + 959 0194 0131 adds r1, r1, #1 +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 960 .loc 1 1078 23 view .LVU263 + 961 0196 FFF7FEFF bl __aeabi_uidiv + 962 .LVL59: +1078:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 963 .loc 1 1078 23 view .LVU264 + 964 019a DBE7 b .L34 + 965 .LVL60: + 966 .L97: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 967 .loc 1 672 5 view .LVU265 + 968 019c 8023 movs r3, #128 + 969 019e 1B01 lsls r3, r3, #4 + 970 01a0 9C42 cmp r4, r3 + 971 01a2 1CD1 bne .L98 + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 972 .loc 1 943 9 is_stmt 1 view .LVU266 + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 973 .loc 1 943 18 is_stmt 0 view .LVU267 + 974 01a4 574B ldr r3, .L108 + 975 01a6 5B6D ldr r3, [r3, #84] + 943:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 976 .loc 1 943 16 view .LVU268 + 977 01a8 C021 movs r1, #192 + 978 01aa 0902 lsls r1, r1, #8 + 979 01ac 0B40 ands r3, r1 + 980 .LVL61: + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 981 .loc 1 945 9 is_stmt 1 view .LVU269 + 945:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 982 .loc 1 945 12 is_stmt 0 view .LVU270 + 983 01ae 8021 movs r1, #128 + 984 01b0 C901 lsls r1, r1, #7 + 985 01b2 8B42 cmp r3, r1 + 986 01b4 00D1 bne .LCB912 + 987 01b6 88E0 b .L99 @long jump + 988 .LCB912: + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 989 .loc 1 954 14 is_stmt 1 view .LVU271 + 954:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 990 .loc 1 954 17 is_stmt 0 view .LVU272 + 991 01b8 002B cmp r3, #0 + 992 01ba 00D1 bne .LCB915 + 993 01bc 9CE0 b .L100 @long jump + 994 .LCB915: + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 995 .loc 1 958 14 is_stmt 1 view .LVU273 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 996 .loc 1 958 19 is_stmt 0 view .LVU274 + 997 01be 514A ldr r2, .L108 + 998 01c0 1268 ldr r2, [r2] + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 999 .loc 1 958 17 view .LVU275 + 1000 01c2 5205 lsls r2, r2, #21 + 1001 01c4 04D5 bpl .L61 + 958:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccW75d03.s page 41 + + + 1002 .loc 1 958 59 discriminator 1 view .LVU276 + 1003 01c6 8022 movs r2, #128 + 1004 01c8 1202 lsls r2, r2, #8 + 1005 01ca 9342 cmp r3, r2 + 1006 01cc 00D1 bne .LCB926 + 1007 01ce E1E0 b .L81 @long jump + 1008 .LCB926: + 1009 .L61: + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1010 .loc 1 962 14 is_stmt 1 view .LVU277 + 962:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1011 .loc 1 962 17 is_stmt 0 view .LVU278 + 1012 01d0 C022 movs r2, #192 + 1013 01d2 1202 lsls r2, r2, #8 + 1014 01d4 9342 cmp r3, r2 + 1015 01d6 00D1 bne .LCB932 + 1016 01d8 DEE0 b .L82 @long jump + 1017 .LCB932: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1018 .loc 1 614 12 view .LVU279 + 1019 01da 0020 movs r0, #0 + 1020 .LVL62: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1021 .loc 1 614 12 view .LVU280 + 1022 01dc BAE7 b .L34 + 1023 .LVL63: + 1024 .L98: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1025 .loc 1 672 5 view .LVU281 + 1026 01de 0020 movs r0, #0 + 1027 .LVL64: + 672:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1028 .loc 1 672 5 view .LVU282 + 1029 01e0 B8E7 b .L34 + 1030 .LVL65: + 1031 .L44: + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1032 .loc 1 704 9 is_stmt 1 view .LVU283 + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1033 .loc 1 704 18 is_stmt 0 view .LVU284 + 1034 01e2 484B ldr r3, .L108 + 1035 01e4 5B6D ldr r3, [r3, #84] + 704:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1036 .loc 1 704 16 view .LVU285 + 1037 01e6 0322 movs r2, #3 + 1038 01e8 1100 movs r1, r2 + 1039 01ea 1940 ands r1, r3 + 1040 .LVL66: + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1041 .loc 1 706 9 is_stmt 1 view .LVU286 + 706:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1042 .loc 1 706 12 is_stmt 0 view .LVU287 + 1043 01ec 1A42 tst r2, r3 + 1044 01ee 14D0 beq .L101 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1045 .loc 1 710 14 is_stmt 1 view .LVU288 + 710:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccW75d03.s page 42 + + + 1046 .loc 1 710 17 is_stmt 0 view .LVU289 + 1047 01f0 0129 cmp r1, #1 + 1048 01f2 15D0 beq .L102 + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1049 .loc 1 714 14 is_stmt 1 view .LVU290 + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1050 .loc 1 714 19 is_stmt 0 view .LVU291 + 1051 01f4 434B ldr r3, .L108 + 1052 01f6 1B68 ldr r3, [r3] + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1053 .loc 1 714 17 view .LVU292 + 1054 01f8 5B05 lsls r3, r3, #21 + 1055 01fa 02D5 bpl .L52 + 714:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1056 .loc 1 714 59 discriminator 1 view .LVU293 + 1057 01fc 0229 cmp r1, #2 + 1058 01fe 00D1 bne .LCB969 + 1059 0200 BAE0 b .L74 @long jump + 1060 .LCB969: + 1061 .L52: + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1062 .loc 1 718 14 is_stmt 1 view .LVU294 + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1063 .loc 1 718 19 is_stmt 0 view .LVU295 + 1064 0202 404B ldr r3, .L108 + 1065 0204 DB6D ldr r3, [r3, #92] + 1066 0206 0222 movs r2, #2 + 1067 0208 1000 movs r0, r2 + 1068 .LVL67: + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1069 .loc 1 718 19 view .LVU296 + 1070 020a 1840 ands r0, r3 + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1071 .loc 1 718 17 view .LVU297 + 1072 020c 1A42 tst r2, r3 + 1073 020e A1D0 beq .L34 + 718:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1074 .loc 1 718 63 discriminator 1 view .LVU298 + 1075 0210 0329 cmp r1, #3 + 1076 0212 00D1 bne .LCB981 + 1077 0214 B2E0 b .L75 @long jump + 1078 .LCB981: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1079 .loc 1 614 12 view .LVU299 + 1080 0216 0020 movs r0, #0 + 1081 0218 9CE7 b .L34 + 1082 .LVL68: + 1083 .L101: + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1084 .loc 1 708 11 is_stmt 1 view .LVU300 + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1085 .loc 1 708 23 is_stmt 0 view .LVU301 + 1086 021a FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1087 .LVL69: + 708:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1088 .loc 1 708 23 view .LVU302 + 1089 021e 99E7 b .L34 + ARM GAS /tmp/ccW75d03.s page 43 + + + 1090 .LVL70: + 1091 .L102: + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1092 .loc 1 712 11 is_stmt 1 view .LVU303 + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1093 .loc 1 712 23 is_stmt 0 view .LVU304 + 1094 0220 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1095 .LVL71: + 712:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1096 .loc 1 712 23 view .LVU305 + 1097 0224 96E7 b .L34 + 1098 .LVL72: + 1099 .L95: + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1100 .loc 1 814 11 is_stmt 1 view .LVU306 + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1101 .loc 1 814 23 is_stmt 0 view .LVU307 + 1102 0226 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1103 .LVL73: + 814:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1104 .loc 1 814 23 view .LVU308 + 1105 022a 93E7 b .L34 + 1106 .LVL74: + 1107 .L96: + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1108 .loc 1 818 11 is_stmt 1 view .LVU309 + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1109 .loc 1 818 23 is_stmt 0 view .LVU310 + 1110 022c FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1111 .LVL75: + 818:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1112 .loc 1 818 23 view .LVU311 + 1113 0230 90E7 b .L34 + 1114 .LVL76: + 1115 .L47: + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1116 .loc 1 867 9 is_stmt 1 view .LVU312 + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1117 .loc 1 867 18 is_stmt 0 view .LVU313 + 1118 0232 344B ldr r3, .L108 + 1119 0234 5B6D ldr r3, [r3, #84] + 867:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1120 .loc 1 867 16 view .LVU314 + 1121 0236 9B0F lsrs r3, r3, #30 + 1122 0238 9907 lsls r1, r3, #30 + 1123 .LVL77: + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1124 .loc 1 869 9 is_stmt 1 view .LVU315 + 869:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1125 .loc 1 869 12 is_stmt 0 view .LVU316 + 1126 023a 002B cmp r3, #0 + 1127 023c 0AD0 beq .L103 + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1128 .loc 1 873 14 is_stmt 1 view .LVU317 + 873:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1129 .loc 1 873 17 is_stmt 0 view .LVU318 + 1130 023e 8023 movs r3, #128 + ARM GAS /tmp/ccW75d03.s page 44 + + + 1131 0240 1B06 lsls r3, r3, #24 + 1132 0242 9942 cmp r1, r3 + 1133 0244 00D1 bne .LCB1049 + 1134 0246 A1E0 b .L78 @long jump + 1135 .LCB1049: + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1136 .loc 1 877 14 is_stmt 1 view .LVU319 + 877:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1137 .loc 1 877 17 is_stmt 0 view .LVU320 + 1138 0248 8023 movs r3, #128 + 1139 024a DB05 lsls r3, r3, #23 + 1140 024c 9942 cmp r1, r3 + 1141 024e 04D0 beq .L104 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1142 .loc 1 614 12 view .LVU321 + 1143 0250 0020 movs r0, #0 + 1144 .LVL78: + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1145 .loc 1 614 12 view .LVU322 + 1146 0252 7FE7 b .L34 + 1147 .LVL79: + 1148 .L103: + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1149 .loc 1 871 11 is_stmt 1 view .LVU323 + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1150 .loc 1 871 23 is_stmt 0 view .LVU324 + 1151 0254 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1152 .LVL80: + 871:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1153 .loc 1 871 23 view .LVU325 + 1154 0258 7CE7 b .L34 + 1155 .LVL81: + 1156 .L104: + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1157 .loc 1 879 11 is_stmt 1 view .LVU326 + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1158 .loc 1 879 15 is_stmt 0 view .LVU327 + 1159 025a 2A4B ldr r3, .L108 + 1160 025c D968 ldr r1, [r3, #12] + 1161 .LVL82: + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1162 .loc 1 879 15 view .LVU328 + 1163 025e 8023 movs r3, #128 + 1164 0260 5B02 lsls r3, r3, #9 + 1165 0262 0800 movs r0, r1 + 1166 .LVL83: + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1167 .loc 1 879 15 view .LVU329 + 1168 0264 1840 ands r0, r3 + 879:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1169 .loc 1 879 14 view .LVU330 + 1170 0266 1942 tst r1, r3 + 1171 0268 00D1 bne .LCB1084 + 1172 026a 73E7 b .L34 @long jump + 1173 .LCB1084: + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1174 .loc 1 882 13 is_stmt 1 view .LVU331 + ARM GAS /tmp/ccW75d03.s page 45 + + + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1175 .loc 1 882 20 is_stmt 0 view .LVU332 + 1176 026c 2549 ldr r1, .L108 + 1177 026e CB68 ldr r3, [r1, #12] + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1178 .loc 1 882 61 view .LVU333 + 1179 0270 1B0A lsrs r3, r3, #8 + 882:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1180 .loc 1 882 18 view .LVU334 + 1181 0272 7F20 movs r0, #127 + 1182 0274 1840 ands r0, r3 + 1183 .LVL84: + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1184 .loc 1 883 13 is_stmt 1 view .LVU335 + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1185 .loc 1 883 33 is_stmt 0 view .LVU336 + 1186 0276 5043 muls r0, r2 + 1187 .LVL85: + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1188 .loc 1 883 45 view .LVU337 + 1189 0278 CB68 ldr r3, [r1, #12] + 1190 .LVL86: + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1191 .loc 1 883 86 view .LVU338 + 1192 027a 5B0C lsrs r3, r3, #17 + 1193 027c 1F21 movs r1, #31 + 1194 027e 1940 ands r1, r3 + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1195 .loc 1 883 111 view .LVU339 + 1196 0280 0131 adds r1, r1, #1 + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1197 .loc 1 883 23 view .LVU340 + 1198 0282 FFF7FEFF bl __aeabi_uidiv + 1199 .LVL87: + 883:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1200 .loc 1 883 23 view .LVU341 + 1201 0286 65E7 b .L34 + 1202 .LVL88: + 1203 .L42: + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1204 .loc 1 895 9 is_stmt 1 view .LVU342 + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1205 .loc 1 895 18 is_stmt 0 view .LVU343 + 1206 0288 1E4B ldr r3, .L108 + 1207 028a 5A6D ldr r2, [r3, #84] + 895:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1208 .loc 1 895 16 view .LVU344 + 1209 028c C023 movs r3, #192 + 1210 028e 9B01 lsls r3, r3, #6 + 1211 0290 1100 movs r1, r2 + 1212 0292 1940 ands r1, r3 + 1213 .LVL89: + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1214 .loc 1 897 9 is_stmt 1 view .LVU345 + 897:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1215 .loc 1 897 12 is_stmt 0 view .LVU346 + 1216 0294 1A42 tst r2, r3 + ARM GAS /tmp/ccW75d03.s page 46 + + + 1217 0296 12D0 beq .L105 + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1218 .loc 1 901 14 is_stmt 1 view .LVU347 + 901:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1219 .loc 1 901 17 is_stmt 0 view .LVU348 + 1220 0298 8023 movs r3, #128 + 1221 029a 5B01 lsls r3, r3, #5 + 1222 029c 9942 cmp r1, r3 + 1223 029e 11D0 beq .L106 + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1224 .loc 1 905 14 is_stmt 1 view .LVU349 + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1225 .loc 1 905 19 is_stmt 0 view .LVU350 + 1226 02a0 184B ldr r3, .L108 + 1227 02a2 1A68 ldr r2, [r3] + 1228 02a4 8023 movs r3, #128 + 1229 02a6 DB00 lsls r3, r3, #3 + 1230 02a8 1000 movs r0, r2 + 1231 .LVL90: + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1232 .loc 1 905 19 view .LVU351 + 1233 02aa 1840 ands r0, r3 + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1234 .loc 1 905 17 view .LVU352 + 1235 02ac 1A42 tst r2, r3 + 1236 02ae 00D1 bne .LCB1137 + 1237 02b0 50E7 b .L34 @long jump + 1238 .LCB1137: + 905:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1239 .loc 1 905 59 discriminator 1 view .LVU353 + 1240 02b2 8023 movs r3, #128 + 1241 02b4 9B01 lsls r3, r3, #6 + 1242 02b6 9942 cmp r1, r3 + 1243 02b8 6AD0 beq .L80 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1244 .loc 1 614 12 view .LVU354 + 1245 02ba 0020 movs r0, #0 + 1246 02bc 4AE7 b .L34 + 1247 .LVL91: + 1248 .L105: + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1249 .loc 1 899 11 is_stmt 1 view .LVU355 + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1250 .loc 1 899 23 is_stmt 0 view .LVU356 + 1251 02be FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1252 .LVL92: + 899:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1253 .loc 1 899 23 view .LVU357 + 1254 02c2 47E7 b .L34 + 1255 .LVL93: + 1256 .L106: + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1257 .loc 1 903 11 is_stmt 1 view .LVU358 + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1258 .loc 1 903 23 is_stmt 0 view .LVU359 + 1259 02c4 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1260 .LVL94: + ARM GAS /tmp/ccW75d03.s page 47 + + + 903:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1261 .loc 1 903 23 view .LVU360 + 1262 02c8 44E7 b .L34 + 1263 .LVL95: + 1264 .L99: + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1265 .loc 1 947 11 is_stmt 1 view .LVU361 + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1266 .loc 1 947 15 is_stmt 0 view .LVU362 + 1267 02ca 0E4B ldr r3, .L108 + 1268 .LVL96: + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1269 .loc 1 947 15 view .LVU363 + 1270 02cc D968 ldr r1, [r3, #12] + 1271 02ce 8023 movs r3, #128 + 1272 02d0 5B02 lsls r3, r3, #9 + 1273 02d2 0800 movs r0, r1 + 1274 .LVL97: + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1275 .loc 1 947 15 view .LVU364 + 1276 02d4 1840 ands r0, r3 + 947:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1277 .loc 1 947 14 view .LVU365 + 1278 02d6 1942 tst r1, r3 + 1279 02d8 00D1 bne .LCB1182 + 1280 02da 3BE7 b .L34 @long jump + 1281 .LCB1182: + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1282 .loc 1 950 13 is_stmt 1 view .LVU366 + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1283 .loc 1 950 20 is_stmt 0 view .LVU367 + 1284 02dc 0949 ldr r1, .L108 + 1285 02de CB68 ldr r3, [r1, #12] + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1286 .loc 1 950 61 view .LVU368 + 1287 02e0 1B0A lsrs r3, r3, #8 + 950:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR + 1288 .loc 1 950 18 view .LVU369 + 1289 02e2 7F20 movs r0, #127 + 1290 02e4 1840 ands r0, r3 + 1291 .LVL98: + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1292 .loc 1 951 13 is_stmt 1 view .LVU370 + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1293 .loc 1 951 33 is_stmt 0 view .LVU371 + 1294 02e6 5043 muls r0, r2 + 1295 .LVL99: + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1296 .loc 1 951 45 view .LVU372 + 1297 02e8 CB68 ldr r3, [r1, #12] + 1298 .LVL100: + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1299 .loc 1 951 86 view .LVU373 + 1300 02ea 5B0C lsrs r3, r3, #17 + 1301 02ec 1F21 movs r1, #31 + 1302 02ee 1940 ands r1, r3 + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccW75d03.s page 48 + + + 1303 .loc 1 951 111 view .LVU374 + 1304 02f0 0131 adds r1, r1, #1 + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1305 .loc 1 951 23 view .LVU375 + 1306 02f2 FFF7FEFF bl __aeabi_uidiv + 1307 .LVL101: + 951:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1308 .loc 1 951 23 view .LVU376 + 1309 02f6 2DE7 b .L34 + 1310 .LVL102: + 1311 .L100: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1312 .loc 1 956 11 is_stmt 1 view .LVU377 + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1313 .loc 1 956 23 is_stmt 0 view .LVU378 + 1314 02f8 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1315 .LVL103: + 956:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1316 .loc 1 956 23 view .LVU379 + 1317 02fc 2AE7 b .L34 + 1318 .LVL104: + 1319 .L93: +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1320 .loc 1 1016 11 is_stmt 1 view .LVU380 +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1321 .loc 1 1016 23 is_stmt 0 view .LVU381 + 1322 02fe FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1323 .LVL105: +1016:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1324 .loc 1 1016 23 view .LVU382 + 1325 0302 27E7 b .L34 + 1326 .L109: + 1327 .align 2 + 1328 .L108: + 1329 0304 00100240 .word 1073876992 + 1330 0308 00127A00 .word 8000000 + 1331 030c 0024F400 .word 16000000 + 1332 .LVL106: + 1333 .L40: +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1334 .loc 1 1041 9 is_stmt 1 view .LVU383 +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1335 .loc 1 1041 18 is_stmt 0 view .LVU384 + 1336 0310 2A4B ldr r3, .L110 + 1337 0312 5A6D ldr r2, [r3, #84] +1041:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1338 .loc 1 1041 16 view .LVU385 + 1339 0314 C023 movs r3, #192 + 1340 0316 9B03 lsls r3, r3, #14 + 1341 0318 1100 movs r1, r2 + 1342 031a 1940 ands r1, r3 + 1343 .LVL107: +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1344 .loc 1 1043 9 is_stmt 1 view .LVU386 +1043:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1345 .loc 1 1043 12 is_stmt 0 view .LVU387 + 1346 031c 1A42 tst r2, r3 + ARM GAS /tmp/ccW75d03.s page 49 + + + 1347 031e 1DD0 beq .L107 +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1348 .loc 1 1047 14 is_stmt 1 view .LVU388 +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1349 .loc 1 1047 19 is_stmt 0 view .LVU389 + 1350 0320 264B ldr r3, .L110 + 1351 0322 1B6E ldr r3, [r3, #96] +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1352 .loc 1 1047 17 view .LVU390 + 1353 0324 9B07 lsls r3, r3, #30 + 1354 0326 03D5 bpl .L66 +1047:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1355 .loc 1 1047 61 discriminator 1 view .LVU391 + 1356 0328 8023 movs r3, #128 + 1357 032a 5B03 lsls r3, r3, #13 + 1358 032c 9942 cmp r1, r3 + 1359 032e 3DD0 beq .L86 + 1360 .L66: +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1361 .loc 1 1051 14 is_stmt 1 view .LVU392 +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1362 .loc 1 1051 19 is_stmt 0 view .LVU393 + 1363 0330 224B ldr r3, .L110 + 1364 0332 1B68 ldr r3, [r3] +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1365 .loc 1 1051 17 view .LVU394 + 1366 0334 5B05 lsls r3, r3, #21 + 1367 0336 03D5 bpl .L67 +1051:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1368 .loc 1 1051 59 discriminator 1 view .LVU395 + 1369 0338 8023 movs r3, #128 + 1370 033a 9B03 lsls r3, r3, #14 + 1371 033c 9942 cmp r1, r3 + 1372 033e 38D0 beq .L87 + 1373 .L67: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1374 .loc 1 1055 14 is_stmt 1 view .LVU396 +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1375 .loc 1 1055 19 is_stmt 0 view .LVU397 + 1376 0340 1E4B ldr r3, .L110 + 1377 0342 DB6D ldr r3, [r3, #92] + 1378 0344 0222 movs r2, #2 + 1379 0346 1000 movs r0, r2 + 1380 .LVL108: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1381 .loc 1 1055 19 view .LVU398 + 1382 0348 1840 ands r0, r3 +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1383 .loc 1 1055 17 view .LVU399 + 1384 034a 1A42 tst r2, r3 + 1385 034c 00D1 bne .LCB1285 + 1386 034e 01E7 b .L34 @long jump + 1387 .LCB1285: +1055:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1388 .loc 1 1055 63 discriminator 1 view .LVU400 + 1389 0350 C023 movs r3, #192 + 1390 0352 9B03 lsls r3, r3, #14 + ARM GAS /tmp/ccW75d03.s page 50 + + + 1391 0354 9942 cmp r1, r3 + 1392 0356 2ED0 beq .L88 + 614:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** uint32_t srcclk; + 1393 .loc 1 614 12 view .LVU401 + 1394 0358 0020 movs r0, #0 + 1395 035a FBE6 b .L34 + 1396 .LVL109: + 1397 .L107: +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1398 .loc 1 1045 11 is_stmt 1 view .LVU402 +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1399 .loc 1 1045 23 is_stmt 0 view .LVU403 + 1400 035c FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1401 .LVL110: +1045:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1402 .loc 1 1045 23 view .LVU404 + 1403 0360 F8E6 b .L34 + 1404 .LVL111: + 1405 .L68: +1081:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1406 .loc 1 1081 14 is_stmt 1 view .LVU405 +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1407 .loc 1 1083 11 view .LVU406 +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1408 .loc 1 1083 23 is_stmt 0 view .LVU407 + 1409 0362 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1410 .LVL112: +1083:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1411 .loc 1 1083 23 view .LVU408 + 1412 0366 F5E6 b .L34 + 1413 .LVL113: + 1414 .L69: + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1415 .loc 1 633 17 view .LVU409 + 1416 0368 8020 movs r0, #128 + 1417 .LVL114: + 633:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1418 .loc 1 633 17 view .LVU410 + 1419 036a 0002 lsls r0, r0, #8 + 1420 036c F2E6 b .L34 + 1421 .LVL115: + 1422 .L70: + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1423 .loc 1 638 17 view .LVU411 + 1424 036e FA20 movs r0, #250 + 1425 .LVL116: + 638:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1426 .loc 1 638 17 view .LVU412 + 1427 0370 C001 lsls r0, r0, #7 + 1428 0372 EFE6 b .L34 + 1429 .L71: + 643:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1430 .loc 1 643 17 view .LVU413 + 1431 0374 1248 ldr r0, .L110+4 + 1432 0376 EDE6 b .L34 + 1433 .LVL117: + 1434 .L74: + ARM GAS /tmp/ccW75d03.s page 51 + + + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1435 .loc 1 716 21 view .LVU414 + 1436 0378 1248 ldr r0, .L110+8 + 1437 .LVL118: + 716:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1438 .loc 1 716 21 view .LVU415 + 1439 037a EBE6 b .L34 + 1440 .L75: + 720:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1441 .loc 1 720 21 view .LVU416 + 1442 037c 8020 movs r0, #128 + 1443 037e 0002 lsls r0, r0, #8 + 1444 0380 E8E6 b .L34 + 1445 .LVL119: + 1446 .L76: + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1447 .loc 1 822 21 view .LVU417 + 1448 0382 1048 ldr r0, .L110+8 + 1449 .LVL120: + 822:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1450 .loc 1 822 21 view .LVU418 + 1451 0384 E6E6 b .L34 + 1452 .L77: + 826:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1453 .loc 1 826 21 view .LVU419 + 1454 0386 8020 movs r0, #128 + 1455 0388 0002 lsls r0, r0, #8 + 1456 038a E3E6 b .L34 + 1457 .LVL121: + 1458 .L78: + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1459 .loc 1 875 21 view .LVU420 + 1460 038c 0D48 ldr r0, .L110+8 + 1461 .LVL122: + 875:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1462 .loc 1 875 21 view .LVU421 + 1463 038e E1E6 b .L34 + 1464 .LVL123: + 1465 .L80: + 907:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1466 .loc 1 907 21 view .LVU422 + 1467 0390 0C48 ldr r0, .L110+8 + 1468 0392 DFE6 b .L34 + 1469 .LVL124: + 1470 .L81: + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1471 .loc 1 960 21 view .LVU423 + 1472 0394 0B48 ldr r0, .L110+8 + 1473 .LVL125: + 960:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1474 .loc 1 960 21 view .LVU424 + 1475 0396 DDE6 b .L34 + 1476 .LVL126: + 1477 .L82: + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1478 .loc 1 965 21 view .LVU425 + 1479 0398 0B48 ldr r0, .L110+12 + ARM GAS /tmp/ccW75d03.s page 52 + + + 1480 .LVL127: + 965:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1481 .loc 1 965 21 view .LVU426 + 1482 039a DBE6 b .L34 + 1483 .LVL128: + 1484 .L83: +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1485 .loc 1 1020 21 view .LVU427 + 1486 039c FA20 movs r0, #250 + 1487 .LVL129: +1020:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1488 .loc 1 1020 21 view .LVU428 + 1489 039e C001 lsls r0, r0, #7 + 1490 03a0 D8E6 b .L34 + 1491 .LVL130: + 1492 .L84: +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1493 .loc 1 1024 21 view .LVU429 + 1494 03a2 0848 ldr r0, .L110+8 + 1495 .LVL131: +1024:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1496 .loc 1 1024 21 view .LVU430 + 1497 03a4 D6E6 b .L34 + 1498 .L85: +1028:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1499 .loc 1 1028 21 view .LVU431 + 1500 03a6 8020 movs r0, #128 + 1501 03a8 0002 lsls r0, r0, #8 + 1502 03aa D3E6 b .L34 + 1503 .LVL132: + 1504 .L86: +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1505 .loc 1 1049 21 view .LVU432 + 1506 03ac FA20 movs r0, #250 + 1507 .LVL133: +1049:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1508 .loc 1 1049 21 view .LVU433 + 1509 03ae C001 lsls r0, r0, #7 + 1510 03b0 D0E6 b .L34 + 1511 .LVL134: + 1512 .L87: +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1513 .loc 1 1053 21 view .LVU434 + 1514 03b2 0448 ldr r0, .L110+8 + 1515 .LVL135: +1053:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1516 .loc 1 1053 21 view .LVU435 + 1517 03b4 CEE6 b .L34 + 1518 .L88: +1057:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1519 .loc 1 1057 21 view .LVU436 + 1520 03b6 8020 movs r0, #128 + 1521 03b8 0002 lsls r0, r0, #8 + 1522 .LVL136: +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1523 .loc 1 1188 3 is_stmt 1 view .LVU437 +1188:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccW75d03.s page 53 + + + 1524 .loc 1 1188 10 is_stmt 0 view .LVU438 + 1525 03ba CBE6 b .L34 + 1526 .L111: + 1527 .align 2 + 1528 .L110: + 1529 03bc 00100240 .word 1073876992 + 1530 03c0 90D00300 .word 250000 + 1531 03c4 0024F400 .word 16000000 + 1532 03c8 0080BB00 .word 12288000 + 1533 .cfi_endproc + 1534 .LFE299: + 1536 .section .text.HAL_RCCEx_EnableLSCO,"ax",%progbits + 1537 .align 1 + 1538 .global HAL_RCCEx_EnableLSCO + 1539 .syntax unified + 1540 .code 16 + 1541 .thumb_func + 1542 .fpu softvfp + 1544 HAL_RCCEx_EnableLSCO: + 1545 .LVL137: + 1546 .LFB300: +1190:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1191:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** +1192:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @} +1193:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ +1194:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1195:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions +1196:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Extended Clock management functions +1197:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * +1198:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** @verbatim +1199:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** =============================================================================== +1200:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** ##### Extended clock management functions ##### +1201:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** =============================================================================== +1202:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** [..] +1203:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the +1204:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** activation or deactivation of LSE CSS, Low speed clock output and +1205:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** clock after wake-up from STOP mode. +1206:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** @endverbatim +1207:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @{ +1208:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ +1209:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1210:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** +1211:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Select the Low Speed clock source to output on LSCO pin (PA2). +1212:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @param LSCOSource specifies the Low Speed clock source to output. +1213:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * This parameter can be one of the following values: +1214:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source +1215:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source +1216:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @retval None +1217:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ +1218:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +1219:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1547 .loc 1 1219 1 is_stmt 1 view -0 + 1548 .cfi_startproc + 1549 @ args = 0, pretend = 0, frame = 32 + 1550 @ frame_needed = 0, uses_anonymous_args = 0 + 1551 .loc 1 1219 1 is_stmt 0 view .LVU440 + 1552 0000 30B5 push {r4, r5, lr} + ARM GAS /tmp/ccW75d03.s page 54 + + + 1553 .LCFI3: + 1554 .cfi_def_cfa_offset 12 + 1555 .cfi_offset 4, -12 + 1556 .cfi_offset 5, -8 + 1557 .cfi_offset 14, -4 + 1558 0002 89B0 sub sp, sp, #36 + 1559 .LCFI4: + 1560 .cfi_def_cfa_offset 48 + 1561 0004 0500 movs r5, r0 +1220:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** GPIO_InitTypeDef GPIO_InitStruct; + 1562 .loc 1 1220 3 is_stmt 1 view .LVU441 +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 1563 .loc 1 1221 3 view .LVU442 + 1564 .LVL138: +1222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET; + 1565 .loc 1 1222 3 view .LVU443 +1223:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1224:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Check the parameters */ +1225:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + 1566 .loc 1 1225 3 view .LVU444 +1226:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1227:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* LSCO Pin Clock Enable */ +1228:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** LSCO_CLK_ENABLE(); + 1567 .loc 1 1228 3 view .LVU445 + 1568 .LBB5: + 1569 .loc 1 1228 3 view .LVU446 + 1570 .loc 1 1228 3 view .LVU447 + 1571 0006 224C ldr r4, .L122 + 1572 0008 626B ldr r2, [r4, #52] + 1573 000a 0123 movs r3, #1 + 1574 000c 1A43 orrs r2, r3 + 1575 000e 6263 str r2, [r4, #52] + 1576 .loc 1 1228 3 view .LVU448 + 1577 0010 626B ldr r2, [r4, #52] + 1578 0012 1340 ands r3, r2 + 1579 0014 0193 str r3, [sp, #4] + 1580 .loc 1 1228 3 view .LVU449 + 1581 0016 019B ldr r3, [sp, #4] + 1582 .LBE5: + 1583 .loc 1 1228 3 view .LVU450 +1229:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1230:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Configure the LSCO pin in analog mode */ +1231:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** GPIO_InitStruct.Pin = LSCO_PIN; + 1584 .loc 1 1231 3 view .LVU451 + 1585 .loc 1 1231 23 is_stmt 0 view .LVU452 + 1586 0018 0423 movs r3, #4 + 1587 001a 0393 str r3, [sp, #12] +1232:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 1588 .loc 1 1232 3 is_stmt 1 view .LVU453 + 1589 .loc 1 1232 24 is_stmt 0 view .LVU454 + 1590 001c 013B subs r3, r3, #1 + 1591 001e 0493 str r3, [sp, #16] +1233:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 1592 .loc 1 1233 3 is_stmt 1 view .LVU455 + 1593 .loc 1 1233 25 is_stmt 0 view .LVU456 + 1594 0020 0693 str r3, [sp, #24] +1234:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + ARM GAS /tmp/ccW75d03.s page 55 + + + 1595 .loc 1 1234 3 is_stmt 1 view .LVU457 + 1596 .loc 1 1234 24 is_stmt 0 view .LVU458 + 1597 0022 0023 movs r3, #0 + 1598 0024 0593 str r3, [sp, #20] +1235:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); + 1599 .loc 1 1235 3 is_stmt 1 view .LVU459 + 1600 0026 A020 movs r0, #160 + 1601 .LVL139: + 1602 .loc 1 1235 3 is_stmt 0 view .LVU460 + 1603 0028 03A9 add r1, sp, #12 + 1604 002a C005 lsls r0, r0, #23 + 1605 002c FFF7FEFF bl HAL_GPIO_Init + 1606 .LVL140: +1236:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1237:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Update LSCOSEL clock source in Backup Domain control register */ +1238:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 1607 .loc 1 1238 3 is_stmt 1 view .LVU461 + 1608 .loc 1 1238 7 is_stmt 0 view .LVU462 + 1609 0030 E36B ldr r3, [r4, #60] + 1610 .loc 1 1238 6 view .LVU463 + 1611 0032 DB00 lsls r3, r3, #3 + 1612 0034 1DD4 bmi .L117 +1239:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1240:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 1613 .loc 1 1240 5 is_stmt 1 view .LVU464 + 1614 .LBB6: + 1615 .loc 1 1240 5 view .LVU465 + 1616 .loc 1 1240 5 view .LVU466 + 1617 0036 E16B ldr r1, [r4, #60] + 1618 0038 8020 movs r0, #128 + 1619 003a 4005 lsls r0, r0, #21 + 1620 003c 0143 orrs r1, r0 + 1621 003e E163 str r1, [r4, #60] + 1622 .loc 1 1240 5 view .LVU467 + 1623 0040 E36B ldr r3, [r4, #60] + 1624 0042 0340 ands r3, r0 + 1625 0044 0293 str r3, [sp, #8] + 1626 .loc 1 1240 5 view .LVU468 + 1627 0046 029B ldr r3, [sp, #8] + 1628 .LBE6: + 1629 .loc 1 1240 5 view .LVU469 +1241:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 1630 .loc 1 1241 5 view .LVU470 + 1631 .LVL141: + 1632 .loc 1 1241 19 is_stmt 0 view .LVU471 + 1633 0048 0124 movs r4, #1 + 1634 .LVL142: + 1635 .L113: +1242:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1243:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 1636 .loc 1 1243 3 is_stmt 1 view .LVU472 + 1637 .loc 1 1243 7 is_stmt 0 view .LVU473 + 1638 004a 124B ldr r3, .L122+4 + 1639 004c 1B68 ldr r3, [r3] + 1640 .loc 1 1243 6 view .LVU474 + 1641 004e DB05 lsls r3, r3, #23 + 1642 0050 11D5 bpl .L119 + ARM GAS /tmp/ccW75d03.s page 56 + + +1222:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1643 .loc 1 1222 20 view .LVU475 + 1644 0052 0021 movs r1, #0 + 1645 .LVL143: + 1646 .L114: +1244:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_PWR_EnableBkUpAccess(); +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** backupchanged = SET; +1247:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1248:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1249:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); + 1647 .loc 1 1249 3 is_stmt 1 view .LVU476 + 1648 0054 0E4A ldr r2, .L122 + 1649 0056 D06D ldr r0, [r2, #92] + 1650 0058 0F4B ldr r3, .L122+8 + 1651 005a 1840 ands r0, r3 + 1652 005c 2843 orrs r0, r5 + 1653 005e 8023 movs r3, #128 + 1654 0060 5B04 lsls r3, r3, #17 + 1655 0062 1843 orrs r0, r3 + 1656 0064 D065 str r0, [r2, #92] +1250:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1251:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (backupchanged == SET) + 1657 .loc 1 1251 3 view .LVU477 + 1658 .loc 1 1251 6 is_stmt 0 view .LVU478 + 1659 0066 0129 cmp r1, #1 + 1660 0068 09D0 beq .L120 + 1661 .LVL144: + 1662 .L115: +1252:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_PWR_DisableBkUpAccess(); +1254:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1255:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (pwrclkchanged == SET) + 1663 .loc 1 1255 3 is_stmt 1 view .LVU479 + 1664 .loc 1 1255 6 is_stmt 0 view .LVU480 + 1665 006a 012C cmp r4, #1 + 1666 006c 0AD0 beq .L121 + 1667 .L112: +1256:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); +1258:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1259:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1668 .loc 1 1259 1 view .LVU481 + 1669 006e 09B0 add sp, sp, #36 + 1670 @ sp needed + 1671 .LVL145: + 1672 .LVL146: + 1673 .loc 1 1259 1 view .LVU482 + 1674 0070 30BD pop {r4, r5, pc} + 1675 .LVL147: + 1676 .L117: +1221:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET; + 1677 .loc 1 1221 20 view .LVU483 + 1678 0072 0024 movs r4, #0 + 1679 0074 E9E7 b .L113 + 1680 .LVL148: + 1681 .L119: + ARM GAS /tmp/ccW75d03.s page 57 + + +1245:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** backupchanged = SET; + 1682 .loc 1 1245 5 is_stmt 1 view .LVU484 + 1683 0076 FFF7FEFF bl HAL_PWR_EnableBkUpAccess + 1684 .LVL149: +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1685 .loc 1 1246 5 view .LVU485 +1246:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1686 .loc 1 1246 19 is_stmt 0 view .LVU486 + 1687 007a 0121 movs r1, #1 + 1688 007c EAE7 b .L114 + 1689 .LVL150: + 1690 .L120: +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1691 .loc 1 1253 5 is_stmt 1 view .LVU487 + 1692 007e FFF7FEFF bl HAL_PWR_DisableBkUpAccess + 1693 .LVL151: +1253:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1694 .loc 1 1253 5 is_stmt 0 view .LVU488 + 1695 0082 F2E7 b .L115 + 1696 .L121: +1257:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1697 .loc 1 1257 5 is_stmt 1 view .LVU489 + 1698 0084 024A ldr r2, .L122 + 1699 0086 D36B ldr r3, [r2, #60] + 1700 0088 0449 ldr r1, .L122+12 + 1701 008a 0B40 ands r3, r1 + 1702 008c D363 str r3, [r2, #60] + 1703 .loc 1 1259 1 is_stmt 0 view .LVU490 + 1704 008e EEE7 b .L112 + 1705 .L123: + 1706 .align 2 + 1707 .L122: + 1708 0090 00100240 .word 1073876992 + 1709 0094 00700040 .word 1073770496 + 1710 0098 FFFFFFFC .word -50331649 + 1711 009c FFFFFFEF .word -268435457 + 1712 .cfi_endproc + 1713 .LFE300: + 1715 .section .text.HAL_RCCEx_DisableLSCO,"ax",%progbits + 1716 .align 1 + 1717 .global HAL_RCCEx_DisableLSCO + 1718 .syntax unified + 1719 .code 16 + 1720 .thumb_func + 1721 .fpu softvfp + 1723 HAL_RCCEx_DisableLSCO: + 1724 .LFB301: +1260:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1261:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /** +1262:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @brief Disable the Low Speed clock output. +1263:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** * @retval None +1264:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** */ +1265:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** void HAL_RCCEx_DisableLSCO(void) +1266:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { + 1725 .loc 1 1266 1 is_stmt 1 view -0 + 1726 .cfi_startproc + 1727 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccW75d03.s page 58 + + + 1728 @ frame_needed = 0, uses_anonymous_args = 0 + 1729 0000 10B5 push {r4, lr} + 1730 .LCFI5: + 1731 .cfi_def_cfa_offset 8 + 1732 .cfi_offset 4, -8 + 1733 .cfi_offset 14, -4 + 1734 0002 82B0 sub sp, sp, #8 + 1735 .LCFI6: + 1736 .cfi_def_cfa_offset 16 +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 1737 .loc 1 1267 3 view .LVU492 + 1738 .LVL152: +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET; + 1739 .loc 1 1268 3 view .LVU493 +1269:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1270:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Update LSCOEN bit in Backup Domain control register */ +1271:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + 1740 .loc 1 1271 3 view .LVU494 + 1741 .loc 1 1271 7 is_stmt 0 view .LVU495 + 1742 0004 164B ldr r3, .L134 + 1743 0006 DB6B ldr r3, [r3, #60] + 1744 .loc 1 1271 6 view .LVU496 + 1745 0008 DB00 lsls r3, r3, #3 + 1746 000a 1AD4 bmi .L129 +1272:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1273:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 1747 .loc 1 1273 5 is_stmt 1 view .LVU497 + 1748 .LBB7: + 1749 .loc 1 1273 5 view .LVU498 + 1750 .loc 1 1273 5 view .LVU499 + 1751 000c 144A ldr r2, .L134 + 1752 000e D16B ldr r1, [r2, #60] + 1753 0010 8020 movs r0, #128 + 1754 0012 4005 lsls r0, r0, #21 + 1755 0014 0143 orrs r1, r0 + 1756 0016 D163 str r1, [r2, #60] + 1757 .loc 1 1273 5 view .LVU500 + 1758 0018 D36B ldr r3, [r2, #60] + 1759 001a 0340 ands r3, r0 + 1760 001c 0193 str r3, [sp, #4] + 1761 .loc 1 1273 5 view .LVU501 + 1762 001e 019B ldr r3, [sp, #4] + 1763 .LBE7: + 1764 .loc 1 1273 5 view .LVU502 +1274:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 1765 .loc 1 1274 5 view .LVU503 + 1766 .LVL153: + 1767 .loc 1 1274 19 is_stmt 0 view .LVU504 + 1768 0020 0124 movs r4, #1 + 1769 .LVL154: + 1770 .L125: +1275:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1276:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + 1771 .loc 1 1276 3 is_stmt 1 view .LVU505 + 1772 .loc 1 1276 7 is_stmt 0 view .LVU506 + 1773 0022 104B ldr r3, .L134+4 + 1774 0024 1B68 ldr r3, [r3] + ARM GAS /tmp/ccW75d03.s page 59 + + + 1775 .loc 1 1276 6 view .LVU507 + 1776 0026 DB05 lsls r3, r3, #23 + 1777 0028 0DD5 bpl .L131 +1268:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** + 1778 .loc 1 1268 20 view .LVU508 + 1779 002a 0021 movs r1, #0 + 1780 .LVL155: + 1781 .L126: +1277:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1278:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Enable access to the backup domain */ +1279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_PWR_EnableBkUpAccess(); +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** backupchanged = SET; +1281:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1282:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1283:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); + 1782 .loc 1 1283 3 is_stmt 1 view .LVU509 + 1783 002c 0C4A ldr r2, .L134 + 1784 002e D36D ldr r3, [r2, #92] + 1785 0030 0D48 ldr r0, .L134+8 + 1786 0032 0340 ands r3, r0 + 1787 0034 D365 str r3, [r2, #92] +1284:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** +1285:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Restore previous configuration */ +1286:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (backupchanged == SET) + 1788 .loc 1 1286 3 view .LVU510 + 1789 .loc 1 1286 6 is_stmt 0 view .LVU511 + 1790 0036 0129 cmp r1, #1 + 1791 0038 09D0 beq .L132 + 1792 .LVL156: + 1793 .L127: +1287:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1288:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** /* Disable access to the backup domain */ +1289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** HAL_PWR_DisableBkUpAccess(); +1290:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1291:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** if (pwrclkchanged == SET) + 1794 .loc 1 1291 3 is_stmt 1 view .LVU512 + 1795 .loc 1 1291 6 is_stmt 0 view .LVU513 + 1796 003a 012C cmp r4, #1 + 1797 003c 0AD0 beq .L133 + 1798 .L124: +1292:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** { +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); +1294:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } +1295:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1799 .loc 1 1295 1 view .LVU514 + 1800 003e 02B0 add sp, sp, #8 + 1801 @ sp needed + 1802 .LVL157: + 1803 .loc 1 1295 1 view .LVU515 + 1804 0040 10BD pop {r4, pc} + 1805 .LVL158: + 1806 .L129: +1267:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** FlagStatus backupchanged = RESET; + 1807 .loc 1 1267 20 view .LVU516 + 1808 0042 0024 movs r4, #0 + 1809 0044 EDE7 b .L125 + 1810 .LVL159: + ARM GAS /tmp/ccW75d03.s page 60 + + + 1811 .L131: +1279:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** backupchanged = SET; + 1812 .loc 1 1279 5 is_stmt 1 view .LVU517 + 1813 0046 FFF7FEFF bl HAL_PWR_EnableBkUpAccess + 1814 .LVL160: +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1815 .loc 1 1280 5 view .LVU518 +1280:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1816 .loc 1 1280 19 is_stmt 0 view .LVU519 + 1817 004a 0121 movs r1, #1 + 1818 004c EEE7 b .L126 + 1819 .LVL161: + 1820 .L132: +1289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1821 .loc 1 1289 5 is_stmt 1 view .LVU520 + 1822 004e FFF7FEFF bl HAL_PWR_DisableBkUpAccess + 1823 .LVL162: +1289:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1824 .loc 1 1289 5 is_stmt 0 view .LVU521 + 1825 0052 F2E7 b .L127 + 1826 .L133: +1293:Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c **** } + 1827 .loc 1 1293 5 is_stmt 1 view .LVU522 + 1828 0054 024A ldr r2, .L134 + 1829 0056 D36B ldr r3, [r2, #60] + 1830 0058 0449 ldr r1, .L134+12 + 1831 005a 0B40 ands r3, r1 + 1832 005c D363 str r3, [r2, #60] + 1833 .loc 1 1295 1 is_stmt 0 view .LVU523 + 1834 005e EEE7 b .L124 + 1835 .L135: + 1836 .align 2 + 1837 .L134: + 1838 0060 00100240 .word 1073876992 + 1839 0064 00700040 .word 1073770496 + 1840 0068 FFFFFFFE .word -16777217 + 1841 006c FFFFFFEF .word -268435457 + 1842 .cfi_endproc + 1843 .LFE301: + 1845 .text + 1846 .Letext0: + 1847 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 1848 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 1849 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h" + 1850 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h" + 1851 .file 6 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h" + 1852 .file 7 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h" + 1853 .file 8 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 1854 .file 9 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h" + 1855 .file 10 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h" + 1856 .file 11 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + ARM GAS /tmp/ccW75d03.s page 61 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_hal_rcc_ex.c + /tmp/ccW75d03.s:16 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 $t + /tmp/ccW75d03.s:24 .text.HAL_RCCEx_PeriphCLKConfig:0000000000000000 HAL_RCCEx_PeriphCLKConfig + /tmp/ccW75d03.s:444 .text.HAL_RCCEx_PeriphCLKConfig:00000000000001c4 $d + /tmp/ccW75d03.s:460 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 $t + /tmp/ccW75d03.s:467 .text.HAL_RCCEx_GetPeriphCLKConfig:0000000000000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/ccW75d03.s:568 .text.HAL_RCCEx_GetPeriphCLKConfig:000000000000006c $d + /tmp/ccW75d03.s:578 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 $t + /tmp/ccW75d03.s:585 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/ccW75d03.s:1329 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000304 $d + /tmp/ccW75d03.s:1336 .text.HAL_RCCEx_GetPeriphCLKFreq:0000000000000310 $t + /tmp/ccW75d03.s:1529 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000000003bc $d + /tmp/ccW75d03.s:1537 .text.HAL_RCCEx_EnableLSCO:0000000000000000 $t + /tmp/ccW75d03.s:1544 .text.HAL_RCCEx_EnableLSCO:0000000000000000 HAL_RCCEx_EnableLSCO + /tmp/ccW75d03.s:1708 .text.HAL_RCCEx_EnableLSCO:0000000000000090 $d + /tmp/ccW75d03.s:1716 .text.HAL_RCCEx_DisableLSCO:0000000000000000 $t + /tmp/ccW75d03.s:1723 .text.HAL_RCCEx_DisableLSCO:0000000000000000 HAL_RCCEx_DisableLSCO + /tmp/ccW75d03.s:1838 .text.HAL_RCCEx_DisableLSCO:0000000000000060 $d + +UNDEFINED SYMBOLS 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Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h \ + Drivers/CMSIS/Include/core_cm0plus.h \ + Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: 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Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h \ + Core/Inc/stm32g0xx_it.h +Core/Inc/main.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: +Core/Inc/stm32g0xx_it.h: diff --git a/squero/build/stm32g0xx_it.lst b/squero/build/stm32g0xx_it.lst new file mode 100644 index 0000000..ecd8847 --- /dev/null +++ b/squero/build/stm32g0xx_it.lst @@ -0,0 +1,298 @@ +ARM GAS /tmp/ccacA7RR.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_it.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.NMI_Handler,"ax",%progbits + 16 .align 1 + 17 .global NMI_Handler + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 NMI_Handler: + 25 .LFB297: + 26 .file 1 "Core/Src/stm32g0xx_it.c" + 1:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32g0xx_it.c **** /** + 3:Core/Src/stm32g0xx_it.c **** ****************************************************************************** + 4:Core/Src/stm32g0xx_it.c **** * @file stm32g0xx_it.c + 5:Core/Src/stm32g0xx_it.c **** * @brief Interrupt Service Routines. + 6:Core/Src/stm32g0xx_it.c **** ****************************************************************************** + 7:Core/Src/stm32g0xx_it.c **** * @attention + 8:Core/Src/stm32g0xx_it.c **** * + 9:Core/Src/stm32g0xx_it.c **** * Copyright (c) 2021 STMicroelectronics. + 10:Core/Src/stm32g0xx_it.c **** * All rights reserved. + 11:Core/Src/stm32g0xx_it.c **** * + 12:Core/Src/stm32g0xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/stm32g0xx_it.c **** * in the root directory of this software component. + 14:Core/Src/stm32g0xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/stm32g0xx_it.c **** * + 16:Core/Src/stm32g0xx_it.c **** ****************************************************************************** + 17:Core/Src/stm32g0xx_it.c **** */ + 18:Core/Src/stm32g0xx_it.c **** /* USER CODE END Header */ + 19:Core/Src/stm32g0xx_it.c **** + 20:Core/Src/stm32g0xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 21:Core/Src/stm32g0xx_it.c **** #include "main.h" + 22:Core/Src/stm32g0xx_it.c **** #include "stm32g0xx_it.h" + 23:Core/Src/stm32g0xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 24:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN Includes */ + 25:Core/Src/stm32g0xx_it.c **** /* USER CODE END Includes */ + 26:Core/Src/stm32g0xx_it.c **** + 27:Core/Src/stm32g0xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN TD */ + 29:Core/Src/stm32g0xx_it.c **** + 30:Core/Src/stm32g0xx_it.c **** /* USER CODE END TD */ + 31:Core/Src/stm32g0xx_it.c **** + 32:Core/Src/stm32g0xx_it.c **** /* Private define ------------------------------------------------------------*/ + ARM GAS /tmp/ccacA7RR.s page 2 + + + 33:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PD */ + 34:Core/Src/stm32g0xx_it.c **** + 35:Core/Src/stm32g0xx_it.c **** /* USER CODE END PD */ + 36:Core/Src/stm32g0xx_it.c **** + 37:Core/Src/stm32g0xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 38:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PM */ + 39:Core/Src/stm32g0xx_it.c **** + 40:Core/Src/stm32g0xx_it.c **** /* USER CODE END PM */ + 41:Core/Src/stm32g0xx_it.c **** + 42:Core/Src/stm32g0xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 43:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PV */ + 44:Core/Src/stm32g0xx_it.c **** + 45:Core/Src/stm32g0xx_it.c **** /* USER CODE END PV */ + 46:Core/Src/stm32g0xx_it.c **** + 47:Core/Src/stm32g0xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PFP */ + 49:Core/Src/stm32g0xx_it.c **** + 50:Core/Src/stm32g0xx_it.c **** /* USER CODE END PFP */ + 51:Core/Src/stm32g0xx_it.c **** + 52:Core/Src/stm32g0xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 53:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN 0 */ + 54:Core/Src/stm32g0xx_it.c **** + 55:Core/Src/stm32g0xx_it.c **** /* USER CODE END 0 */ + 56:Core/Src/stm32g0xx_it.c **** + 57:Core/Src/stm32g0xx_it.c **** /* External variables --------------------------------------------------------*/ + 58:Core/Src/stm32g0xx_it.c **** + 59:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN EV */ + 60:Core/Src/stm32g0xx_it.c **** + 61:Core/Src/stm32g0xx_it.c **** /* USER CODE END EV */ + 62:Core/Src/stm32g0xx_it.c **** + 63:Core/Src/stm32g0xx_it.c **** /******************************************************************************/ + 64:Core/Src/stm32g0xx_it.c **** /* Cortex-M0+ Processor Interruption and Exception Handlers */ + 65:Core/Src/stm32g0xx_it.c **** /******************************************************************************/ + 66:Core/Src/stm32g0xx_it.c **** /** + 67:Core/Src/stm32g0xx_it.c **** * @brief This function handles Non maskable interrupt. + 68:Core/Src/stm32g0xx_it.c **** */ + 69:Core/Src/stm32g0xx_it.c **** void NMI_Handler(void) + 70:Core/Src/stm32g0xx_it.c **** { + 27 .loc 1 70 1 view -0 + 28 .cfi_startproc + 29 @ Volatile: function does not return. + 30 @ args = 0, pretend = 0, frame = 0 + 31 @ frame_needed = 0, uses_anonymous_args = 0 + 32 @ link register save eliminated. + 33 .L2: + 71:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + 72:Core/Src/stm32g0xx_it.c **** + 73:Core/Src/stm32g0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 74:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 75:Core/Src/stm32g0xx_it.c **** while (1) + 34 .loc 1 75 3 discriminator 1 view .LVU1 + 76:Core/Src/stm32g0xx_it.c **** { + 77:Core/Src/stm32g0xx_it.c **** } + 35 .loc 1 77 3 discriminator 1 view .LVU2 + 75:Core/Src/stm32g0xx_it.c **** { + 36 .loc 1 75 9 discriminator 1 view .LVU3 + 37 0000 FEE7 b .L2 + ARM GAS /tmp/ccacA7RR.s page 3 + + + 38 .cfi_endproc + 39 .LFE297: + 41 .section .text.HardFault_Handler,"ax",%progbits + 42 .align 1 + 43 .global HardFault_Handler + 44 .syntax unified + 45 .code 16 + 46 .thumb_func + 47 .fpu softvfp + 49 HardFault_Handler: + 50 .LFB298: + 78:Core/Src/stm32g0xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 79:Core/Src/stm32g0xx_it.c **** } + 80:Core/Src/stm32g0xx_it.c **** + 81:Core/Src/stm32g0xx_it.c **** /** + 82:Core/Src/stm32g0xx_it.c **** * @brief This function handles Hard fault interrupt. + 83:Core/Src/stm32g0xx_it.c **** */ + 84:Core/Src/stm32g0xx_it.c **** void HardFault_Handler(void) + 85:Core/Src/stm32g0xx_it.c **** { + 51 .loc 1 85 1 view -0 + 52 .cfi_startproc + 53 @ Volatile: function does not return. + 54 @ args = 0, pretend = 0, frame = 0 + 55 @ frame_needed = 0, uses_anonymous_args = 0 + 56 @ link register save eliminated. + 57 .L4: + 86:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 87:Core/Src/stm32g0xx_it.c **** + 88:Core/Src/stm32g0xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 89:Core/Src/stm32g0xx_it.c **** while (1) + 58 .loc 1 89 3 discriminator 1 view .LVU5 + 90:Core/Src/stm32g0xx_it.c **** { + 91:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 92:Core/Src/stm32g0xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 93:Core/Src/stm32g0xx_it.c **** } + 59 .loc 1 93 3 discriminator 1 view .LVU6 + 89:Core/Src/stm32g0xx_it.c **** { + 60 .loc 1 89 9 discriminator 1 view .LVU7 + 61 0000 FEE7 b .L4 + 62 .cfi_endproc + 63 .LFE298: + 65 .section .text.SVC_Handler,"ax",%progbits + 66 .align 1 + 67 .global SVC_Handler + 68 .syntax unified + 69 .code 16 + 70 .thumb_func + 71 .fpu softvfp + 73 SVC_Handler: + 74 .LFB299: + 94:Core/Src/stm32g0xx_it.c **** } + 95:Core/Src/stm32g0xx_it.c **** + 96:Core/Src/stm32g0xx_it.c **** /** + 97:Core/Src/stm32g0xx_it.c **** * @brief This function handles System service call via SWI instruction. + 98:Core/Src/stm32g0xx_it.c **** */ + 99:Core/Src/stm32g0xx_it.c **** void SVC_Handler(void) + 100:Core/Src/stm32g0xx_it.c **** { + ARM GAS /tmp/ccacA7RR.s page 4 + + + 75 .loc 1 100 1 view -0 + 76 .cfi_startproc + 77 @ args = 0, pretend = 0, frame = 0 + 78 @ frame_needed = 0, uses_anonymous_args = 0 + 79 @ link register save eliminated. + 101:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 0 */ + 102:Core/Src/stm32g0xx_it.c **** + 103:Core/Src/stm32g0xx_it.c **** /* USER CODE END SVC_IRQn 0 */ + 104:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN SVC_IRQn 1 */ + 105:Core/Src/stm32g0xx_it.c **** + 106:Core/Src/stm32g0xx_it.c **** /* USER CODE END SVC_IRQn 1 */ + 107:Core/Src/stm32g0xx_it.c **** } + 80 .loc 1 107 1 view .LVU9 + 81 @ sp needed + 82 0000 7047 bx lr + 83 .cfi_endproc + 84 .LFE299: + 86 .section .text.PendSV_Handler,"ax",%progbits + 87 .align 1 + 88 .global PendSV_Handler + 89 .syntax unified + 90 .code 16 + 91 .thumb_func + 92 .fpu softvfp + 94 PendSV_Handler: + 95 .LFB300: + 108:Core/Src/stm32g0xx_it.c **** + 109:Core/Src/stm32g0xx_it.c **** /** + 110:Core/Src/stm32g0xx_it.c **** * @brief This function handles Pendable request for system service. + 111:Core/Src/stm32g0xx_it.c **** */ + 112:Core/Src/stm32g0xx_it.c **** void PendSV_Handler(void) + 113:Core/Src/stm32g0xx_it.c **** { + 96 .loc 1 113 1 view -0 + 97 .cfi_startproc + 98 @ args = 0, pretend = 0, frame = 0 + 99 @ frame_needed = 0, uses_anonymous_args = 0 + 100 @ link register save eliminated. + 114:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 115:Core/Src/stm32g0xx_it.c **** + 116:Core/Src/stm32g0xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 117:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 118:Core/Src/stm32g0xx_it.c **** + 119:Core/Src/stm32g0xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 120:Core/Src/stm32g0xx_it.c **** } + 101 .loc 1 120 1 view .LVU11 + 102 @ sp needed + 103 0000 7047 bx lr + 104 .cfi_endproc + 105 .LFE300: + 107 .section .text.SysTick_Handler,"ax",%progbits + 108 .align 1 + 109 .global SysTick_Handler + 110 .syntax unified + 111 .code 16 + 112 .thumb_func + 113 .fpu softvfp + 115 SysTick_Handler: + ARM GAS /tmp/ccacA7RR.s page 5 + + + 116 .LFB301: + 121:Core/Src/stm32g0xx_it.c **** + 122:Core/Src/stm32g0xx_it.c **** /** + 123:Core/Src/stm32g0xx_it.c **** * @brief This function handles System tick timer. + 124:Core/Src/stm32g0xx_it.c **** */ + 125:Core/Src/stm32g0xx_it.c **** void SysTick_Handler(void) + 126:Core/Src/stm32g0xx_it.c **** { + 117 .loc 1 126 1 view -0 + 118 .cfi_startproc + 119 @ args = 0, pretend = 0, frame = 0 + 120 @ frame_needed = 0, uses_anonymous_args = 0 + 121 0000 10B5 push {r4, lr} + 122 .LCFI0: + 123 .cfi_def_cfa_offset 8 + 124 .cfi_offset 4, -8 + 125 .cfi_offset 14, -4 + 127:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 128:Core/Src/stm32g0xx_it.c **** + 129:Core/Src/stm32g0xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 130:Core/Src/stm32g0xx_it.c **** HAL_IncTick(); + 126 .loc 1 130 3 view .LVU13 + 127 0002 FFF7FEFF bl HAL_IncTick + 128 .LVL0: + 131:Core/Src/stm32g0xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 132:Core/Src/stm32g0xx_it.c **** + 133:Core/Src/stm32g0xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 134:Core/Src/stm32g0xx_it.c **** } + 129 .loc 1 134 1 is_stmt 0 view .LVU14 + 130 @ sp needed + 131 0006 10BD pop {r4, pc} + 132 .cfi_endproc + 133 .LFE301: + 135 .text + 136 .Letext0: + 137 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 138 .file 3 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + 139 .file 4 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h" + ARM GAS /tmp/ccacA7RR.s page 6 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_it.c + /tmp/ccacA7RR.s:16 .text.NMI_Handler:0000000000000000 $t + /tmp/ccacA7RR.s:24 .text.NMI_Handler:0000000000000000 NMI_Handler + /tmp/ccacA7RR.s:42 .text.HardFault_Handler:0000000000000000 $t + /tmp/ccacA7RR.s:49 .text.HardFault_Handler:0000000000000000 HardFault_Handler + /tmp/ccacA7RR.s:66 .text.SVC_Handler:0000000000000000 $t + /tmp/ccacA7RR.s:73 .text.SVC_Handler:0000000000000000 SVC_Handler + /tmp/ccacA7RR.s:87 .text.PendSV_Handler:0000000000000000 $t + /tmp/ccacA7RR.s:94 .text.PendSV_Handler:0000000000000000 PendSV_Handler + /tmp/ccacA7RR.s:108 .text.SysTick_Handler:0000000000000000 $t + /tmp/ccacA7RR.s:115 .text.SysTick_Handler:0000000000000000 SysTick_Handler + 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a/squero/build/stm32g0xx_ll_dma.d b/squero/build/stm32g0xx_ll_dma.d new file mode 100644 index 0000000..d8b0345 --- /dev/null +++ b/squero/build/stm32g0xx_ll_dma.d @@ -0,0 +1,2 @@ +build/stm32g0xx_ll_dma.o: \ + Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c diff --git a/squero/build/stm32g0xx_ll_dma.lst b/squero/build/stm32g0xx_ll_dma.lst new file mode 100644 index 0000000..2e62f12 --- /dev/null +++ b/squero/build/stm32g0xx_ll_dma.lst @@ -0,0 +1,25 @@ +ARM GAS /tmp/cc6RDb7g.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "stm32g0xx_ll_dma.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .Letext0: + ARM GAS /tmp/cc6RDb7g.s page 2 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 stm32g0xx_ll_dma.c + +NO UNDEFINED SYMBOLS diff --git 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Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h \ + Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h: +Drivers/CMSIS/Include/core_cm0plus.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h: +Core/Inc/stm32g0xx_hal_conf.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h: +Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h: +Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h: diff --git a/squero/build/system_stm32g0xx.lst b/squero/build/system_stm32g0xx.lst new file mode 100644 index 0000000..85b076c --- /dev/null +++ b/squero/build/system_stm32g0xx.lst @@ -0,0 +1,631 @@ +ARM GAS /tmp/cceaHdIc.s page 1 + + + 1 .cpu cortex-m0plus + 2 .eabi_attribute 20, 1 + 3 .eabi_attribute 21, 1 + 4 .eabi_attribute 23, 3 + 5 .eabi_attribute 24, 1 + 6 .eabi_attribute 25, 1 + 7 .eabi_attribute 26, 1 + 8 .eabi_attribute 30, 1 + 9 .eabi_attribute 34, 0 + 10 .eabi_attribute 18, 4 + 11 .file "system_stm32g0xx.c" + 12 .text + 13 .Ltext0: + 14 .cfi_sections .debug_frame + 15 .section .text.SystemInit,"ax",%progbits + 16 .align 1 + 17 .global SystemInit + 18 .arch armv6s-m + 19 .syntax unified + 20 .code 16 + 21 .thumb_func + 22 .fpu softvfp + 24 SystemInit: + 25 .LFB297: + 26 .file 1 "Core/Src/system_stm32g0xx.c" + 1:Core/Src/system_stm32g0xx.c **** /** + 2:Core/Src/system_stm32g0xx.c **** ****************************************************************************** + 3:Core/Src/system_stm32g0xx.c **** * @file system_stm32g0xx.c + 4:Core/Src/system_stm32g0xx.c **** * @author MCD Application Team + 5:Core/Src/system_stm32g0xx.c **** * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + 6:Core/Src/system_stm32g0xx.c **** * + 7:Core/Src/system_stm32g0xx.c **** * This file provides two functions and one global variable to be called from + 8:Core/Src/system_stm32g0xx.c **** * user application: + 9:Core/Src/system_stm32g0xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Core/Src/system_stm32g0xx.c **** * before branch to main program. This call is made inside + 11:Core/Src/system_stm32g0xx.c **** * the "startup_stm32g0xx.s" file. + 12:Core/Src/system_stm32g0xx.c **** * + 13:Core/Src/system_stm32g0xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Core/Src/system_stm32g0xx.c **** * by the user application to setup the SysTick + 15:Core/Src/system_stm32g0xx.c **** * timer or configure other parameters. + 16:Core/Src/system_stm32g0xx.c **** * + 17:Core/Src/system_stm32g0xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Core/Src/system_stm32g0xx.c **** * be called whenever the core clock is changed + 19:Core/Src/system_stm32g0xx.c **** * during program execution. + 20:Core/Src/system_stm32g0xx.c **** * + 21:Core/Src/system_stm32g0xx.c **** * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + 22:Core/Src/system_stm32g0xx.c **** * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + 23:Core/Src/system_stm32g0xx.c **** * configure the system clock before to branch to main program. + 24:Core/Src/system_stm32g0xx.c **** * + 25:Core/Src/system_stm32g0xx.c **** * This file configures the system clock as follows: + 26:Core/Src/system_stm32g0xx.c **** *============================================================================= + 27:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 28:Core/Src/system_stm32g0xx.c **** * System Clock source | HSI + 29:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 30:Core/Src/system_stm32g0xx.c **** * SYSCLK(Hz) | 16000000 + 31:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 32:Core/Src/system_stm32g0xx.c **** * HCLK(Hz) | 16000000 + ARM GAS /tmp/cceaHdIc.s page 2 + + + 33:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 34:Core/Src/system_stm32g0xx.c **** * AHB Prescaler | 1 + 35:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 36:Core/Src/system_stm32g0xx.c **** * APB Prescaler | 1 + 37:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 38:Core/Src/system_stm32g0xx.c **** * HSI Division factor | 1 + 39:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 40:Core/Src/system_stm32g0xx.c **** * PLL_M | 1 + 41:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 42:Core/Src/system_stm32g0xx.c **** * PLL_N | 8 + 43:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 44:Core/Src/system_stm32g0xx.c **** * PLL_P | 7 + 45:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 46:Core/Src/system_stm32g0xx.c **** * PLL_Q | 2 + 47:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 48:Core/Src/system_stm32g0xx.c **** * PLL_R | 2 + 49:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 50:Core/Src/system_stm32g0xx.c **** * Require 48MHz for RNG | Disabled + 51:Core/Src/system_stm32g0xx.c **** *----------------------------------------------------------------------------- + 52:Core/Src/system_stm32g0xx.c **** *============================================================================= + 53:Core/Src/system_stm32g0xx.c **** ****************************************************************************** + 54:Core/Src/system_stm32g0xx.c **** * @attention + 55:Core/Src/system_stm32g0xx.c **** * + 56:Core/Src/system_stm32g0xx.c **** * Copyright (c) 2018-2021 STMicroelectronics. + 57:Core/Src/system_stm32g0xx.c **** * All rights reserved. + 58:Core/Src/system_stm32g0xx.c **** * + 59:Core/Src/system_stm32g0xx.c **** * This software is licensed under terms that can be found in the LICENSE file + 60:Core/Src/system_stm32g0xx.c **** * in the root directory of this software component. + 61:Core/Src/system_stm32g0xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 62:Core/Src/system_stm32g0xx.c **** * + 63:Core/Src/system_stm32g0xx.c **** ****************************************************************************** + 64:Core/Src/system_stm32g0xx.c **** */ + 65:Core/Src/system_stm32g0xx.c **** /** @addtogroup CMSIS + 66:Core/Src/system_stm32g0xx.c **** * @{ + 67:Core/Src/system_stm32g0xx.c **** */ + 68:Core/Src/system_stm32g0xx.c **** + 69:Core/Src/system_stm32g0xx.c **** /** @addtogroup stm32g0xx_system + 70:Core/Src/system_stm32g0xx.c **** * @{ + 71:Core/Src/system_stm32g0xx.c **** */ + 72:Core/Src/system_stm32g0xx.c **** + 73:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_Includes + 74:Core/Src/system_stm32g0xx.c **** * @{ + 75:Core/Src/system_stm32g0xx.c **** */ + 76:Core/Src/system_stm32g0xx.c **** + 77:Core/Src/system_stm32g0xx.c **** #include "stm32g0xx.h" + 78:Core/Src/system_stm32g0xx.c **** + 79:Core/Src/system_stm32g0xx.c **** #if !defined (HSE_VALUE) + 80:Core/Src/system_stm32g0xx.c **** #define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ + 81:Core/Src/system_stm32g0xx.c **** #endif /* HSE_VALUE */ + 82:Core/Src/system_stm32g0xx.c **** + 83:Core/Src/system_stm32g0xx.c **** #if !defined (HSI_VALUE) + 84:Core/Src/system_stm32g0xx.c **** #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ + 85:Core/Src/system_stm32g0xx.c **** #endif /* HSI_VALUE */ + 86:Core/Src/system_stm32g0xx.c **** + 87:Core/Src/system_stm32g0xx.c **** #if !defined (LSI_VALUE) + 88:Core/Src/system_stm32g0xx.c **** #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ + 89:Core/Src/system_stm32g0xx.c **** #endif /* LSI_VALUE */ + ARM GAS /tmp/cceaHdIc.s page 3 + + + 90:Core/Src/system_stm32g0xx.c **** + 91:Core/Src/system_stm32g0xx.c **** #if !defined (LSE_VALUE) + 92:Core/Src/system_stm32g0xx.c **** #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ + 93:Core/Src/system_stm32g0xx.c **** #endif /* LSE_VALUE */ + 94:Core/Src/system_stm32g0xx.c **** + 95:Core/Src/system_stm32g0xx.c **** /** + 96:Core/Src/system_stm32g0xx.c **** * @} + 97:Core/Src/system_stm32g0xx.c **** */ + 98:Core/Src/system_stm32g0xx.c **** + 99:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_TypesDefinitions + 100:Core/Src/system_stm32g0xx.c **** * @{ + 101:Core/Src/system_stm32g0xx.c **** */ + 102:Core/Src/system_stm32g0xx.c **** + 103:Core/Src/system_stm32g0xx.c **** /** + 104:Core/Src/system_stm32g0xx.c **** * @} + 105:Core/Src/system_stm32g0xx.c **** */ + 106:Core/Src/system_stm32g0xx.c **** + 107:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_Defines + 108:Core/Src/system_stm32g0xx.c **** * @{ + 109:Core/Src/system_stm32g0xx.c **** */ + 110:Core/Src/system_stm32g0xx.c **** + 111:Core/Src/system_stm32g0xx.c **** /************************* Miscellaneous Configuration ************************/ + 112:Core/Src/system_stm32g0xx.c **** /* Note: Following vector table addresses must be defined in line with linker + 113:Core/Src/system_stm32g0xx.c **** configuration. */ + 114:Core/Src/system_stm32g0xx.c **** /*!< Uncomment the following line if you need to relocate the vector table + 115:Core/Src/system_stm32g0xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic + 116:Core/Src/system_stm32g0xx.c **** remap of boot address selected */ + 117:Core/Src/system_stm32g0xx.c **** /* #define USER_VECT_TAB_ADDRESS */ + 118:Core/Src/system_stm32g0xx.c **** + 119:Core/Src/system_stm32g0xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 120:Core/Src/system_stm32g0xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table + 121:Core/Src/system_stm32g0xx.c **** in Sram else user remap will be done in Flash. */ + 122:Core/Src/system_stm32g0xx.c **** /* #define VECT_TAB_SRAM */ + 123:Core/Src/system_stm32g0xx.c **** #if defined(VECT_TAB_SRAM) + 124:Core/Src/system_stm32g0xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + 125:Core/Src/system_stm32g0xx.c **** This value must be a multiple of 0x200. */ + 126:Core/Src/system_stm32g0xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 127:Core/Src/system_stm32g0xx.c **** This value must be a multiple of 0x200. */ + 128:Core/Src/system_stm32g0xx.c **** #else + 129:Core/Src/system_stm32g0xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + 130:Core/Src/system_stm32g0xx.c **** This value must be a multiple of 0x200. */ + 131:Core/Src/system_stm32g0xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 132:Core/Src/system_stm32g0xx.c **** This value must be a multiple of 0x200. */ + 133:Core/Src/system_stm32g0xx.c **** #endif /* VECT_TAB_SRAM */ + 134:Core/Src/system_stm32g0xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 135:Core/Src/system_stm32g0xx.c **** /******************************************************************************/ + 136:Core/Src/system_stm32g0xx.c **** /** + 137:Core/Src/system_stm32g0xx.c **** * @} + 138:Core/Src/system_stm32g0xx.c **** */ + 139:Core/Src/system_stm32g0xx.c **** + 140:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_Macros + 141:Core/Src/system_stm32g0xx.c **** * @{ + 142:Core/Src/system_stm32g0xx.c **** */ + 143:Core/Src/system_stm32g0xx.c **** + 144:Core/Src/system_stm32g0xx.c **** /** + 145:Core/Src/system_stm32g0xx.c **** * @} + 146:Core/Src/system_stm32g0xx.c **** */ + ARM GAS /tmp/cceaHdIc.s page 4 + + + 147:Core/Src/system_stm32g0xx.c **** + 148:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_Variables + 149:Core/Src/system_stm32g0xx.c **** * @{ + 150:Core/Src/system_stm32g0xx.c **** */ + 151:Core/Src/system_stm32g0xx.c **** /* The SystemCoreClock variable is updated in three ways: + 152:Core/Src/system_stm32g0xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 153:Core/Src/system_stm32g0xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 154:Core/Src/system_stm32g0xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 155:Core/Src/system_stm32g0xx.c **** Note: If you use this function to configure the system clock; then there + 156:Core/Src/system_stm32g0xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock + 157:Core/Src/system_stm32g0xx.c **** variable is updated automatically. + 158:Core/Src/system_stm32g0xx.c **** */ + 159:Core/Src/system_stm32g0xx.c **** uint32_t SystemCoreClock = 16000000UL; + 160:Core/Src/system_stm32g0xx.c **** + 161:Core/Src/system_stm32g0xx.c **** const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, + 162:Core/Src/system_stm32g0xx.c **** const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + 163:Core/Src/system_stm32g0xx.c **** + 164:Core/Src/system_stm32g0xx.c **** /** + 165:Core/Src/system_stm32g0xx.c **** * @} + 166:Core/Src/system_stm32g0xx.c **** */ + 167:Core/Src/system_stm32g0xx.c **** + 168:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + 169:Core/Src/system_stm32g0xx.c **** * @{ + 170:Core/Src/system_stm32g0xx.c **** */ + 171:Core/Src/system_stm32g0xx.c **** + 172:Core/Src/system_stm32g0xx.c **** /** + 173:Core/Src/system_stm32g0xx.c **** * @} + 174:Core/Src/system_stm32g0xx.c **** */ + 175:Core/Src/system_stm32g0xx.c **** + 176:Core/Src/system_stm32g0xx.c **** /** @addtogroup STM32G0xx_System_Private_Functions + 177:Core/Src/system_stm32g0xx.c **** * @{ + 178:Core/Src/system_stm32g0xx.c **** */ + 179:Core/Src/system_stm32g0xx.c **** + 180:Core/Src/system_stm32g0xx.c **** /** + 181:Core/Src/system_stm32g0xx.c **** * @brief Setup the microcontroller system. + 182:Core/Src/system_stm32g0xx.c **** * @param None + 183:Core/Src/system_stm32g0xx.c **** * @retval None + 184:Core/Src/system_stm32g0xx.c **** */ + 185:Core/Src/system_stm32g0xx.c **** void SystemInit(void) + 186:Core/Src/system_stm32g0xx.c **** { + 27 .loc 1 186 1 view -0 + 28 .cfi_startproc + 29 @ args = 0, pretend = 0, frame = 0 + 30 @ frame_needed = 0, uses_anonymous_args = 0 + 31 @ link register save eliminated. + 187:Core/Src/system_stm32g0xx.c **** /* Configure the Vector Table location -------------------------------------*/ + 188:Core/Src/system_stm32g0xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 189:Core/Src/system_stm32g0xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ + 190:Core/Src/system_stm32g0xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 191:Core/Src/system_stm32g0xx.c **** } + 32 .loc 1 191 1 view .LVU1 + 33 @ sp needed + 34 0000 7047 bx lr + 35 .cfi_endproc + 36 .LFE297: + 38 .global __aeabi_uidiv + 39 .section .text.SystemCoreClockUpdate,"ax",%progbits + ARM GAS /tmp/cceaHdIc.s page 5 + + + 40 .align 1 + 41 .global SystemCoreClockUpdate + 42 .syntax unified + 43 .code 16 + 44 .thumb_func + 45 .fpu softvfp + 47 SystemCoreClockUpdate: + 48 .LFB298: + 192:Core/Src/system_stm32g0xx.c **** + 193:Core/Src/system_stm32g0xx.c **** /** + 194:Core/Src/system_stm32g0xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 195:Core/Src/system_stm32g0xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 196:Core/Src/system_stm32g0xx.c **** * be used by the user application to setup the SysTick timer or configure + 197:Core/Src/system_stm32g0xx.c **** * other parameters. + 198:Core/Src/system_stm32g0xx.c **** * + 199:Core/Src/system_stm32g0xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 200:Core/Src/system_stm32g0xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 201:Core/Src/system_stm32g0xx.c **** * based on this variable will be incorrect. + 202:Core/Src/system_stm32g0xx.c **** * + 203:Core/Src/system_stm32g0xx.c **** * @note - The system frequency computed by this function is not the real + 204:Core/Src/system_stm32g0xx.c **** * frequency in the chip. It is calculated based on the predefined + 205:Core/Src/system_stm32g0xx.c **** * constant and the selected clock source: + 206:Core/Src/system_stm32g0xx.c **** * + 207:Core/Src/system_stm32g0xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI divis + 208:Core/Src/system_stm32g0xx.c **** * + 209:Core/Src/system_stm32g0xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + 210:Core/Src/system_stm32g0xx.c **** * + 211:Core/Src/system_stm32g0xx.c **** * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + 212:Core/Src/system_stm32g0xx.c **** * + 213:Core/Src/system_stm32g0xx.c **** * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + 214:Core/Src/system_stm32g0xx.c **** * + 215:Core/Src/system_stm32g0xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + 216:Core/Src/system_stm32g0xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 217:Core/Src/system_stm32g0xx.c **** * + 218:Core/Src/system_stm32g0xx.c **** * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + 219:Core/Src/system_stm32g0xx.c **** * 16 MHz) but the real value may vary depending on the variations + 220:Core/Src/system_stm32g0xx.c **** * in voltage and temperature. + 221:Core/Src/system_stm32g0xx.c **** * + 222:Core/Src/system_stm32g0xx.c **** * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + 223:Core/Src/system_stm32g0xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 224:Core/Src/system_stm32g0xx.c **** * frequency of the crystal used. Otherwise, this function may + 225:Core/Src/system_stm32g0xx.c **** * have wrong result. + 226:Core/Src/system_stm32g0xx.c **** * + 227:Core/Src/system_stm32g0xx.c **** * - The result of this function could be not correct when using fractional + 228:Core/Src/system_stm32g0xx.c **** * value for HSE crystal. + 229:Core/Src/system_stm32g0xx.c **** * + 230:Core/Src/system_stm32g0xx.c **** * @param None + 231:Core/Src/system_stm32g0xx.c **** * @retval None + 232:Core/Src/system_stm32g0xx.c **** */ + 233:Core/Src/system_stm32g0xx.c **** void SystemCoreClockUpdate(void) + 234:Core/Src/system_stm32g0xx.c **** { + 49 .loc 1 234 1 view -0 + 50 .cfi_startproc + 51 @ args = 0, pretend = 0, frame = 0 + 52 @ frame_needed = 0, uses_anonymous_args = 0 + 53 0000 10B5 push {r4, lr} + 54 .LCFI0: + ARM GAS /tmp/cceaHdIc.s page 6 + + + 55 .cfi_def_cfa_offset 8 + 56 .cfi_offset 4, -8 + 57 .cfi_offset 14, -4 + 235:Core/Src/system_stm32g0xx.c **** uint32_t tmp; + 58 .loc 1 235 3 view .LVU3 + 236:Core/Src/system_stm32g0xx.c **** uint32_t pllvco; + 59 .loc 1 236 3 view .LVU4 + 237:Core/Src/system_stm32g0xx.c **** uint32_t pllr; + 60 .loc 1 237 3 view .LVU5 + 238:Core/Src/system_stm32g0xx.c **** uint32_t pllsource; + 61 .loc 1 238 3 view .LVU6 + 239:Core/Src/system_stm32g0xx.c **** uint32_t pllm; + 62 .loc 1 239 3 view .LVU7 + 240:Core/Src/system_stm32g0xx.c **** uint32_t hsidiv; + 63 .loc 1 240 3 view .LVU8 + 241:Core/Src/system_stm32g0xx.c **** + 242:Core/Src/system_stm32g0xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 243:Core/Src/system_stm32g0xx.c **** switch (RCC->CFGR & RCC_CFGR_SWS) + 64 .loc 1 243 3 view .LVU9 + 65 .loc 1 243 14 is_stmt 0 view .LVU10 + 66 0002 284B ldr r3, .L13 + 67 0004 9A68 ldr r2, [r3, #8] + 68 .loc 1 243 21 view .LVU11 + 69 0006 3823 movs r3, #56 + 70 0008 1340 ands r3, r2 + 71 .loc 1 243 3 view .LVU12 + 72 000a 182B cmp r3, #24 + 73 000c 37D0 beq .L3 + 74 000e 1FD8 bhi .L4 + 75 0010 082B cmp r3, #8 + 76 0012 24D0 beq .L5 + 77 0014 102B cmp r3, #16 + 78 0016 3BD1 bne .L7 + 244:Core/Src/system_stm32g0xx.c **** { + 245:Core/Src/system_stm32g0xx.c **** case RCC_CFGR_SWS_0: /* HSE used as system clock */ + 246:Core/Src/system_stm32g0xx.c **** SystemCoreClock = HSE_VALUE; + 247:Core/Src/system_stm32g0xx.c **** break; + 248:Core/Src/system_stm32g0xx.c **** + 249:Core/Src/system_stm32g0xx.c **** case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + 250:Core/Src/system_stm32g0xx.c **** SystemCoreClock = LSI_VALUE; + 251:Core/Src/system_stm32g0xx.c **** break; + 252:Core/Src/system_stm32g0xx.c **** + 253:Core/Src/system_stm32g0xx.c **** case RCC_CFGR_SWS_2: /* LSE used as system clock */ + 254:Core/Src/system_stm32g0xx.c **** SystemCoreClock = LSE_VALUE; + 255:Core/Src/system_stm32g0xx.c **** break; + 256:Core/Src/system_stm32g0xx.c **** + 257:Core/Src/system_stm32g0xx.c **** case RCC_CFGR_SWS_1: /* PLL used as system clock */ + 258:Core/Src/system_stm32g0xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + 259:Core/Src/system_stm32g0xx.c **** SYSCLK = PLL_VCO / PLLR + 260:Core/Src/system_stm32g0xx.c **** */ + 261:Core/Src/system_stm32g0xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + 79 .loc 1 261 7 is_stmt 1 view .LVU13 + 80 .loc 1 261 23 is_stmt 0 view .LVU14 + 81 0018 224A ldr r2, .L13 + 82 001a D168 ldr r1, [r2, #12] + 83 .loc 1 261 17 view .LVU15 + 84 001c 0323 movs r3, #3 + ARM GAS /tmp/cceaHdIc.s page 7 + + + 85 001e 0B40 ands r3, r1 + 86 .LVL0: + 262:Core/Src/system_stm32g0xx.c **** pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + 87 .loc 1 262 7 is_stmt 1 view .LVU16 + 88 .loc 1 262 19 is_stmt 0 view .LVU17 + 89 0020 D268 ldr r2, [r2, #12] + 90 .loc 1 262 49 view .LVU18 + 91 0022 1209 lsrs r2, r2, #4 + 92 0024 0721 movs r1, #7 + 93 0026 1140 ands r1, r2 + 94 .loc 1 262 12 view .LVU19 + 95 0028 0131 adds r1, r1, #1 + 96 .LVL1: + 263:Core/Src/system_stm32g0xx.c **** + 264:Core/Src/system_stm32g0xx.c **** if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + 97 .loc 1 264 7 is_stmt 1 view .LVU20 + 98 .loc 1 264 9 is_stmt 0 view .LVU21 + 99 002a 032B cmp r3, #3 + 100 002c 2CD0 beq .L12 + 265:Core/Src/system_stm32g0xx.c **** { + 266:Core/Src/system_stm32g0xx.c **** pllvco = (HSE_VALUE / pllm); + 267:Core/Src/system_stm32g0xx.c **** } + 268:Core/Src/system_stm32g0xx.c **** else /* HSI used as PLL clock source */ + 269:Core/Src/system_stm32g0xx.c **** { + 270:Core/Src/system_stm32g0xx.c **** pllvco = (HSI_VALUE / pllm); + 101 .loc 1 270 11 is_stmt 1 view .LVU22 + 102 .loc 1 270 18 is_stmt 0 view .LVU23 + 103 002e 1E48 ldr r0, .L13+4 + 104 0030 FFF7FEFF bl __aeabi_uidiv + 105 .LVL2: + 106 .L11: + 271:Core/Src/system_stm32g0xx.c **** } + 272:Core/Src/system_stm32g0xx.c **** pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 107 .loc 1 272 7 is_stmt 1 view .LVU24 + 108 .loc 1 272 30 is_stmt 0 view .LVU25 + 109 0034 1B49 ldr r1, .L13 + 110 0036 CA68 ldr r2, [r1, #12] + 111 .loc 1 272 60 view .LVU26 + 112 0038 120A lsrs r2, r2, #8 + 113 003a 7F23 movs r3, #127 + 114 003c 1340 ands r3, r2 + 115 .loc 1 272 14 view .LVU27 + 116 003e 5843 muls r0, r3 + 117 .LVL3: + 273:Core/Src/system_stm32g0xx.c **** pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + 118 .loc 1 273 7 is_stmt 1 view .LVU28 + 119 .loc 1 273 20 is_stmt 0 view .LVU29 + 120 0040 C968 ldr r1, [r1, #12] + 121 .loc 1 273 50 view .LVU30 + 122 0042 490F lsrs r1, r1, #29 + 123 .loc 1 273 12 view .LVU31 + 124 0044 0131 adds r1, r1, #1 + 125 .LVL4: + 274:Core/Src/system_stm32g0xx.c **** + 275:Core/Src/system_stm32g0xx.c **** SystemCoreClock = pllvco/pllr; + 126 .loc 1 275 7 is_stmt 1 view .LVU32 + 127 .loc 1 275 31 is_stmt 0 view .LVU33 + ARM GAS /tmp/cceaHdIc.s page 8 + + + 128 0046 FFF7FEFF bl __aeabi_uidiv + 129 .LVL5: + 130 .loc 1 275 23 view .LVU34 + 131 004a 184B ldr r3, .L13+8 + 132 004c 1860 str r0, [r3] + 276:Core/Src/system_stm32g0xx.c **** break; + 133 .loc 1 276 7 is_stmt 1 view .LVU35 + 134 004e 09E0 b .L9 + 135 .L4: + 243:Core/Src/system_stm32g0xx.c **** { + 136 .loc 1 243 3 is_stmt 0 view .LVU36 + 137 0050 202B cmp r3, #32 + 138 0052 1DD1 bne .L7 + 254:Core/Src/system_stm32g0xx.c **** break; + 139 .loc 1 254 7 is_stmt 1 view .LVU37 + 254:Core/Src/system_stm32g0xx.c **** break; + 140 .loc 1 254 23 is_stmt 0 view .LVU38 + 141 0054 154B ldr r3, .L13+8 + 142 0056 8022 movs r2, #128 + 143 0058 1202 lsls r2, r2, #8 + 144 005a 1A60 str r2, [r3] + 255:Core/Src/system_stm32g0xx.c **** + 145 .loc 1 255 7 is_stmt 1 view .LVU39 + 146 005c 02E0 b .L9 + 147 .L5: + 246:Core/Src/system_stm32g0xx.c **** break; + 148 .loc 1 246 7 view .LVU40 + 246:Core/Src/system_stm32g0xx.c **** break; + 149 .loc 1 246 23 is_stmt 0 view .LVU41 + 150 005e 134B ldr r3, .L13+8 + 151 0060 134A ldr r2, .L13+12 + 152 0062 1A60 str r2, [r3] + 247:Core/Src/system_stm32g0xx.c **** + 153 .loc 1 247 7 is_stmt 1 view .LVU42 + 154 .L9: + 277:Core/Src/system_stm32g0xx.c **** + 278:Core/Src/system_stm32g0xx.c **** case 0x00000000U: /* HSI used as system clock */ + 279:Core/Src/system_stm32g0xx.c **** default: /* HSI used as system clock */ + 280:Core/Src/system_stm32g0xx.c **** hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + 281:Core/Src/system_stm32g0xx.c **** SystemCoreClock = (HSI_VALUE/hsidiv); + 282:Core/Src/system_stm32g0xx.c **** break; + 283:Core/Src/system_stm32g0xx.c **** } + 284:Core/Src/system_stm32g0xx.c **** /* Compute HCLK clock frequency --------------------------------------------*/ + 285:Core/Src/system_stm32g0xx.c **** /* Get HCLK prescaler */ + 286:Core/Src/system_stm32g0xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 155 .loc 1 286 3 view .LVU43 + 156 .loc 1 286 28 is_stmt 0 view .LVU44 + 157 0064 0F4B ldr r3, .L13 + 158 0066 9A68 ldr r2, [r3, #8] + 159 .loc 1 286 52 view .LVU45 + 160 0068 120A lsrs r2, r2, #8 + 161 006a 0F23 movs r3, #15 + 162 006c 1340 ands r3, r2 + 163 .loc 1 286 7 view .LVU46 + 164 006e 9B00 lsls r3, r3, #2 + 165 0070 104A ldr r2, .L13+16 + 166 0072 9B58 ldr r3, [r3, r2] + ARM GAS /tmp/cceaHdIc.s page 9 + + + 167 .LVL6: + 287:Core/Src/system_stm32g0xx.c **** /* HCLK clock frequency */ + 288:Core/Src/system_stm32g0xx.c **** SystemCoreClock >>= tmp; + 168 .loc 1 288 3 is_stmt 1 view .LVU47 + 169 .loc 1 288 19 is_stmt 0 view .LVU48 + 170 0074 0D4A ldr r2, .L13+8 + 171 0076 1168 ldr r1, [r2] + 172 0078 D940 lsrs r1, r1, r3 + 173 007a 1160 str r1, [r2] + 289:Core/Src/system_stm32g0xx.c **** } + 174 .loc 1 289 1 view .LVU49 + 175 @ sp needed + 176 007c 10BD pop {r4, pc} + 177 .LVL7: + 178 .L3: + 250:Core/Src/system_stm32g0xx.c **** break; + 179 .loc 1 250 7 is_stmt 1 view .LVU50 + 250:Core/Src/system_stm32g0xx.c **** break; + 180 .loc 1 250 23 is_stmt 0 view .LVU51 + 181 007e 0B4B ldr r3, .L13+8 + 182 0080 FA22 movs r2, #250 + 183 0082 D201 lsls r2, r2, #7 + 184 0084 1A60 str r2, [r3] + 251:Core/Src/system_stm32g0xx.c **** + 185 .loc 1 251 7 is_stmt 1 view .LVU52 + 186 0086 EDE7 b .L9 + 187 .LVL8: + 188 .L12: + 266:Core/Src/system_stm32g0xx.c **** } + 189 .loc 1 266 9 view .LVU53 + 266:Core/Src/system_stm32g0xx.c **** } + 190 .loc 1 266 16 is_stmt 0 view .LVU54 + 191 0088 0948 ldr r0, .L13+12 + 192 008a FFF7FEFF bl __aeabi_uidiv + 193 .LVL9: + 266:Core/Src/system_stm32g0xx.c **** } + 194 .loc 1 266 16 view .LVU55 + 195 008e D1E7 b .L11 + 196 .LVL10: + 197 .L7: + 280:Core/Src/system_stm32g0xx.c **** SystemCoreClock = (HSI_VALUE/hsidiv); + 198 .loc 1 280 7 is_stmt 1 view .LVU56 + 280:Core/Src/system_stm32g0xx.c **** SystemCoreClock = (HSI_VALUE/hsidiv); + 199 .loc 1 280 26 is_stmt 0 view .LVU57 + 200 0090 044B ldr r3, .L13 + 201 0092 1B68 ldr r3, [r3] + 280:Core/Src/system_stm32g0xx.c **** SystemCoreClock = (HSI_VALUE/hsidiv); + 202 .loc 1 280 59 view .LVU58 + 203 0094 DB0A lsrs r3, r3, #11 + 204 0096 0722 movs r2, #7 + 205 0098 1A40 ands r2, r3 + 206 .LVL11: + 281:Core/Src/system_stm32g0xx.c **** break; + 207 .loc 1 281 7 is_stmt 1 view .LVU59 + 281:Core/Src/system_stm32g0xx.c **** break; + 208 .loc 1 281 35 is_stmt 0 view .LVU60 + 209 009a 034B ldr r3, .L13+4 + ARM GAS /tmp/cceaHdIc.s page 10 + + + 210 009c D340 lsrs r3, r3, r2 + 281:Core/Src/system_stm32g0xx.c **** break; + 211 .loc 1 281 23 view .LVU61 + 212 009e 034A ldr r2, .L13+8 + 213 .LVL12: + 281:Core/Src/system_stm32g0xx.c **** break; + 214 .loc 1 281 23 view .LVU62 + 215 00a0 1360 str r3, [r2] + 282:Core/Src/system_stm32g0xx.c **** } + 216 .loc 1 282 7 is_stmt 1 view .LVU63 + 217 00a2 DFE7 b .L9 + 218 .L14: + 219 .align 2 + 220 .L13: + 221 00a4 00100240 .word 1073876992 + 222 00a8 0024F400 .word 16000000 + 223 00ac 00000000 .word .LANCHOR0 + 224 00b0 00127A00 .word 8000000 + 225 00b4 00000000 .word .LANCHOR1 + 226 .cfi_endproc + 227 .LFE298: + 229 .global APBPrescTable + 230 .global AHBPrescTable + 231 .global SystemCoreClock + 232 .section .data.SystemCoreClock,"aw" + 233 .align 2 + 234 .set .LANCHOR0,. + 0 + 237 SystemCoreClock: + 238 0000 0024F400 .word 16000000 + 239 .section .rodata.AHBPrescTable,"a" + 240 .align 2 + 241 .set .LANCHOR1,. + 0 + 244 AHBPrescTable: + 245 0000 00000000 .word 0 + 246 0004 00000000 .word 0 + 247 0008 00000000 .word 0 + 248 000c 00000000 .word 0 + 249 0010 00000000 .word 0 + 250 0014 00000000 .word 0 + 251 0018 00000000 .word 0 + 252 001c 00000000 .word 0 + 253 0020 01000000 .word 1 + 254 0024 02000000 .word 2 + 255 0028 03000000 .word 3 + 256 002c 04000000 .word 4 + 257 0030 06000000 .word 6 + 258 0034 07000000 .word 7 + 259 0038 08000000 .word 8 + 260 003c 09000000 .word 9 + 261 .section .rodata.APBPrescTable,"a" + 262 .align 2 + 265 APBPrescTable: + 266 0000 00000000 .word 0 + 267 0004 00000000 .word 0 + 268 0008 00000000 .word 0 + 269 000c 00000000 .word 0 + 270 0010 01000000 .word 1 + ARM GAS /tmp/cceaHdIc.s page 11 + + + 271 0014 02000000 .word 2 + 272 0018 03000000 .word 3 + 273 001c 04000000 .word 4 + 274 .text + 275 .Letext0: + 276 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" + 277 .file 3 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h" + 278 .file 4 "Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h" + 279 .file 5 "Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h" + ARM GAS /tmp/cceaHdIc.s page 12 + + +DEFINED SYMBOLS + *ABS*:0000000000000000 system_stm32g0xx.c + /tmp/cceaHdIc.s:16 .text.SystemInit:0000000000000000 $t + /tmp/cceaHdIc.s:24 .text.SystemInit:0000000000000000 SystemInit + /tmp/cceaHdIc.s:40 .text.SystemCoreClockUpdate:0000000000000000 $t + /tmp/cceaHdIc.s:47 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate + /tmp/cceaHdIc.s:221 .text.SystemCoreClockUpdate:00000000000000a4 $d + /tmp/cceaHdIc.s:265 .rodata.APBPrescTable:0000000000000000 APBPrescTable + /tmp/cceaHdIc.s:244 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable + /tmp/cceaHdIc.s:237 .data.SystemCoreClock:0000000000000000 SystemCoreClock + /tmp/cceaHdIc.s:233 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Si5351_ConfigStruct->HW_I2C_Address, reg_data, sizeof(reg_data), HAL_MAX_DELAY); +} + +uint8_t Si5351_ReadRegister(Si5351_ConfigTypeDef *Si5351_ConfigStruct, uint8_t reg_address){ + uint8_t reg_data; + HAL_I2C_Master_Receive (&hi2c2, Si5351_ConfigStruct->HW_I2C_Address, reg_data, 1, HAL_MAX_DELAY); +} + +https://www.rfzero.net/tutorials/si5351a/ +make clean && make && gdb-multiarch -ex "target extended-remote /dev/ttyACM0" -ex "monitor swdp_scan" -ex "attach 1" -ex "load build/squero.elf" -ex "quit" + +fout = (fref * (a+(b/c)) / (R * (d + (e/f))) diff --git a/squero/squero.ioc b/squero/squero.ioc new file mode 100644 index 0000000..e0761cd --- /dev/null +++ b/squero/squero.ioc @@ -0,0 +1,110 @@ +#MicroXplorer Configuration settings - do not modify +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.Family=STM32G0 +Mcu.IP0=I2C2 +Mcu.IP1=NVIC +Mcu.IP2=RCC +Mcu.IP3=SYS +Mcu.IPNb=4 +Mcu.Name=STM32G031J(4-6)Mx +Mcu.Package=SO8N +Mcu.Pin0=PC14-OSC32_IN (PC14) +Mcu.Pin1=PB7 +Mcu.Pin2=PB8 +Mcu.Pin3=PB9 +Mcu.Pin4=PA11 [PA9] +Mcu.Pin5=PA12 [PA10] +Mcu.Pin6=PA13 +Mcu.Pin7=PA14-BOOT0 +Mcu.Pin8=VP_SYS_VS_Systick +Mcu.PinsNb=9 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32G031J6Mx +MxCube.Version=6.4.0 +MxDb.Version=DB.6.0.40 +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true +PA11\ [PA9].Mode=I2C +PA11\ [PA9].Signal=I2C2_SCL +PA12\ [PA10].Mode=I2C +PA12\ [PA10].Signal=I2C2_SDA +PA13.Mode=Serial_Wire +PA13.Signal=SYS_SWDIO +PA14-BOOT0.Mode=Serial_Wire +PA14-BOOT0.Signal=SYS_SWCLK +PB7.Locked=true +PB8.Locked=true +PB9.Locked=true +PC14-OSC32_IN\ (PC14).GPIOParameters=GPIO_PuPd,GPIO_Label +PC14-OSC32_IN\ (PC14).GPIO_Label=UP +PC14-OSC32_IN\ (PC14).GPIO_PuPd=GPIO_PULLDOWN +PC14-OSC32_IN\ (PC14).Locked=true +PC14-OSC32_IN\ (PC14).Signal=GPIO_Input +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G031J6Mx +ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.5.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=squero.ioc +ProjectManager.ProjectName=squero +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C2_Init-I2C2-false-HAL-true +RCC.AHBFreq_Value=16000000 +RCC.APBFreq_Value=16000000 +RCC.APBTimFreq_Value=16000000 +RCC.CortexFreq_Value=16000000 +RCC.EXTERNAL_CLOCK_VALUE=12288000 +RCC.FCLKCortexFreq_Value=16000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=16000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=16000000 +RCC.I2S1Freq_Value=16000000 +RCC.IPParameters=AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,TIM1Freq_Value,USART1Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=16000000 +RCC.LPTIM2Freq_Value=16000000 +RCC.LPUART1Freq_Value=16000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=16000000 +RCC.PLLPoutputFreq_Value=64000000 +RCC.PLLQoutputFreq_Value=64000000 +RCC.PLLRCLKFreq_Value=64000000 +RCC.PWRFreq_Value=16000000 +RCC.SYSCLKFreq_VALUE=16000000 +RCC.TIM1Freq_Value=16000000 +RCC.USART1Freq_Value=16000000 +RCC.VCOInputFreq_Value=16000000 +RCC.VCOOutputFreq_Value=128000000 +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/squero/startup_stm32g031xx.s b/squero/startup_stm32g031xx.s new file mode 100644 index 0000000..1507667 --- /dev/null +++ b/squero/startup_stm32g031xx.s @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file startup_stm32g031xx.s + * @author MCD Application Team + * @brief STM32G031xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word LPTIM2_IRQHandler /* LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + .word 0 /* reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +