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fix interfaccia

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This commit is contained in:
nzasch
2022-01-12 01:09:32 +01:00
parent b9a7a1e15b
commit 6d0c31556a
435 changed files with 436215 additions and 10940 deletions
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22
codice/Core/Src/si5351.c
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@@ -44,14 +44,14 @@ void CalcRegisters(uint32_t fout, uint8_t *regs){
rd++;
}
rx_div = rd << 4;
d = 600e6 / (r * fout); // Use lowest VCO frequency but handle d minimum
if (d % 2) // Make d even to reduce spurious and phase noise/jitter, see datasheet 4.1.2.1.
d++;
if (d * r * fout < 600e6) // VCO frequency to low check and maintain an even d value
d += 2;
}
}
else // 292968 Hz <= fout <= 150 MHz
{
d = 600e6 / fout; // Use lowest VCO frequency but handle d minimum
@@ -144,20 +144,22 @@ void si53531_initialize(){
// si5351_write8(SI5351_OUT_ENABLE, 0xFC); // Output Enable Control. Active low
}
void si53531_set_frequency(uint32_t freq){
void si53531_set_frequency(uint32_t freq, uint8_t synth){
uint8_t regs[16];
CalcRegisters(freq, regs);
// Load PLLA Feedback Multisynth NA
for (int i = 0; i < 8; i++)
si5351_write8(SI5351_PLLA + i, regs[i]);
// Load Output Multisynth0 with d (e and f already set during init. and never changed)
for (int i = 10; i < 13; i++)
si5351_write8(34 + i, regs[i]);
for (int i = 10; i < 13; i++)
si5351_write8(42 + i, regs[i]);
if(synth = 0){
for (int i = 10; i < 13; i++)
si5351_write8(34 + i, regs[i]);
} else if(synth = 1){
for (int i = 10; i < 13; i++)
si5351_write8(42 + i, regs[i]);
}
// Reset PLLA
// delayMicroseconds(500); // Allow registers to settle before resetting the PLL