fix interfaccia
This commit is contained in:
@@ -39,14 +39,12 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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******************************************************************************
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*/
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@@ -83,9 +81,13 @@
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/** @defgroup RCC_Private_Macros RCC Private Macros
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* @{
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*/
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#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define MCO1_GPIO_PORT GPIOA
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#define MCO1_PIN GPIO_PIN_8
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#define RCC_GET_MCO_GPIO_PIN(__RCC_MCOx__) ((__RCC_MCOx__) & GPIO_PIN_MASK)
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#define RCC_GET_MCO_GPIO_AF(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOAF_MASK) >> RCC_MCO_GPIOAF_POS)
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#define RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__) (((__RCC_MCOx__) & RCC_MCO_GPIOPORT_MASK) >> RCC_MCO_GPIOPORT_POS)
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#define RCC_GET_MCO_GPIO_PORT(__RCC_MCOx__) (AHB2PERIPH_BASE + ((0x00000400UL) * RCC_GET_MCO_GPIO_INDEX(__RCC_MCOx__)))
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#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \
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(MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__HAL_RCC_PLLSOURCE__)))
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@@ -961,11 +963,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
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*/
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/**
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* @brief Select the clock source to output on MCO pin(PA8).
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* @note PA8 should be configured in alternate function mode.
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* @brief Select the clock source to output on MCO pin(PA8/PG10).
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* @note PA8/PG10 should be configured in alternate function mode.
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* @note The default configuration of the GPIOG pin 10 (PG10) is set to reset mode (NRST pin)
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* and user shall set the NRST_MODE Bit in the FLASH OPTR register to be able to use it
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* as an MCO pin.
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* The @ref HAL_FLASHEx_OBProgram() API can be used to configure the NRST_MODE Bit value.
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* @param RCC_MCOx specifies the output direction for the clock source.
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* For STM32G4xx family this parameter can have only one value:
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* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
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* @arg @ref RCC_MCO_PA8 Clock source to output on MCO1 pin(PA8).
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* @arg @ref RCC_MCO_PG10 Clock source to output on MCO1 pin(PG10).
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* @param RCC_MCOSource specifies the clock source to output.
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* This parameter can be one of the following values:
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* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO
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@@ -987,29 +994,41 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
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*/
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void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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GPIO_InitTypeDef gpio_initstruct;
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uint32_t mcoindex;
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uint32_t mco_gpio_index;
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GPIO_TypeDef * mco_gpio_port;
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/* Check the parameters */
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assert_param(IS_RCC_MCO(RCC_MCOx));
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assert_param(IS_RCC_MCODIV(RCC_MCODiv));
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assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
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/* Prevent unused argument(s) compilation warning if no assert_param check */
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UNUSED(RCC_MCOx);
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/* Common GPIO init parameters */
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gpio_initstruct.Mode = GPIO_MODE_AF_PP;
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gpio_initstruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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gpio_initstruct.Pull = GPIO_NOPULL;
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/* MCO Clock Enable */
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MCO1_CLK_ENABLE();
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/* Get MCOx selection */
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mcoindex = RCC_MCOx & RCC_MCO_INDEX_MASK;
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/* Configure the MCO1 pin in alternate function mode */
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GPIO_InitStruct.Pin = MCO1_PIN;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
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HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
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/* Get MCOx GPIO Port */
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mco_gpio_port = (GPIO_TypeDef *) RCC_GET_MCO_GPIO_PORT(RCC_MCOx);
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/* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */
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MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
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/* MCOx Clock Enable */
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mco_gpio_index = RCC_GET_MCO_GPIO_INDEX(RCC_MCOx);
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SET_BIT(RCC->AHB2ENR, (1UL << mco_gpio_index ));
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/* Configure the MCOx pin in alternate function mode */
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gpio_initstruct.Pin = RCC_GET_MCO_GPIO_PIN(RCC_MCOx);
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gpio_initstruct.Alternate = RCC_GET_MCO_GPIO_AF(RCC_MCOx);
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HAL_GPIO_Init(mco_gpio_port, &gpio_initstruct);
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if (mcoindex == RCC_MCO1_INDEX)
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{
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assert_param(IS_RCC_MCODIV(RCC_MCODiv));
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assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
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/* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
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MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
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}
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}
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/**
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@@ -1380,4 +1399,3 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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