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fix interfaccia

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This commit is contained in:
nzasch
2022-01-12 01:09:32 +01:00
parent b9a7a1e15b
commit 6d0c31556a
435 changed files with 436215 additions and 10940 deletions
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2
README.md
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@@ -15,6 +15,6 @@ con frequenza intermedia minore di 150khz, oppure in undersampling a 455khz.
* Controllo del guadagno di ingresso su 6 step * Controllo del guadagno di ingresso su 6 step
* 1 LO in onda quadra complementare * 1 LO in onda quadra complementare
* 1 LO in onda quadra semplice * 1 LO in onda quadra semplice
* FIltro audio regolabile * Filtro audio configurabile
* S-Meter * S-Meter

6
codice/.mxproject
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File diff suppressed because one or more lines are too long

16
codice/Core/Inc/bassofono.h
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@@ -45,7 +45,10 @@
#define MOD_DC 0 #define MOD_DC 0
#define MOD_LSB 1 #define MOD_LSB 1
#define MOD_USB 2 #define MOD_USB 2
#define MOD_AM 3 #define MOD_CWL 3
#define MOD_CWU 4
#define MOD_AM 5
#define MOD_FM 6
#define STATUS_RX 0 #define STATUS_RX 0
#define STATUS_TX 1 #define STATUS_TX 1
@@ -72,7 +75,7 @@ extern uint32_t frequency;
extern int32_t rit; extern int32_t rit;
extern uint16_t pwm_tx_period; extern uint16_t pwm_tx_period;
extern int32_t modulation; extern int32_t modulation;
extern int32_t gain; extern int32_t rx_gain;
extern int32_t peak, oldpeak, peakset; extern int32_t peak, oldpeak, peakset;
extern int32_t volume; extern int32_t volume;
extern int32_t squelch; extern int32_t squelch;
@@ -111,9 +114,16 @@ extern q31_t lf_buffer[2][LF_BUFFER_SIZE];
// ======== FUNZIONI ======== // ======== FUNZIONI ========
void start_transmit(void);
void stop_transmit(void);
void start_receive(void);
void stop_receive(void);
void set_rx_gain(void);
int32_t set_nco1_freq(int32_t freq); int32_t set_nco1_freq(int32_t freq);
void set_filter(void); // void set_filter(void);
void set_frequency(void); void set_frequency(void);
void set_modulation(void); void set_modulation(void);
void set_dummy (void); void set_dummy (void);

2
codice/Core/Inc/interface.h
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@@ -82,7 +82,7 @@ struct menu_item {
extern uint8_t menu_item, menu_page; extern uint8_t menu_item, menu_page;
extern uint8_t menu_last_item[MENU_PAGE_EOM + 1]; extern uint8_t menu_last_item[MENU_PAGE_EOM + 1];
extern char modulation_list[4][4]; extern char modulation_list[][4];
extern char status_list[3][3]; extern char status_list[3][3];
extern struct menu_item items[]; extern struct menu_item items[];

2
codice/Core/Inc/main.h
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@@ -54,7 +54,7 @@ extern "C" {
void Error_Handler(void); void Error_Handler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
void set_gain(void); // void set_rx_gain(void);
/* USER CODE END EFP */ /* USER CODE END EFP */

1
codice/Core/Inc/rx.h
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@@ -78,6 +78,7 @@ void am_demodulator(q31_t *in_I, q31_t *in_Q, uint16_t size, q31_t *out);
// filtri // filtri
// void filter_init(void); // void filter_init(void);
void set_rx_audio_filter(void);
void st2_filter_init(void); void st2_filter_init(void);
void audio_filter_init(void); void audio_filter_init(void);
void audio_filter_generate_coeffs(int32_t *Coeffs, uint32_t freq, uint32_t bw, uint8_t beta); void audio_filter_generate_coeffs(int32_t *Coeffs, uint32_t freq, uint32_t bw, uint8_t beta);

7
codice/Core/Inc/si5351.h
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@@ -5,6 +5,8 @@
#define SI5351_MIN_FREQ 3000 #define SI5351_MIN_FREQ 3000
#define SI5351_MAX_FREQ 200000000 #define SI5351_MAX_FREQ 200000000
// #### registri ####
#define SI5351_OUT_ENABLE 3 #define SI5351_OUT_ENABLE 3
#define SI5351_OUT_DIS_STATE 24 #define SI5351_OUT_DIS_STATE 24
@@ -25,3 +27,8 @@
#define SI5351_CRYSTAL_LOAD 183 #define SI5351_CRYSTAL_LOAD 183
extern I2C_HandleTypeDef hi2c1; extern I2C_HandleTypeDef hi2c1;
void si53531_initialize(void);
void si53531_set_frequency(uint32_t freq, uint8_t synth);
void si5351_off(void);
void si5351_on(void);

10
codice/Core/Inc/tx.h
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@@ -4,12 +4,15 @@
#include <stdint.h> #include <stdint.h>
#include <arm_math.h> #include <arm_math.h>
#define CW_TONE_INCREMENT 0.15
#define CW_TONE_VOLUME 2
#define TX_TYPE_NONE 0 #define TX_TYPE_NONE 0
#define TX_TYPE_DAC 1 #define TX_TYPE_DAC 1
#define TX_TYPE_PWM 2 #define TX_TYPE_PWM 2
#define TX_TYPE_SI5351 3 #define TX_TYPE_SI5351 3
// #define TX_TYPE TX_TYPE_SI5351 #define TX_TYPE TX_TYPE_SI5351
#define TX_TYPE TX_TYPE_NONE // #define TX_TYPE TX_TYPE_NONE
#define TX_AUDIO_FILTER_INTERPOLATION_FACTOR (16) #define TX_AUDIO_FILTER_INTERPOLATION_FACTOR (16)
#define TX_AUDIO_FILTER_BLOCK_SIZE (1024) #define TX_AUDIO_FILTER_BLOCK_SIZE (1024)
@@ -43,4 +46,7 @@ void ssb_modulator(q31_t *in_I, q31_t *in_Q, uint16_t size, q31_t *out, q31_t nc
void dc_modulator(q31_t *in, uint16_t size, q31_t *out); void dc_modulator(q31_t *in, uint16_t size, q31_t *out);
void am_modulator(q31_t *in_I, q31_t *in_Q, uint16_t size, q31_t *out); void am_modulator(q31_t *in_I, q31_t *in_Q, uint16_t size, q31_t *out);
uint16_t u12_sine(void);
void generate_tone(q31_t *buffer, uint16_t buffer_size);
#endif #endif

21
codice/Core/Src/bassofono.c
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@@ -37,7 +37,7 @@ uint32_t frequency;
int32_t rit; int32_t rit;
uint16_t pwm_tx_period; uint16_t pwm_tx_period;
int32_t modulation; int32_t modulation;
int32_t gain; int32_t rx_gain;
int32_t peak, oldpeak, peakset; int32_t peak, oldpeak, peakset;
int32_t volume; int32_t volume;
int32_t squelch; int32_t squelch;
@@ -79,8 +79,8 @@ q31_t tx_dac_buffer[2][TX_DAC_BUFFER_SIZE];
int32_t set_nco1_freq(int32_t freq){ int32_t set_nco1_freq(int32_t freq){
int64_t tmp_increment; int64_t tmp_increment;
if(modulation == MOD_USB) freq += (NCO2_FREQUENCY); if(modulation == MOD_USB || modulation == MOD_CWU) freq += (NCO2_FREQUENCY);
else if(modulation == MOD_LSB) freq -= (NCO2_FREQUENCY); else if(modulation == MOD_LSB || modulation == MOD_CWL) freq -= (NCO2_FREQUENCY);
tmp_increment = ((int64_t)freq * 0x100000000LL)/RX_ADC_SAMPLE_RATE; tmp_increment = ((int64_t)freq * 0x100000000LL)/RX_ADC_SAMPLE_RATE;
return (int32_t)tmp_increment; return (int32_t)tmp_increment;
} }
@@ -130,14 +130,15 @@ void set_frequency(void){
pwm_tx_period = get_pwm_period(frequency); pwm_tx_period = get_pwm_period(frequency);
} }
else if(TX_TYPE == TX_TYPE_SI5351){ else if(TX_TYPE == TX_TYPE_SI5351){
si53531_set_frequency(frequency); si53531_set_frequency(frequency, 0);
} }
} }
/*
void set_filter(void){ void set_filter(void){
audio_filter_generate_coeffs(audio_filter_coeffs, audio_filter_freq, audio_filter_bw, audio_filter_beta); audio_filter_generate_coeffs(audio_filter_coeffs, audio_filter_freq, audio_filter_bw, audio_filter_beta);
} }
*/
void set_modulation(void){ void set_modulation(void){
st2_filter_init(); st2_filter_init();
// cambia offset // cambia offset
@@ -162,11 +163,11 @@ uint8_t get_changed(uint8_t state){
} }
void state_set_default(void){ void state_set_default(void){
modulation = MOD_USB; modulation = MOD_CWU;
frequency = 128000; frequency = 128000;
rit = 0; rit = 0;
set_frequency(); set_frequency();
gain = 2; rx_gain = 2;
volume = 8; volume = 8;
audio_filter_freq = RX_AUDIO_FILTER_FREQ_DEF; audio_filter_freq = RX_AUDIO_FILTER_FREQ_DEF;
audio_filter_bw = RX_AUDIO_FILTER_BW_DEF; audio_filter_bw = RX_AUDIO_FILTER_BW_DEF;
@@ -184,7 +185,7 @@ void diag(void){
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"1st out sample rate: %d\n", ST1_OUT_SAMPLE_RATE); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"1st out sample rate: %d\n", ST1_OUT_SAMPLE_RATE);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"2st buffer size: %d\n2st decimation factor: %d\n", ST2_BUFFER_SIZE, ST2_DECIMATION_FACTOR * 2); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"2st buffer size: %d\n2st decimation factor: %d\n", ST2_BUFFER_SIZE, ST2_DECIMATION_FACTOR * 2);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"2st out sample rate: %d\n", ST2_OUT_SAMPLE_RATE); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"2st out sample rate: %d\n", ST2_OUT_SAMPLE_RATE);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"in gain %d\n", gain); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"in rx_gain %d\n", rx_gain);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"af gain %d\n", volume); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"af gain %d\n", volume);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"rx nco1 inc %d\n", rx_nco1_increment); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"rx nco1 inc %d\n", rx_nco1_increment);
uart_tx_buf_in_idx += sprintf(uart_tx_buf,"nco2 inc %d\n", NCO2_INCREMENT); uart_tx_buf_in_idx += sprintf(uart_tx_buf,"nco2 inc %d\n", NCO2_INCREMENT);
@@ -216,3 +217,7 @@ uint8_t measure_log_abs_mean(q31_t *samples, uint16_t size){
} }
return log_sig; return log_sig;
} }
void set_LO_freq(uint32_t freq){
}

31
codice/Core/Src/interface.c
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@@ -32,18 +32,18 @@ struct menu_item {
// name, type, size,row,col,step, min, max, wrap suffix *varptr, set_function_ptr print_function_ptr // name, type, size,row,col,step, min, max, wrap suffix *varptr, set_function_ptr print_function_ptr
struct menu_item items[] = { struct menu_item items[] = {
{MENU_PAGE_DEFAULT, " Frequency", TYP_INT, 9, 1, 0, 100, 1000, 175000, WRAP, "", " Hz", &frequency, &set_frequency, &print_frequency}, {MENU_PAGE_DEFAULT, " Frequency", TYP_INT, 9, 1, 0, 100, 1000, 1750000,WRAP, "", " Hz", &frequency, &set_frequency, &print_frequency},
// {MENU_PAGE_DEFAULT, " Rit ", TYP_INT, 4, 2, 0, 10, 0, 9999, SAT, "", "", &rit, &set_frequency, &print_frequency}, // {MENU_PAGE_DEFAULT, " Rit ", TYP_INT, 4, 2, 0, 10, 0, 9999, SAT, "", "", &rit, &set_frequency, &print_frequency},
{MENU_PAGE_DEFAULT, " Volume ", TYP_INT, 5, 2, 0, 1, 0, 32, SAT, "", "|", &volume, &set_dummy, &print_bar}, {MENU_PAGE_DEFAULT, " Volume ", TYP_INT, 5, 2, 0, 1, 0, 32, SAT, "", "|", &volume, &set_dummy, &print_bar},
{MENU_PAGE_DEFAULT, " Gain ", TYP_INT, 1, 2, 7, 1, 1, 6, SAT, "", "x", &gain, &set_gain, &print_integer}, {MENU_PAGE_DEFAULT, " Gain ", TYP_INT, 1, 2, 7, 1, 1, 6, SAT, "", "x", &rx_gain, &set_rx_gain, &print_integer},
{MENU_PAGE_DEFAULT, " Modulation", TYP_INT, 3, 2, 10, 1, 0, 3, WRAP, "", "", &modulation, &set_modulation,&print_modulation}, {MENU_PAGE_DEFAULT, " Modulation", TYP_INT, 3, 2, 10, 1, 0, 6, WRAP, "", "", &modulation, &set_modulation,&print_modulation},
// {MENU_PAGE_DEFAULT, " Squelch ", TYP_INT, 2, 3, 10, 1, 0, 32, SAT, "", "", &squelch, &set_dummy, &print_integer}, // {MENU_PAGE_DEFAULT, " Squelch ", TYP_INT, 2, 3, 10, 1, 0, 32, SAT, "", "", &squelch, &set_dummy, &print_integer},
{MENU_PAGE_AUDIO, " Filter CF ", TYP_INT, 4, 1, 0, 50, 50, 3500, SAT, "", " Hz", &audio_filter_freq, &set_filter, &print_integer}, {MENU_PAGE_AUDIO, " Filter CF ", TYP_INT, 4, 1, 0, 50, 50, 3500, SAT, "", " Hz", &audio_filter_freq, &set_rx_audio_filter, &print_integer},
{MENU_PAGE_AUDIO, " Filter BW ", TYP_INT, 4, 2, 0, 50, 50, 2500, SAT, "", " Hz", &audio_filter_bw, &set_filter, &print_integer}, {MENU_PAGE_AUDIO, " Filter BW ", TYP_INT, 4, 2, 0, 50, 50, 2500, SAT, "", " Hz", &audio_filter_bw, &set_rx_audio_filter, &print_integer},
{MENU_PAGE_AUDIO, " Filter Q ", TYP_INT, 2, 3, 0, 1, 1, 32, SAT, "", " Q", &audio_filter_beta, &set_filter, &print_integer}, {MENU_PAGE_AUDIO, " Filter Q ", TYP_INT, 2, 3, 0, 1, 1, 32, SAT, "", " Q", &audio_filter_beta, &set_rx_audio_filter, &print_integer},
{MENU_PAGE_ALL, " Signal ", TYP_NED, 13, 4, 0, 0, 0, 0, SAT, "S", "", &s_meter, &set_dummy, &print_bar}, {MENU_PAGE_ALL, " Signal ", TYP_NED, 13, 4, 0, 0, 0, 0, SAT, "S", "", &s_meter, &set_dummy, &print_bar},
{MENU_PAGE_ALL, " TX tab ", TYP_NED, 3, 5, 0, 0, 0, 0, SAT, "", "", "PTT", &set_dummy, &print_string}, {MENU_PAGE_ALL, " TX tab ", TYP_NED, 3, 5, 0, 0, 0, 0, SAT, "", "", "PTT", &set_dummy, &print_string},
{MENU_PAGE_ALL, " Tabs ", TYP_NED, 3, 5, 4, 0, 0, 0, SAT, "", "", "SET", &set_dummy, &print_string}, {MENU_PAGE_ALL, " Tabs ", TYP_NED, 3, 5, 4, 0, 0, 0, SAT, "", "", "SET", &set_dummy, &print_string},
{MENU_PAGE_ALL, " Tabs ", TYP_NED, 2, 5, 9, 0, 0, 0, SAT, "", "", "BL", &set_dummy, &print_string}, {MENU_PAGE_ALL, " Tabs ", TYP_NED, 2, 5, 9, 0, 0, 0, SAT, "", "", "BL", &set_dummy, &print_string},
@@ -63,7 +63,10 @@ char modulation_list[][4] = {
[MOD_DC] = "DC", [MOD_DC] = "DC",
[MOD_LSB] = "LSB", [MOD_LSB] = "LSB",
[MOD_USB] = "USB", [MOD_USB] = "USB",
[MOD_AM] = "AM" [MOD_CWL] = "CWL",
[MOD_CWU] = "CWU",
[MOD_AM] = "AM",
[MOD_FM] = "FM"
}; };
uint8_t modulation_list_count = sizeof(modulation_list)/sizeof(modulation_list[0]); uint8_t modulation_list_count = sizeof(modulation_list)/sizeof(modulation_list[0]);
@@ -334,12 +337,12 @@ void tab_down(uint8_t tab){
void display_init(void){ void display_init(void){
// https://git.lattuga.net/asdrea/tosta // https://git.lattuga.net/asdrea/tosta
// caratteri print_bar // caratteri print_bar
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[128,255,0,0,0,0,0c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[128,127,0,0,0,0,0c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[129,255,255,0,0,0,0c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[129,127,127,0,0,0,0c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[130,255,255,255,0,0,0c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[130,127,127,127,0,0,0c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[131,255,255,255,255,0,0c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[131,127,127,127,127,0,0c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[132,255,255,255,255,255,0c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[132,127,127,127,127,127,0c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[133,255,255,255,255,255,255c"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[133,127,127,127,127,127,127c");
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[%ds",DISPLAY_STANDBY_TIMER); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[%ds",DISPLAY_STANDBY_TIMER);
uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[150,100q"); uart_tx_buf_in_idx += sprintf(uart_tx_buf+uart_tx_buf_in_idx,"\x1B[150,100q");

34
codice/Core/Src/main.c
View File

@@ -235,6 +235,12 @@ void start_transmit(void){
} else if(TX_TYPE == TX_TYPE_SI5351){ } else if(TX_TYPE == TX_TYPE_SI5351){
si5351_on(); si5351_on();
} }
if(modulation == MOD_CWL || modulation == MOD_CWU){
// TONO su DAC
HAL_TIM_Base_Start(&htim6);
HAL_DAC_Start(&hdac1,DAC_CHANNEL_1);
HAL_DAC_Start_DMA(&hdac1, DAC_CHANNEL_1, lf_buffer, (LF_BUFFER_SIZE * 2), DAC_ALIGN_12B_R);
}
} }
void stop_transmit(void){ void stop_transmit(void){
@@ -252,6 +258,12 @@ void stop_transmit(void){
} else if(TX_TYPE == TX_TYPE_SI5351){ } else if(TX_TYPE == TX_TYPE_SI5351){
si5351_off(); si5351_off();
} }
if(modulation == MOD_CWL || modulation == MOD_CWU){
// DAC
HAL_TIM_Base_Stop(&htim6);
HAL_DAC_Stop(&hdac1,DAC_CHANNEL_1);
HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);
}
} }
void start_receive(void){ void start_receive(void){
@@ -276,9 +288,9 @@ void stop_receive(void){
HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1); HAL_DAC_Stop_DMA(&hdac1, DAC_CHANNEL_1);
} }
void set_gain(void){ void set_rx_gain(void){
HAL_OPAMP_Stop(&hopamp1); HAL_OPAMP_Stop(&hopamp1);
switch (gain){ switch (rx_gain){
case 1: case 1:
hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1; hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1;
break; break;
@@ -301,9 +313,8 @@ void set_gain(void){
hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1; hopamp1.Init.PgaGain = OPAMP_PGA_GAIN_2_OR_MINUS_1;
break; break;
} }
HAL_OPAMP_Init(&hopamp1); HAL_OPAMP_Init(&hopamp1);
HAL_OPAMP_Start(&hopamp1); HAL_OPAMP_Start(&hopamp1);
} }
@@ -367,7 +378,7 @@ int main(void)
audio_filter_init(); audio_filter_init();
// diag(); // diag();
HAL_OPAMP_Start(&hopamp1); HAL_OPAMP_Start(&hopamp1);
set_gain(); set_rx_gain();
HAL_TIM_Base_Start_IT(&htim7); HAL_TIM_Base_Start_IT(&htim7);
HAL_UART_Receive_IT(&huart1, uart_rx_buf, 1); HAL_UART_Receive_IT(&huart1, uart_rx_buf, 1);
// HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1); // HAL_UART_Receive_IT(&huart2, uart_rx_buf, 1);
@@ -377,7 +388,6 @@ int main(void)
si53531_initialize(); si53531_initialize();
} }
start_receive(); start_receive();
/* USER CODE END 2 */ /* USER CODE END 2 */
@@ -387,7 +397,7 @@ int main(void)
/* USER CODE END WHILE */ /* USER CODE END WHILE */
/* USER CODE BEGIN 3 */ /* USER CODE BEGIN 3 */
HAL_GPIO_TogglePin(GPIO1_GPIO_Port, GPIO1_Pin); // HAL_GPIO_TogglePin(GPIO1_GPIO_Port, GPIO1_Pin);
// receive = transmit = 0; // receive = transmit = 0;
if(receive){ if(receive){
if(rx_adc_buffer_ready){ if(rx_adc_buffer_ready){
@@ -399,7 +409,7 @@ int main(void)
if(half_rx_dac_buffer_empty){ if(half_rx_dac_buffer_empty){
// HAL_GPIO_WritePin(GPIO1_GPIO_Port, GPIO1_Pin, SET); // HAL_GPIO_WritePin(GPIO1_GPIO_Port, GPIO1_Pin, SET);
if (modulation == MOD_DC) dc_demodulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer); if (modulation == MOD_DC) dc_demodulator(if_I, LF_BUFFER_SIZE, prefilter_lf_buffer);
else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer, NCO2_INCREMENT); else if(modulation == MOD_LSB || modulation == MOD_USB || modulation == MOD_CWL || modulation == MOD_CWU) ssb_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer, NCO2_INCREMENT);
else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer); else if (modulation == MOD_AM) am_demodulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer[lf_buffer_toggle], RX_AUDIO_FILTER_BLOCK_SIZE); arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer[lf_buffer_toggle], RX_AUDIO_FILTER_BLOCK_SIZE);
// arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer_test[lf_buffer_toggle], AUDIO_FILTER_BLOCK_SIZE); // arm_fir_q31(&audio_filter_struct, prefilter_lf_buffer, lf_buffer_test[lf_buffer_toggle], AUDIO_FILTER_BLOCK_SIZE);
@@ -419,6 +429,12 @@ int main(void)
else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_modulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer, NCO2_INCREMENT); else if(modulation == MOD_LSB || modulation == MOD_USB) ssb_modulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer, NCO2_INCREMENT);
else if (modulation == MOD_AM) am_modulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer); else if (modulation == MOD_AM) am_modulator(if_I, if_Q, LF_BUFFER_SIZE, prefilter_lf_buffer);
} }
if(half_rx_dac_buffer_empty && (modulation == MOD_CWL || modulation == MOD_CWU)){
generate_tone(lf_buffer[lf_buffer_toggle], LF_BUFFER_SIZE);
half_rx_dac_buffer_empty = 0;
}
} }
if(tick){ if(tick){
// consuma coda comandi // consuma coda comandi

8
codice/Core/Src/rx.c
View File

@@ -234,10 +234,10 @@ inline q31_t hb_fir15(q31_t * samples_ringbuf, uint8_t sample_index, uint8_t buf
} }
void st2_filter_init(void){ void st2_filter_init(void){
if((modulation == MOD_LSB) || (modulation == MOD_USB)){ if((modulation == MOD_LSB) || (modulation == MOD_USB || modulation == MOD_CWL || modulation == MOD_CWU)){
arm_fir_decimate_init_q31(&st2_filter_I_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_filter_taps[0], &st2_filter_I_state[0], ST2_FILTER_BLOCK_SIZE); arm_fir_decimate_init_q31(&st2_filter_I_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_filter_taps[0], &st2_filter_I_state[0], ST2_FILTER_BLOCK_SIZE);
arm_fir_decimate_init_q31(&st2_filter_Q_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_filter_taps[0], &st2_filter_Q_state[0], ST2_FILTER_BLOCK_SIZE); arm_fir_decimate_init_q31(&st2_filter_Q_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_filter_taps[0], &st2_filter_Q_state[0], ST2_FILTER_BLOCK_SIZE);
} else if ((modulation == MOD_DC) || (modulation == MOD_AM)){ } else if ((modulation == MOD_DC) || (modulation == MOD_AM || modulation == MOD_FM)){
arm_fir_decimate_init_q31(&st2_filter_I_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_wide_taps[0], &st2_filter_I_state[0], ST2_FILTER_BLOCK_SIZE); arm_fir_decimate_init_q31(&st2_filter_I_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_wide_taps[0], &st2_filter_I_state[0], ST2_FILTER_BLOCK_SIZE);
arm_fir_decimate_init_q31(&st2_filter_Q_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_wide_taps[0], &st2_filter_Q_state[0], ST2_FILTER_BLOCK_SIZE); arm_fir_decimate_init_q31(&st2_filter_Q_struct, ST2_FILTER_TAP_NUM, ST2_DECIMATION_FACTOR, &st2_wide_taps[0], &st2_filter_Q_state[0], ST2_FILTER_BLOCK_SIZE);
} }
@@ -260,3 +260,7 @@ void audio_filter_generate_coeffs(int32_t *Coeffs, uint32_t freq, uint32_t bw, u
Coeffs[index] = (int32_t) ( (double)(FPCoeff[index])*(double)0x7FFFFFFF ); Coeffs[index] = (int32_t) ( (double)(FPCoeff[index])*(double)0x7FFFFFFF );
} }
} }
void set_rx_audio_filter(void){
audio_filter_generate_coeffs(audio_filter_coeffs, audio_filter_freq, audio_filter_bw, audio_filter_beta);
}

14
codice/Core/Src/si5351.c
View File

@@ -144,7 +144,7 @@ void si53531_initialize(){
// si5351_write8(SI5351_OUT_ENABLE, 0xFC); // Output Enable Control. Active low // si5351_write8(SI5351_OUT_ENABLE, 0xFC); // Output Enable Control. Active low
} }
void si53531_set_frequency(uint32_t freq){ void si53531_set_frequency(uint32_t freq, uint8_t synth){
uint8_t regs[16]; uint8_t regs[16];
CalcRegisters(freq, regs); CalcRegisters(freq, regs);
@@ -153,11 +153,13 @@ void si53531_set_frequency(uint32_t freq){
si5351_write8(SI5351_PLLA + i, regs[i]); si5351_write8(SI5351_PLLA + i, regs[i]);
// Load Output Multisynth0 with d (e and f already set during init. and never changed) // Load Output Multisynth0 with d (e and f already set during init. and never changed)
for (int i = 10; i < 13; i++) if(synth = 0){
si5351_write8(34 + i, regs[i]); for (int i = 10; i < 13; i++)
si5351_write8(34 + i, regs[i]);
for (int i = 10; i < 13; i++) } else if(synth = 1){
si5351_write8(42 + i, regs[i]); for (int i = 10; i < 13; i++)
si5351_write8(42 + i, regs[i]);
}
// Reset PLLA // Reset PLLA
// delayMicroseconds(500); // Allow registers to settle before resetting the PLL // delayMicroseconds(500); // Allow registers to settle before resetting the PLL

15
codice/Core/Src/tx.c
View File

@@ -87,3 +87,18 @@ void tx_audio_filter_init(void){
arm_fir_interpolate_init_q15 (&tx_audio_filter_I_struct, TX_AUDIO_FILTER_INTERPOLATION_FACTOR, TX_AUDIO_FILTER_TAP_NUM, tx_audio_filter_coeffs, &tx_audio_filter_I_state[0], TX_AUDIO_FILTER_BLOCK_SIZE); arm_fir_interpolate_init_q15 (&tx_audio_filter_I_struct, TX_AUDIO_FILTER_INTERPOLATION_FACTOR, TX_AUDIO_FILTER_TAP_NUM, tx_audio_filter_coeffs, &tx_audio_filter_I_state[0], TX_AUDIO_FILTER_BLOCK_SIZE);
arm_fir_interpolate_init_q15 (&tx_audio_filter_Q_struct, TX_AUDIO_FILTER_INTERPOLATION_FACTOR, TX_AUDIO_FILTER_TAP_NUM, tx_audio_filter_coeffs, &tx_audio_filter_Q_state[0], TX_AUDIO_FILTER_BLOCK_SIZE); arm_fir_interpolate_init_q15 (&tx_audio_filter_Q_struct, TX_AUDIO_FILTER_INTERPOLATION_FACTOR, TX_AUDIO_FILTER_TAP_NUM, tx_audio_filter_coeffs, &tx_audio_filter_Q_state[0], TX_AUDIO_FILTER_BLOCK_SIZE);
} }
uint16_t u12_sine(void){
static double angle;
angle += CW_TONE_INCREMENT;
if(angle >= 6.28) angle = 0;
return (uint16_t)((sin(angle) * CW_TONE_VOLUME) + 0x7ff);
}
void generate_tone(q31_t *buffer, uint16_t buffer_size){
uint16_t i;
while(i < buffer_size){
buffer[i] = u12_sine();
i++;
}
}

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -912,6 +911,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1189,6 +1192,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -13125,4 +13137,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -944,6 +943,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1223,6 +1226,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -13357,4 +13369,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

230
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -125,7 +124,6 @@ typedef enum
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */
@@ -141,6 +139,10 @@ typedef enum
COMP4_IRQn = 65, /*!< COMP4 */ COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */ CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */
I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
@@ -967,6 +969,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1002,7 +1008,6 @@ typedef struct
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
@@ -1052,6 +1057,7 @@ typedef struct
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
@@ -1144,7 +1150,6 @@ typedef struct
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE)
@@ -1192,6 +1197,7 @@ typedef struct
#define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
@@ -1277,6 +1283,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -2928,9 +2943,6 @@ typedef struct
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */ #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */ #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
@@ -2980,6 +2992,9 @@ typedef struct
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@@ -8101,9 +8116,6 @@ typedef struct
#define RCC_APB1RSTR1_TIM4RST_Pos (2U) #define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */ #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U) #define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */ #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
@@ -8192,6 +8204,9 @@ typedef struct
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
@@ -8272,9 +8287,6 @@ typedef struct
#define RCC_APB1ENR1_TIM4EN_Pos (2U) #define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */ #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM5EN_Pos (3U)
#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U) #define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */ #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
@@ -8369,6 +8381,9 @@ typedef struct
#define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
@@ -8458,9 +8473,6 @@ typedef struct
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U) #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */ #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */ #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
@@ -8555,6 +8567,9 @@ typedef struct
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U) #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */ #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
@@ -13396,122 +13411,127 @@ typedef struct
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/ /****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
((INSTANCE) == TIM5))
/****************** TIM Instances : supporting the break function *************/ /****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/ /************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/ /****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/ /************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/ /************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/ /************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/ /************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/ /****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/ /****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/ /******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/ /******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
@@ -13541,12 +13561,6 @@ typedef struct
((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \ ((CHANNEL) == TIM_CHANNEL_4))) \
|| \ || \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \ (((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \ (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_2) || \
@@ -13563,7 +13577,15 @@ typedef struct
(((CHANNEL) == TIM_CHANNEL_1))) \ (((CHANNEL) == TIM_CHANNEL_1))) \
|| \ || \
(((INSTANCE) == TIM17) && \ (((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1)))) (((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/ /****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
@@ -13586,135 +13608,143 @@ typedef struct
((CHANNEL) == TIM_CHANNEL_1)) \ ((CHANNEL) == TIM_CHANNEL_1)) \
|| \ || \
(((INSTANCE) == TIM17) && \ (((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1))) ((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/ /****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/ /****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/ /****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/ /****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/ /****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/ /**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/ /************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/ /****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
@@ -13723,51 +13753,54 @@ typedef struct
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/ /****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/ /****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/ /******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)) ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/ /******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/ /****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8)) ((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/ /****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \ #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
@@ -13907,4 +13940,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -1009,6 +1008,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1358,6 +1361,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -14535,4 +14547,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

264
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -1492,6 +1491,15 @@ typedef struct {
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -8047,6 +8055,8 @@ typedef struct {
#define HRTIM_RSTR_EXTEVNT10_Pos (18U) #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */ #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */ #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
/* Slave Timer A reset enable bits upon other slave timers events */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U) #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */ #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */ #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
@@ -8056,6 +8066,7 @@ typedef struct {
#define HRTIM_RSTR_TIMBCMP4_Pos (21U) #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */ #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */ #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTR_TIMCCMP1_Pos (22U) #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */ #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */ #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
@@ -8065,6 +8076,7 @@ typedef struct {
#define HRTIM_RSTR_TIMCCMP4_Pos (24U) #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */ #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */ #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTR_TIMDCMP1_Pos (25U) #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */ #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */ #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
@@ -8074,6 +8086,7 @@ typedef struct {
#define HRTIM_RSTR_TIMDCMP4_Pos (27U) #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */ #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */ #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTR_TIMECMP1_Pos (28U) #define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */ #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */ #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
@@ -8083,10 +8096,236 @@ typedef struct {
#define HRTIM_RSTR_TIMECMP4_Pos (30U) #define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */ #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */ #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTR_TIMFCMP2_Pos (31U) #define HRTIM_RSTR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */ #define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */ #define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer B reset enable bits upon other slave timers events */
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer C reset enable bits upon other slave timers events */
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer D reset enable bits upon other slave timers events */
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer E reset enable bits upon other slave timers events */
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer F reset enable bits upon other slave timers events */
#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Chopper register *************************/ /**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U) #define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */ #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
@@ -17889,4 +18128,3 @@ typedef struct {
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g483xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -1041,6 +1040,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1392,6 +1395,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -14767,4 +14779,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

264
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g484xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -1526,6 +1525,15 @@ typedef struct {
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -8268,6 +8276,8 @@ typedef struct {
#define HRTIM_RSTR_EXTEVNT10_Pos (18U) #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */ #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */ #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
/* Slave Timer A reset enable bits upon other slave timers events */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U) #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */ #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */ #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
@@ -8277,6 +8287,7 @@ typedef struct {
#define HRTIM_RSTR_TIMBCMP4_Pos (21U) #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */ #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */ #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTR_TIMCCMP1_Pos (22U) #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */ #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */ #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
@@ -8286,6 +8297,7 @@ typedef struct {
#define HRTIM_RSTR_TIMCCMP4_Pos (24U) #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */ #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */ #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTR_TIMDCMP1_Pos (25U) #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */ #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */ #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
@@ -8295,6 +8307,7 @@ typedef struct {
#define HRTIM_RSTR_TIMDCMP4_Pos (27U) #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */ #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */ #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTR_TIMECMP1_Pos (28U) #define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */ #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */ #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
@@ -8304,10 +8317,236 @@ typedef struct {
#define HRTIM_RSTR_TIMECMP4_Pos (30U) #define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */ #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */ #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTR_TIMFCMP2_Pos (31U) #define HRTIM_RSTR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */ #define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */ #define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer B reset enable bits upon other slave timers events */
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer C reset enable bits upon other slave timers events */
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer D reset enable bits upon other slave timers events */
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer E reset enable bits upon other slave timers events */
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer F reset enable bits upon other slave timers events */
#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Chopper register *************************/ /**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U) #define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */ #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
@@ -18121,4 +18360,3 @@ typedef struct {
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -961,6 +960,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1269,6 +1272,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -13699,4 +13711,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -993,6 +992,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1303,6 +1306,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -13931,4 +13943,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

71
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h
View File

@@ -16,13 +16,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -85,11 +84,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V1.2.1 * @brief CMSIS Device version number V1.2.2
*/ */
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ #define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ #define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\ |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
@@ -178,6 +177,61 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/** /**
* @} * @}
@@ -203,4 +257,3 @@ typedef enum
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

37
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32gbk1cb.h
View File

@@ -7,18 +7,17 @@
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition * - Peripheral's registers declarations and bits definition
* - Macros to access peripheral’s registers hardware * - Macros to access peripheral's registers hardware
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -45,11 +44,11 @@
/** /**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/ */
#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ #define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ #define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ #define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_PRESENT 1U /*!< FPU present */
/** /**
* @} * @}
@@ -902,6 +901,10 @@ typedef struct
} UCPD_TypeDef; } UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map /** @addtogroup Peripheral_memory_map
* @{ * @{
*/ */
@@ -1175,6 +1178,15 @@ typedef struct
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@@ -13063,4 +13075,3 @@ typedef struct
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -103,4 +102,3 @@ extern void SystemCoreClockUpdate(void);
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
codice/Drivers/CMSIS/Device/ST/STM32G4xx/LICENSE.txt Normal file
View File

@@ -0,0 +1,6 @@
This software component is provided to you as part of a software package and
applicable license terms are in the Package_license file. If you received this
software component outside of a package or without applicable license terms,
the terms of the Apache-2.0 license shall apply.
You may obtain a copy of the Apache-2.0 at:
https://opensource.org/licenses/Apache-2.0

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g431xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -422,4 +421,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g441xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -424,4 +423,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g471xx.s
View File

@@ -17,14 +17,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -441,4 +440,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g473xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -468,4 +467,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g474xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -484,4 +483,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g483xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -470,4 +469,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g484xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -486,4 +485,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g491xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -448,4 +447,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32g4a1xx.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -450,4 +449,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/arm/startup_stm32gbk1cb.s
View File

@@ -16,14 +16,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>> ;* <<< Use Configuration Wizard in Context Menu >>>
; ;
@@ -420,4 +419,3 @@ __user_initial_stackheap
END END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -496,4 +495,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -499,4 +498,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -523,4 +522,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -565,4 +564,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -589,4 +588,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -568,4 +567,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -591,4 +590,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g491xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -535,4 +534,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g4a1xx.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -538,4 +537,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s
View File

@@ -15,13 +15,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -489,4 +488,3 @@ g_pfnVectors:
.weak FMAC_IRQHandler .weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler .thumb_set FMAC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g431xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; The modules in this file are included in the libraries, and may be replaced ; The modules in this file are included in the libraries, and may be replaced
@@ -584,4 +583,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g441xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -590,4 +589,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g471xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -630,4 +629,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g473xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -700,4 +699,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g474xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -740,4 +739,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g483xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -705,4 +704,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g484xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -745,4 +744,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g491xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -650,4 +649,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32g4a1xx.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; ;
@@ -655,4 +654,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/iar/startup_stm32gbk1cb.s
View File

@@ -15,14 +15,13 @@
;******************************************************************************** ;********************************************************************************
;* @attention ;* @attention
;* ;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. ;* Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2> ;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;* ;*
;* This software is licensed under terms that can be found in the LICENSE file
;* in the root directory of this software component.
;* If no LICENSE file comes with this software, it is provided AS-IS.
;
;******************************************************************************* ;*******************************************************************************
; ;
; The modules in this file are included in the libraries, and may be replaced ; The modules in this file are included in the libraries, and may be replaced
@@ -579,4 +578,3 @@ FMAC_IRQHandler
B FMAC_IRQHandler B FMAC_IRQHandler
END END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c
View File

@@ -53,13 +53,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -283,5 +282,4 @@ void SystemCoreClockUpdate(void)
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

198
codice/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

@@ -7,13 +7,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2021 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -38,6 +37,14 @@ extern "C" {
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@@ -206,6 +213,20 @@ extern "C" {
* @{ * @{
*/ */
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
#if defined(STM32U5)
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/** /**
* @} * @}
*/ */
@@ -235,11 +256,18 @@ extern "C" {
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7) #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif #endif
#if defined(STM32U5)
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -382,7 +410,6 @@ extern "C" {
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
* @} * @}
*/ */
@@ -470,15 +497,24 @@ extern "C" {
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif #endif
#if defined(STM32H7) #if defined(STM32H7)
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */ #endif /* STM32H7 */
#if defined(STM32U5)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U5 */
/** /**
* @} * @}
@@ -521,6 +557,7 @@ extern "C" {
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */ #endif /* STM32G4 */
/** /**
* @} * @}
*/ */
@@ -595,12 +632,12 @@ extern "C" {
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -616,6 +653,20 @@ extern "C" {
#endif /* STM32F0 || STM32F3 || STM32F1 */ #endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@@ -853,6 +904,31 @@ extern "C" {
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
/**
* @}
*/
/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
/**
* @}
*/
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@@ -1379,6 +1455,20 @@ extern "C" {
*/ */
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|| defined(STM32H7) || defined(STM32U5)
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
for compatibility with legacy code */
/**
* @}
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@@ -1397,6 +1487,29 @@ extern "C" {
* @} * @}
*/ */
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
#endif /* STM32U5 */
/**
* @}
*/
#if !defined(STM32F2)
/** @defgroup HASH_alias HASH API alias
* @{
*/
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
/**
*
* @}
*/
#endif /* STM32F2 */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
@@ -3329,6 +3442,31 @@ extern "C" {
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#endif
/** /**
* @} * @}
@@ -3346,7 +3484,7 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@@ -3403,13 +3541,22 @@ extern "C" {
* @} * @}
*/ */
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
#endif
#if defined(STM32F4) || defined(STM32F2) #if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@@ -3738,6 +3885,16 @@ extern "C" {
* @} * @}
*/ */
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32F7)
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
#endif /* STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
@@ -3752,5 +3909,4 @@ extern "C" {
#endif /* STM32_HAL_LEGACY */ #endif /* STM32_HAL_LEGACY */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h
View File

@@ -8,13 +8,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -54,4 +53,3 @@ void assert_failed(uint8_t *file, uint32_t line);
#endif /* STM32_ASSERT_H */ #endif /* STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h
View File

@@ -7,13 +7,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -623,4 +622,3 @@ void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
#endif /* STM32G4xx_HAL_H */ #endif /* STM32G4xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -2033,5 +2032,3 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma);
#endif /* STM32G4xx_HAL_ADC_H */ #endif /* STM32G4xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -1392,6 +1391,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *h
#endif #endif
#endif /* STM32G4xx_HAL_ADC_EX_H */ #endif /* STM32G4xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -90,7 +89,7 @@ typedef enum
typedef struct __COMP_HandleTypeDef typedef struct __COMP_HandleTypeDef
#else #else
typedef struct typedef struct
#endif #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
{ {
COMP_TypeDef *Instance; /*!< Register base address */ COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */ COMP_InitTypeDef Init; /*!< COMP required parameters */
@@ -294,7 +293,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
} while(0) } while(0)
#else #else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
#endif #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/** /**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
@@ -963,7 +962,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
#endif #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/** /**
* @} * @}
*/ */
@@ -1009,7 +1008,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \ :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
: COMP_EXTI_LINE_COMP4) : COMP_EXTI_LINE_COMP4)
#endif #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/** /**
* @} * @}
*/ */
@@ -1252,7 +1251,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
) )
#endif #endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
@@ -1349,5 +1348,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
#endif #endif
#endif /* STM32G4xx_HAL_COMP_H */ #endif /* STM32G4xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_conf_template.h
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@@ -8,13 +8,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -379,4 +378,3 @@ void assert_failed(uint8_t *file, uint32_t line);
#endif /* STM32G4xx_HAL_CONF_H */ #endif /* STM32G4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h
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@@ -7,13 +7,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -608,5 +607,3 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
#endif #endif
#endif /* STM32G4xx_HAL_CORDIC_H */ #endif /* STM32G4xx_HAL_CORDIC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -418,4 +417,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __STM32G4xx_HAL_CORTEX_H */ #endif /* __STM32G4xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

65
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -60,19 +59,22 @@ typedef struct
{ {
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field. In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field. 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal representation, respectively equal to 7, 8, 16 or 32. This field is written in normal,
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ is written 0x65. No need to specify it if DefaultPolynomialUse is set to
DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of Value can be either one of
@@ -87,14 +89,18 @@ typedef struct
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
into 0x22CC4488 */
} CRC_InitTypeDef; } CRC_InitTypeDef;
/** /**
@@ -112,12 +118,16 @@ typedef struct
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) (8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
must occur if InputBufferFormat is not one of the three values listed above */ error must occur if InputBufferFormat is not one of the three values listed
above */
} CRC_HandleTypeDef; } CRC_HandleTypeDef;
/** /**
* @} * @}
@@ -199,15 +209,6 @@ typedef struct
* @} * @}
*/ */
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
/** /**
* @} * @}
*/ */
@@ -339,5 +340,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
#endif #endif
#endif /* STM32G4xx_HAL_CRC_H */ #endif /* STM32G4xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -149,5 +148,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
#endif #endif
#endif /* STM32G4xx_HAL_CRC_EX_H */ #endif /* STM32G4xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

15
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -107,7 +106,7 @@ typedef enum
typedef struct __CRYP_HandleTypeDef typedef struct __CRYP_HandleTypeDef
#else #else
typedef struct typedef struct
#endif #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
{ {
AES_TypeDef *Instance; /*!< AES Register base address */ AES_TypeDef *Instance; /*!< AES Register base address */
@@ -644,5 +643,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
#endif #endif
#endif /* STM32G4xx_HAL_CRYP_H */ #endif /* STM32G4xx_HAL_CRYP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -129,5 +128,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
#endif #endif
#endif /* STM32G4xx_HAL_CRYP_EX_H */ #endif /* STM32G4xx_HAL_CRYP_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

32
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -79,19 +78,19 @@ typedef struct
__IO uint32_t ErrorCode; /*!< DAC Error code */ __IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef; } DAC_HandleTypeDef;
@@ -613,4 +612,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
#endif /* STM32G4xx_HAL_DAC_H */ #endif /* STM32G4xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -344,4 +343,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
#endif /* STM32G4xx_HAL_DAC_EX_H */ #endif /* STM32G4xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h
View File

@@ -7,13 +7,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -208,4 +207,3 @@ typedef enum
#endif /* ___STM32G4xx_HAL_DEF */ #endif /* ___STM32G4xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -851,4 +850,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#endif /* __STM32G4xx_HAL_DMA_H */ #endif /* __STM32G4xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -263,4 +262,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
#endif /* __STM32G4xx_HAL_DMA_EX_H */ #endif /* __STM32G4xx_HAL_DMA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -314,4 +313,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
#endif /* STM32G4xx_HAL_EXTI_H */ #endif /* STM32G4xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

40
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -1268,14 +1267,6 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/** @defgroup FDCAN_Private_Types FDCAN Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/** @defgroup FDCAN_Private_Variables FDCAN Private Variables /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
* @{ * @{
@@ -1330,8 +1321,8 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
((MODE) == FDCAN_TX_QUEUE_OPERATION)) ((MODE) == FDCAN_TX_QUEUE_OPERATION))
#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
@@ -1420,22 +1411,8 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
*/ */
/* Private functions prototypes ----------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/
/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
* @{
*/
/**
* @}
*/
/** /**
* @} * @}
*/ */
@@ -1450,6 +1427,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
#endif #endif
#endif /* STM32G4xx_HAL_FDCAN_H */ #endif /* STM32G4xx_HAL_FDCAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

15
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2> * Copyright (c) 2019 STMicroelectronics.
* * All rights reserved.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* *
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
****************************************************************************** ******************************************************************************
*/ */
@@ -880,7 +879,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \ #define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U)) (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
#define FLASH_BANK_SIZE (FLASH_SIZE) #define FLASH_BANK_SIZE (FLASH_SIZE)
#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : 64U) #define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \
((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
#endif #endif
#define FLASH_PAGE_SIZE 0x800U /* 2 KB */ #define FLASH_PAGE_SIZE 0x800U /* 2 KB */
@@ -1015,4 +1015,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#endif /* STM32G4xx_HAL_FLASH_H */ #endif /* STM32G4xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2> * Copyright (c) 2019 STMicroelectronics.
* * All rights reserved.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* *
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
****************************************************************************** ******************************************************************************
*/ */
@@ -88,4 +87,3 @@ void FLASH_FlushCaches(void);
#endif /* STM32G4xx_HAL_FLASH_EX_H */ #endif /* STM32G4xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2> * Copyright (c) 2019 STMicroelectronics.
* * All rights reserved.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* *
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
****************************************************************************** ******************************************************************************
*/ */
@@ -73,4 +72,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
#endif /* STM32G4xx_FLASH_RAMFUNC_H */ #endif /* STM32G4xx_FLASH_RAMFUNC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -689,5 +688,3 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
#endif #endif
#endif /* STM32G4xx_HAL_FMAC_H */ #endif /* STM32G4xx_HAL_FMAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

75
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -107,26 +106,28 @@ typedef enum
/** @defgroup GPIO_mode GPIO mode /** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode * @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ * Elements values convention: 0x00WX00YZ
* - X : GPIO mode or EXTI Mode * - W : EXTI trigger detection on 3 bits
* - y : External IT or Event trigger detection * - X : EXTI mode (IT or Event) on 2 bits
* - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Y : Output type (Push Pull or Open Drain) * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{ * @{
*/ */
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
@@ -208,6 +209,31 @@ typedef enum
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0U
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4U
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16U
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20U
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros /** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{ * @{
*/ */
@@ -298,4 +324,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
#endif /* STM32G4xx_HAL_GPIO_H */ #endif /* STM32G4xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -339,4 +338,3 @@ extern "C" {
#endif /* STM32G4xx_HAL_GPIO_EX_H */ #endif /* STM32G4xx_HAL_GPIO_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -1290,7 +1289,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{ * @{
* @brief Constants defining the events that can be selected to configure the * @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output * reset crossbar of a timer output
*/ */
#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
@@ -1793,10 +1792,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
* @brief Constants defining the source and event to be sent on the * @brief Constants defining the source and event to be sent on the
* synchronization outputs * synchronization outputs
*/ */
#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */ #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/ #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */ #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */ #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/** /**
* @} * @}
*/ */
@@ -5140,5 +5139,3 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * h
#endif #endif
#endif /* STM32G4xx_HAL_HRTIM_H */ #endif /* STM32G4xx_HAL_HRTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

134
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -48,29 +47,30 @@ extern "C" {
typedef struct typedef struct
{ {
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization This parameter calculated by referring to I2C initialization section
section in Reference manual */ in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address. uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */ This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */ This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */ This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef; } I2C_InitTypeDef;
@@ -200,7 +200,8 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t PreviousState; /*!< I2C communication Previous state */ __IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
@@ -217,20 +218,32 @@ typedef struct __I2C_HandleTypeDef
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ /*!< I2C Master Tx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ /*!< I2C Master Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ /*!< I2C Slave Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ /*!< I2C Slave Rx Transfer completed callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ /*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef; } I2C_HandleTypeDef;
@@ -259,8 +272,11 @@ typedef enum
/** /**
* @brief HAL I2C Callback pointer definition * @brief HAL I2C Callback pointer definition
*/ */
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** /**
@@ -440,14 +456,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
* @retval None * @retval None
*/ */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0) } while(0)
#else #else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt. /** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
@@ -542,26 +558,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
* *
* @retval None * @retval None
*/ */
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
: ((__HANDLE__)->Instance->ICR = (__FLAG__))) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral. /** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral. /** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle. * @param __HANDLE__ specifies the I2C Handle.
* @retval None * @retval None
*/ */
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) #define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/** /**
* @} * @}
*/ */
@@ -601,12 +618,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
*/ */
/* IO operation functions ****************************************************/ /* IO operation functions ****************************************************/
/******* Blocking mode: Polling */ /******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint32_t Timeout); uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout); uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
@@ -757,10 +776,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) >> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
@@ -772,10 +795,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
(uint16_t)(0xFF00U))) >> 8U))) (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ #define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/** /**
@@ -805,5 +833,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif /* STM32G4xx_HAL_I2C_H */ #endif /* STM32G4xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

22
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -66,7 +65,7 @@ extern "C" {
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ #define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else #else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ #define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif #endif /* SYSCFG_CFGR1_I2C4_FMP */
/** /**
* @} * @}
*/ */
@@ -89,7 +88,7 @@ extern "C" {
* @{ * @{
*/ */
/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
@@ -99,7 +98,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
* @} * @}
*/ */
/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{ * @{
*/ */
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
@@ -108,7 +107,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
* @} * @}
*/ */
/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{ * @{
*/ */
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
@@ -117,7 +116,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
@@ -175,5 +173,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#endif #endif
#endif /* STM32G4xx_HAL_I2C_EX_H */ #endif /* STM32G4xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2s.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -553,4 +552,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
#endif /* STM32G4xx_HAL_I2S_H */ #endif /* STM32G4xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

20
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -144,7 +143,7 @@ typedef struct
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
@@ -828,11 +827,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
@@ -891,4 +890,3 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
#endif /* STM32G4xx_HAL_IRDA_H */ #endif /* STM32G4xx_HAL_IRDA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -421,4 +420,3 @@ extern "C" {
#endif /* STM32G4xx_HAL_IRDA_EX_H */ #endif /* STM32G4xx_HAL_IRDA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -236,5 +235,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
#endif #endif
#endif /* STM32G4xx_HAL_IWDG_H */ #endif /* STM32G4xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

47
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -97,30 +96,30 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
uint32_t OutputPolarity; /*!< Specifies the Output polarity. uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */ This parameter can be a value of @ref LPTIM_Output_Polarity */
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period. values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */ This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event. or each external event.
This parameter can be a value of @ref LPTIM_Counter_Source */ This parameter can be a value of @ref LPTIM_Counter_Source */
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
This parameter can be a value of @ref LPTIM_Input1_Source */ This parameter can be a value of @ref LPTIM_Input1_Source */
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
Note: This parameter is used only for encoder feature so is used only Note: This parameter is used only for encoder feature so is used only
for LPTIM1 instance. for LPTIM1 instance.
This parameter can be a value of @ref LPTIM_Input2_Source */ This parameter can be a value of @ref LPTIM_Input2_Source */
} LPTIM_InitTypeDef; } LPTIM_InitTypeDef;
/** /**
@@ -874,5 +873,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
#endif #endif
#endif /* STM32G4xx_HAL_LPTIM_H */ #endif /* STM32G4xx_HAL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

19
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -325,8 +324,10 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
* @retval NAND Raw address value * @retval NAND Raw address value
*/ */
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ (((__ADDRESS__)->Block + \
((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) (((__ADDRESS__)->Plane) * \
((__HANDLE__)->Config.PlaneSize))) * \
((__HANDLE__)->Config.BlockSize)))
/** /**
* @brief NAND memory Column address computation. * @brief NAND memory Column address computation.
@@ -376,5 +377,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
#endif #endif
#endif /* STM32G4xx_HAL_NAND_H */ #endif /* STM32G4xx_HAL_NAND_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

13
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nor.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -325,5 +324,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
#endif #endif
#endif /* STM32G4xx_HAL_NOR_H */ #endif /* STM32G4xx_HAL_NOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

14
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -452,7 +451,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \ ((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \
((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63)) ((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63))
#define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMAL) || \ #define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMALSPEED) || \
((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) ) ((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) )
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \ #define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
@@ -572,4 +571,3 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp,
#endif /* STM32G4xx_HAL_OPAMP_H */ #endif /* STM32G4xx_HAL_OPAMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -84,4 +83,3 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA
#endif /* STM32G4xx_HAL_OPAMP_EX_H */ #endif /* STM32G4xx_HAL_OPAMP_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

71
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -193,13 +192,16 @@ typedef struct
*/ */
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE) &= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
/** /**
@@ -343,13 +345,11 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len); uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/** /**
* @} * @}
@@ -433,7 +433,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define USB_CNTRX_BLSIZE (0x1U << 15) #define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */ /* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */ /* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) #define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
@@ -448,7 +449,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wType Endpoint Type. * @param wType Endpoint Type.
* @retval None * @retval None
*/ */
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) #define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
& USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/** /**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -465,7 +468,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum, bDir * @param bEpNum, bDir
* @retval None * @retval None
*/ */
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ #define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \ do { \
if ((bDir) == 0U) \ if ((bDir) == 0U) \
{ \ { \
@@ -633,8 +636,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number. * @param bEpNum Endpoint Number.
* @retval None * @retval None
*/ */
#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) #define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) #define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/** /**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register. * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
@@ -737,8 +740,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/ */
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) #define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/** /**
* @brief sets address of the tx/rx buffer. * @brief sets address of the tx/rx buffer.
@@ -806,18 +813,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ #define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \ do { \
uint32_t wNBlocks; \ uint32_t wNBlocks; \
if ((wCount) == 0U) \ \
if ((wCount) > 62U) \
{ \ { \
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else if((wCount) <= 62U) \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \ } \
else \ else \
{ \ { \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ if ((wCount) == 0U) \
{ \
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
} \ } \
} while(0) /* PCD_SET_EP_CNT_RX_REG */ } while(0) /* PCD_SET_EP_CNT_RX_REG */
@@ -990,5 +1001,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#endif #endif
#endif /* STM32G4xx_HAL_PCD_H */ #endif /* STM32G4xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

17
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -23,7 +22,7 @@
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h" #include "stm32g4xx_hal_def.h"
@@ -83,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif /* __cplusplus */
#endif /* STM32G4xx_HAL_PCD_EX_H */ #endif /* STM32G4xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -410,4 +409,3 @@ void HAL_PWR_PVDCallback(void);
#endif /* STM32G4xx_HAL_PWR_H */ #endif /* STM32G4xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

12
codice/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h
View File

@@ -6,13 +6,12 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software is licensed under terms that can be found in the LICENSE file
* the "License"; You may not use this file except in compliance with the * in the root directory of this software component.
* License. You may obtain a copy of the License at: * If no LICENSE file comes with this software, it is provided AS-IS.
* opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
@@ -816,4 +815,3 @@ void HAL_PWREx_DisableUCPDDeadBattery(void);
#endif /* STM32G4xx_HAL_PWR_EX_H */ #endif /* STM32G4xx_HAL_PWR_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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