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437171f10f527dfbc8d3f85390f318456a4f9a75
bassofono/codice/build/SupportFunctions.lst
nzasch 36ef31c453 opamp, peak detect
2021-07-03 18:17:05 +02:00

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ARM GAS /tmp/cce2LIhc.s page 1
1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 23, 1
5 .eabi_attribute 24, 1
6 .eabi_attribute 25, 1
7 .eabi_attribute 26, 1
8 .eabi_attribute 30, 2
9 .eabi_attribute 34, 1
10 .eabi_attribute 18, 4
11 .file "SupportFunctions.c"
12 .text
13 .Ltext0:
14 .cfi_sections .debug_frame
15 .section .text.arm_quick_sort_core_f32,"ax",%progbits
16 .align 1
17 .p2align 2,,3
18 .syntax unified
19 .thumb
20 .thumb_func
21 .fpu fpv4-sp-d16
23 arm_quick_sort_core_f32:
24 .LFB168:
25 .file 1 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Title: arm_quick_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Description: Floating point quick sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** static uint32_t arm_quick_sort_partition_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 2
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* This function will be called */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** int32_t i, j, pivot_index;
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t pivot;
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t temp;
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The first element is the pivot */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pivot_index = first;
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pivot = pSrc[pivot_index];
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Initialize indices for do-while loops */
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** i = first - 1;
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** j = last + 1;
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** while(i < j)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The loop will stop as soon as the indices i and j cross each other.
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * This event will happen surely since the values of the indices are incremented and
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * decrement in the do-while loops that are executed at least once.
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * It is impossible to loop forever inside the do-while loops since the pivot is
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * always an element of the array and the conditions cannot be always true (at least
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * the i-th or the j-th element will be equal to the pivot-th element).
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * For example, in the extreme case of an ordered array the do-while loop related to i will
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * at the first iteration (because pSrc[i]=pSrc[pivot] already), and the loop related to j
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * will stop after (last-first) iterations (when j=pivot=i=first). j is returned and
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * j+1 is going to be used as pivot by other calls of the function, until j=pivot=last. */
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Move indices to the right and to the left */
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** if(dir)
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Compare left elements with pivot */
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** do
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** i++;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[i] < pivot && i<last);
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Compare right elements with pivot */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** do
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** j--;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[j] > pivot);
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** else
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Compare left elements with pivot */
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** do
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** i++;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[i] > pivot && i<last);
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Compare right elements with pivot */
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** do
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** j--;
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[j] < pivot);
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 3
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* If the indices didn't cross each other */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** if (i < j)
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* i and j are in the wrong position -> Swap */
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** temp=pSrc[i];
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pSrc[i]=pSrc[j];
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pSrc[j]=temp;
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** return j;
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** static void arm_quick_sort_core_f32(float32_t *pSrc, int32_t first, int32_t last, uint8_t dir)
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
26 .loc 1 105 0
27 .cfi_startproc
28 @ args = 0, pretend = 0, frame = 0
29 @ frame_needed = 0, uses_anonymous_args = 0
30 .LVL0:
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* If the array [first ... last] has more than one element */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** if(first<last)
31 .loc 1 107 0
32 0000 9142 cmp r1, r2
33 0002 58DA bge .L25
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* If the array [first ... last] has more than one element */
34 .loc 1 105 0
35 0004 2DE9F041 push {r4, r5, r6, r7, r8, lr}
36 .LCFI0:
37 .cfi_def_cfa_offset 24
38 .cfi_offset 4, -24
39 .cfi_offset 5, -20
40 .cfi_offset 6, -16
41 .cfi_offset 7, -12
42 .cfi_offset 8, -8
43 .cfi_offset 14, -4
44 0008 1546 mov r5, r2
45 000a 0646 mov r6, r0
46 000c 1F46 mov r7, r3
47 000e 02F10108 add r8, r2, #1
48 .LVL1:
49 .L15:
50 .LBB7:
51 .LBB8:
52 .LBB9:
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** j = last + 1;
53 .loc 1 44 0
54 0012 481E subs r0, r1, #1
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
55 .loc 1 41 0
56 0014 06EB8103 add r3, r6, r1, lsl #2
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
57 .loc 1 47 0
58 0018 4045 cmp r0, r8
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
59 .loc 1 41 0
60 001a D3ED006A vldr.32 s13, [r3]
ARM GAS /tmp/cce2LIhc.s page 4
61 .LVL2:
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
62 .loc 1 47 0
63 001e 4446 mov r4, r8
64 0020 1FDA bge .L3
65 .L14:
66 .LVL3:
67 0022 431C adds r3, r0, #1
68 0024 06EB8302 add r2, r6, r3, lsl #2
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
69 .loc 1 62 0
70 0028 47B3 cbz r7, .L12
71 002a 02E0 b .L7
72 .L29:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
73 .loc 1 68 0
74 002c 9D42 cmp r5, r3
75 002e 09DD ble .L5
76 0030 0133 adds r3, r3, #1
77 .L7:
78 .LVL4:
79 0032 9446 mov ip, r2
80 0034 F2EC017A vldmia.32 r2!, {s15}
81 0038 F4EEE76A vcmpe.f32 s13, s15
82 003c F1EE10FA vmrs APSR_nzcv, FPSCR
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[i] < pivot && i<last);
83 .loc 1 67 0
84 0040 1846 mov r0, r3
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
85 .loc 1 68 0
86 0042 F3DC bgt .L29
87 .L5:
88 0044 06EB8402 add r2, r6, r4, lsl #2
89 .L8:
90 0048 043A subs r2, r2, #4
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
91 .loc 1 74 0
92 004a 92ED007A vldr.32 s14, [r2]
93 004e F4EEC76A vcmpe.f32 s13, s14
94 0052 F1EE10FA vmrs APSR_nzcv, FPSCR
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[j] > pivot);
95 .loc 1 73 0
96 0056 04F1FF34 add r4, r4, #-1
97 .LVL5:
98 005a 9646 mov lr, r2
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
99 .loc 1 74 0
100 005c F4D4 bmi .L8
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
101 .loc 1 92 0
102 005e A342 cmp r3, r4
103 0060 24DB blt .L30
104 .LVL6:
105 .L3:
106 .LBE9:
107 .LBE8:
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 5
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** int32_t pivot;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Compute pivot */
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pivot = arm_quick_sort_partition_f32(pSrc, first, last, dir);
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Iterate algorithm with two sub-arrays [first ... pivot] and [pivot+1 ... last] */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** arm_quick_sort_core_f32(pSrc, first, pivot, dir);
108 .loc 1 115 0
109 0062 3B46 mov r3, r7
110 0064 2246 mov r2, r4
111 0066 3046 mov r0, r6
112 0068 FFF7CAFF bl arm_quick_sort_core_f32
113 .LVL7:
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** arm_quick_sort_core_f32(pSrc, pivot+1, last, dir);
114 .loc 1 116 0
115 006c 611C adds r1, r4, #1
116 .LBE7:
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
117 .loc 1 107 0
118 006e A942 cmp r1, r5
119 0070 CFDB blt .L15
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
120 .loc 1 118 0
121 0072 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
122 .LVL8:
123 .L31:
124 .LBB12:
125 .LBB11:
126 .LBB10:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
127 .loc 1 82 0
128 0076 9D42 cmp r5, r3
129 0078 09DD ble .L10
130 007a 0133 adds r3, r3, #1
131 .L12:
132 .LVL9:
133 007c 9446 mov ip, r2
134 007e F2EC017A vldmia.32 r2!, {s15}
135 0082 F4EEE76A vcmpe.f32 s13, s15
136 0086 F1EE10FA vmrs APSR_nzcv, FPSCR
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[i] > pivot && i<last);
137 .loc 1 81 0
138 008a 1846 mov r0, r3
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
139 .loc 1 82 0
140 008c F3D4 bmi .L31
141 .L10:
142 008e 06EB8402 add r2, r6, r4, lsl #2
143 .L13:
144 0092 043A subs r2, r2, #4
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
145 .loc 1 88 0
146 0094 92ED007A vldr.32 s14, [r2]
147 0098 F4EEC76A vcmpe.f32 s13, s14
148 009c F1EE10FA vmrs APSR_nzcv, FPSCR
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** } while (pSrc[j] < pivot);
ARM GAS /tmp/cce2LIhc.s page 6
149 .loc 1 87 0
150 00a0 04F1FF34 add r4, r4, #-1
151 .LVL10:
152 00a4 9646 mov lr, r2
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
153 .loc 1 88 0
154 00a6 F4DC bgt .L13
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
155 .loc 1 92 0
156 00a8 A342 cmp r3, r4
157 00aa DADA bge .L3
158 .LVL11:
159 .L30:
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pSrc[j]=temp;
160 .loc 1 96 0
161 00ac 8CED007A vstr.32 s14, [ip]
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
162 .loc 1 97 0
163 00b0 CEED007A vstr.32 s15, [lr]
164 00b4 B5E7 b .L14
165 .LVL12:
166 .L25:
167 .LCFI1:
168 .cfi_def_cfa_offset 0
169 .cfi_restore 4
170 .cfi_restore 5
171 .cfi_restore 6
172 .cfi_restore 7
173 .cfi_restore 8
174 .cfi_restore 14
175 00b6 7047 bx lr
176 .LBE10:
177 .LBE11:
178 .LBE12:
179 .cfi_endproc
180 .LFE168:
182 .section .text.arm_merge_sort_core_f32,"ax",%progbits
183 .align 1
184 .p2align 2,,3
185 .syntax unified
186 .thumb
187 .thumb_func
188 .fpu fpv4-sp-d16
190 arm_merge_sort_core_f32:
191 .LFB164:
192 .file 2 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Title: arm_merge_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Description: Floating point merge sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /*
ARM GAS /tmp/cce2LIhc.s page 7
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** static void topDownMerge(float32_t * pA, uint32_t begin, uint32_t middle, uint32_t end, float32_t *
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /* Left array is pA[begin:middle-1]
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * Right Array is pA[middle:end-1]
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * They are merged in pB
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t i = begin;
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t j = middle;
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t k;
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** // Read all the elements in the sublist
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** for (k = begin; k < end; k++)
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** // Merge
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** if (i < middle && (j >= end || dir==(pA[i] <= pA[j])) )
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** pB[k] = pA[i];
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** i++;
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** else
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** pB[k] = pA[j];
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** j++;
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** static void arm_merge_sort_core_f32(float32_t * pB, uint32_t begin, uint32_t end, float32_t * pA, u
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
193 .loc 2 62 0
194 .cfi_startproc
195 @ args = 4, pretend = 0, frame = 0
196 @ frame_needed = 0, uses_anonymous_args = 0
197 .LVL13:
198 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr}
ARM GAS /tmp/cce2LIhc.s page 8
199 .LCFI2:
200 .cfi_def_cfa_offset 32
201 .cfi_offset 4, -32
202 .cfi_offset 5, -28
203 .cfi_offset 6, -24
204 .cfi_offset 7, -20
205 .cfi_offset 8, -16
206 .cfi_offset 9, -12
207 .cfi_offset 10, -8
208 .cfi_offset 14, -4
209 0004 1646 mov r6, r2
210 0006 82B0 sub sp, sp, #8
211 .LCFI3:
212 .cfi_def_cfa_offset 40
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide
213 .loc 2 63 0
214 0008 521A subs r2, r2, r1
215 .LVL14:
216 000a 012A cmp r2, #1
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** if((int32_t)end - (int32_t)begin >= 2 ) // If run size != 1 divide
217 .loc 2 62 0
218 000c 9DF82890 ldrb r9, [sp, #40] @ zero_extendqisi2
219 .loc 2 63 0
220 0010 02DC bgt .L55
221 .LVL15:
222 .L32:
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** int32_t middle = (end + begin) / 2; // Take the middle point
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, begin, middle, pB, dir); // Sort the left part
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** topDownMerge(pB, begin, middle, end, pA, dir);
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
223 .loc 2 72 0
224 0012 02B0 add sp, sp, #8
225 .LCFI4:
226 .cfi_remember_state
227 .cfi_def_cfa_offset 32
228 @ sp needed
229 0014 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc}
230 .LVL16:
231 .L55:
232 .LCFI5:
233 .cfi_restore_state
234 .LBB27:
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
235 .loc 2 65 0
236 0018 06EB0108 add r8, r6, r1
237 001c 4FEA5808 lsr r8, r8, #1
238 .LVL17:
239 .LBB28:
240 .LBB29:
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
241 .loc 2 63 0
242 0020 A8EB0102 sub r2, r8, r1
ARM GAS /tmp/cce2LIhc.s page 9
243 0024 012A cmp r2, #1
244 0026 0D46 mov r5, r1
245 0028 0746 mov r7, r0
246 002a 1C46 mov r4, r3
247 002c 70DC bgt .L56
248 .LVL18:
249 .L34:
250 .LBE29:
251 .LBE28:
252 .LBB38:
253 .LBB39:
254 002e A6EB0803 sub r3, r6, r8
255 0032 012B cmp r3, #1
256 0034 2CDC bgt .L57
257 .L40:
258 .LVL19:
259 .LBE39:
260 .LBE38:
261 .LBB48:
262 .LBB49:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
263 .loc 2 45 0
264 0036 AE42 cmp r6, r5
265 0038 EBD9 bls .L32
266 003a 04EB8503 add r3, r4, r5, lsl #2
267 003e 2A46 mov r2, r5
268 .LBE49:
269 .LBE48:
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
270 .loc 2 65 0
271 0040 4146 mov r1, r8
272 0042 18E0 b .L50
273 .LVL20:
274 .L58:
275 .LBB51:
276 .LBB50:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
277 .loc 2 48 0
278 0044 8E42 cmp r6, r1
279 0046 07EB8104 add r4, r7, r1, lsl #2
280 004a 90ED007A vldr.32 s14, [r0]
281 004e 1BD9 bls .L47
282 0050 D4ED007A vldr.32 s15, [r4]
283 0054 F4EEC77A vcmpe.f32 s15, s14
284 0058 F1EE10FA vmrs APSR_nzcv, FPSCR
285 005c ACBF ite ge
286 005e 0120 movge r0, #1
287 0060 0020 movlt r0, #0
288 0062 4845 cmp r0, r9
289 0064 10D0 beq .L47
290 .L48:
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** j++;
291 .loc 2 55 0
292 0066 C3ED007A vstr.32 s15, [r3]
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
293 .loc 2 56 0
294 006a 0131 adds r1, r1, #1
ARM GAS /tmp/cce2LIhc.s page 10
295 .LVL21:
296 .L49:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
297 .loc 2 45 0
298 006c 0132 adds r2, r2, #1
299 .LVL22:
300 006e 9642 cmp r6, r2
301 0070 03F10403 add r3, r3, #4
302 0074 CDD0 beq .L32
303 .L50:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
304 .loc 2 48 0
305 0076 A845 cmp r8, r5
306 0078 07EB8500 add r0, r7, r5, lsl #2
307 007c E2D8 bhi .L58
308 007e 07EB8100 add r0, r7, r1, lsl #2
309 0082 D0ED007A vldr.32 s15, [r0]
310 0086 EEE7 b .L48
311 .L47:
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** i++;
312 .loc 2 50 0
313 0088 83ED007A vstr.32 s14, [r3]
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
314 .loc 2 51 0
315 008c 0135 adds r5, r5, #1
316 .LVL23:
317 008e EDE7 b .L49
318 .LVL24:
319 .L57:
320 .LBE50:
321 .LBE51:
322 .LBB52:
323 .LBB46:
324 .LBB40:
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
325 .loc 2 65 0
326 0090 08EB060A add r10, r8, r6
327 0094 4FEA5A0A lsr r10, r10, #1
328 .LVL25:
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
329 .loc 2 67 0
330 0098 5246 mov r2, r10
331 009a 2346 mov r3, r4
332 009c 4146 mov r1, r8
333 009e 3846 mov r0, r7
334 00a0 CDF80090 str r9, [sp]
335 00a4 FFF7ACFF bl arm_merge_sort_core_f32
336 .LVL26:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
337 .loc 2 68 0
338 00a8 CDF80090 str r9, [sp]
339 00ac 5146 mov r1, r10
340 00ae 2346 mov r3, r4
341 00b0 3246 mov r2, r6
342 00b2 3846 mov r0, r7
343 00b4 FFF7A4FF bl arm_merge_sort_core_f32
344 .LVL27:
ARM GAS /tmp/cce2LIhc.s page 11
345 .LBB41:
346 .LBB42:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
347 .loc 2 45 0
348 00b8 B045 cmp r8, r6
349 00ba BCD2 bcs .L40
350 00bc 07EB8802 add r2, r7, r8, lsl #2
351 00c0 4346 mov r3, r8
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t k;
352 .loc 2 41 0
353 00c2 5146 mov r1, r10
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
354 .loc 2 45 0
355 00c4 4046 mov r0, r8
356 00c6 1AE0 b .L45
357 .LVL28:
358 .L59:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
359 .loc 2 48 0
360 00c8 8E42 cmp r6, r1
361 00ca 04EB810E add lr, r4, r1, lsl #2
362 00ce 9CED007A vldr.32 s14, [ip]
363 00d2 5CD9 bls .L42
364 00d4 DEED007A vldr.32 s15, [lr]
365 00d8 F4EEC77A vcmpe.f32 s15, s14
366 00dc F1EE10FA vmrs APSR_nzcv, FPSCR
367 00e0 ACBF ite ge
368 00e2 4FF0010C movge ip, #1
369 00e6 4FF0000C movlt ip, #0
370 00ea CC45 cmp ip, r9
371 00ec 4FD0 beq .L42
372 .L43:
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** j++;
373 .loc 2 55 0
374 00ee C2ED007A vstr.32 s15, [r2]
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
375 .loc 2 56 0
376 00f2 0131 adds r1, r1, #1
377 .LVL29:
378 .L44:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
379 .loc 2 45 0
380 00f4 0133 adds r3, r3, #1
381 .LVL30:
382 00f6 9E42 cmp r6, r3
383 00f8 02F10402 add r2, r2, #4
384 00fc 9BD0 beq .L40
385 .L45:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
386 .loc 2 48 0
387 00fe 8245 cmp r10, r0
388 0100 04EB800C add ip, r4, r0, lsl #2
389 0104 E0D8 bhi .L59
390 0106 04EB810C add ip, r4, r1, lsl #2
391 010a DCED007A vldr.32 s15, [ip]
392 010e EEE7 b .L43
393 .LVL31:
ARM GAS /tmp/cce2LIhc.s page 12
394 .L56:
395 .LBE42:
396 .LBE41:
397 .LBE40:
398 .LBE46:
399 .LBE52:
400 .LBB53:
401 .LBB36:
402 .LBB30:
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
403 .loc 2 65 0
404 0110 08EB010A add r10, r8, r1
405 0114 4FEA5A0A lsr r10, r10, #1
406 .LVL32:
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
407 .loc 2 67 0
408 0118 5246 mov r2, r10
409 011a CDF80090 str r9, [sp]
410 011e FFF76FFF bl arm_merge_sort_core_f32
411 .LVL33:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
412 .loc 2 68 0
413 0122 CDF80090 str r9, [sp]
414 0126 5146 mov r1, r10
415 0128 2346 mov r3, r4
416 012a 4246 mov r2, r8
417 012c 3846 mov r0, r7
418 012e FFF767FF bl arm_merge_sort_core_f32
419 .LVL34:
420 .LBB31:
421 .LBB32:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
422 .loc 2 45 0
423 0132 A845 cmp r8, r5
424 0134 7FF67BAF bls .L34
425 0138 07EB8502 add r2, r7, r5, lsl #2
426 013c 2B46 mov r3, r5
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t k;
427 .loc 2 41 0
428 013e 5146 mov r1, r10
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
429 .loc 2 45 0
430 0140 2846 mov r0, r5
431 0142 1BE0 b .L39
432 .LVL35:
433 .L60:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
434 .loc 2 48 0
435 0144 8845 cmp r8, r1
436 0146 04EB810E add lr, r4, r1, lsl #2
437 014a 9CED007A vldr.32 s14, [ip]
438 014e 22D9 bls .L36
439 0150 DEED007A vldr.32 s15, [lr]
440 0154 F4EEC77A vcmpe.f32 s15, s14
441 0158 F1EE10FA vmrs APSR_nzcv, FPSCR
442 015c ACBF ite ge
443 015e 4FF0010C movge ip, #1
ARM GAS /tmp/cce2LIhc.s page 13
444 0162 4FF0000C movlt ip, #0
445 0166 CC45 cmp ip, r9
446 0168 15D0 beq .L36
447 .L37:
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** j++;
448 .loc 2 55 0
449 016a C2ED007A vstr.32 s15, [r2]
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
450 .loc 2 56 0
451 016e 0131 adds r1, r1, #1
452 .LVL36:
453 .L38:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
454 .loc 2 45 0
455 0170 0133 adds r3, r3, #1
456 .LVL37:
457 0172 9845 cmp r8, r3
458 0174 02F10402 add r2, r2, #4
459 0178 3FF459AF beq .L34
460 .L39:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
461 .loc 2 48 0
462 017c 8245 cmp r10, r0
463 017e 04EB800C add ip, r4, r0, lsl #2
464 0182 DFD8 bhi .L60
465 0184 04EB810C add ip, r4, r1, lsl #2
466 0188 DCED007A vldr.32 s15, [ip]
467 018c EDE7 b .L37
468 .LVL38:
469 .L42:
470 .LBE32:
471 .LBE31:
472 .LBE30:
473 .LBE36:
474 .LBE53:
475 .LBB54:
476 .LBB47:
477 .LBB45:
478 .LBB44:
479 .LBB43:
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** i++;
480 .loc 2 50 0
481 018e 82ED007A vstr.32 s14, [r2]
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
482 .loc 2 51 0
483 0192 0130 adds r0, r0, #1
484 .LVL39:
485 0194 AEE7 b .L44
486 .LVL40:
487 .L36:
488 .LBE43:
489 .LBE44:
490 .LBE45:
491 .LBE47:
492 .LBE54:
493 .LBB55:
494 .LBB37:
ARM GAS /tmp/cce2LIhc.s page 14
495 .LBB35:
496 .LBB34:
497 .LBB33:
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** i++;
498 .loc 2 50 0
499 0196 82ED007A vstr.32 s14, [r2]
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
500 .loc 2 51 0
501 019a 0130 adds r0, r0, #1
502 .LVL41:
503 019c E8E7 b .L38
504 .LBE33:
505 .LBE34:
506 .LBE35:
507 .LBE37:
508 .LBE55:
509 .LBE27:
510 .cfi_endproc
511 .LFE164:
513 019e 00BF .section .text.arm_barycenter_f32,"ax",%progbits
514 .align 1
515 .p2align 2,,3
516 .global arm_barycenter_f32
517 .syntax unified
518 .thumb
519 .thumb_func
520 .fpu fpv4-sp-d16
522 arm_barycenter_f32:
523 .LFB148:
524 .file 3 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Title: arm_barycenter_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Description: Barycenter
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * -------------------------------------------------------------------- */
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /*
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * SPDX-License-Identifier: Apache-2.0
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * not use this file except in compliance with the License.
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * You may obtain a copy of the License at
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * www.apache.org/licenses/LICENSE-2.0
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * Unless required by applicable law or agreed to in writing, software
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * See the License for the specific language governing permissions and
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * limitations under the License.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** */
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #include "arm_math.h"
ARM GAS /tmp/cce2LIhc.s page 15
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #include <limits.h>
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #include <math.h>
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /**
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @brief Barycenter
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @param[in] *in List of vectors
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @param[in] *weights Weights of the vectors
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @param[out] *out Barycenter
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @param[in] nbVectors Number of vectors
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @param[in] vecDim Dimension of space (vector dimension)
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** * @return None
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** */
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** void arm_barycenter_f32(const float32_t *in,
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** const float32_t *weights,
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t *out,
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** uint32_t nbVectors,
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** uint32_t vecDim)
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** const float32_t *pIn, *pW;
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** const float32_t *pIn1, *pIn2, *pIn3, *pIn4;
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t *pOut;
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** uint32_t blkCntVector, blkCntSample;
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t accum, w;
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum = 0.0f;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pW = weights;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn = in;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** arm_fill_f32(0.0f, out, vecDim);
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Sum */
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 = pIn;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 = pIn1 + vecDim;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 = pIn2 + vecDim;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 = pIn3 + vecDim;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors >> 2;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntVector > 0)
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** f32x4_t outV, inV1, inV2, inV3, inV4;
ARM GAS /tmp/cce2LIhc.s page 16
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t w1, w2, w3, w4;
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w1 = *pW++;
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w2 = *pW++;
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w3 = *pW++;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w4 = *pW++;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum += w1 + w2 + w3 + w4;
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0) {
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vld1q((const float32_t *) pOut);
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV1 = vld1q(pIn1);
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV2 = vld1q(pIn2);
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV3 = vld1q(pIn3);
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV4 = vld1q(pIn4);
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vfmaq(outV, inV1, w1);
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vfmaq(outV, inV2, w2);
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vfmaq(outV, inV3, w3);
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vfmaq(outV, inV4, w4);
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q(pOut, outV);
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 += 4;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 += 4;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 += 4;
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 += 4;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0) {
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn1++ * w1;
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn2++ * w2;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn3++ * w3;
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn4++ * w4;
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 += 3 * vecDim;
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 += 3 * vecDim;
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 += 3 * vecDim;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 += 3 * vecDim;
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector--;
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn = pIn1;
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors & 3;
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntVector > 0)
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** f32x4_t inV, outV;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
ARM GAS /tmp/cce2LIhc.s page 17
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w = *pW++;
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum += w;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0)
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vld1q_f32(pOut);
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV = vld1q_f32(pIn);
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vfmaq(outV, inV, w);
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q_f32(pOut, outV);
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn += 4;
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0)
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn++ * w;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector--;
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Normalize */
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum = 1.0f / accum;
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0)
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** f32x4_t tmp;
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** tmp = vld1q((const float32_t *) pOut);
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** tmp = vmulq(tmp, accum);
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q(pOut, tmp);
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while (blkCntSample > 0)
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut * accum;
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #else
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #if defined(ARM_MATH_NEON)
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #include "NEMath.h"
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbV
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 18
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** const float32_t *pIn,*pW, *pIn1, *pIn2, *pIn3, *pIn4;
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t *pOut;
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** uint32_t blkCntVector,blkCntSample;
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t accum, w,w1,w2,w3,w4;
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32x4_t tmp, inV,outV, inV1, inV2, inV3, inV4;
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors;
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum = 0.0f;
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pW = weights;
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn = in;
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Set counters to 0 */
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** tmp = vdupq_n_f32(0.0f);
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q_f32(pOut, tmp);
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = 0.0f;
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Sum */
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 = pIn;
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 = pIn1 + vecDim;
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 = pIn2 + vecDim;
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 = pIn3 + vecDim;
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors >> 2;
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntVector > 0)
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w1 = *pW++;
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w2 = *pW++;
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w3 = *pW++;
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w4 = *pW++;
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum += w1 + w2 + w3 + w4;
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vld1q_f32(pOut);
ARM GAS /tmp/cce2LIhc.s page 19
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV1 = vld1q_f32(pIn1);
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV2 = vld1q_f32(pIn2);
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV3 = vld1q_f32(pIn3);
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV4 = vld1q_f32(pIn4);
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vmlaq_n_f32(outV,inV1,w1);
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vmlaq_n_f32(outV,inV2,w2);
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vmlaq_n_f32(outV,inV3,w3);
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vmlaq_n_f32(outV,inV4,w4);
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q_f32(pOut, outV);
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 += 4;
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 += 4;
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 += 4;
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 += 4;
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn1++ * w1;
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn2++ * w2;
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn3++ * w3;
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn4++ * w4;
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn1 += 3*vecDim;
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn2 += 3*vecDim;
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn3 += 3*vecDim;
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn4 += 3*vecDim;
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector--;
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn = pIn1;
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors & 3;
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntVector > 0)
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w = *pW++;
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum += w;
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
304:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
305:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vld1q_f32(pOut);
306:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** inV = vld1q_f32(pIn);
307:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** outV = vmlaq_n_f32(outV,inV,w);
308:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q_f32(pOut, outV);
309:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
310:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn += 4;
311:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
312:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
ARM GAS /tmp/cce2LIhc.s page 20
313:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
314:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
315:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
316:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
317:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
318:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn++ * w;
319:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
320:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
321:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
322:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
323:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector--;
324:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
325:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
326:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Normalize */
327:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
328:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum = 1.0f / accum;
329:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
330:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim >> 2;
331:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
332:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
333:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** tmp = vld1q_f32(pOut);
334:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** tmp = vmulq_n_f32(tmp,accum);
335:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** vst1q_f32(pOut, tmp);
336:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut += 4;
337:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
338:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
339:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
340:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim & 3;
341:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
342:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
343:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut * accum;
344:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
345:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
346:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
347:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
348:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
349:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** #else
350:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** void arm_barycenter_f32(const float32_t *in, const float32_t *weights, float32_t *out, uint32_t nbV
351:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
525 .loc 3 351 0
526 .cfi_startproc
527 @ args = 4, pretend = 0, frame = 0
528 @ frame_needed = 0, uses_anonymous_args = 0
529 .LVL42:
530 0000 2DE9F843 push {r3, r4, r5, r6, r7, r8, r9, lr}
531 .LCFI6:
532 .cfi_def_cfa_offset 32
533 .cfi_offset 3, -32
534 .cfi_offset 4, -28
535 .cfi_offset 5, -24
536 .cfi_offset 6, -20
537 .cfi_offset 7, -16
538 .cfi_offset 8, -12
539 .cfi_offset 9, -8
540 .cfi_offset 14, -4
541 .loc 3 351 0
542 0004 089C ldr r4, [sp, #32]
ARM GAS /tmp/cce2LIhc.s page 21
543 0006 0746 mov r7, r0
544 0008 8846 mov r8, r1
545 000a 1546 mov r5, r2
546 000c 1E46 mov r6, r3
547 .LVL43:
352:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
353:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** const float32_t *pIn,*pW;
354:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t *pOut;
355:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** uint32_t blkCntVector,blkCntSample;
356:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** float32_t accum, w;
357:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
358:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector = nbVectors;
359:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
360:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
361:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum = 0.0f;
362:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
363:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pW = weights;
364:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pIn = in;
365:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
366:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Set counters to 0 */
367:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
368:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
369:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
370:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
548 .loc 3 370 0
549 000e 6CB3 cbz r4, .L62
371:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
372:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = 0.0f;
550 .loc 3 372 0
551 0010 4FEA8409 lsl r9, r4, #2
552 0014 4A46 mov r2, r9
553 .LVL44:
554 0016 0021 movs r1, #0
555 .LVL45:
556 0018 2846 mov r0, r5
557 .LVL46:
558 001a FFF7FEFF bl memset
559 .LVL47:
373:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
374:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
375:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
376:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
377:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Sum */
378:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntVector > 0)
560 .loc 3 378 0
561 001e 4EB3 cbz r6, .L70
562 .L69:
351:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
563 .loc 3 351 0
564 0020 9FED166A vldr.32 s12, .L82
565 .LVL48:
566 .L66:
379:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
380:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
381:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** w = *pW++;
567 .loc 3 381 0
568 0024 F8EC016A vldmia.32 r8!, {s13}
ARM GAS /tmp/cce2LIhc.s page 22
569 .LVL49:
382:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** accum += w;
570 .loc 3 382 0
571 0028 36EE266A vadd.f32 s12, s12, s13
572 .LVL50:
383:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
384:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
385:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
573 .loc 3 385 0
574 002c 6CB1 cbz r4, .L64
575 002e 2946 mov r1, r5
576 0030 2246 mov r2, r4
577 0032 3846 mov r0, r7
578 .LVL51:
579 .L65:
386:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
387:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut + *pIn++ * w;
580 .loc 3 387 0
581 0034 D1ED007A vldr.32 s15, [r1]
582 0038 B0EC017A vldmia.32 r0!, {s14}
583 .LVL52:
584 003c E7EE267A vfma.f32 s15, s14, s13
385:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
585 .loc 3 385 0
586 0040 013A subs r2, r2, #1
587 .LVL53:
588 .loc 3 387 0
589 0042 E1EC017A vstmia.32 r1!, {s15}
590 .LVL54:
385:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
591 .loc 3 385 0
592 0046 F5D1 bne .L65
593 0048 4F44 add r7, r7, r9
594 .LVL55:
595 .L64:
378:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
596 .loc 3 378 0
597 004a 013E subs r6, r6, #1
598 .LVL56:
599 004c EAD1 bne .L66
600 .LVL57:
388:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
389:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
390:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
391:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
392:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntVector--;
393:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
394:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
395:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** /* Normalize */
396:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample = vecDim;
397:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut = out;
398:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
399:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** while(blkCntSample > 0)
601 .loc 3 399 0
602 004e 5CB1 cbz r4, .L61
603 .LVL58:
604 .L63:
ARM GAS /tmp/cce2LIhc.s page 23
605 0050 F7EE007A vmov.f32 s15, #1.0e+0
606 0054 87EE867A vdiv.f32 s14, s15, s12
607 .LVL59:
608 .L68:
609 0058 013C subs r4, r4, #1
610 .LVL60:
400:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
401:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** *pOut = *pOut / accum;
611 .loc 3 401 0
612 005a D5ED007A vldr.32 s15, [r5]
613 005e 67EE877A vmul.f32 s15, s15, s14
614 0062 E5EC017A vstmia.32 r5!, {s15}
615 .LVL61:
399:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
616 .loc 3 399 0
617 0066 F7D1 bne .L68
618 .L61:
402:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** pOut++;
403:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** blkCntSample--;
404:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
405:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
406:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** }
619 .loc 3 406 0
620 0068 BDE8F883 pop {r3, r4, r5, r6, r7, r8, r9, pc}
621 .LVL62:
622 .L62:
378:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c **** {
623 .loc 3 378 0
624 006c 002B cmp r3, #0
625 006e FBD0 beq .L61
626 0070 A146 mov r9, r4
627 0072 D5E7 b .L69
628 .LVL63:
629 .L70:
361:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_barycenter_f32.c ****
630 .loc 3 361 0
631 0074 9FED016A vldr.32 s12, .L82
632 0078 EAE7 b .L63
633 .L83:
634 007a 00BF .align 2
635 .L82:
636 007c 00000000 .word 0
637 .cfi_endproc
638 .LFE148:
640 .section .text.arm_bitonic_sort_f32,"ax",%progbits
641 .align 1
642 .p2align 2,,3
643 .global arm_bitonic_sort_f32
644 .syntax unified
645 .thumb
646 .thumb_func
647 .fpu fpv4-sp-d16
649 arm_bitonic_sort_f32:
650 .LFB150:
651 .file 4 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Project: CMSIS DSP Library
ARM GAS /tmp/cce2LIhc.s page 24
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Title: arm_bitonic_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Description: Floating point bitonic sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #if !defined(ARM_MATH_NEON)
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_sort_core_f32(float32_t *pSrc, uint32_t n, uint8_t dir)
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint32_t step;
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint32_t k, j;
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t *leftPtr, *rightPtr;
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t temp;
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** step = n>>1;
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** leftPtr = pSrc;
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** rightPtr = pSrc+n-1;
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(k=0; k<step; k++)
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir == (*leftPtr > *rightPtr))
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Swap
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp=*leftPtr;
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *leftPtr=*rightPtr;
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *rightPtr=temp;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** leftPtr++; // Move right
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** rightPtr--; // Move left
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 25
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(step=(n>>2); step>0; step/=2)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(j=0; j<n; j=j+step*2)
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** leftPtr = pSrc+j;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** rightPtr = pSrc+j+step;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(k=0; k<step; k++)
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(*leftPtr > *rightPtr)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Swap
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp=*leftPtr;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *leftPtr=*rightPtr;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *rightPtr=temp;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** leftPtr++;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** rightPtr++;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #endif
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #if defined(ARM_MATH_NEON)
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static float32x4x2_t arm_bitonic_resort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* Start with two vectors:
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | b | c | d |
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | e | f | g | h |
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * All the elements of the first are guaranteed to be less than or equal to
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * all of the elements in the second, and both vectors are bitonic.
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * We need to perform these operations to completely sort both lists:
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * vminmax([abcd],[efgh])
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * vminmax([acbd],[egfh])
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vtrn128_64q(a, b);
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* +---+---+---+---+
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | b | e | f |
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | c | d | g | h |
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, b);
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, a);
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 26
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vtrn128_32q(a, b);
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* +---+---+---+---+
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | c | e | g |
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | b | d | f | h |
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, b);
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, a);
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** return vzipq_f32(a, b);
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static float32x4x2_t arm_bitonic_merge_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* a and b are guaranteed to be bitonic */
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Reverse the element of the second vector
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** b = vrev128q_f32(b);
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Compare the two vectors
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, b);
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, a);
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge the two vectors
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab = arm_bitonic_resort_8_f32(a, b, dir);
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** return ab;
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_resort_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t d
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* Start with two vectors:
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | b | c | d | e | f | g | h |
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | i | j | k | l | m | n | o | p |
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * All the elements of the first are guaranteed to be less than or equal to
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * all of the elements in the second, and both vectors are bitonic.
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * We need to perform these operations to completely sort both lists:
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * vminmax([abcd],[efgh]) vminmax([ijkl],[mnop])
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * vminmax([abef],[cdgh]) vminmax([ijmn],[klop])
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * vminmax([acef],[bdfh]) vminmax([ikmo],[jlmp])
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vtrn256_128q(a, b);
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* +---+---+---+---+---+---+---+---+
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | b | c | d | i | j | k | l |
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
ARM GAS /tmp/cce2LIhc.s page 27
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | e | f | g | h | m | n | o | p |
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(a, b);
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(b, a);
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vtrn256_64q(a, b);
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* +---+---+---+---+---+---+---+---+
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | b | e | f | i | j | m | n |
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | c | d | g | h | k | l | o | p |
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(a, b);
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(b, a);
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vtrn256_32q(a, b);
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /* We now have:
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | a | c | e | g | i | k | m | o |
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * | b | d | f | h | j | l | n | p |
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * +---+---+---+---+---+---+---+---+
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(a, b);
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(b, a);
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t out1 = vzipq_f32(a.val[0], b.val[0]);
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t out2 = vzipq_f32(a.val[1], b.val[1]);
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut, out1.val[0]);
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut+4, out1.val[1]);
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut+8, out2.val[0]);
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut+12, out2.val[1]);
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_merge_16_f32(float32_t * pOut, float32x4x2_t a, float32x4x2_t b, uint8_t di
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge two preordered float32x4x2_t
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vrev256q_f32(b);
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(a, b);
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(b, a);
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_resort_16_f32(pOut, a, b, dir);
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
ARM GAS /tmp/cce2LIhc.s page 28
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_sort_16_f32(float32_t *pSrc, float32_t *pDst, uint8_t dir)
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t a;
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t b;
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t c;
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t d;
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Load 16 samples
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = vld1q_f32(pSrc);
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** b = vld1q_f32(pSrc+4);
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** c = vld1q_f32(pSrc+8);
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** d = vld1q_f32(pSrc+12);
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Bitonic sorting network for 4 samples x 4 times
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, b);
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(c, d);
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, d);
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, c);
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(a, b);
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(c, d);
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, a);
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(d, c);
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(d, a);
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(c, b);
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(b, a);
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmaxq(d, c);
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab = vtrnq_f32 (a, b);
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd = vtrnq_f32 (c, d);
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Transpose 4 ordered arrays of 4 samples
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = vcombine_f32(vget_low_f32(ab.val[0]), vget_low_f32(cd.val[0]));
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** b = vcombine_f32(vget_low_f32(ab.val[1]), vget_low_f32(cd.val[1]));
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** c = vcombine_f32(vget_high_f32(ab.val[0]), vget_high_f32(cd.val[0]));
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** d = vcombine_f32(vget_high_f32(ab.val[1]), vget_high_f32(cd.val[1]));
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge pairs of arrays of 4 samples
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab = arm_bitonic_merge_8_f32(a, b, dir);
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd = arm_bitonic_merge_8_f32(c, d, dir);
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge arrays of 8 samples
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_16_f32(pDst, ab, cd, dir);
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 29
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_merge_32_f32(float32_t * pSrc, float32x4x2_t ab1, float32x4x2_t ab2, float3
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose 256
304:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t temp;
305:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
306:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab2.val[0];
307:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[0] = cd1.val[0];
308:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[0] = temp;
309:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab2.val[1];
310:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[1] = cd1.val[1];
311:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[1] = temp;
312:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
313:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
314:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
315:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
316:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
317:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
318:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
319:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
320:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
321:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
322:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
323:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
324:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
325:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose 128
326:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_16_f32(pSrc+0, ab1, cd1, dir);
327:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_16_f32(pSrc+16, ab2, cd2, dir);
328:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
329:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
330:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_merge_64_f32(float32_t * pSrc, uint8_t dir)
331:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
332:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab1, ab2, ab3, ab4;
333:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd1, cd2, cd3, cd4;
334:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
335:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Load and reverse second array
336:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[0] = vld1q_f32(pSrc+0 );
337:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[1] = vld1q_f32(pSrc+4 );
338:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[0] = vld1q_f32(pSrc+8 );
339:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[1] = vld1q_f32(pSrc+12);
340:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[0] = vld1q_f32(pSrc+16);
341:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[1] = vld1q_f32(pSrc+20);
342:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[0] = vld1q_f32(pSrc+24);
343:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[1] = vld1q_f32(pSrc+28);
344:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 30
345:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[1], pSrc+32);
346:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[0], pSrc+36);
347:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[1], pSrc+40);
348:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[0], pSrc+44);
349:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[1], pSrc+48);
350:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[0], pSrc+52);
351:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[1], pSrc+56);
352:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[0], pSrc+60);
353:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
354:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
355:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
356:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
357:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
358:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
359:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3, cd3);
360:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4, cd4);
361:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
362:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
363:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
364:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
365:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
366:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3, ab3);
367:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4, ab4);
368:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
369:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
370:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose 512
371:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t temp;
372:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
373:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab3.val[0];
374:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[0] = cd1.val[0];
375:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[0] = temp;
376:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab3.val[1];
377:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[1] = cd1.val[1];
378:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[1] = temp;
379:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab4.val[0];
380:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[0] = cd2.val[0];
381:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[0] = temp;
382:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab4.val[1];
383:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[1] = cd2.val[1];
384:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[1] = temp;
385:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
386:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
387:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
388:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
389:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
390:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
391:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3, cd3);
392:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4, cd4);
393:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
394:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
395:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
396:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
397:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
398:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3, ab3);
399:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4, ab4);
400:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
401:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 31
402:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose 256
403:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_32_f32(pSrc+0, ab1, ab2, cd1, cd2, dir);
404:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_32_f32(pSrc+32, ab3, ab4, cd3, cd4, dir);
405:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
406:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
407:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_merge_128_f32(float32_t * pSrc, uint8_t dir)
408:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
409:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8;
410:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8;
411:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
412:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Load and reverse second array
413:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[0] = vld1q_f32(pSrc+0 );
414:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[1] = vld1q_f32(pSrc+4 );
415:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[0] = vld1q_f32(pSrc+8 );
416:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[1] = vld1q_f32(pSrc+12);
417:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[0] = vld1q_f32(pSrc+16);
418:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[1] = vld1q_f32(pSrc+20);
419:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[0] = vld1q_f32(pSrc+24);
420:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[1] = vld1q_f32(pSrc+28);
421:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[0] = vld1q_f32(pSrc+32);
422:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[1] = vld1q_f32(pSrc+36);
423:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[0] = vld1q_f32(pSrc+40);
424:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[1] = vld1q_f32(pSrc+44);
425:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[0] = vld1q_f32(pSrc+48);
426:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[1] = vld1q_f32(pSrc+52);
427:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[0] = vld1q_f32(pSrc+56);
428:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[1] = vld1q_f32(pSrc+60);
429:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
430:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd8.val[1], pSrc+64);
431:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd8.val[0], pSrc+68);
432:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd7.val[1], pSrc+72);
433:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd7.val[0], pSrc+76);
434:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd6.val[1], pSrc+80);
435:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd6.val[0], pSrc+84);
436:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd5.val[1], pSrc+88);
437:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd5.val[0], pSrc+92);
438:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[1], pSrc+96);
439:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[0], pSrc+100);
440:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[1], pSrc+104);
441:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[0], pSrc+108);
442:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[1], pSrc+112);
443:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[0], pSrc+116);
444:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[1], pSrc+120);
445:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[0], pSrc+124);
446:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
447:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
448:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
449:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
450:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
451:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
452:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3, cd3);
453:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4, cd4);
454:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab5, cd5);
455:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab6, cd6);
456:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab7, cd7);
457:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab8, cd8);
458:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
ARM GAS /tmp/cce2LIhc.s page 32
459:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
460:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
461:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
462:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
463:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3, ab3);
464:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4, ab4);
465:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd5, ab5);
466:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd6, ab6);
467:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd7, ab7);
468:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd8, ab8);
469:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
470:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
471:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose
472:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t temp;
473:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
474:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab5.val[0];
475:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[0] = cd1.val[0];
476:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[0] = temp;
477:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab5.val[1];
478:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[1] = cd1.val[1];
479:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[1] = temp;
480:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab6.val[0];
481:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[0] = cd2.val[0];
482:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[0] = temp;
483:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab6.val[1];
484:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[1] = cd2.val[1];
485:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[1] = temp;
486:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab7.val[0];
487:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[0] = cd3.val[0];
488:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd3.val[0] = temp;
489:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab7.val[1];
490:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[1] = cd3.val[1];
491:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd3.val[1] = temp;
492:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab8.val[0];
493:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[0] = cd4.val[0];
494:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd4.val[0] = temp;
495:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab8.val[1];
496:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[1] = cd4.val[1];
497:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd4.val[1] = temp;
498:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
499:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
500:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
501:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
502:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1, cd1);
503:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2, cd2);
504:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3, cd3);
505:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4, cd4);
506:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab5, cd5);
507:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab6, cd6);
508:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab7, cd7);
509:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab8, cd8);
510:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
511:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
512:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
513:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1, ab1);
514:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2, ab2);
515:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3, ab3);
ARM GAS /tmp/cce2LIhc.s page 33
516:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4, ab4);
517:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd5, ab5);
518:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd6, ab6);
519:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd7, ab7);
520:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd8, ab8);
521:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
522:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
523:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc, ab1.val[0]);
524:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+4, ab1.val[1]);
525:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+8, ab2.val[0]);
526:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+12, ab2.val[1]);
527:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+16, ab3.val[0]);
528:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+20, ab3.val[1]);
529:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+24, ab4.val[0]);
530:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+28, ab4.val[1]);
531:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+32, cd1.val[0]);
532:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+36, cd1.val[1]);
533:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+40, cd2.val[0]);
534:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+44, cd2.val[1]);
535:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+48, cd3.val[0]);
536:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+52, cd3.val[1]);
537:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+56, cd4.val[0]);
538:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+60, cd4.val[1]);
539:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+64, ab5.val[0]);
540:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+68, ab5.val[1]);
541:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+72, ab6.val[0]);
542:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+76, ab6.val[1]);
543:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+80, ab7.val[0]);
544:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+84, ab7.val[1]);
545:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+88, ab8.val[0]);
546:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+92, ab8.val[1]);
547:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+96, cd5.val[0]);
548:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+100, cd5.val[1]);
549:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+104, cd6.val[0]);
550:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+108, cd6.val[1]);
551:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+112, cd7.val[0]);
552:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+116, cd7.val[1]);
553:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+120, cd8.val[0]);
554:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+124, cd8.val[1]);
555:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
556:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose
557:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_64_f32(pSrc+0 , dir);
558:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_64_f32(pSrc+64, dir);
559:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
560:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
561:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static void arm_bitonic_merge_256_f32(float32_t * pSrc, uint8_t dir)
562:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
563:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab1, ab2, ab3, ab4, ab5, ab6, ab7, ab8;
564:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16;
565:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd1, cd2, cd3, cd4, cd5, cd6, cd7, cd8;
566:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd9, cd10, cd11, cd12, cd13, cd14, cd15, cd16;
567:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
568:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Load and reverse second array
569:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[0] = vld1q_f32(pSrc+0 );
570:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[1] = vld1q_f32(pSrc+4 );
571:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[0] = vld1q_f32(pSrc+8 );
572:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[1] = vld1q_f32(pSrc+12 );
ARM GAS /tmp/cce2LIhc.s page 34
573:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[0] = vld1q_f32(pSrc+16 );
574:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab3.val[1] = vld1q_f32(pSrc+20 );
575:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[0] = vld1q_f32(pSrc+24 );
576:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab4.val[1] = vld1q_f32(pSrc+28 );
577:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[0] = vld1q_f32(pSrc+32 );
578:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab5.val[1] = vld1q_f32(pSrc+36 );
579:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[0] = vld1q_f32(pSrc+40 );
580:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab6.val[1] = vld1q_f32(pSrc+44 );
581:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[0] = vld1q_f32(pSrc+48 );
582:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab7.val[1] = vld1q_f32(pSrc+52 );
583:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[0] = vld1q_f32(pSrc+56 );
584:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab8.val[1] = vld1q_f32(pSrc+60 );
585:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab9.val[0] = vld1q_f32(pSrc+64 );
586:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab9.val[1] = vld1q_f32(pSrc+68 );
587:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab10.val[0] = vld1q_f32(pSrc+72 );
588:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab10.val[1] = vld1q_f32(pSrc+76 );
589:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab11.val[0] = vld1q_f32(pSrc+80 );
590:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab11.val[1] = vld1q_f32(pSrc+84 );
591:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab12.val[0] = vld1q_f32(pSrc+88 );
592:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab12.val[1] = vld1q_f32(pSrc+92 );
593:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab13.val[0] = vld1q_f32(pSrc+96 );
594:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab13.val[1] = vld1q_f32(pSrc+100);
595:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab14.val[0] = vld1q_f32(pSrc+104);
596:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab14.val[1] = vld1q_f32(pSrc+108);
597:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab15.val[0] = vld1q_f32(pSrc+112);
598:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab15.val[1] = vld1q_f32(pSrc+116);
599:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab16.val[0] = vld1q_f32(pSrc+120);
600:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab16.val[1] = vld1q_f32(pSrc+124);
601:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
602:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd16.val[1], pSrc+128);
603:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd16.val[0], pSrc+132);
604:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd15.val[1], pSrc+136);
605:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd15.val[0], pSrc+140);
606:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd14.val[1], pSrc+144);
607:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd14.val[0], pSrc+148);
608:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd13.val[1], pSrc+152);
609:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd13.val[0], pSrc+156);
610:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd12.val[1], pSrc+160);
611:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd12.val[0], pSrc+164);
612:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd11.val[1], pSrc+168);
613:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd11.val[0], pSrc+172);
614:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd10.val[1], pSrc+176);
615:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd10.val[0], pSrc+180);
616:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd9.val[1] , pSrc+184);
617:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd9.val[0] , pSrc+188);
618:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd8.val[1] , pSrc+192);
619:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd8.val[0] , pSrc+196);
620:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd7.val[1] , pSrc+200);
621:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd7.val[0] , pSrc+204);
622:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd6.val[1] , pSrc+208);
623:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd6.val[0] , pSrc+212);
624:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd5.val[1] , pSrc+216);
625:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd5.val[0] , pSrc+220);
626:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[1] , pSrc+224);
627:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd4.val[0] , pSrc+228);
628:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[1] , pSrc+232);
629:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd3.val[0] , pSrc+236);
ARM GAS /tmp/cce2LIhc.s page 35
630:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[1] , pSrc+240);
631:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[0] , pSrc+244);
632:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[1] , pSrc+248);
633:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[0] , pSrc+252);
634:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
635:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
636:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
637:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
638:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1 , cd1 );
639:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2 , cd2 );
640:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3 , cd3 );
641:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4 , cd4 );
642:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab5 , cd5 );
643:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab6 , cd6 );
644:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab7 , cd7 );
645:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab8 , cd8 );
646:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab9 , cd9 );
647:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab10, cd10);
648:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab11, cd11);
649:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab12, cd12);
650:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab13, cd13);
651:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab14, cd14);
652:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab15, cd15);
653:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab16, cd16);
654:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
655:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
656:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
657:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1 , ab1 );
658:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2 , ab2 );
659:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3 , ab3 );
660:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4 , ab4 );
661:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd5 , ab5 );
662:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd6 , ab6 );
663:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd7 , ab7 );
664:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd8 , ab8 );
665:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd9 , ab9 );
666:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd10, ab10);
667:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd11, ab11);
668:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd12, ab12);
669:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd13, ab13);
670:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd14, ab14);
671:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd15, ab15);
672:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd16, ab16);
673:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
674:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
675:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose
676:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t temp;
677:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
678:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab9.val[0];
679:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab9.val[0] = cd1.val[0];
680:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[0] = temp;
681:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab9.val[1];
682:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab9.val[1] = cd1.val[1];
683:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd1.val[1] = temp;
684:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab10.val[0];
685:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab10.val[0] = cd2.val[0];
686:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[0] = temp;
ARM GAS /tmp/cce2LIhc.s page 36
687:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab10.val[1];
688:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab10.val[1] = cd2.val[1];
689:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd2.val[1] = temp;
690:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab11.val[0];
691:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab11.val[0] = cd3.val[0];
692:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd3.val[0] = temp;
693:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab11.val[1];
694:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab11.val[1] = cd3.val[1];
695:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd3.val[1] = temp;
696:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab12.val[0];
697:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab12.val[0] = cd4.val[0];
698:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd4.val[0] = temp;
699:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab12.val[1];
700:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab12.val[1] = cd4.val[1];
701:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd4.val[1] = temp;
702:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab13.val[0];
703:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab13.val[0] = cd5.val[0];
704:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd5.val[0] = temp;
705:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab13.val[1];
706:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab13.val[1] = cd5.val[1];
707:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd5.val[1] = temp;
708:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab14.val[0];
709:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab14.val[0] = cd6.val[0];
710:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd6.val[0] = temp;
711:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab14.val[1];
712:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab14.val[1] = cd6.val[1];
713:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd6.val[1] = temp;
714:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab15.val[0];
715:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab15.val[0] = cd7.val[0];
716:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd7.val[0] = temp;
717:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab15.val[1];
718:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab15.val[1] = cd7.val[1];
719:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd7.val[1] = temp;
720:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab16.val[0];
721:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab16.val[0] = cd8.val[0];
722:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd8.val[0] = temp;
723:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = ab16.val[1];
724:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab16.val[1] = cd8.val[1];
725:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** cd8.val[1] = temp;
726:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
727:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Compare
728:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(dir)
729:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
730:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab1 , cd1 );
731:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab2 , cd2 );
732:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab3 , cd3 );
733:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab4 , cd4 );
734:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab5 , cd5 );
735:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab6 , cd6 );
736:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab7 , cd7 );
737:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab8 , cd8 );
738:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab9 , cd9 );
739:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab10, cd10);
740:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab11, cd11);
741:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab12, cd12);
742:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab13, cd13);
743:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab14, cd14);
ARM GAS /tmp/cce2LIhc.s page 37
744:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab15, cd15);
745:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(ab16, cd16);
746:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
747:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
748:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
749:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd1 , ab1 );
750:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd2 , ab2 );
751:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd3 , ab3 );
752:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd4 , ab4 );
753:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd5 , ab5 );
754:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd6 , ab6 );
755:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd7 , ab7 );
756:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd8 , ab8 );
757:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd9 , ab9 );
758:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd10, ab10);
759:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd11, ab11);
760:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd12, ab12);
761:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd13, ab13);
762:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd14, ab14);
763:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd15, ab15);
764:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vminmax256q(cd16, ab16);
765:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
766:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
767:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc, ab1.val[0] );
768:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+4, ab1.val[1] );
769:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+8, ab2.val[0] );
770:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+12, ab2.val[1] );
771:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+16, ab3.val[0] );
772:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+20, ab3.val[1] );
773:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+24, ab4.val[0] );
774:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+28, ab4.val[1] );
775:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+32, ab5.val[0] );
776:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+36, ab5.val[1] );
777:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+40, ab6.val[0] );
778:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+44, ab6.val[1] );
779:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+48, ab7.val[0] );
780:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+52, ab7.val[1] );
781:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+56, ab8.val[0] );
782:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+60, ab8.val[1] );
783:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+64, cd1.val[0] );
784:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+68, cd1.val[1] );
785:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+72, cd2.val[0] );
786:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+76, cd2.val[1] );
787:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+80, cd3.val[0] );
788:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+84, cd3.val[1] );
789:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+88, cd4.val[0] );
790:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+92, cd4.val[1] );
791:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+96, cd5.val[0] );
792:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+100, cd5.val[1] );
793:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+104, cd6.val[0] );
794:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+108, cd6.val[1] );
795:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+112, cd7.val[0] );
796:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+116, cd7.val[1] );
797:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+120, cd8.val[0] );
798:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+124, cd8.val[1] );
799:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+128, ab9.val[0] );
800:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+132, ab9.val[1] );
ARM GAS /tmp/cce2LIhc.s page 38
801:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+136, ab10.val[0]);
802:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+140, ab10.val[1]);
803:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+144, ab11.val[0]);
804:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+148, ab11.val[1]);
805:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+152, ab12.val[0]);
806:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+156, ab12.val[1]);
807:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+160, ab13.val[0]);
808:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+164, ab13.val[1]);
809:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+168, ab14.val[0]);
810:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+172, ab14.val[1]);
811:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+176, ab15.val[0]);
812:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+180, ab15.val[1]);
813:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+184, ab16.val[0]);
814:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+188, ab16.val[1]);
815:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+192, cd9.val[0] );
816:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+196, cd9.val[1] );
817:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+200, cd10.val[0]);
818:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+204, cd10.val[1]);
819:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+208, cd11.val[0]);
820:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+212, cd11.val[1]);
821:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+216, cd12.val[0]);
822:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+220, cd12.val[1]);
823:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+224, cd13.val[0]);
824:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+228, cd13.val[1]);
825:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+232, cd14.val[0]);
826:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+236, cd14.val[1]);
827:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+240, cd15.val[0]);
828:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+244, cd15.val[1]);
829:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+248, cd16.val[0]);
830:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pSrc+252, cd16.val[1]);
831:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
832:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** //Transpose
833:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_128_f32(pSrc+0 , dir);
834:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_128_f32(pSrc+128, dir);
835:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
836:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
837:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #define SWAP(a,i,j) \
838:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = vgetq_lane_f32(a, j); \
839:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = vsetq_lane_f32(vgetq_lane_f32(a, i), a, j);\
840:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = vsetq_lane_f32(temp, a, i);
841:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
842:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static float32x4_t arm_bitonic_sort_4_f32(float32x4_t a, uint8_t dir)
843:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
844:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t temp;
845:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
846:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
847:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) )
848:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
849:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,0,1);
850:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
851:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 2) > vgetq_lane_f32(a, 3)) )
852:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
853:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,2,3);
854:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
855:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
856:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 3)) )
857:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 39
858:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,0,3);
859:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
860:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 1) > vgetq_lane_f32(a, 2)) )
861:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
862:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,1,2);
863:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
864:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
865:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 0) > vgetq_lane_f32(a, 1)) )
866:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
867:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,0,1);
868:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
869:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(vgetq_lane_f32(a, 2)>vgetq_lane_f32(a, 3)) )
870:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
871:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** SWAP(a,2,3);
872:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
873:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
874:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** return a;
875:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
876:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
877:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** static float32x4x2_t arm_bitonic_sort_8_f32(float32x4_t a, float32x4_t b, uint8_t dir)
878:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
879:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = arm_bitonic_sort_4_f32(a, dir);
880:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** b = arm_bitonic_sort_4_f32(b, dir);
881:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** return arm_bitonic_merge_8_f32(a, b, dir);
882:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
883:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
884:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
885:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
886:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #endif
887:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
888:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /**
889:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** @ingroup groupSupport
890:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
891:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
892:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /**
893:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** @defgroup Sorting Vector sorting algorithms
894:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
895:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** Sort the elements of a vector
896:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
897:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** There are separate functions for floating-point, Q31, Q15, and Q7 data types.
898:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
899:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
900:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /**
901:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** @addtogroup Sorting
902:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** @{
903:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
904:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
905:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** /**
906:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * @private
907:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
908:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * @param[in] pSrc points to the block of input data.
909:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * @param[out] pDst points to the block of output data
910:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** * @param[in] blockSize number of samples to process.
911:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** */
912:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** void arm_bitonic_sort_f32(
913:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** const arm_sort_instance_f32 * S,
914:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t * pSrc,
ARM GAS /tmp/cce2LIhc.s page 40
915:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t * pDst,
916:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint32_t blockSize)
917:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
652 .loc 4 917 0
653 .cfi_startproc
654 @ args = 0, pretend = 0, frame = 16
655 @ frame_needed = 0, uses_anonymous_args = 0
656 .LVL64:
657 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
658 .LCFI7:
659 .cfi_def_cfa_offset 36
660 .cfi_offset 4, -36
661 .cfi_offset 5, -32
662 .cfi_offset 6, -28
663 .cfi_offset 7, -24
664 .cfi_offset 8, -20
665 .cfi_offset 9, -16
666 .cfi_offset 10, -12
667 .cfi_offset 11, -8
668 .cfi_offset 14, -4
918:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint16_t s, i;
919:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint8_t dir = S->dir;
920:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
921:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #ifdef ARM_MATH_NEON
922:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** (void)s;
923:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
924:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t * pOut;
925:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint16_t counter = blockSize>>5;
926:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
927:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only
928:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
929:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(pSrc == pDst) // in-place
930:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut = pSrc;
931:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
932:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut = pDst;
933:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
934:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab1, ab2;
935:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t cd1, cd2;
936:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
937:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(blockSize == 1)
938:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut = pSrc;
939:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else if(blockSize == 2)
940:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
941:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t temp;
942:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
943:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( dir==(pSrc[0]>pSrc[1]) )
944:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
945:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** temp = pSrc[1];
946:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut[1] = pSrc[0];
947:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut[0] = temp;
948:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
949:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
950:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pOut = pSrc;
951:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
952:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else if(blockSize == 4)
953:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
954:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t a = vld1q_f32(pSrc);
ARM GAS /tmp/cce2LIhc.s page 41
955:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
956:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = arm_bitonic_sort_4_f32(a, dir);
957:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
958:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut, a);
959:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
960:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else if(blockSize == 8)
961:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
962:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t a;
963:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4_t b;
964:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32x4x2_t ab;
965:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
966:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** a = vld1q_f32(pSrc);
967:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** b = vld1q_f32(pSrc+4);
968:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
969:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab = arm_bitonic_sort_8_f32(a, b, dir);
970:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
971:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut, ab.val[0]);
972:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vst1q_f32(pOut+4, ab.val[1]);
973:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
974:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else if(blockSize >=16)
975:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
976:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Order 16 bits long vectors
977:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<blockSize; i=i+16)
978:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_sort_16_f32(pSrc+i, pOut+i, dir);
979:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
980:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Merge
981:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<counter; i++)
982:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
983:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Load and reverse second vector
984:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[0] = vld1q_f32(pOut+32*i+0 );
985:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab1.val[1] = vld1q_f32(pOut+32*i+4 );
986:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[0] = vld1q_f32(pOut+32*i+8 );
987:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** ab2.val[1] = vld1q_f32(pOut+32*i+12);
988:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
989:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[1], pOut+32*i+16);
990:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd2.val[0], pOut+32*i+20);
991:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[1], pOut+32*i+24);
992:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** vldrev128q_f32(cd1.val[0], pOut+32*i+28);
993:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
994:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_32_f32(pOut+32*i, ab1, ab2, cd1, cd2, dir);
995:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
996:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
997:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** counter = counter>>1;
998:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<counter; i++)
999:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_64_f32(pOut+64*i, dir);
1000:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1001:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** counter = counter>>1;
1002:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<counter; i++)
1003:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_128_f32(pOut+128*i, dir);
1004:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1005:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** counter = counter>>1;
1006:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<counter; i++)
1007:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_merge_256_f32(pOut+256*i, dir);
1008:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1009:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** // Etc...
1010:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
1011:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
ARM GAS /tmp/cce2LIhc.s page 42
1012:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1013:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #else
1014:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1015:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** float32_t * pA;
1016:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1017:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if(pSrc != pDst) // out-of-place
669 .loc 4 1017 0
670 0004 8A42 cmp r2, r1
917:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint16_t s, i;
671 .loc 4 917 0
672 0006 85B0 sub sp, sp, #20
673 .LCFI8:
674 .cfi_def_cfa_offset 56
919:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
675 .loc 4 919 0
676 0008 90F801A0 ldrb r10, [r0, #1] @ zero_extendqisi2
677 .LVL65:
917:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** uint16_t s, i;
678 .loc 4 917 0
679 000c CDE90132 strd r3, r2, [sp, #4]
680 .loc 4 1017 0
681 0010 1046 mov r0, r2
682 .LVL66:
683 0012 02D0 beq .L85
1018:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
1019:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
684 .loc 4 1019 0
685 0014 9A00 lsls r2, r3, #2
686 .LVL67:
687 0016 FFF7FEFF bl memcpy
688 .LVL68:
689 .L85:
1020:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pA = pDst;
1021:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
1022:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** else
1023:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** pA = pSrc;
1024:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1025:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
1026:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** if( (blockSize & (blockSize-1)) == 0 ) // Powers of 2 only
690 .loc 4 1026 0
691 001a 019A ldr r2, [sp, #4]
692 001c 531E subs r3, r2, #1
693 001e 1342 tst r3, r2
694 0020 62D1 bne .L84
695 .LVL69:
696 0022 012A cmp r2, #1
697 0024 60D9 bls .L84
1027:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
1028:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(s=2; s<=blockSize; s=s*2)
698 .loc 4 1028 0
699 0026 4FF0020B mov fp, #2
700 002a DC46 mov ip, fp
701 .LVL70:
702 .L87:
703 .LBB58:
704 .LBB59:
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 43
705 .loc 4 44 0
706 002c 0CF18043 add r3, ip, #1073741824
707 0030 013B subs r3, r3, #1
708 0032 9B00 lsls r3, r3, #2
709 0034 0433 adds r3, r3, #4
710 .LBE59:
711 .LBE58:
1029:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
1030:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** for(i=0; i<blockSize; i=i+s)
712 .loc 4 1030 0
713 0036 4FF0000E mov lr, #0
714 003a 0393 str r3, [sp, #12]
715 .LBB63:
716 .LBB60:
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
717 .loc 4 61 0
718 003c 4FEA9C03 lsr r3, ip, #2
719 .LBE60:
720 .LBE63:
721 .loc 4 1030 0
722 0040 F146 mov r9, lr
723 .LBB64:
724 .LBB61:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** leftPtr = pSrc;
725 .loc 4 42 0
726 0042 4FEA5C08 lsr r8, ip, #1
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
727 .loc 4 61 0
728 0046 0093 str r3, [sp]
729 .LVL71:
730 .L96:
731 .LBE61:
732 .LBE64:
1031:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_sort_core_f32(pA+i, s, dir);
733 .loc 4 1031 0 discriminator 3
734 0048 029B ldr r3, [sp, #8]
735 004a 03EB8E0E add lr, r3, lr, lsl #2
736 .LVL72:
737 .LBB65:
738 .LBB62:
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
739 .loc 4 46 0 discriminator 3
740 004e B8F1000F cmp r8, #0
741 0052 19D0 beq .L88
742 0054 039B ldr r3, [sp, #12]
743 0056 7146 mov r1, lr
744 0058 0EEB0302 add r2, lr, r3
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
745 .loc 4 46 0 is_stmt 0
746 005c 0023 movs r3, #0
747 .LVL73:
748 .L90:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
749 .loc 4 48 0 is_stmt 1
750 005e F1EC017A vldmia.32 r1!, {s15}
751 .LVL74:
752 0062 32ED017A vldmdb.32 r2!, {s14}
ARM GAS /tmp/cce2LIhc.s page 44
753 .LVL75:
754 0066 F4EEC77A vcmpe.f32 s15, s14
755 006a F1EE10FA vmrs APSR_nzcv, FPSCR
756 006e CCBF ite gt
757 0070 0120 movgt r0, #1
758 0072 0020 movle r0, #0
759 0074 5045 cmp r0, r10
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
760 .loc 4 46 0
761 0076 03F10103 add r3, r3, #1
762 .LVL76:
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *rightPtr=temp;
763 .loc 4 52 0
764 007a 04BF itt eq
765 007c 01ED017A vstreq.32 s14, [r1, #-4]
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
766 .loc 4 53 0
767 0080 C2ED007A vstreq.32 s15, [r2]
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
768 .loc 4 46 0
769 0084 9845 cmp r8, r3
770 0086 EAD1 bne .L90
771 .LVL77:
772 .L88:
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
773 .loc 4 61 0
774 0088 009B ldr r3, [sp]
775 008a FBB1 cbz r3, .L95
776 008c 1846 mov r0, r3
777 .L97:
778 .LVL78:
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
779 .loc 4 63 0
780 008e 4700 lsls r7, r0, #1
781 0090 7246 mov r2, lr
782 0092 8600 lsls r6, r0, #2
783 0094 0024 movs r4, #0
784 .LVL79:
785 .L94:
786 0096 B518 adds r5, r6, r2
787 0098 2946 mov r1, r5
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
788 .loc 4 68 0
789 009a 0023 movs r3, #0
790 .LVL80:
791 .L93:
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
792 .loc 4 70 0
793 009c F2EC017A vldmia.32 r2!, {s15}
794 .LVL81:
795 00a0 B1EC017A vldmia.32 r1!, {s14}
796 00a4 F4EEC77A vcmpe.f32 s15, s14
797 00a8 F1EE10FA vmrs APSR_nzcv, FPSCR
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
798 .loc 4 68 0
799 00ac 03F10103 add r3, r3, #1
800 .LVL82:
ARM GAS /tmp/cce2LIhc.s page 45
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** *rightPtr=temp;
801 .loc 4 74 0
802 00b0 C4BF itt gt
803 00b2 02ED017A vstrgt.32 s14, [r2, #-4]
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
804 .loc 4 75 0
805 00b6 41ED017A vstrgt.32 s15, [r1, #-4]
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
806 .loc 4 68 0
807 00ba 8342 cmp r3, r0
808 00bc EED3 bcc .L93
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
809 .loc 4 63 0
810 00be 3C44 add r4, r4, r7
811 .LVL83:
812 00c0 6445 cmp r4, ip
813 00c2 05EB0602 add r2, r5, r6
814 .LVL84:
815 00c6 E6D3 bcc .L94
816 .LVL85:
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
817 .loc 4 61 0
818 00c8 4008 lsrs r0, r0, #1
819 .LVL86:
820 00ca E0D1 bne .L97
821 .LVL87:
822 .L95:
823 .LBE62:
824 .LBE65:
1030:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** arm_bitonic_sort_core_f32(pA+i, s, dir);
825 .loc 4 1030 0
826 00cc D944 add r9, r9, fp
827 .LVL88:
828 00ce 019B ldr r3, [sp, #4]
829 00d0 1FFA89F9 uxth r9, r9
830 .LVL89:
831 00d4 9945 cmp r9, r3
832 00d6 CE46 mov lr, r9
833 00d8 B6D3 bcc .L96
1028:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** {
834 .loc 4 1028 0
835 00da 4FEA4B0B lsl fp, fp, #1
836 .LVL90:
837 00de 1FFA8BFB uxth fp, fp
838 .LVL91:
839 00e2 9B45 cmp fp, r3
840 00e4 DC46 mov ip, fp
841 00e6 A1D9 bls .L87
842 .LVL92:
843 .L84:
1032:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
1033:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
1034:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** #endif
1035:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bitonic_sort_f32.c **** }
844 .loc 4 1035 0
845 00e8 05B0 add sp, sp, #20
846 .LCFI9:
ARM GAS /tmp/cce2LIhc.s page 46
847 .cfi_def_cfa_offset 36
848 @ sp needed
849 00ea BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
850 .cfi_endproc
851 .LFE150:
853 00ee 00BF .section .text.arm_bubble_sort_f32,"ax",%progbits
854 .align 1
855 .p2align 2,,3
856 .global arm_bubble_sort_f32
857 .syntax unified
858 .thumb
859 .thumb_func
860 .fpu fpv4-sp-d16
862 arm_bubble_sort_f32:
863 .LFB151:
864 .file 5 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Title: arm_bubble_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Description: Floating point bubble sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** /**
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** @addtogroup Sorting
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** @{
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** /**
ARM GAS /tmp/cce2LIhc.s page 47
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @private
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @param[in] pSrc points to the block of input data.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @param[out] pDst points to the block of output data
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @param[in] blockSize number of samples to process.
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @par Algorithm
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * The bubble sort algorithm is a simple comparison algorithm that
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * reads the elements of a vector from the beginning to the end,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * compares the adjacent ones and swaps them if they are in the
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * wrong order. The procedure is repeated until there is nothing
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * left to swap. Bubble sort is fast for input vectors that are
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * nearly sorted.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** *
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * @par It's an in-place algorithm. In order to obtain an out-of-place
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** * function, a memcpy of the source vector is performed
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** */
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** void arm_bubble_sort_f32(
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** const arm_sort_instance_f32 * S,
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** float32_t * pSrc,
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** float32_t * pDst,
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint32_t blockSize)
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
865 .loc 5 65 0
866 .cfi_startproc
867 @ args = 0, pretend = 0, frame = 0
868 @ frame_needed = 0, uses_anonymous_args = 0
869 .LVL93:
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint8_t dir = S->dir;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint32_t i;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint8_t swapped =1;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** float32_t * pA;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** float32_t temp;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** if(pSrc != pDst) // out-of-place
870 .loc 5 72 0
871 0000 8A42 cmp r2, r1
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint8_t dir = S->dir;
872 .loc 5 65 0
873 0002 F8B5 push {r3, r4, r5, r6, r7, lr}
874 .LCFI10:
875 .cfi_def_cfa_offset 24
876 .cfi_offset 3, -24
877 .cfi_offset 4, -20
878 .cfi_offset 5, -16
879 .cfi_offset 6, -12
880 .cfi_offset 7, -8
881 .cfi_offset 14, -4
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint8_t dir = S->dir;
882 .loc 5 65 0
883 0004 1746 mov r7, r2
884 0006 1E46 mov r6, r3
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint8_t dir = S->dir;
885 .loc 5 66 0
886 0008 4578 ldrb r5, [r0, #1] @ zero_extendqisi2
887 .LVL94:
ARM GAS /tmp/cce2LIhc.s page 48
888 .loc 5 72 0
889 000a 03D0 beq .L113
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
890 .loc 5 74 0
891 000c 9A00 lsls r2, r3, #2
892 .LVL95:
893 000e 3846 mov r0, r7
894 .LVL96:
895 0010 FFF7FEFF bl memcpy
896 .LVL97:
897 .L113:
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA = pDst;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** else
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA = pSrc;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** while(swapped==1) // If nothing has been swapped after one loop stop
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** swapped=0;
898 .loc 5 82 0
899 0014 0023 movs r3, #0
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** for(i=0; i<blockSize-1; i++)
900 .loc 5 84 0
901 0016 1946 mov r1, r3
902 .LVL98:
903 .L114:
904 .loc 5 84 0 is_stmt 0 discriminator 1
905 0018 701E subs r0, r6, #1
906 001a 8842 cmp r0, r1
907 001c 21D9 bls .L123
908 .LVL99:
909 .L117:
910 001e 07EB8102 add r2, r7, r1, lsl #2
911 .L115:
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** if(dir==(pA[i]>pA[i+1]))
912 .loc 5 86 0 is_stmt 1
913 0022 D2ED007A vldr.32 s15, [r2]
914 0026 0432 adds r2, r2, #4
915 0028 92ED007A vldr.32 s14, [r2]
916 002c F4EEC77A vcmpe.f32 s15, s14
917 0030 F1EE10FA vmrs APSR_nzcv, FPSCR
918 0034 CCBF ite gt
919 0036 0124 movgt r4, #1
920 0038 0024 movle r4, #0
921 003a AC42 cmp r4, r5
922 003c 01F10101 add r1, r1, #1
923 0040 EAD1 bne .L114
924 .LVL100:
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
925 .loc 5 84 0
926 0042 8142 cmp r1, r0
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** // Swap
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** temp = pA[i];
ARM GAS /tmp/cce2LIhc.s page 49
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA[i] = pA[i+1];
927 .loc 5 90 0
928 0044 02ED017A vstr.32 s14, [r2, #-4]
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA[i+1] = temp;
929 .loc 5 91 0
930 0048 C2ED007A vstr.32 s15, [r2]
931 .LVL101:
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** // Update flag
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** swapped = 1;
932 .loc 5 94 0
933 004c 4FF00103 mov r3, #1
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
934 .loc 5 84 0
935 0050 E7D3 bcc .L115
936 0052 0646 mov r6, r0
937 .LVL102:
938 0054 0021 movs r1, #0
939 0056 012E cmp r6, #1
940 0058 00F1FF30 add r0, r0, #-1
941 005c 0B46 mov r3, r1
942 005e DED1 bne .L117
943 .LVL103:
944 .L112:
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** blockSize--;
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
945 .loc 5 100 0
946 0060 F8BD pop {r3, r4, r5, r6, r7, pc}
947 .LVL104:
948 .L123:
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
949 .loc 5 80 0
950 0062 002B cmp r3, #0
951 0064 FCD0 beq .L112
952 0066 0646 mov r6, r0
953 .LVL105:
954 0068 0021 movs r1, #0
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
955 .loc 5 84 0
956 006a 012E cmp r6, #1
957 006c 00F1FF30 add r0, r0, #-1
958 .LVL106:
959 0070 0B46 mov r3, r1
960 0072 D4D1 bne .L117
961 0074 F4E7 b .L112
962 .cfi_endproc
963 .LFE151:
965 0076 00BF .section .text.arm_copy_f32,"ax",%progbits
966 .align 1
967 .p2align 2,,3
968 .global arm_copy_f32
969 .syntax unified
970 .thumb
ARM GAS /tmp/cce2LIhc.s page 50
971 .thumb_func
972 .fpu fpv4-sp-d16
974 arm_copy_f32:
975 .LFB152:
976 .file 6 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Title: arm_copy_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Description: Copies the elements of a floating-point vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @defgroup copy Vector Copy
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** Copies sample by sample from source vector to destination vector.
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** <pre>
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** pDst[n] = pSrc[n]; 0 <= n < blockSize.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** </pre>
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** There are separate functions for floating point, Q31, Q15, and Q7 data types.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /**
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @addtogroup copy
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @{
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /**
ARM GAS /tmp/cce2LIhc.s page 51
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @brief Copies the elements of a floating-point vector.
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @param[in] pSrc points to input vector
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @param[out] pDst points to output vector
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @param[in] blockSize number of samples in each vector
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** @return none
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** void arm_copy_f32(
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** const float32_t * pSrc,
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** float32_t * pDst,
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blockSize)
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blkCnt;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize >> 2U;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Compute 4 outputs at a time */
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** vstrwq_f32(pDst, vldrwq_f32(pSrc));
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /*
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Decrement the blockSize loop counter
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** * Advance vector source and destination pointers
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** */
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** pSrc += 4;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** pDst += 4;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt --;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize & 3;
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* C = A */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Copy and store result in destination buffer */
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Decrement loop counter */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt--;
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #else
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #if defined(ARM_MATH_NEON_EXPERIMENTAL)
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** void arm_copy_f32(
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** const float32_t * pSrc,
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** float32_t * pDst,
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blockSize)
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blkCnt; /* loop counter */
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** float32x4_t inV;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize >> 2U;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 52
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Compute 4 outputs at a time.
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** ** a second loop below computes the remaining 1 to 3 samples. */
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* C = A */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Copy and then store the results in the destination buffer */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** inV = vld1q_f32(pSrc);
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** vst1q_f32(pDst, inV);
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** pSrc += 4;
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** pDst += 4;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Decrement the loop counter */
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt--;
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** ** No loop unrolling is used. */
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize & 3;
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* C = A */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Copy and then store the results in the destination buffer */
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Decrement the loop counter */
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt--;
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #else
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** void arm_copy_f32(
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** const float32_t * pSrc,
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** float32_t * pDst,
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blockSize)
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
977 .loc 6 144 0
978 .cfi_startproc
979 @ args = 0, pretend = 0, frame = 0
980 @ frame_needed = 0, uses_anonymous_args = 0
981 @ link register save eliminated.
982 .LVL107:
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** uint32_t blkCnt; /* Loop counter */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #if defined (ARM_MATH_LOOPUNROLL)
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Loop unrolling: Compute 4 outputs at a time */
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize >> 2U;
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* C = A */
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Copy and store result in destination buffer */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
ARM GAS /tmp/cce2LIhc.s page 53
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Decrement loop counter */
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt--;
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Loop unrolling: Compute remaining outputs */
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize % 0x4U;
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #else
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Initialize blkCnt with number of samples */
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt = blockSize;
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** while (blkCnt > 0U)
983 .loc 6 176 0
984 0000 2AB1 cbz r2, .L124
985 .LVL108:
986 .L126:
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* C = A */
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Copy and store result in destination buffer */
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** *pDst++ = *pSrc++;
987 .loc 6 181 0
988 0002 50F8043B ldr r3, [r0], #4 @ float
989 .LVL109:
990 0006 41F8043B str r3, [r1], #4 @ float
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** {
991 .loc 6 176 0
992 000a 013A subs r2, r2, #1
993 .LVL110:
994 000c F9D1 bne .L126
995 .LVL111:
996 .L124:
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c ****
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** /* Decrement loop counter */
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** blkCnt--;
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c **** }
997 .loc 6 186 0
998 000e 7047 bx lr
999 .cfi_endproc
1000 .LFE152:
1002 .section .text.arm_copy_q15,"ax",%progbits
1003 .align 1
1004 .p2align 2,,3
1005 .global arm_copy_q15
1006 .syntax unified
1007 .thumb
1008 .thumb_func
1009 .fpu fpv4-sp-d16
1011 arm_copy_q15:
1012 .LFB153:
1013 .file 7 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* ----------------------------------------------------------------------
ARM GAS /tmp/cce2LIhc.s page 54
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Title: arm_copy_q15.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Description: Copies the elements of a Q15 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @addtogroup copy
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @brief Copies the elements of a Q15 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @param[in] pSrc points to input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** void arm_copy_q15(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** const q15_t * pSrc,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** q15_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** uint32_t blkCnt;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt = blockSize >> 3;
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** while (blkCnt > 0U)
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** vstrhq_s16(pDst,vldrhq_s16(pSrc));
ARM GAS /tmp/cce2LIhc.s page 55
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /*
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Decrement the blockSize loop counter
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** * Advance vector source and destination pointers
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** */
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** pSrc += 8;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** pDst += 8;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt --;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt = blockSize & 7;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** while (blkCnt > 0U)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* C = A */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Copy and store result in destination buffer */
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *pDst++ = *pSrc++;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Decrement loop counter */
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt--;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #else
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** void arm_copy_q15(
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** const q15_t * pSrc,
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** q15_t * pDst,
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** uint32_t blockSize)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
1014 .loc 7 85 0
1015 .cfi_startproc
1016 @ args = 0, pretend = 0, frame = 0
1017 @ frame_needed = 0, uses_anonymous_args = 0
1018 @ link register save eliminated.
1019 .LVL112:
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** uint32_t blkCnt; /* Loop counter */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #if defined (ARM_MATH_LOOPUNROLL)
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Loop unrolling: Compute 4 outputs at a time */
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt = blockSize >> 2U;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** while (blkCnt > 0U)
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* C = A */
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* read 2 times 2 samples at a time */
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc));
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc));
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Decrement loop counter */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt--;
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Loop unrolling: Compute remaining outputs */
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt = blockSize % 0x4U;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #else
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
ARM GAS /tmp/cce2LIhc.s page 56
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Initialize blkCnt with number of samples */
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt = blockSize;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** while (blkCnt > 0U)
1020 .loc 7 115 0
1021 0000 002A cmp r2, #0
1022 0002 41D0 beq .L155
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** uint32_t blkCnt; /* Loop counter */
1023 .loc 7 85 0
1024 0004 F0B4 push {r4, r5, r6, r7}
1025 .LCFI11:
1026 .cfi_def_cfa_offset 16
1027 .cfi_offset 4, -16
1028 .cfi_offset 5, -12
1029 .cfi_offset 6, -8
1030 .cfi_offset 7, -4
1031 0006 031D adds r3, r0, #4
1032 0008 0C1D adds r4, r1, #4
1033 000a A042 cmp r0, r4
1034 000c 38BF it cc
1035 000e 9942 cmpcc r1, r3
1036 0010 31D3 bcc .L133
1037 0012 0D2A cmp r2, #13
1038 0014 2FD9 bls .L133
1039 0016 C0F34003 ubfx r3, r0, #1, #1
1040 001a 561E subs r6, r2, #1
1041 001c 3BB3 cbz r3, .L139
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* C = A */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Copy and store result in destination buffer */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** *pDst++ = *pSrc++;
1042 .loc 7 120 0
1043 001e B0F90040 ldrsh r4, [r0]
1044 0022 0C80 strh r4, [r1] @ movhi
1045 0024 00F1020C add ip, r0, #2
1046 .LVL113:
1047 0028 8F1C adds r7, r1, #2
1048 .LVL114:
1049 .L134:
1050 002a D21A subs r2, r2, r3
1051 .LVL115:
1052 002c 5B00 lsls r3, r3, #1
1053 002e 1844 add r0, r0, r3
1054 0030 1944 add r1, r1, r3
1055 0032 5508 lsrs r5, r2, #1
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
1056 .loc 7 115 0
1057 0034 0023 movs r3, #0
1058 .LVL116:
1059 .L135:
1060 0036 0133 adds r3, r3, #1
1061 .loc 7 120 0
1062 0038 50F8044B ldr r4, [r0], #4
1063 003c 41F8044B str r4, [r1], #4 @ unaligned
ARM GAS /tmp/cce2LIhc.s page 57
1064 0040 AB42 cmp r3, r5
1065 0042 F8D3 bcc .L135
1066 0044 22F00103 bic r3, r2, #1
1067 0048 5900 lsls r1, r3, #1
1068 004a 9A42 cmp r2, r3
1069 004c 0CEB0100 add r0, ip, r1
1070 0050 A6EB0306 sub r6, r6, r3
1071 0054 3944 add r1, r1, r7
1072 0056 08D0 beq .L131
1073 .LVL117:
1074 0058 3CF91320 ldrsh r2, [ip, r3, lsl #1]
1075 005c 27F81320 strh r2, [r7, r3, lsl #1] @ movhi
1076 .LVL118:
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
1077 .loc 7 115 0
1078 0060 012E cmp r6, #1
1079 0062 02D0 beq .L131
1080 .LVL119:
1081 .loc 7 120 0
1082 0064 B0F90230 ldrsh r3, [r0, #2]
1083 0068 4B80 strh r3, [r1, #2] @ movhi
1084 .LVL120:
1085 .L131:
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** /* Decrement loop counter */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** blkCnt--;
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** }
1086 .loc 7 125 0
1087 006a F0BC pop {r4, r5, r6, r7}
1088 .LCFI12:
1089 .cfi_remember_state
1090 .cfi_restore 7
1091 .cfi_restore 6
1092 .cfi_restore 5
1093 .cfi_restore 4
1094 .cfi_def_cfa_offset 0
1095 006c 7047 bx lr
1096 .LVL121:
1097 .L139:
1098 .LCFI13:
1099 .cfi_restore_state
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
1100 .loc 7 115 0
1101 006e 1646 mov r6, r2
1102 0070 0F46 mov r7, r1
1103 0072 8446 mov ip, r0
1104 0074 D9E7 b .L134
1105 .L133:
1106 0076 0239 subs r1, r1, #2
1107 .LVL122:
1108 .L137:
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c ****
1109 .loc 7 120 0
1110 0078 30F9023B ldrsh r3, [r0], #2
1111 .LVL123:
1112 007c 21F8023F strh r3, [r1, #2]! @ movhi
ARM GAS /tmp/cce2LIhc.s page 58
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c **** {
1113 .loc 7 115 0
1114 0080 013A subs r2, r2, #1
1115 .LVL124:
1116 0082 F9D1 bne .L137
1117 .loc 7 125 0
1118 0084 F0BC pop {r4, r5, r6, r7}
1119 .LCFI14:
1120 .cfi_restore 7
1121 .cfi_restore 6
1122 .cfi_restore 5
1123 .cfi_restore 4
1124 .cfi_def_cfa_offset 0
1125 .LVL125:
1126 0086 7047 bx lr
1127 .LVL126:
1128 .L155:
1129 0088 7047 bx lr
1130 .cfi_endproc
1131 .LFE153:
1133 008a 00BF .section .text.arm_copy_q31,"ax",%progbits
1134 .align 1
1135 .p2align 2,,3
1136 .global arm_copy_q31
1137 .syntax unified
1138 .thumb
1139 .thumb_func
1140 .fpu fpv4-sp-d16
1142 arm_copy_q31:
1143 .LFB154:
1144 .file 8 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Title: arm_copy_q31.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Description: Copies the elements of a Q31 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * limitations under the License.
ARM GAS /tmp/cce2LIhc.s page 59
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @addtogroup copy
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @brief Copies the elements of a Q31 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @param[in] pSrc points to input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** void arm_copy_q31(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** const q31_t * pSrc,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** q31_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** uint32_t blkCnt;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt = blockSize >> 2U;
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Compute 4 outputs at a time */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** while (blkCnt > 0U)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** vstrwq_s32(pDst,vldrwq_s32(pSrc));
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /*
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Decrement the blockSize loop counter
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** * Advance vector source and destination pointers
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** */
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** pSrc += 4;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** pDst += 4;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt --;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt = blockSize & 3;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** while (blkCnt > 0U)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* C = A */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Copy and store result in destination buffer */
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Decrement loop counter */
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt--;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #else
ARM GAS /tmp/cce2LIhc.s page 60
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** void arm_copy_q31(
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** const q31_t * pSrc,
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** q31_t * pDst,
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** uint32_t blockSize)
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
1145 .loc 8 88 0
1146 .cfi_startproc
1147 @ args = 0, pretend = 0, frame = 0
1148 @ frame_needed = 0, uses_anonymous_args = 0
1149 @ link register save eliminated.
1150 .LVL127:
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** uint32_t blkCnt; /* Loop counter */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Loop unrolling: Compute 4 outputs at a time */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt = blockSize >> 2U;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** while (blkCnt > 0U)
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* C = A */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Copy and store result in destination buffer */
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Decrement loop counter */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt--;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Loop unrolling: Compute remaining outputs */
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt = blockSize % 0x4U;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #else
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Initialize blkCnt with number of samples */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt = blockSize;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** while (blkCnt > 0U)
1151 .loc 8 120 0
1152 0000 32B1 cbz r2, .L158
1153 0002 0439 subs r1, r1, #4
1154 .LVL128:
1155 .L160:
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* C = A */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Copy and store result in destination buffer */
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** *pDst++ = *pSrc++;
1156 .loc 8 125 0
1157 0004 50F8043B ldr r3, [r0], #4
1158 .LVL129:
1159 0008 41F8043F str r3, [r1, #4]!
ARM GAS /tmp/cce2LIhc.s page 61
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** {
1160 .loc 8 120 0
1161 000c 013A subs r2, r2, #1
1162 .LVL130:
1163 000e F9D1 bne .L160
1164 .LVL131:
1165 .L158:
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** /* Decrement loop counter */
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** blkCnt--;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c **** }
1166 .loc 8 130 0
1167 0010 7047 bx lr
1168 .cfi_endproc
1169 .LFE154:
1171 .section .text.arm_copy_q7,"ax",%progbits
1172 .align 1
1173 .p2align 2,,3
1174 .global arm_copy_q7
1175 .syntax unified
1176 .thumb
1177 .thumb_func
1178 .fpu fpv4-sp-d16
1180 arm_copy_q7:
1181 .LFB155:
1182 .file 9 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Title: arm_copy_q7.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Description: Copies the elements of a Q7 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
ARM GAS /tmp/cce2LIhc.s page 62
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @addtogroup copy
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @brief Copies the elements of a Q7 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @param[in] pSrc points to input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** void arm_copy_q7(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** const q7_t * pSrc,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** q7_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** uint32_t blkCnt;
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt = blockSize >> 4;
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** while (blkCnt > 0U)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** vstrbq_s8(pDst,vldrbq_s8(pSrc));
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /*
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Decrement the blockSize loop counter
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** * Advance vector source and destination pointers
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** */
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** pSrc += 16;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** pDst += 16;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt --;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt = blockSize & 0xF;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** while (blkCnt > 0U)
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* C = A */
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Copy and store result in destination buffer */
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *pDst++ = *pSrc++;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Decrement loop counter */
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt--;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #else
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** void arm_copy_q7(
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** const q7_t * pSrc,
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** q7_t * pDst,
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** uint32_t blockSize)
ARM GAS /tmp/cce2LIhc.s page 63
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1183 .loc 9 88 0
1184 .cfi_startproc
1185 @ args = 0, pretend = 0, frame = 0
1186 @ frame_needed = 0, uses_anonymous_args = 0
1187 @ link register save eliminated.
1188 .LVL132:
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** uint32_t blkCnt; /* Loop counter */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #if defined (ARM_MATH_LOOPUNROLL)
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Loop unrolling: Compute 4 outputs at a time */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt = blockSize >> 2U;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** while (blkCnt > 0U)
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* C = A */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* read 4 samples at a time */
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** write_q7x4_ia (&pDst, read_q7x4_ia ((q7_t **) &pSrc));
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Decrement loop counter */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt--;
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Loop unrolling: Compute remaining outputs */
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt = blockSize % 0x4U;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #else
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Initialize blkCnt with number of samples */
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt = blockSize;
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** while (blkCnt > 0U)
1189 .loc 9 117 0
1190 0000 002A cmp r2, #0
1191 0002 6BD0 beq .L205
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** uint32_t blkCnt; /* Loop counter */
1192 .loc 9 88 0
1193 0004 F0B4 push {r4, r5, r6, r7}
1194 .LCFI15:
1195 .cfi_def_cfa_offset 16
1196 .cfi_offset 4, -16
1197 .cfi_offset 5, -12
1198 .cfi_offset 6, -8
1199 .cfi_offset 7, -4
1200 0006 031D adds r3, r0, #4
1201 0008 0C1D adds r4, r1, #4
1202 000a A042 cmp r0, r4
1203 000c 38BF it cc
1204 000e 9942 cmpcc r1, r3
1205 0010 5AD3 bcc .L167
1206 0012 0B2A cmp r2, #11
1207 0014 58D9 bls .L167
1208 0016 4342 negs r3, r0
ARM GAS /tmp/cce2LIhc.s page 64
1209 0018 13F00303 ands r3, r3, #3
1210 001c 02F1FF35 add r5, r2, #-1
1211 0020 4ED0 beq .L174
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* C = A */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Copy and store result in destination buffer */
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** *pDst++ = *pSrc++;
1212 .loc 9 122 0
1213 0022 90F90040 ldrsb r4, [r0]
1214 0026 0C70 strb r4, [r1]
1215 0028 012B cmp r3, #1
1216 002a 00F1010C add ip, r0, #1
1217 .LVL133:
1218 002e 01F10107 add r7, r1, #1
1219 .LVL134:
1220 0032 11D0 beq .L168
1221 .LVL135:
1222 0034 90F90140 ldrsb r4, [r0, #1]
1223 0038 4C70 strb r4, [r1, #1]
1224 003a 032B cmp r3, #3
1225 003c 00F1020C add ip, r0, #2
1226 .LVL136:
1227 0040 01F10207 add r7, r1, #2
1228 .LVL137:
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** /* Decrement loop counter */
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** blkCnt--;
1229 .loc 9 125 0
1230 0044 A2F10205 sub r5, r2, #2
1231 .LVL138:
1232 0048 06D1 bne .L168
1233 .LVL139:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1234 .loc 9 122 0
1235 004a 90F90240 ldrsb r4, [r0, #2]
1236 004e 8C70 strb r4, [r1, #2]
1237 0050 00F1030C add ip, r0, #3
1238 .LVL140:
1239 0054 CF1C adds r7, r1, #3
1240 .LVL141:
1241 .loc 9 125 0
1242 0056 D51E subs r5, r2, #3
1243 .LVL142:
1244 .L168:
1245 0058 D21A subs r2, r2, r3
1246 .LVL143:
1247 005a 1844 add r0, r0, r3
1248 005c 1944 add r1, r1, r3
1249 005e 9608 lsrs r6, r2, #2
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1250 .loc 9 117 0
1251 0060 0023 movs r3, #0
1252 .L170:
1253 0062 0133 adds r3, r3, #1
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1254 .loc 9 122 0
ARM GAS /tmp/cce2LIhc.s page 65
1255 0064 50F8044B ldr r4, [r0], #4
1256 0068 41F8044B str r4, [r1], #4 @ unaligned
1257 006c 9E42 cmp r6, r3
1258 006e F8D8 bhi .L170
1259 0070 22F00301 bic r1, r2, #3
1260 0074 8A42 cmp r2, r1
1261 0076 A5EB0103 sub r3, r5, r1
1262 007a 0CEB0104 add r4, ip, r1
1263 007e 07EB0100 add r0, r7, r1
1264 0082 1BD0 beq .L165
1265 .LVL144:
1266 0084 1CF90120 ldrsb r2, [ip, r1]
1267 0088 7A54 strb r2, [r7, r1]
1268 .LVL145:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1269 .loc 9 117 0
1270 008a 012B cmp r3, #1
1271 008c 16D0 beq .L165
1272 .LVL146:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1273 .loc 9 122 0
1274 008e 94F90120 ldrsb r2, [r4, #1]
1275 0092 4270 strb r2, [r0, #1]
1276 .LVL147:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1277 .loc 9 117 0
1278 0094 022B cmp r3, #2
1279 0096 11D0 beq .L165
1280 .LVL148:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1281 .loc 9 122 0
1282 0098 94F90220 ldrsb r2, [r4, #2]
1283 009c 8270 strb r2, [r0, #2]
1284 .LVL149:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1285 .loc 9 117 0
1286 009e 032B cmp r3, #3
1287 00a0 0CD0 beq .L165
1288 .LVL150:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1289 .loc 9 122 0
1290 00a2 94F90320 ldrsb r2, [r4, #3]
1291 00a6 C270 strb r2, [r0, #3]
1292 .LVL151:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1293 .loc 9 117 0
1294 00a8 042B cmp r3, #4
1295 00aa 07D0 beq .L165
1296 .LVL152:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1297 .loc 9 122 0
1298 00ac 94F90420 ldrsb r2, [r4, #4]
1299 00b0 0271 strb r2, [r0, #4]
1300 .LVL153:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1301 .loc 9 117 0
1302 00b2 052B cmp r3, #5
ARM GAS /tmp/cce2LIhc.s page 66
1303 00b4 02D0 beq .L165
1304 .LVL154:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1305 .loc 9 122 0
1306 00b6 94F90530 ldrsb r3, [r4, #5]
1307 .LVL155:
1308 00ba 4371 strb r3, [r0, #5]
1309 .LVL156:
1310 .L165:
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** }
1311 .loc 9 127 0
1312 00bc F0BC pop {r4, r5, r6, r7}
1313 .LCFI16:
1314 .cfi_remember_state
1315 .cfi_restore 7
1316 .cfi_restore 6
1317 .cfi_restore 5
1318 .cfi_restore 4
1319 .cfi_def_cfa_offset 0
1320 00be 7047 bx lr
1321 .LVL157:
1322 .L174:
1323 .LCFI17:
1324 .cfi_restore_state
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1325 .loc 9 117 0
1326 00c0 1546 mov r5, r2
1327 00c2 0F46 mov r7, r1
1328 00c4 8446 mov ip, r0
1329 00c6 C7E7 b .L168
1330 .L167:
1331 00c8 0139 subs r1, r1, #1
1332 .LVL158:
1333 00ca 0244 add r2, r2, r0
1334 .LVL159:
1335 .L172:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c ****
1336 .loc 9 122 0
1337 00cc 10F9013B ldrsb r3, [r0], #1
1338 .LVL160:
1339 00d0 01F8013F strb r3, [r1, #1]!
1340 .LVL161:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c **** {
1341 .loc 9 117 0
1342 00d4 9042 cmp r0, r2
1343 00d6 F9D1 bne .L172
1344 .loc 9 127 0
1345 00d8 F0BC pop {r4, r5, r6, r7}
1346 .LCFI18:
1347 .cfi_restore 7
1348 .cfi_restore 6
1349 .cfi_restore 5
1350 .cfi_restore 4
1351 .cfi_def_cfa_offset 0
1352 .LVL162:
1353 00da 7047 bx lr
ARM GAS /tmp/cce2LIhc.s page 67
1354 .LVL163:
1355 .L205:
1356 00dc 7047 bx lr
1357 .cfi_endproc
1358 .LFE155:
1360 00de 00BF .section .text.arm_fill_f32,"ax",%progbits
1361 .align 1
1362 .p2align 2,,3
1363 .global arm_fill_f32
1364 .syntax unified
1365 .thumb
1366 .thumb_func
1367 .fpu fpv4-sp-d16
1369 arm_fill_f32:
1370 .LFB156:
1371 .file 10 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Title: arm_fill_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Description: Fills a constant value into a floating-point vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @defgroup Fill Vector Fill
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** Fills the destination vector with a constant value.
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** <pre>
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** pDst[n] = value; 0 <= n < blockSize.
ARM GAS /tmp/cce2LIhc.s page 68
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** </pre>
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** There are separate functions for floating point, Q31, Q15, and Q7 data types.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /**
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @addtogroup Fill
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @{
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /**
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @brief Fills a constant value into a floating-point vector.
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @param[in] value input value to be filled
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @param[out] pDst points to output vector
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @param[in] blockSize number of samples in each vector
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** @return none
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** void arm_fill_f32(
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t value,
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t * pDst,
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blockSize)
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blkCnt;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize >> 2U;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Compute 4 outputs at a time */
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** vstrwq_f32(pDst,vdupq_n_f32(value));
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /*
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Decrement the blockSize loop counter
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** * Advance vector source and destination pointers
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** */
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** pDst += 4;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt --;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize & 3;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* C = value */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Fill value in destination buffer */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Decrement loop counter */
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt--;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #else
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #if defined(ARM_MATH_NEON_EXPERIMENTAL)
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** void arm_fill_f32(
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t value,
ARM GAS /tmp/cce2LIhc.s page 69
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t * pDst,
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blockSize)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blkCnt; /* loop counter */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32x4_t inV = vdupq_n_f32(value);
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize >> 2U;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Compute 4 outputs at a time.
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** ** a second loop below computes the remaining 1 to 3 samples. */
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* C = value */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Fill the value in the destination buffer */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** vst1q_f32(pDst, inV);
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** pDst += 4;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Decrement the loop counter */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt--;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** ** No loop unrolling is used. */
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize & 3;
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* C = value */
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Fill the value in the destination buffer */
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Decrement the loop counter */
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt--;
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #else
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** void arm_fill_f32(
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t value,
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** float32_t * pDst,
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blockSize)
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
1372 .loc 10 141 0
1373 .cfi_startproc
1374 @ args = 0, pretend = 0, frame = 0
1375 @ frame_needed = 0, uses_anonymous_args = 0
1376 @ link register save eliminated.
1377 .LVL164:
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** uint32_t blkCnt; /* Loop counter */
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #if defined (ARM_MATH_LOOPUNROLL)
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Loop unrolling: Compute 4 outputs at a time */
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize >> 2U;
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
ARM GAS /tmp/cce2LIhc.s page 70
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* C = value */
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Fill value in destination buffer */
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Decrement loop counter */
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt--;
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Loop unrolling: Compute remaining outputs */
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize % 0x4U;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #else
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Initialize blkCnt with number of samples */
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt = blockSize;
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** while (blkCnt > 0U)
1378 .loc 10 173 0
1379 0000 19B1 cbz r1, .L208
1380 .LVL165:
1381 .L210:
1382 0002 0139 subs r1, r1, #1
1383 .LVL166:
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* C = value */
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Fill value in destination buffer */
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** *pDst++ = value;
1384 .loc 10 178 0
1385 0004 A0EC010A vstmia.32 r0!, {s0}
1386 .LVL167:
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** {
1387 .loc 10 173 0
1388 0008 FBD1 bne .L210
1389 .L208:
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c ****
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** /* Decrement loop counter */
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** blkCnt--;
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c **** }
1390 .loc 10 183 0
1391 000a 7047 bx lr
1392 .cfi_endproc
1393 .LFE156:
1395 .section .text.arm_fill_q15,"ax",%progbits
1396 .align 1
1397 .p2align 2,,3
1398 .global arm_fill_q15
1399 .syntax unified
1400 .thumb
ARM GAS /tmp/cce2LIhc.s page 71
1401 .thumb_func
1402 .fpu fpv4-sp-d16
1404 arm_fill_q15:
1405 .LFB157:
1406 .file 11 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Title: arm_fill_q15.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Description: Fills a constant value into a Q15 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @addtogroup Fill
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @brief Fills a constant value into a Q15 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @param[in] value input value to be filled
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** void arm_fill_q15(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** q15_t value,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** q15_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
ARM GAS /tmp/cce2LIhc.s page 72
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** uint32_t blkCnt;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt = blockSize >> 3;
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** while (blkCnt > 0U)
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** vstrhq_s16(pDst,vdupq_n_s16(value));
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /*
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Decrement the blockSize loop counter
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** * Advance vector source and destination pointers
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** */
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** pDst += 8;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt --;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt = blockSize & 7;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** while (blkCnt > 0U)
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* C = value */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Fill value in destination buffer */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *pDst++ = value;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Decrement loop counter */
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt--;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #else
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** void arm_fill_q15(
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** q15_t value,
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** q15_t * pDst,
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** uint32_t blockSize)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1407 .loc 11 85 0
1408 .cfi_startproc
1409 @ args = 0, pretend = 0, frame = 0
1410 @ frame_needed = 0, uses_anonymous_args = 0
1411 @ link register save eliminated.
1412 .LVL168:
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** uint32_t blkCnt; /* Loop counter */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #if defined (ARM_MATH_LOOPUNROLL)
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** q31_t packedValue; /* value packed to 32 bits */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Packing two 16 bit values to 32 bit value in order to use SIMD */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** packedValue = __PKHBT(value, value, 16U);
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Loop unrolling: Compute 4 outputs at a time */
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt = blockSize >> 2U;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** while (blkCnt > 0U)
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* C = value */
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* fill 2 times 2 samples at a time */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** write_q15x2_ia (&pDst, packedValue);
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** write_q15x2_ia (&pDst, packedValue);
ARM GAS /tmp/cce2LIhc.s page 73
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Decrement loop counter */
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt--;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Loop unrolling: Compute remaining outputs */
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt = blockSize % 0x4U;
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #else
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Initialize blkCnt with number of samples */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt = blockSize;
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** while (blkCnt > 0U)
1413 .loc 11 119 0
1414 0000 92B3 cbz r2, .L239
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** uint32_t blkCnt; /* Loop counter */
1415 .loc 11 85 0
1416 0002 F0B4 push {r4, r5, r6, r7}
1417 .LCFI19:
1418 .cfi_def_cfa_offset 16
1419 .cfi_offset 4, -16
1420 .cfi_offset 5, -12
1421 .cfi_offset 6, -8
1422 .cfi_offset 7, -4
1423 0004 551E subs r5, r2, #1
1424 0006 042D cmp r5, #4
1425 0008 2C46 mov r4, r5
1426 000a C1F34003 ubfx r3, r1, #1, #1
1427 000e 1AD9 bls .L217
1428 0010 3BB3 cbz r3, .L221
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* C = value */
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Fill value in destination buffer */
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** *pDst++ = value;
1429 .loc 11 124 0
1430 0012 0880 strh r0, [r1] @ movhi
1431 0014 8F1C adds r7, r1, #2
1432 .LVL169:
1433 .L218:
1434 0016 0024 movs r4, #0
1435 0018 D61A subs r6, r2, r3
1436 001a 60F30F04 bfi r4, r0, #0, #16
1437 .LVL170:
1438 001e 01EB4301 add r1, r1, r3, lsl #1
1439 0022 60F31F44 bfi r4, r0, #16, #16
1440 0026 7208 lsrs r2, r6, #1
1441 .LVL171:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1442 .loc 11 119 0
1443 0028 0023 movs r3, #0
1444 .LVL172:
1445 .L219:
1446 002a 0133 adds r3, r3, #1
ARM GAS /tmp/cce2LIhc.s page 74
1447 002c 9342 cmp r3, r2
1448 .loc 11 124 0
1449 002e 41F8044B str r4, [r1], #4
1450 0032 FAD3 bcc .L219
1451 0034 26F00103 bic r3, r6, #1
1452 0038 9E42 cmp r6, r3
1453 003a 07EB4301 add r1, r7, r3, lsl #1
1454 003e A5EB0302 sub r2, r5, r3
1455 0042 0CD0 beq .L215
1456 0044 541E subs r4, r2, #1
1457 .L217:
1458 .LVL173:
1459 0046 0880 strh r0, [r1] @ movhi
1460 .LVL174:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1461 .loc 11 119 0
1462 0048 4CB1 cbz r4, .L215
1463 .LVL175:
1464 004a 022A cmp r2, #2
1465 .loc 11 124 0
1466 004c 4880 strh r0, [r1, #2] @ movhi
1467 .LVL176:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1468 .loc 11 119 0
1469 004e 06D0 beq .L215
1470 .LVL177:
1471 0050 032A cmp r2, #3
1472 .loc 11 124 0
1473 0052 8880 strh r0, [r1, #4] @ movhi
1474 .LVL178:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1475 .loc 11 119 0
1476 0054 03D0 beq .L215
1477 .LVL179:
1478 0056 042A cmp r2, #4
1479 .loc 11 124 0
1480 0058 C880 strh r0, [r1, #6] @ movhi
1481 .LVL180:
1482 005a 18BF it ne
1483 005c 0881 strhne r0, [r1, #8] @ movhi
1484 .LVL181:
1485 .L215:
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c ****
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** /* Decrement loop counter */
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** blkCnt--;
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** }
1486 .loc 11 129 0
1487 005e F0BC pop {r4, r5, r6, r7}
1488 .LCFI20:
1489 .cfi_remember_state
1490 .cfi_restore 7
1491 .cfi_restore 6
1492 .cfi_restore 5
1493 .cfi_restore 4
1494 .cfi_def_cfa_offset 0
1495 0060 7047 bx lr
ARM GAS /tmp/cce2LIhc.s page 75
1496 .LVL182:
1497 .L221:
1498 .LCFI21:
1499 .cfi_restore_state
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c **** {
1500 .loc 11 119 0
1501 0062 1546 mov r5, r2
1502 0064 0F46 mov r7, r1
1503 0066 D6E7 b .L218
1504 .L239:
1505 .LCFI22:
1506 .cfi_def_cfa_offset 0
1507 .cfi_restore 4
1508 .cfi_restore 5
1509 .cfi_restore 6
1510 .cfi_restore 7
1511 0068 7047 bx lr
1512 .cfi_endproc
1513 .LFE157:
1515 006a 00BF .section .text.arm_fill_q31,"ax",%progbits
1516 .align 1
1517 .p2align 2,,3
1518 .global arm_fill_q31
1519 .syntax unified
1520 .thumb
1521 .thumb_func
1522 .fpu fpv4-sp-d16
1524 arm_fill_q31:
1525 .LFB158:
1526 .file 12 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Title: arm_fill_q31.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Description: Fills a constant value into a Q31 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** */
ARM GAS /tmp/cce2LIhc.s page 76
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @addtogroup Fill
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @brief Fills a constant value into a Q31 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @param[in] value input value to be filled
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** void arm_fill_q31(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** q31_t value,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** q31_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** uint32_t blkCnt;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt = blockSize >> 2U;
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Compute 4 outputs at a time */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** while (blkCnt > 0U)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** vstrwq_s32(pDst,vdupq_n_s32(value));
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /*
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Decrement the blockSize loop counter
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** * Advance vector source and destination pointers
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** */
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** pDst += 4;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt --;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt = blockSize & 3;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** while (blkCnt > 0U)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* C = value */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Fill value in destination buffer */
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Decrement loop counter */
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt--;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #else
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** void arm_fill_q31(
ARM GAS /tmp/cce2LIhc.s page 77
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** q31_t value,
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** q31_t * pDst,
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** uint32_t blockSize)
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
1527 .loc 12 88 0
1528 .cfi_startproc
1529 @ args = 0, pretend = 0, frame = 0
1530 @ frame_needed = 0, uses_anonymous_args = 0
1531 @ link register save eliminated.
1532 .LVL183:
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** uint32_t blkCnt; /* Loop counter */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Loop unrolling: Compute 4 outputs at a time */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt = blockSize >> 2U;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** while (blkCnt > 0U)
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* C = value */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Fill value in destination buffer */
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Decrement loop counter */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt--;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Loop unrolling: Compute remaining outputs */
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt = blockSize % 0x4U;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #else
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Initialize blkCnt with number of samples */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt = blockSize;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** while (blkCnt > 0U)
1533 .loc 12 120 0
1534 0000 1AB1 cbz r2, .L242
1535 .LVL184:
1536 .L244:
1537 0002 013A subs r2, r2, #1
1538 .LVL185:
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* C = value */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Fill value in destination buffer */
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** *pDst++ = value;
1539 .loc 12 125 0
1540 0004 41F8040B str r0, [r1], #4
1541 .LVL186:
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** {
ARM GAS /tmp/cce2LIhc.s page 78
1542 .loc 12 120 0
1543 0008 FBD1 bne .L244
1544 .L242:
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** /* Decrement loop counter */
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** blkCnt--;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c **** }
1545 .loc 12 130 0
1546 000a 7047 bx lr
1547 .cfi_endproc
1548 .LFE158:
1550 .section .text.arm_fill_q7,"ax",%progbits
1551 .align 1
1552 .p2align 2,,3
1553 .global arm_fill_q7
1554 .syntax unified
1555 .thumb
1556 .thumb_func
1557 .fpu fpv4-sp-d16
1559 arm_fill_q7:
1560 .LFB159:
1561 .file 13 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Title: arm_fill_q7.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Description: Fills a constant value into a Q7 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
ARM GAS /tmp/cce2LIhc.s page 79
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @addtogroup Fill
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @brief Fills a constant value into a Q7 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @param[in] value input value to be filled
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @param[out] pDst points to output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #if defined(ARM_MATH_MVEI)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** void arm_fill_q7(
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** q7_t value,
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** q7_t * pDst,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** uint32_t blockSize)
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** uint32_t blkCnt;
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt = blockSize >> 4;
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** while (blkCnt > 0U)
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** vstrbq_s8(pDst,vdupq_n_s8(value));
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /*
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Decrement the blockSize loop counter
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** * Advance vector source and destination pointers
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** */
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** pDst += 16;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt --;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt = blockSize & 0xF;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** while (blkCnt > 0U)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* C = value */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Fill value in destination buffer */
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *pDst++ = value;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Decrement loop counter */
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt--;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #else
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** void arm_fill_q7(
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** q7_t value,
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** q7_t * pDst,
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** uint32_t blockSize)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
1562 .loc 13 85 0
1563 .cfi_startproc
1564 @ args = 0, pretend = 0, frame = 0
1565 @ frame_needed = 0, uses_anonymous_args = 0
1566 @ link register save eliminated.
1567 .LVL187:
ARM GAS /tmp/cce2LIhc.s page 80
1568 .loc 13 85 0
1569 0000 0B46 mov r3, r1
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** uint32_t blkCnt; /* Loop counter */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #if defined (ARM_MATH_LOOPUNROLL)
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** q31_t packedValue; /* value packed to 32 bits */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Packing four 8 bit values to 32 bit value in order to use SIMD */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** packedValue = __PACKq7(value, value, value, value);
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Loop unrolling: Compute 4 outputs at a time */
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt = blockSize >> 2U;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** while (blkCnt > 0U)
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* C = value */
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* fill 4 samples at a time */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** write_q7x4_ia (&pDst, packedValue);
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Decrement loop counter */
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt--;
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Loop unrolling: Compute remaining outputs */
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt = blockSize % 0x4U;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #else
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Initialize blkCnt with number of samples */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt = blockSize;
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** while (blkCnt > 0U)
1570 .loc 13 118 0
1571 0002 1AB1 cbz r2, .L249
1572 0004 0146 mov r1, r0
1573 .LVL188:
1574 0006 1846 mov r0, r3
1575 .LVL189:
1576 0008 FFF7FEBF b memset
1577 .LVL190:
1578 .L249:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** {
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* C = value */
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Fill value in destination buffer */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** *pDst++ = value;
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** /* Decrement loop counter */
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** blkCnt--;
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c **** }
1579 .loc 13 128 0
1580 000c 7047 bx lr
1581 .cfi_endproc
ARM GAS /tmp/cce2LIhc.s page 81
1582 .LFE159:
1584 000e 00BF .section .text.arm_heap_sort_f32,"ax",%progbits
1585 .align 1
1586 .p2align 2,,3
1587 .global arm_heap_sort_f32
1588 .syntax unified
1589 .thumb
1590 .thumb_func
1591 .fpu fpv4-sp-d16
1593 arm_heap_sort_f32:
1594 .LFB161:
1595 .file 14 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Title: arm_heap_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Description: Floating point heap sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** static void arm_heapify(float32_t * pSrc, uint32_t n, uint32_t i, uint8_t dir)
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /* Put all the elements of pSrc in heap order */
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t k = i; // Initialize largest/smallest as root
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t l = 2*i + 1; // left = 2*i + 1
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t r = 2*i + 2; // right = 2*i + 2
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t temp;
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** if (l < n && dir==(pSrc[l] > pSrc[k]) )
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = l;
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** if (r < n && dir==(pSrc[r] > pSrc[k]) )
ARM GAS /tmp/cce2LIhc.s page 82
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = r;
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** if (k != i)
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** temp = pSrc[i];
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pSrc[i]=pSrc[k];
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pSrc[k]=temp;
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** arm_heapify(pSrc, n, k, dir);
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** }
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** }
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /**
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** @ingroup groupSupport
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** */
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /**
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** @addtogroup Sorting
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** @{
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** */
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** /**
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @private
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @param[in] pSrc points to the block of input data.
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @param[out] pDst points to the block of output data
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @param[in] blockSize number of samples to process.
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @par Algorithm
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * The heap sort algorithm is a comparison algorithm that
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * divides the input array into a sorted and an unsorted region,
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * and shrinks the unsorted region by extracting the largest
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * element and moving it to the sorted region. A heap data
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * structure is used to find the maximum.
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** *
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * @par It's an in-place algorithm. In order to obtain an out-of-place
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** * function, a memcpy of the source vector is performed.
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** */
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** void arm_heap_sort_f32(
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** const arm_sort_instance_f32 * S,
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t * pSrc,
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t * pDst,
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t blockSize)
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
1596 .loc 14 89 0
1597 .cfi_startproc
1598 @ args = 0, pretend = 0, frame = 0
1599 @ frame_needed = 0, uses_anonymous_args = 0
1600 .LVL191:
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t * pA;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** int32_t i;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t temp;
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** if(pSrc != pDst) // out-of-place
1601 .loc 14 94 0
1602 0000 8A42 cmp r2, r1
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t * pA;
ARM GAS /tmp/cce2LIhc.s page 83
1603 .loc 14 89 0
1604 0002 2DE9F041 push {r4, r5, r6, r7, r8, lr}
1605 .LCFI23:
1606 .cfi_def_cfa_offset 24
1607 .cfi_offset 4, -24
1608 .cfi_offset 5, -20
1609 .cfi_offset 6, -16
1610 .cfi_offset 7, -12
1611 .cfi_offset 8, -8
1612 .cfi_offset 14, -4
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t * pA;
1613 .loc 14 89 0
1614 0006 1446 mov r4, r2
1615 0008 0646 mov r6, r0
1616 000a 1D46 mov r5, r3
1617 .loc 14 94 0
1618 000c 03D0 beq .L252
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
1619 .loc 14 96 0
1620 000e 9A00 lsls r2, r3, #2
1621 .LVL192:
1622 0010 2046 mov r0, r4
1623 .LVL193:
1624 0012 FFF7FEFF bl memcpy
1625 .LVL194:
1626 .L252:
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA = pDst;
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** }
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** else
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA = pSrc;
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** // Build the heap array so that the largest value is the root
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** for (i = blockSize/2 - 1; i >= 0; i--)
1627 .loc 14 103 0
1628 0016 6B08 lsrs r3, r5, #1
1629 .LVL195:
1630 0018 03F1FF38 add r8, r3, #-1
1631 .LVL196:
1632 001c 002B cmp r3, #0
1633 001e 45D0 beq .L253
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** arm_heapify(pA, blockSize, i, S->dir);
1634 .loc 14 104 0
1635 0020 96F801E0 ldrb lr, [r6, #1] @ zero_extendqisi2
1636 .LVL197:
1637 .L258:
1638 .loc 14 104 0 is_stmt 0 discriminator 3
1639 0024 4246 mov r2, r8
1640 .LVL198:
1641 0026 22E0 b .L257
1642 .LVL199:
1643 .L254:
1644 .LBB70:
1645 .LBB71:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = r;
1646 .loc 14 45 0 is_stmt 1
1647 0028 8542 cmp r5, r0
ARM GAS /tmp/cce2LIhc.s page 84
1648 002a 3CD9 bls .L256
1649 002c 1346 mov r3, r2
1650 .LVL200:
1651 002e 9100 lsls r1, r2, #2
1652 .LVL201:
1653 .L265:
1654 0030 2144 add r1, r1, r4
1655 0032 04EB8007 add r7, r4, r0, lsl #2
1656 0036 D7ED007A vldr.32 s15, [r7]
1657 003a 91ED007A vldr.32 s14, [r1]
1658 003e F4EEC77A vcmpe.f32 s15, s14
1659 0042 F1EE10FA vmrs APSR_nzcv, FPSCR
1660 0046 CCBF ite gt
1661 0048 4FF0010C movgt ip, #1
1662 004c 4FF0000C movle ip, #0
1663 0050 F445 cmp ip, lr
1664 0052 1ABF itte ne
1665 0054 F0EE477A vmovne.f32 s15, s14
1666 0058 0F46 movne r7, r1
1667 005a 0346 moveq r3, r0
1668 .LVL202:
1669 .L255:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
1670 .loc 14 48 0
1671 005c 9A42 cmp r2, r3
1672 005e 22D0 beq .L256
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pSrc[i]=pSrc[k];
1673 .loc 14 50 0
1674 0060 04EB8202 add r2, r4, r2, lsl #2
1675 0064 1168 ldr r1, [r2] @ float
1676 .LVL203:
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pSrc[k]=temp;
1677 .loc 14 51 0
1678 0066 C2ED007A vstr.32 s15, [r2]
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
1679 .loc 14 52 0
1680 006a 1A46 mov r2, r3
1681 006c 3960 str r1, [r7] @ float
1682 .LVL204:
1683 .L257:
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t r = 2*i + 2; // right = 2*i + 2
1684 .loc 14 38 0
1685 006e 5100 lsls r1, r2, #1
1686 0070 4B1C adds r3, r1, #1
1687 .LVL205:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = l;
1688 .loc 14 42 0
1689 0072 9D42 cmp r5, r3
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t temp;
1690 .loc 14 39 0
1691 0074 01F10200 add r0, r1, #2
1692 .LVL206:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = l;
1693 .loc 14 42 0
1694 0078 D6D9 bls .L254
1695 007a 9900 lsls r1, r3, #2
1696 007c 04EB820C add ip, r4, r2, lsl #2
ARM GAS /tmp/cce2LIhc.s page 85
1697 0080 6718 adds r7, r4, r1
1698 0082 9CED007A vldr.32 s14, [ip]
1699 0086 D7ED007A vldr.32 s15, [r7]
1700 008a F4EEC77A vcmpe.f32 s15, s14
1701 008e F1EE10FA vmrs APSR_nzcv, FPSCR
1702 0092 CCBF ite gt
1703 0094 4FF0010C movgt ip, #1
1704 0098 4FF0000C movle ip, #0
1705 009c F445 cmp ip, lr
1706 009e C3D1 bne .L254
1707 .LVL207:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = r;
1708 .loc 14 45 0
1709 00a0 8542 cmp r5, r0
1710 00a2 DBD9 bls .L255
1711 00a4 C4E7 b .L265
1712 .LVL208:
1713 .L256:
1714 .LBE71:
1715 .LBE70:
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** arm_heapify(pA, blockSize, i, S->dir);
1716 .loc 14 103 0 discriminator 3
1717 00a6 18F1FF38 adds r8, r8, #-1
1718 .LVL209:
1719 00aa BBD2 bcs .L258
1720 .LVL210:
1721 .L253:
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** for (i = blockSize - 1; i >= 0; i--)
1722 .loc 14 106 0
1723 00ac 6F1E subs r7, r5, #1
1724 .LVL211:
1725 00ae 49D4 bmi .L251
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** // Swap
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** temp = pA[i];
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA[i] = pA[0];
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA[0] = temp;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** // Restore heap order
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** arm_heapify(pA, i, 0, S->dir);
1726 .loc 14 114 0
1727 00b0 7678 ldrb r6, [r6, #1] @ zero_extendqisi2
1728 .LVL212:
1729 00b2 04EB8505 add r5, r4, r5, lsl #2
1730 .LVL213:
1731 .L264:
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA[i] = pA[0];
1732 .loc 14 109 0 discriminator 3
1733 00b6 35ED017A vldmdb.32 r5!, {s14}
1734 .LVL214:
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pA[0] = temp;
1735 .loc 14 110 0 discriminator 3
1736 00ba 2268 ldr r2, [r4] @ float
1737 00bc 2A60 str r2, [r5] @ float
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
1738 .loc 14 111 0 discriminator 3
ARM GAS /tmp/cce2LIhc.s page 86
1739 00be 0023 movs r3, #0
1740 00c0 84ED007A vstr.32 s14, [r4]
1741 .LVL215:
1742 00c4 21E0 b .L263
1743 .LVL216:
1744 .L260:
1745 .LBB72:
1746 .LBB73:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = r;
1747 .loc 14 45 0
1748 00c6 9742 cmp r7, r2
1749 00c8 39D9 bls .L262
1750 00ca F0EE476A vmov.f32 s13, s14
1751 00ce 1946 mov r1, r3
1752 .LVL217:
1753 .L266:
1754 00d0 04EB8200 add r0, r4, r2, lsl #2
1755 00d4 D0ED007A vldr.32 s15, [r0]
1756 00d8 F4EEE67A vcmpe.f32 s15, s13
1757 00dc F1EE10FA vmrs APSR_nzcv, FPSCR
1758 00e0 CCBF ite gt
1759 00e2 4FF0010C movgt ip, #1
1760 00e6 4FF0000C movle ip, #0
1761 00ea B445 cmp ip, r6
1762 00ec 1ABF itte ne
1763 00ee F0EE667A vmovne.f32 s15, s13
1764 00f2 04EB8100 addne r0, r4, r1, lsl #2
1765 00f6 1146 moveq r1, r2
1766 .LVL218:
1767 .L261:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
1768 .loc 14 48 0
1769 00f8 8B42 cmp r3, r1
1770 00fa 20D0 beq .L262
1771 .LVL219:
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** pSrc[k]=temp;
1772 .loc 14 51 0
1773 00fc 04EB8303 add r3, r4, r3, lsl #2
1774 .LVL220:
1775 0100 C3ED007A vstr.32 s15, [r3]
1776 .LVL221:
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c ****
1777 .loc 14 52 0
1778 0104 0B46 mov r3, r1
1779 0106 80ED007A vstr.32 s14, [r0]
1780 .LVL222:
1781 .L263:
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** uint32_t r = 2*i + 2; // right = 2*i + 2
1782 .loc 14 38 0
1783 010a 5A00 lsls r2, r3, #1
1784 010c 511C adds r1, r2, #1
1785 .LVL223:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = l;
1786 .loc 14 42 0
1787 010e 8F42 cmp r7, r1
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** float32_t temp;
1788 .loc 14 39 0
ARM GAS /tmp/cce2LIhc.s page 87
1789 0110 02F10202 add r2, r2, #2
1790 .LVL224:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = l;
1791 .loc 14 42 0
1792 0114 D7D9 bls .L260
1793 0116 04EB8100 add r0, r4, r1, lsl #2
1794 011a D0ED007A vldr.32 s15, [r0]
1795 011e B4EEE77A vcmpe.f32 s14, s15
1796 0122 F1EE10FA vmrs APSR_nzcv, FPSCR
1797 0126 4CBF ite mi
1798 0128 4FF0010C movmi ip, #1
1799 012c 4FF0000C movpl ip, #0
1800 0130 B445 cmp ip, r6
1801 0132 C8D1 bne .L260
1802 .LVL225:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** k = r;
1803 .loc 14 45 0
1804 0134 9742 cmp r7, r2
1805 0136 DFD9 bls .L261
1806 0138 F0EE676A vmov.f32 s13, s15
1807 013c C8E7 b .L266
1808 .LVL226:
1809 .L262:
1810 .LBE73:
1811 .LBE72:
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** {
1812 .loc 14 106 0 discriminator 3
1813 013e 17F1FF37 adds r7, r7, #-1
1814 .LVL227:
1815 0142 B8D2 bcs .L264
1816 .LVL228:
1817 .L251:
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** }
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_heap_sort_f32.c **** }
1818 .loc 14 116 0
1819 0144 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
1820 .cfi_endproc
1821 .LFE161:
1823 .section .text.arm_insertion_sort_f32,"ax",%progbits
1824 .align 1
1825 .p2align 2,,3
1826 .global arm_insertion_sort_f32
1827 .syntax unified
1828 .thumb
1829 .thumb_func
1830 .fpu fpv4-sp-d16
1832 arm_insertion_sort_f32:
1833 .LFB162:
1834 .file 15 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Title: arm_insertion_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Description: Floating point insertion sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
ARM GAS /tmp/cce2LIhc.s page 88
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** /**
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** @addtogroup Sorting
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** @{
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** /**
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @private
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @param[in] pSrc points to the block of input data.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @param[out] pDst points to the block of output data
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @param[in] blockSize number of samples to process.
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @par Algorithm
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * The insertion sort is a simple sorting algorithm that
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * reads all the element of the input array and removes one element
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * at a time, finds the location it belongs in the final sorted list,
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * and inserts it there.
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** *
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * @par It's an in-place algorithm. In order to obtain an out-of-place
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** * function, a memcpy of the source vector is performed.
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** void arm_insertion_sort_f32(
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** const arm_sort_instance_f32 * S,
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t *pSrc,
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t* pDst,
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** uint32_t blockSize)
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
1835 .loc 15 63 0
1836 .cfi_startproc
ARM GAS /tmp/cce2LIhc.s page 89
1837 @ args = 0, pretend = 0, frame = 0
1838 @ frame_needed = 0, uses_anonymous_args = 0
1839 .LVL229:
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t * pA;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** uint8_t dir = S->dir;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** uint32_t i, j;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t temp;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** if(pSrc != pDst) // out-of-place
1840 .loc 15 69 0
1841 0000 8A42 cmp r2, r1
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t * pA;
1842 .loc 15 63 0
1843 0002 F8B5 push {r3, r4, r5, r6, r7, lr}
1844 .LCFI24:
1845 .cfi_def_cfa_offset 24
1846 .cfi_offset 3, -24
1847 .cfi_offset 4, -20
1848 .cfi_offset 5, -16
1849 .cfi_offset 6, -12
1850 .cfi_offset 7, -8
1851 .cfi_offset 14, -4
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** float32_t * pA;
1852 .loc 15 63 0
1853 0004 1446 mov r4, r2
1854 0006 1F46 mov r7, r3
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** uint32_t i, j;
1855 .loc 15 65 0
1856 0008 4678 ldrb r6, [r0, #1] @ zero_extendqisi2
1857 .LVL230:
1858 .loc 15 69 0
1859 000a 03D0 beq .L278
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
1860 .loc 15 71 0
1861 000c 9A00 lsls r2, r3, #2
1862 .LVL231:
1863 000e 2046 mov r0, r4
1864 .LVL232:
1865 0010 FFF7FEFF bl memcpy
1866 .LVL233:
1867 .L278:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA = pDst;
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** }
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** else
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA = pSrc;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c ****
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** // Real all the element of the input array
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** for(i=0; i<blockSize; i++)
1868 .loc 15 78 0
1869 0014 6FB3 cbz r7, .L277
1870 0016 0023 movs r3, #0
1871 0018 0133 adds r3, r3, #1
1872 .LVL234:
1873 001a 9F42 cmp r7, r3
1874 001c 2246 mov r2, r4
1875 001e 28D0 beq .L277
ARM GAS /tmp/cce2LIhc.s page 90
1876 .LVL235:
1877 .L294:
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** // Move the i-th element to the right position
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** for (j = i; j>0 && dir==(pA[j]<pA[j-1]); j--)
1878 .loc 15 81 0
1879 0020 92ED017A vldr.32 s14, [r2, #4]
1880 0024 D2ED007A vldr.32 s15, [r2]
1881 0028 B4EEE77A vcmpe.f32 s14, s15
1882 002c F1EE10FA vmrs APSR_nzcv, FPSCR
1883 0030 4CBF ite mi
1884 0032 0121 movmi r1, #1
1885 0034 0021 movpl r1, #0
1886 0036 B142 cmp r1, r6
1887 0038 02F1040C add ip, r2, #4
1888 003c 15D1 bne .L281
1889 003e 6446 mov r4, ip
1890 0040 02F10800 add r0, r2, #8
1891 0044 1946 mov r1, r3
1892 0046 0AE0 b .L282
1893 .LVL236:
1894 .L293:
1895 .loc 15 81 0 is_stmt 0 discriminator 3
1896 0048 72ED017A vldmdb.32 r2!, {s15}
1897 004c F4EEC77A vcmpe.f32 s15, s14
1898 0050 F1EE10FA vmrs APSR_nzcv, FPSCR
1899 0054 CCBF ite gt
1900 0056 0125 movgt r5, #1
1901 0058 0025 movle r5, #0
1902 005a B542 cmp r5, r6
1903 005c 05D1 bne .L281
1904 .LVL237:
1905 .L282:
1906 .loc 15 81 0 discriminator 4
1907 005e 0139 subs r1, r1, #1
1908 .LVL238:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** // Swap
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** temp = pA[j];
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA[j] = pA[j-1];
1909 .loc 15 85 0 is_stmt 1 discriminator 4
1910 0060 60ED017A vstmdb.32 r0!, {s15}
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA[j-1] = temp;
1911 .loc 15 86 0 discriminator 4
1912 0064 24ED017A vstmdb.32 r4!, {s14}
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
1913 .loc 15 81 0 discriminator 4
1914 0068 EED1 bne .L293
1915 .LVL239:
1916 .L281:
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
1917 .loc 15 78 0
1918 006a 0133 adds r3, r3, #1
1919 .LVL240:
1920 006c 9F42 cmp r7, r3
1921 006e 6246 mov r2, ip
1922 0070 D6D1 bne .L294
ARM GAS /tmp/cce2LIhc.s page 91
1923 .LVL241:
1924 .L277:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** }
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** }
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** }
1925 .loc 15 89 0
1926 0072 F8BD pop {r3, r4, r5, r6, r7, pc}
1927 .cfi_endproc
1928 .LFE162:
1930 .section .text.arm_merge_sort_f32,"ax",%progbits
1931 .align 1
1932 .p2align 2,,3
1933 .global arm_merge_sort_f32
1934 .syntax unified
1935 .thumb
1936 .thumb_func
1937 .fpu fpv4-sp-d16
1939 arm_merge_sort_f32:
1940 .LFB165:
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /**
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** @ingroup groupSupport
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** */
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /**
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** @addtogroup Sorting
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** @{
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** */
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /**
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @param[in] pSrc points to the block of input data.
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @param[out] pDst points to the block of output data
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @param[in] blockSize number of samples to process.
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @par Algorithm
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * The merge sort algorithm is a comparison algorithm that
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * divide the input array in sublists and merge them to produce
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * longer sorted sublists until there is only one list remaining.
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @par A work array is always needed. It must be allocated by the user
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * linked to the instance at initialization time.
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** *
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * @par It's an in-place algorithm. In order to obtain an out-of-place
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** * function, a memcpy of the source vector is performed
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** */
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** void arm_merge_sort_f32(
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** const arm_merge_sort_instance_f32 * S,
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** float32_t *pSrc,
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** float32_t *pDst,
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t blockSize)
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
1941 .loc 2 108 0
1942 .cfi_startproc
ARM GAS /tmp/cce2LIhc.s page 92
1943 @ args = 0, pretend = 0, frame = 0
1944 @ frame_needed = 0, uses_anonymous_args = 0
1945 .LVL242:
1946 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr}
1947 .LCFI25:
1948 .cfi_def_cfa_offset 24
1949 .cfi_offset 4, -24
1950 .cfi_offset 5, -20
1951 .cfi_offset 6, -16
1952 .cfi_offset 7, -12
1953 .cfi_offset 8, -8
1954 .cfi_offset 14, -4
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** float32_t * pA;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /* Out-of-place */
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** if(pSrc != pDst)
1955 .loc 2 112 0
1956 0004 9142 cmp r1, r2
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** float32_t * pA;
1957 .loc 2 108 0
1958 0006 82B0 sub sp, sp, #8
1959 .LCFI26:
1960 .cfi_def_cfa_offset 32
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** float32_t * pA;
1961 .loc 2 108 0
1962 0008 1D46 mov r5, r3
1963 000a 1446 mov r4, r2
1964 000c 0E46 mov r6, r1
1965 000e 8046 mov r8, r0
1966 0010 4FEA8307 lsl r7, r3, #2
1967 .loc 2 112 0
1968 0014 03D0 beq .L296
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t));
1969 .loc 2 114 0
1970 0016 3A46 mov r2, r7
1971 .LVL243:
1972 0018 2046 mov r0, r4
1973 .LVL244:
1974 001a FFF7FEFF bl memcpy
1975 .LVL245:
1976 .L296:
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** pA = pDst;
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** else
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** pA = pSrc;
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** /* A working buffer is needed */
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** memcpy(S->buffer, pSrc, blockSize*sizeof(float32_t));
1977 .loc 2 121 0
1978 001e 3A46 mov r2, r7
1979 0020 3146 mov r1, r6
1980 0022 D8F80400 ldr r0, [r8, #4]
1981 0026 FFF7FEFF bl memcpy
1982 .LVL246:
1983 .LBB79:
1984 .LBB80:
ARM GAS /tmp/cce2LIhc.s page 93
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
1985 .loc 2 63 0
1986 002a 012D cmp r5, #1
1987 002c 02DC bgt .L305
1988 .LVL247:
1989 .L295:
1990 .LBE80:
1991 .LBE79:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(S->buffer, 0, blockSize, pA, S->dir);
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
1992 .loc 2 124 0
1993 002e 02B0 add sp, sp, #8
1994 .LCFI27:
1995 .cfi_remember_state
1996 .cfi_def_cfa_offset 24
1997 @ sp needed
1998 0030 BDE8F081 pop {r4, r5, r6, r7, r8, pc}
1999 .LVL248:
2000 .L305:
2001 .LCFI28:
2002 .cfi_restore_state
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
2003 .loc 2 123 0
2004 0034 D8F80460 ldr r6, [r8, #4]
2005 .LVL249:
2006 0038 98F80080 ldrb r8, [r8] @ zero_extendqisi2
2007 .LVL250:
2008 .LBB85:
2009 .LBB84:
2010 .LBB81:
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
2011 .loc 2 67 0
2012 003c CDF80080 str r8, [sp]
2013 .LVL251:
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
2014 .loc 2 65 0
2015 0040 6F08 lsrs r7, r5, #1
2016 .LVL252:
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** arm_merge_sort_core_f32(pA, middle, end, pB, dir); // Sort the right part
2017 .loc 2 67 0
2018 0042 3346 mov r3, r6
2019 0044 3A46 mov r2, r7
2020 0046 0021 movs r1, #0
2021 0048 2046 mov r0, r4
2022 004a FFF7FEFF bl arm_merge_sort_core_f32
2023 .LVL253:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c ****
2024 .loc 2 68 0
2025 004e 3346 mov r3, r6
2026 0050 3946 mov r1, r7
2027 0052 2A46 mov r2, r5
2028 0054 2046 mov r0, r4
2029 0056 CDF80080 str r8, [sp]
2030 005a FFF7FEFF bl arm_merge_sort_core_f32
2031 .LVL254:
2032 .LBB82:
ARM GAS /tmp/cce2LIhc.s page 94
2033 .LBB83:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
2034 .loc 2 45 0
2035 005e 0023 movs r3, #0
2036 0060 2246 mov r2, r4
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t k;
2037 .loc 2 41 0
2038 0062 3946 mov r1, r7
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** uint32_t j = middle;
2039 .loc 2 40 0
2040 0064 1846 mov r0, r3
2041 0066 18E0 b .L302
2042 .LVL255:
2043 .L306:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
2044 .loc 2 48 0
2045 0068 8D42 cmp r5, r1
2046 006a 06EB810C add ip, r6, r1, lsl #2
2047 006e 94ED007A vldr.32 s14, [r4]
2048 0072 1BD9 bls .L299
2049 0074 DCED007A vldr.32 s15, [ip]
2050 0078 B4EEE77A vcmpe.f32 s14, s15
2051 007c F1EE10FA vmrs APSR_nzcv, FPSCR
2052 0080 94BF ite ls
2053 0082 0124 movls r4, #1
2054 0084 0024 movhi r4, #0
2055 0086 4445 cmp r4, r8
2056 0088 10D0 beq .L299
2057 .L300:
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** j++;
2058 .loc 2 55 0
2059 008a C2ED007A vstr.32 s15, [r2]
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
2060 .loc 2 56 0
2061 008e 0131 adds r1, r1, #1
2062 .LVL256:
2063 .L301:
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
2064 .loc 2 45 0
2065 0090 0133 adds r3, r3, #1
2066 .LVL257:
2067 0092 9D42 cmp r5, r3
2068 0094 02F10402 add r2, r2, #4
2069 0098 C9D0 beq .L295
2070 .LVL258:
2071 .L302:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** {
2072 .loc 2 48 0
2073 009a 8742 cmp r7, r0
2074 009c 06EB8004 add r4, r6, r0, lsl #2
2075 00a0 E2D8 bhi .L306
2076 00a2 06EB8104 add r4, r6, r1, lsl #2
2077 00a6 D4ED007A vldr.32 s15, [r4]
2078 00aa EEE7 b .L300
2079 .L299:
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** i++;
2080 .loc 2 50 0
ARM GAS /tmp/cce2LIhc.s page 95
2081 00ac 82ED007A vstr.32 s14, [r2]
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_f32.c **** }
2082 .loc 2 51 0
2083 00b0 0130 adds r0, r0, #1
2084 .LVL259:
2085 00b2 EDE7 b .L301
2086 .LBE83:
2087 .LBE82:
2088 .LBE81:
2089 .LBE84:
2090 .LBE85:
2091 .cfi_endproc
2092 .LFE165:
2094 .section .text.arm_merge_sort_init_f32,"ax",%progbits
2095 .align 1
2096 .p2align 2,,3
2097 .global arm_merge_sort_init_f32
2098 .syntax unified
2099 .thumb
2100 .thumb_func
2101 .fpu fpv4-sp-d16
2103 arm_merge_sort_init_f32:
2104 .LFB166:
2105 .file 16 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Title: arm_merge_sort_init_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Description: Floating point merge sort initialization function
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** */
ARM GAS /tmp/cce2LIhc.s page 96
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** @addtogroup Sorting
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** /**
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * @param[in,out] S points to an instance of the sorting structure.
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * @param[in] dir Sorting order.
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** * @param[in] buffer Working buffer.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** */
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** void arm_merge_sort_init_f32(arm_merge_sort_instance_f32 * S, arm_sort_dir dir, float32_t * buffer)
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** {
2106 .loc 16 47 0
2107 .cfi_startproc
2108 @ args = 0, pretend = 0, frame = 0
2109 @ frame_needed = 0, uses_anonymous_args = 0
2110 @ link register save eliminated.
2111 .LVL260:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** S->dir = dir;
2112 .loc 16 48 0
2113 0000 0170 strb r1, [r0]
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** S->buffer = buffer;
2114 .loc 16 49 0
2115 0002 4260 str r2, [r0, #4]
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_merge_sort_init_f32.c **** }
2116 .loc 16 50 0
2117 0004 7047 bx lr
2118 .cfi_endproc
2119 .LFE166:
2121 0006 00BF .section .text.arm_quick_sort_f32,"ax",%progbits
2122 .align 1
2123 .p2align 2,,3
2124 .global arm_quick_sort_f32
2125 .syntax unified
2126 .thumb
2127 .thumb_func
2128 .fpu fpv4-sp-d16
2130 arm_quick_sort_f32:
2131 .LFB169:
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /**
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** @ingroup groupSupport
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /**
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** @addtogroup Sorting
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** @{
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** */
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /**
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @private
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @param[in,out] pSrc points to the block of input data.
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @param[out] pDst points to the block of output data.
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @param[in] blockSize number of samples to process.
ARM GAS /tmp/cce2LIhc.s page 97
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @par Algorithm
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * The quick sort algorithm is a comparison algorithm that
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * divides the input array into two smaller sub-arrays and
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * recursively sort them. An element of the array (the pivot)
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * is chosen, all the elements with values smaller than the
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * pivot are moved before the pivot, while all elements with
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * values greater than the pivot are moved after it (partition).
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @par
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * In this implementation the Hoare partition scheme has been
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * used [Hoare, C. A. R. (1 January 1962). "Quicksort". The Computer
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * Journal. 5 (1): 10–16.] The first element has always been chosen
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * as the pivot. The partition algorithm guarantees that the returned
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * pivot is never placed outside the vector, since it is returned only
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * when the pointers crossed each other. In this way it isn't
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * possible to obtain empty partitions and infinite recursion is avoided.
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** *
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * @par
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * It's an in-place algorithm. In order to obtain an out-of-place
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * function, a memcpy of the source vector is performed.
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** void arm_quick_sort_f32(
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** const arm_sort_instance_f32 * S,
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t * pSrc,
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t * pDst,
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** uint32_t blockSize)
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
2132 .loc 1 163 0
2133 .cfi_startproc
2134 @ args = 0, pretend = 0, frame = 0
2135 @ frame_needed = 0, uses_anonymous_args = 0
2136 .LVL261:
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t * pA;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* Out-of-place */
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** if(pSrc != pDst)
2137 .loc 1 167 0
2138 0000 8A42 cmp r2, r1
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t * pA;
2139 .loc 1 163 0
2140 0002 70B5 push {r4, r5, r6, lr}
2141 .LCFI29:
2142 .cfi_def_cfa_offset 16
2143 .cfi_offset 4, -16
2144 .cfi_offset 5, -12
2145 .cfi_offset 6, -8
2146 .cfi_offset 14, -4
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** float32_t * pA;
2147 .loc 1 163 0
2148 0004 1446 mov r4, r2
2149 0006 0646 mov r6, r0
2150 0008 1D46 mov r5, r3
2151 .loc 1 167 0
2152 000a 03D0 beq .L309
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 98
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
2153 .loc 1 169 0
2154 000c 9A00 lsls r2, r3, #2
2155 .LVL262:
2156 000e 2046 mov r0, r4
2157 .LVL263:
2158 0010 FFF7FEFF bl memcpy
2159 .LVL264:
2160 .L309:
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pA = pDst;
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** else
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pA = pSrc;
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c ****
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** arm_quick_sort_core_f32(pA, 0, blockSize-1, S->dir);
2161 .loc 1 175 0
2162 0014 7378 ldrb r3, [r6, #1] @ zero_extendqisi2
2163 0016 6A1E subs r2, r5, #1
2164 0018 2046 mov r0, r4
2165 001a 0021 movs r1, #0
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The previous function could be called recursively a maximum
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** * of (blockSize-1) times, generating a stack consumption of 4*(blockSize-1) bytes. */
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** }
2166 .loc 1 178 0
2167 001c BDE87040 pop {r4, r5, r6, lr}
2168 .LCFI30:
2169 .cfi_restore 14
2170 .cfi_restore 6
2171 .cfi_restore 5
2172 .cfi_restore 4
2173 .cfi_def_cfa_offset 0
2174 .LVL265:
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The previous function could be called recursively a maximum
2175 .loc 1 175 0
2176 0020 FFF7FEBF b arm_quick_sort_core_f32
2177 .LVL266:
2178 .cfi_endproc
2179 .LFE169:
2181 .section .text.arm_selection_sort_f32,"ax",%progbits
2182 .align 1
2183 .p2align 2,,3
2184 .global arm_selection_sort_f32
2185 .syntax unified
2186 .thumb
2187 .thumb_func
2188 .fpu fpv4-sp-d16
2190 arm_selection_sort_f32:
2191 .LFB170:
2192 .file 17 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Title: arm_selection_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Description: Floating point selection sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
ARM GAS /tmp/cce2LIhc.s page 99
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /**
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** @addtogroup Sorting
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** @{
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /**
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @private
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @param[in] pSrc points to the block of input data.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @param[out] pDst points to the block of output data
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @param[in] blockSize number of samples to process.
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @par Algorithm
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * The Selection sort algorithm is a comparison algorithm that
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * divides the input array into a sorted and an unsorted sublist
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * (initially the sorted sublist is empty and the unsorted sublist
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * is the input array), looks for the smallest (or biggest)
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * element in the unsorted sublist, swapping it with the leftmost
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * one, and moving the sublists boundary one element to the right.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** *
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * @par It's an in-place algorithm. In order to obtain an out-of-place
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** * function, a memcpy of the source vector is performed.
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** */
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** void arm_selection_sort_f32(
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** const arm_sort_instance_f32 * S,
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t * pSrc,
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t * pDst,
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** uint32_t blockSize)
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 100
2193 .loc 17 65 0
2194 .cfi_startproc
2195 @ args = 0, pretend = 0, frame = 0
2196 @ frame_needed = 0, uses_anonymous_args = 0
2197 .LVL267:
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** uint32_t i, j, k;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** uint8_t dir = S->dir;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t temp;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t * pA;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** if(pSrc != pDst) // out-of-place
2198 .loc 17 72 0
2199 0000 8A42 cmp r2, r1
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** uint32_t i, j, k;
2200 .loc 17 65 0
2201 0002 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr}
2202 .LCFI31:
2203 .cfi_def_cfa_offset 32
2204 .cfi_offset 4, -32
2205 .cfi_offset 5, -28
2206 .cfi_offset 6, -24
2207 .cfi_offset 7, -20
2208 .cfi_offset 8, -16
2209 .cfi_offset 9, -12
2210 .cfi_offset 10, -8
2211 .cfi_offset 14, -4
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** uint32_t i, j, k;
2212 .loc 17 65 0
2213 0006 9046 mov r8, r2
2214 0008 1E46 mov r6, r3
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t temp;
2215 .loc 17 67 0
2216 000a 4778 ldrb r7, [r0, #1] @ zero_extendqisi2
2217 .LVL268:
2218 .loc 17 72 0
2219 000c 03D0 beq .L312
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** memcpy(pDst, pSrc, blockSize*sizeof(float32_t) );
2220 .loc 17 74 0
2221 000e 9A00 lsls r2, r3, #2
2222 .LVL269:
2223 0010 4046 mov r0, r8
2224 .LVL270:
2225 0012 FFF7FEFF bl memcpy
2226 .LVL271:
2227 .L312:
2228 0016 06F1FF3A add r10, r6, #-1
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA = pDst;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** else
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA = pSrc;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* Move the boundary one element to the right */
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** for (i=0; i<blockSize-1; i++)
2229 .loc 17 81 0
2230 001a 0023 movs r3, #0
ARM GAS /tmp/cce2LIhc.s page 101
2231 001c 5345 cmp r3, r10
2232 001e C146 mov r9, r8
2233 0020 2BD0 beq .L323
2234 .LVL272:
2235 .L317:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* Initialize the minimum/maximum as the first element */
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** k = i;
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* Look in the unsorted list to find the minimum/maximum value */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** for (j=i+1; j<blockSize; j++)
2236 .loc 17 87 0
2237 0022 03F1010E add lr, r3, #1
2238 .LVL273:
2239 0026 7645 cmp r6, lr
2240 0028 29D9 bls .L324
2241 002a CC46 mov ip, r9
2242 002c FCEC016A vldmia.32 ip!, {s13}
2243 0030 1D46 mov r5, r3
2244 0032 B0EE667A vmov.f32 s14, s13
2245 0036 6146 mov r1, ip
2246 0038 7246 mov r2, lr
2247 .LVL274:
2248 .L316:
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** if (dir==(pA[j] < pA[k]) )
2249 .loc 17 89 0
2250 003a 0C46 mov r4, r1
2251 003c F1EC017A vldmia.32 r1!, {s15}
2252 0040 F4EEC77A vcmpe.f32 s15, s14
2253 0044 F1EE10FA vmrs APSR_nzcv, FPSCR
2254 0048 4CBF ite mi
2255 004a 0120 movmi r0, #1
2256 004c 0020 movpl r0, #0
2257 004e B842 cmp r0, r7
2258 0050 08BF it eq
2259 0052 1546 moveq r5, r2
2260 .LVL275:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2261 .loc 17 87 0
2262 0054 02F10102 add r2, r2, #1
2263 .LVL276:
2264 .loc 17 89 0
2265 0058 14BF ite ne
2266 005a 08EB8504 addne r4, r8, r5, lsl #2
2267 005e B0EE677A vmoveq.f32 s14, s15
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2268 .loc 17 87 0
2269 0062 B242 cmp r2, r6
2270 0064 E9D1 bne .L316
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* Update value */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** k = j;
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** if (k != i)
ARM GAS /tmp/cce2LIhc.s page 102
2271 .loc 17 96 0
2272 0066 9D42 cmp r5, r3
2273 .LVL277:
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** /* Swap the minimum/maximum with the leftmost element */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** temp=pA[i];
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA[i]=pA[k];
2274 .loc 17 100 0
2275 0068 1CBF itt ne
2276 006a 89ED007A vstrne.32 s14, [r9]
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA[k]=temp;
2277 .loc 17 101 0
2278 006e C4ED006A vstrne.32 s13, [r4]
2279 .LVL278:
2280 .L314:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2281 .loc 17 87 0 discriminator 1
2282 0072 7346 mov r3, lr
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2283 .loc 17 81 0 discriminator 1
2284 0074 5345 cmp r3, r10
2285 0076 E146 mov r9, ip
2286 .LVL279:
2287 0078 D3D1 bne .L317
2288 .LVL280:
2289 .L323:
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
2290 .loc 17 104 0
2291 007a BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc}
2292 .LVL281:
2293 .L324:
2294 007e 09F1040C add ip, r9, #4
2295 0082 F6E7 b .L314
2296 .cfi_endproc
2297 .LFE170:
2299 .section .text.arm_sort_f32,"ax",%progbits
2300 .align 1
2301 .p2align 2,,3
2302 .global arm_sort_f32
2303 .syntax unified
2304 .thumb
2305 .thumb_func
2306 .fpu fpv4-sp-d16
2308 arm_sort_f32:
2309 .LFB171:
2310 .file 18 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Title: arm_sort_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Description: Floating point sort
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
ARM GAS /tmp/cce2LIhc.s page 103
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** /**
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** @addtogroup Sorting
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** @{
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** /**
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * @brief Generic sorting function
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** *
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * @param[in] S points to an instance of the sorting structure.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * @param[in] pSrc points to the block of input data.
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * @param[out] pDst points to the block of output data.
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** * @param[in] blockSize number of samples to process.
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** */
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** void arm_sort_f32(
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** const arm_sort_instance_f32 * S,
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** float32_t * pSrc,
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** float32_t * pDst,
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** uint32_t blockSize)
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** {
2311 .loc 18 56 0
2312 .cfi_startproc
2313 @ args = 0, pretend = 0, frame = 0
2314 @ frame_needed = 0, uses_anonymous_args = 0
2315 .LVL282:
2316 0000 2DE9F047 push {r4, r5, r6, r7, r8, r9, r10, lr}
2317 .LCFI32:
2318 .cfi_def_cfa_offset 32
2319 .cfi_offset 4, -32
2320 .cfi_offset 5, -28
ARM GAS /tmp/cce2LIhc.s page 104
2321 .cfi_offset 6, -24
2322 .cfi_offset 7, -20
2323 .cfi_offset 8, -16
2324 .cfi_offset 9, -12
2325 .cfi_offset 10, -8
2326 .cfi_offset 14, -4
2327 .loc 18 56 0
2328 0004 0646 mov r6, r0
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** switch(S->alg)
2329 .loc 18 57 0
2330 0006 0078 ldrb r0, [r0] @ zero_extendqisi2
2331 .LVL283:
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** switch(S->alg)
2332 .loc 18 56 0
2333 0008 1446 mov r4, r2
2334 000a 1D46 mov r5, r3
2335 .loc 18 57 0
2336 000c 0528 cmp r0, #5
2337 000e 32D8 bhi .L325
2338 0010 DFE800F0 tbb [pc, r0]
2339 .LVL284:
2340 .L328:
2341 0014 6C .byte (.L327-.L328)/2
2342 0015 03 .byte (.L329-.L328)/2
2343 0016 72 .byte (.L330-.L328)/2
2344 0017 78 .byte (.L331-.L328)/2
2345 0018 AD .byte (.L332-.L328)/2
2346 0019 33 .byte (.L333-.L328)/2
2347 .p2align 1
2348 .L329:
2349 .LBB94:
2350 .LBB95:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2351 .loc 5 72 0
2352 001a 9142 cmp r1, r2
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** uint32_t i;
2353 .loc 5 66 0
2354 001c 7678 ldrb r6, [r6, #1] @ zero_extendqisi2
2355 .LVL285:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2356 .loc 5 72 0
2357 001e 03D0 beq .L334
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA = pDst;
2358 .loc 5 74 0
2359 0020 AA00 lsls r2, r5, #2
2360 .LVL286:
2361 0022 2046 mov r0, r4
2362 0024 FFF7FEFF bl memcpy
2363 .LVL287:
2364 .L334:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
2365 .loc 5 82 0
2366 0028 0027 movs r7, #0
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2367 .loc 5 84 0
2368 002a 3A46 mov r2, r7
2369 .LVL288:
ARM GAS /tmp/cce2LIhc.s page 105
2370 .L335:
2371 002c 691E subs r1, r5, #1
2372 002e 8A42 cmp r2, r1
2373 0030 80F0AB80 bcs .L369
2374 .LVL289:
2375 .L338:
2376 0034 04EB8203 add r3, r4, r2, lsl #2
2377 .L336:
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2378 .loc 5 86 0
2379 0038 D3ED007A vldr.32 s15, [r3]
2380 003c 0433 adds r3, r3, #4
2381 003e 93ED007A vldr.32 s14, [r3]
2382 0042 F4EEC77A vcmpe.f32 s15, s14
2383 0046 F1EE10FA vmrs APSR_nzcv, FPSCR
2384 004a CCBF ite gt
2385 004c 0120 movgt r0, #1
2386 004e 0020 movle r0, #0
2387 0050 B042 cmp r0, r6
2388 0052 02F10102 add r2, r2, #1
2389 0056 E9D1 bne .L335
2390 .LVL290:
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2391 .loc 5 84 0
2392 0058 8A42 cmp r2, r1
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** pA[i+1] = temp;
2393 .loc 5 90 0
2394 005a 03ED017A vstr.32 s14, [r3, #-4]
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c ****
2395 .loc 5 91 0
2396 005e C3ED007A vstr.32 s15, [r3]
2397 .LVL291:
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** }
2398 .loc 5 94 0
2399 0062 4FF00107 mov r7, #1
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2400 .loc 5 84 0
2401 0066 E7D3 bcc .L336
2402 .LVL292:
2403 .L368:
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2404 .loc 5 80 0
2405 0068 0D46 mov r5, r1
2406 .LVL293:
2407 006a 0022 movs r2, #0
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2408 .loc 5 84 0
2409 006c 012D cmp r5, #1
2410 006e 01F1FF31 add r1, r1, #-1
2411 0072 1746 mov r7, r2
2412 0074 DED1 bne .L338
2413 .LVL294:
2414 .L325:
2415 .LBE95:
2416 .LBE94:
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_BITONIC:
ARM GAS /tmp/cce2LIhc.s page 106
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_bitonic_sort_f32(S, pSrc, pDst, blockSize);
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_BUBBLE:
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_bubble_sort_f32(S, pSrc, pDst, blockSize);
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_HEAP:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_heap_sort_f32(S, pSrc, pDst, blockSize);
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_INSERTION:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_insertion_sort_f32(S, pSrc, pDst, blockSize);
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_QUICK:
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_quick_sort_f32(S, pSrc, pDst, blockSize);
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c ****
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** case ARM_SORT_SELECTION:
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** arm_selection_sort_f32(S, pSrc, pDst, blockSize);
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** }
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** }
2417 .loc 18 83 0
2418 0076 BDE8F087 pop {r4, r5, r6, r7, r8, r9, r10, pc}
2419 .LVL295:
2420 .L333:
2421 .LBB97:
2422 .LBB98:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2423 .loc 17 72 0
2424 007a 9142 cmp r1, r2
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** float32_t temp;
2425 .loc 17 67 0
2426 007c 7778 ldrb r7, [r6, #1] @ zero_extendqisi2
2427 .LVL296:
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2428 .loc 17 72 0
2429 007e 03D0 beq .L346
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA = pDst;
2430 .loc 17 74 0
2431 0080 AA00 lsls r2, r5, #2
2432 .LVL297:
2433 0082 2046 mov r0, r4
2434 0084 FFF7FEFF bl memcpy
2435 .LVL298:
2436 .L346:
2437 0088 05F1FF3A add r10, r5, #-1
2438 008c A146 mov r9, r4
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2439 .loc 17 81 0
2440 008e 4FF0000C mov ip, #0
2441 .LVL299:
2442 .L347:
2443 0092 D445 cmp ip, r10
2444 0094 EFD0 beq .L325
ARM GAS /tmp/cce2LIhc.s page 107
2445 .LVL300:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2446 .loc 17 87 0
2447 0096 0CF10108 add r8, ip, #1
2448 .LVL301:
2449 009a 4545 cmp r5, r8
2450 009c 79D9 bls .L370
2451 009e CE46 mov lr, r9
2452 00a0 FEEC016A vldmia.32 lr!, {s13}
2453 00a4 6646 mov r6, ip
2454 00a6 B0EE667A vmov.f32 s14, s13
2455 00aa 7246 mov r2, lr
2456 00ac 4346 mov r3, r8
2457 .LVL302:
2458 .L350:
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2459 .loc 17 89 0
2460 00ae 1046 mov r0, r2
2461 00b0 F2EC017A vldmia.32 r2!, {s15}
2462 00b4 F4EEC77A vcmpe.f32 s15, s14
2463 00b8 F1EE10FA vmrs APSR_nzcv, FPSCR
2464 00bc 4CBF ite mi
2465 00be 0121 movmi r1, #1
2466 00c0 0021 movpl r1, #0
2467 00c2 B942 cmp r1, r7
2468 00c4 08BF it eq
2469 00c6 1E46 moveq r6, r3
2470 .LVL303:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2471 .loc 17 87 0
2472 00c8 03F10103 add r3, r3, #1
2473 .LVL304:
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2474 .loc 17 89 0
2475 00cc 14BF ite ne
2476 00ce 04EB8600 addne r0, r4, r6, lsl #2
2477 00d2 B0EE677A vmoveq.f32 s14, s15
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2478 .loc 17 87 0
2479 00d6 9D42 cmp r5, r3
2480 00d8 E9D1 bne .L350
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
2481 .loc 17 96 0
2482 00da B445 cmp ip, r6
2483 .LVL305:
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** pA[k]=temp;
2484 .loc 17 100 0
2485 00dc 1CBF itt ne
2486 00de 89ED007A vstrne.32 s14, [r9]
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** }
2487 .loc 17 101 0
2488 00e2 C0ED006A vstrne.32 s13, [r0]
2489 .LVL306:
2490 .L348:
2491 00e6 F146 mov r9, lr
2492 .LVL307:
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_selection_sort_f32.c **** {
ARM GAS /tmp/cce2LIhc.s page 108
2493 .loc 17 87 0
2494 00e8 C446 mov ip, r8
2495 00ea D2E7 b .L347
2496 .LVL308:
2497 .L327:
2498 .LBE98:
2499 .LBE97:
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
2500 .loc 18 60 0
2501 00ec 2B46 mov r3, r5
2502 00ee 3046 mov r0, r6
2503 .loc 18 83 0
2504 00f0 BDE8F047 pop {r4, r5, r6, r7, r8, r9, r10, lr}
2505 .LCFI33:
2506 .cfi_remember_state
2507 .cfi_restore 14
2508 .cfi_restore 10
2509 .cfi_restore 9
2510 .cfi_restore 8
2511 .cfi_restore 7
2512 .cfi_restore 6
2513 .cfi_restore 5
2514 .cfi_restore 4
2515 .cfi_def_cfa_offset 0
2516 .LVL309:
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
2517 .loc 18 60 0
2518 00f4 FFF7FEBF b arm_bitonic_sort_f32
2519 .LVL310:
2520 .L330:
2521 .LCFI34:
2522 .cfi_restore_state
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
2523 .loc 18 68 0
2524 00f8 2B46 mov r3, r5
2525 00fa 3046 mov r0, r6
2526 .loc 18 83 0
2527 00fc BDE8F047 pop {r4, r5, r6, r7, r8, r9, r10, lr}
2528 .LCFI35:
2529 .cfi_remember_state
2530 .cfi_restore 14
2531 .cfi_restore 10
2532 .cfi_restore 9
2533 .cfi_restore 8
2534 .cfi_restore 7
2535 .cfi_restore 6
2536 .cfi_restore 5
2537 .cfi_restore 4
2538 .cfi_def_cfa_offset 0
2539 .LVL311:
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_f32.c **** break;
2540 .loc 18 68 0
2541 0100 FFF7FEBF b arm_heap_sort_f32
2542 .LVL312:
2543 .L331:
2544 .LCFI36:
2545 .cfi_restore_state
ARM GAS /tmp/cce2LIhc.s page 109
2546 .LBB99:
2547 .LBB100:
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
2548 .loc 15 69 0
2549 0104 9142 cmp r1, r2
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** uint32_t i, j;
2550 .loc 15 65 0
2551 0106 7678 ldrb r6, [r6, #1] @ zero_extendqisi2
2552 .LVL313:
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
2553 .loc 15 69 0
2554 0108 03D0 beq .L340
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA = pDst;
2555 .loc 15 71 0
2556 010a AA00 lsls r2, r5, #2
2557 .LVL314:
2558 010c 2046 mov r0, r4
2559 010e FFF7FEFF bl memcpy
2560 .LVL315:
2561 .L340:
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
2562 .loc 15 78 0
2563 0112 002D cmp r5, #0
2564 0114 AFD0 beq .L325
2565 0116 2246 mov r2, r4
2566 0118 0027 movs r7, #0
2567 .LVL316:
2568 .L341:
2569 011a 0137 adds r7, r7, #1
2570 .LVL317:
2571 011c BD42 cmp r5, r7
2572 011e AAD0 beq .L325
2573 .LVL318:
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
2574 .loc 15 81 0
2575 0120 92ED017A vldr.32 s14, [r2, #4]
2576 0124 D2ED007A vldr.32 s15, [r2]
2577 0128 F4EEC77A vcmpe.f32 s15, s14
2578 012c F1EE10FA vmrs APSR_nzcv, FPSCR
2579 0130 CCBF ite gt
2580 0132 0123 movgt r3, #1
2581 0134 0023 movle r3, #0
2582 0136 B342 cmp r3, r6
2583 0138 02F1040C add ip, r2, #4
2584 013c 15D1 bne .L342
2585 013e 6046 mov r0, ip
2586 0140 02F10801 add r1, r2, #8
2587 0144 3B46 mov r3, r7
2588 0146 0AE0 b .L343
2589 .LVL319:
2590 .L371:
2591 0148 72ED017A vldmdb.32 r2!, {s15}
2592 014c F4EEC77A vcmpe.f32 s15, s14
2593 0150 F1EE10FA vmrs APSR_nzcv, FPSCR
2594 0154 CCBF ite gt
2595 0156 0124 movgt r4, #1
2596 0158 0024 movle r4, #0
ARM GAS /tmp/cce2LIhc.s page 110
2597 015a B442 cmp r4, r6
2598 015c 05D1 bne .L342
2599 .LVL320:
2600 .L343:
2601 015e 013B subs r3, r3, #1
2602 .LVL321:
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** pA[j-1] = temp;
2603 .loc 15 85 0
2604 0160 61ED017A vstmdb.32 r1!, {s15}
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** }
2605 .loc 15 86 0
2606 0164 20ED017A vstmdb.32 r0!, {s14}
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_insertion_sort_f32.c **** {
2607 .loc 15 81 0
2608 0168 EED1 bne .L371
2609 .LVL322:
2610 .L342:
2611 016a 6246 mov r2, ip
2612 016c D5E7 b .L341
2613 .LVL323:
2614 .L332:
2615 .LBE100:
2616 .LBE99:
2617 .LBB101:
2618 .LBB102:
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** {
2619 .loc 1 167 0
2620 016e 9142 cmp r1, r2
2621 0170 03D0 beq .L345
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** pA = pDst;
2622 .loc 1 169 0
2623 0172 AA00 lsls r2, r5, #2
2624 .LVL324:
2625 0174 2046 mov r0, r4
2626 0176 FFF7FEFF bl memcpy
2627 .LVL325:
2628 .L345:
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The previous function could be called recursively a maximum
2629 .loc 1 175 0
2630 017a 7378 ldrb r3, [r6, #1] @ zero_extendqisi2
2631 017c 6A1E subs r2, r5, #1
2632 017e 2046 mov r0, r4
2633 0180 0021 movs r1, #0
2634 .LBE102:
2635 .LBE101:
2636 .loc 18 83 0
2637 0182 BDE8F047 pop {r4, r5, r6, r7, r8, r9, r10, lr}
2638 .LCFI37:
2639 .cfi_remember_state
2640 .cfi_restore 14
2641 .cfi_restore 10
2642 .cfi_restore 9
2643 .cfi_restore 8
2644 .cfi_restore 7
2645 .cfi_restore 6
2646 .cfi_restore 5
2647 .cfi_restore 4
ARM GAS /tmp/cce2LIhc.s page 111
2648 .cfi_def_cfa_offset 0
2649 .LVL326:
2650 .LBB104:
2651 .LBB103:
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_quick_sort_f32.c **** /* The previous function could be called recursively a maximum
2652 .loc 1 175 0
2653 0186 FFF7FEBF b arm_quick_sort_core_f32
2654 .LVL327:
2655 .L369:
2656 .LCFI38:
2657 .cfi_restore_state
2658 .LBE103:
2659 .LBE104:
2660 .LBB105:
2661 .LBB96:
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_bubble_sort_f32.c **** {
2662 .loc 5 80 0
2663 018a 002F cmp r7, #0
2664 018c 7FF46CAF bne .L368
2665 0190 71E7 b .L325
2666 .LVL328:
2667 .L370:
2668 0192 09F1040E add lr, r9, #4
2669 0196 A6E7 b .L348
2670 .LBE96:
2671 .LBE105:
2672 .cfi_endproc
2673 .LFE171:
2675 .section .text.arm_sort_init_f32,"ax",%progbits
2676 .align 1
2677 .p2align 2,,3
2678 .global arm_sort_init_f32
2679 .syntax unified
2680 .thumb
2681 .thumb_func
2682 .fpu fpv4-sp-d16
2684 arm_sort_init_f32:
2685 .LFB172:
2686 .file 19 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Title: arm_sort_init_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Description: Floating point sort initialization function
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * $Date: 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * You may obtain a copy of the License at
ARM GAS /tmp/cce2LIhc.s page 112
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** #include "arm_sorting.h"
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** @ingroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** */
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c ****
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** /**
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** @addtogroup Sorting
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** @{
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** */
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c ****
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** /**
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * @param[in,out] S points to an instance of the sorting structure.
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * @param[in] alg Selected algorithm.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** * @param[in] dir Sorting order.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** */
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** void arm_sort_init_f32(arm_sort_instance_f32 * S, arm_sort_alg alg, arm_sort_dir dir)
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** {
2687 .loc 19 48 0
2688 .cfi_startproc
2689 @ args = 0, pretend = 0, frame = 0
2690 @ frame_needed = 0, uses_anonymous_args = 0
2691 @ link register save eliminated.
2692 .LVL329:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** S->alg = alg;
2693 .loc 19 49 0
2694 0000 0170 strb r1, [r0]
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** S->dir = dir;
2695 .loc 19 50 0
2696 0002 4270 strb r2, [r0, #1]
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_sort_init_f32.c **** }
2697 .loc 19 51 0
2698 0004 7047 bx lr
2699 .cfi_endproc
2700 .LFE172:
2702 0006 00BF .section .text.arm_spline_f32,"ax",%progbits
2703 .align 1
2704 .p2align 2,,3
2705 .global arm_spline_f32
2706 .syntax unified
2707 .thumb
2708 .thumb_func
2709 .fpu fpv4-sp-d16
2711 arm_spline_f32:
2712 .LFB173:
ARM GAS /tmp/cce2LIhc.s page 113
2713 .file 20 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f3
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Title: arm_spline_interp_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Description: Floating-point cubic spline interpolation
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * $Date: 13 November 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @defgroup SplineInterpolate Cubic Spline Interpolation
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Spline interpolation is a method of interpolation where the interpolant
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** is a piecewise-defined polynomial called "spline".
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @par Introduction
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Given a function f defined on the interval [a,b], a set of n nodes x(i)
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** where a=x(1)<x(2)<...<x(n)=b and a set of n values y(i) = f(x(i)),
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** a cubic spline interpolant S(x) is defined as:
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** S1(x) x(1) < x < x(2)
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** S(x) = ...
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Sn-1(x) x(n-1) < x < x(n)
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** where
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Si(x) = a_i+b_i(x-xi)+c_i(x-xi)^2+d_i(x-xi)^3 i=1, ..., n-1
ARM GAS /tmp/cce2LIhc.s page 114
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @par Algorithm
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Having defined h(i) = x(i+1) - x(i)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** h(i-1)c(i-1)+2[h(i-1)+h(i)]c(i)+h(i)c(i+1) = 3/h(i)*[a(i+1)-a(i)]-3/h(i-1)*[a(i)-a(i-1)] i=2,
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** It is possible to write the previous conditions in matrix form (Ax=B).
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** In order to solve the system two boundary conidtions are needed.
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** - Natural spline: S1''(x1)=2*c(1)=0 ; Sn''(xn)=2*c(n)=0
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** In matrix form:
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 1 0 0 ... 0 0 0 || c(1) | |
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | h(0) 2[h(0)+h(1)] h(1) ... 0 0 0 || c(2) | | 3/h(2)*[a(3)-a(2)]
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | ... ... ... ... ... ... ... || ... |=| .
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 0 0 0 ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 0 0 0 ... 0 0 1 || c(n) | |
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** - Parabolic runout spline: S1''(x1)=2*c(1)=S2''(x2)=2*c(2) ; Sn-1''(xn-1)=2*c(n-1)=Sn''(xn)=2*c(n
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** In matrix form:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 1 -1 0 ... 0 0 0 || c(1) | |
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | h(0) 2[h(0)+h(1)] h(1) ... 0 0 0 || c(2) | | 3/h(2)*[a(3)-a(2)]
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | ... ... ... ... ... ... ... || ... |=| .
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 0 0 0 ... h(n-2) 2[h(n-2)+h(n-1)] h(n-1) || c(n-1) | | 3/h(n-1)*[a(n)-a(n-1)]-
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** | 0 0 0 ... 0 -1 1 || c(n) | |
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** A is a tridiagonal matrix (a band matrix of bandwidth 3) of size N=n+1. The factorization
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** algorithms (A=LU) can be simplified considerably because a large number of zeros appear
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** in regular patterns. The Crout method has been used:
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** 1) Solve LZ=B
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** u(1,2) = A(1,2)/A(1,1)
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** z(1) = B(1)/l(11)
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** FOR i=2, ..., N-1
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** l(i,i) = A(i,i)-A(i,i-1)u(i-1,i)
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** u(i,i+1) = a(i,i+1)/l(i,i)
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** z(i) = [B(i)-A(i,i-1)z(i-1)]/l(i,i)
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** l(N,N) = A(N,N)-A(N,N-1)u(N-1,N)
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** z(N) = [B(N)-A(N,N-1)z(N-1)]/l(N,N)
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** 2) Solve UX=Z
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** <pre>
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** c(N)=z(N)
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 115
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** FOR i=N-1, ..., 1
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** c(i)=z(i)-u(i,i+1)c(i+1)
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** </pre>
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** c(i) for i=1, ..., n-1 are needed to compute the n-1 polynomials.
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** b(i) and d(i) are computed as:
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** - b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** - d(i) = [c(i+1)-c(i)]/[3*h(i)]
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** Moreover, a(i)=y(i).
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @par Behaviour outside the given intervals
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** It is possible to compute the interpolated vector for x values outside the
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** input range (xq<x(1); xq>x(n)). The coefficients used to compute the y values for
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** xq<x(1) are going to be the ones used for the first interval, while for xq>x(n) the
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** coefficients used for the last interval.
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /**
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @addtogroup SplineInterpolate
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** @{
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** */
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /**
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * @brief Processing function for the floating-point cubic spline interpolation.
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * @param[in] S points to an instance of the floating-point spline structure.
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * @param[in] xq points to the x values ot the interpolated data points.
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * @param[out] pDst points to the block of output data.
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** * @param[in] blockSize number of samples of output data.
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** */
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** void arm_spline_f32(
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** arm_spline_instance_f32 * S,
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** const float32_t * xq,
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * pDst,
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** uint32_t blockSize)
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2714 .loc 20 151 0
2715 .cfi_startproc
2716 @ args = 0, pretend = 0, frame = 8
2717 @ frame_needed = 0, uses_anonymous_args = 0
2718 .LVL330:
2719 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2720 .LCFI39:
2721 .cfi_def_cfa_offset 36
2722 .cfi_offset 4, -36
2723 .cfi_offset 5, -32
2724 .cfi_offset 6, -28
2725 .cfi_offset 7, -24
2726 .cfi_offset 8, -20
2727 .cfi_offset 9, -16
2728 .cfi_offset 10, -12
2729 .cfi_offset 11, -8
2730 .cfi_offset 14, -4
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** const float32_t * x = S->x;
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** const float32_t * y = S->y;
ARM GAS /tmp/cce2LIhc.s page 116
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** int32_t n = S->n_x;
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Coefficients (a==y for i<=n-1) */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * b = (S->coeffs);
2731 .loc 20 157 0
2732 0004 D0E9034E ldrd r4, lr, [r0, #12]
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * c = (S->coeffs)+(n-1);
2733 .loc 20 158 0
2734 0008 04F1804B add fp, r4, #1073741824
2735 000c 0BF1FF3B add fp, fp, #-1
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** const float32_t * x = S->x;
2736 .loc 20 151 0
2737 0010 83B0 sub sp, sp, #12
2738 .LCFI40:
2739 .cfi_def_cfa_offset 48
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * d = (S->coeffs)+(2*(n-1));
2740 .loc 20 159 0
2741 0012 04F1FF3C add ip, r4, #-1
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * c = (S->coeffs)+(n-1);
2742 .loc 20 158 0
2743 0016 4FEA8B0B lsl fp, fp, #2
2744 001a 0EEB0B06 add r6, lr, fp
2745 .loc 20 159 0
2746 001e 0EEBCC05 add r5, lr, ip, lsl #3
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** const float32_t * pXq = xq;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** int32_t blkCnt = (int32_t)blockSize;
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** int32_t blkCnt2;
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** int32_t i;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t x_sc;
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #ifdef ARM_MATH_NEON
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t xiv;
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t aiv;
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t biv;
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t civ;
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t div;
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t xqv;
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t temp;
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t diff;
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32x4_t yv;
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #endif
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Create output for x(i)<x<x(i+1) */
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** for (i=0; i<n-1; i++)
2747 .loc 20 182 0
2748 0022 BCF1000F cmp ip, #0
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** int32_t n = S->n_x;
2749 .loc 20 153 0
2750 0026 D0E90189 ldrd r8, r9, [r0, #4]
2751 .LVL331:
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** float32_t * d = (S->coeffs)+(2*(n-1));
2752 .loc 20 158 0
2753 002a 0096 str r6, [sp]
2754 .LVL332:
ARM GAS /tmp/cce2LIhc.s page 117
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
2755 .loc 20 159 0
2756 002c 0195 str r5, [sp, #4]
2757 .LVL333:
2758 .loc 20 182 0
2759 002e 69DD ble .L383
2760 0030 D1ED007A vldr.32 s15, [r1]
2761 0034 C344 add fp, fp, r8
2762 0036 4446 mov r4, r8
2763 .LVL334:
2764 0038 CA46 mov r10, r9
2765 003a 7746 mov r7, lr
2766 .LVL335:
2767 .L375:
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #ifdef ARM_MATH_NEON
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** xiv = vdupq_n_f32(x[i]);
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** aiv = vdupq_n_f32(y[i]);
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** biv = vdupq_n_f32(b[i]);
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** civ = vdupq_n_f32(c[i]);
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** div = vdupq_n_f32(d[i]);
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** while( *(pXq+4) <= x[i+1] && blkCnt > 4 )
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** xqv = vld1q_f32(pXq);
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pXq+=4;
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** diff = vsubq_f32(xqv, xiv);
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = diff;
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* y(i) = a(i) + ... */
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = aiv;
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + b(i)*(x-x(i)) + ... */
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, biv, temp);
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + c(i)*(x-x(i))^2 + ... */
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = vmulq_f32(temp, diff);
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, civ, temp);
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + d(i)*(x-x(i))^3 */
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = vmulq_f32(temp, diff);
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, div, temp);
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Store [y(k) y(k+1) y(k+2) y(k+3)] */
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** vst1q_f32(pDst, yv);
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pDst+=4;
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt-=4;
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #endif
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** while( *pXq <= x[i+1] && blkCnt > 0 )
2768 .loc 20 220 0
2769 003c 94ED017A vldr.32 s14, [r4, #4]
2770 0040 B4EEE77A vcmpe.f32 s14, s15
2771 0044 F1EE10FA vmrs APSR_nzcv, FPSCR
2772 0048 26DB blt .L376
ARM GAS /tmp/cce2LIhc.s page 118
2773 004a 002B cmp r3, #0
2774 004c C8BF it gt
2775 004e 081D addgt r0, r1, #4
2776 0050 01DC bgt .L378
2777 0052 21E0 b .L376
2778 .LVL336:
2779 .L391:
2780 .loc 20 220 0 is_stmt 0 discriminator 1
2781 0054 03B3 cbz r3, .L376
2782 .L378:
2783 .LVL337:
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** x_sc = *pXq++;
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *pDst = y[i]+b[i]*(x_sc-x[i])+c[i]*(x_sc-x[i])*(x_sc-x[i])+d[i]*(x_sc-x[i])*(x_sc-x[i])
2784 .loc 20 224 0 is_stmt 1
2785 0056 94ED007A vldr.32 s14, [r4]
2786 005a D6ED005A vldr.32 s11, [r6]
2787 005e 95ED005A vldr.32 s10, [r5]
2788 0062 97ED006A vldr.32 s12, [r7]
2789 0066 DAED006A vldr.32 s13, [r10]
2790 006a 77EEC77A vsub.f32 s15, s15, s14
2791 006e B0EE657A vmov.f32 s14, s11
2792 0072 A7EE857A vfma.f32 s14, s15, s10
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
2793 .loc 20 222 0
2794 0076 0146 mov r1, r0
2795 .LVL338:
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pDst++;
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt--;
2796 .loc 20 227 0
2797 0078 013B subs r3, r3, #1
2798 .LVL339:
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
2799 .loc 20 224 0
2800 007a A7EE876A vfma.f32 s12, s15, s14
2801 007e E7EE866A vfma.f32 s13, s15, s12
2802 0082 E2EC016A vstmia.32 r2!, {s13}
2803 .LVL340:
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2804 .loc 20 220 0
2805 0086 F0EC017A vldmia.32 r0!, {s15}
2806 .LVL341:
2807 008a 94ED017A vldr.32 s14, [r4, #4]
2808 008e F4EEC77A vcmpe.f32 s15, s14
2809 0092 F1EE10FA vmrs APSR_nzcv, FPSCR
2810 0096 DDD9 bls .L391
2811 .L376:
2812 0098 0434 adds r4, r4, #4
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2813 .loc 20 182 0 discriminator 2
2814 009a A345 cmp fp, r4
2815 009c 0AF1040A add r10, r10, #4
2816 00a0 07F10407 add r7, r7, #4
2817 00a4 06F10406 add r6, r6, #4
2818 00a8 05F10405 add r5, r5, #4
ARM GAS /tmp/cce2LIhc.s page 119
2819 00ac C6D1 bne .L375
2820 .LVL342:
2821 .L374:
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Create output for remaining samples (x>=x(n)) */
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #ifdef ARM_MATH_NEON
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Compute 4 outputs at a time */
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt2 = blkCnt >> 2;
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** while(blkCnt2 > 0)
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Load [xq(k) xq(k+1) xq(k+2) xq(k+3)] */
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** xqv = vld1q_f32(pXq);
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pXq+=4;
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Compute [xq(k)-x(i) xq(k+1)-x(i) xq(k+2)-x(i) xq(k+3)-x(i)] */
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** diff = vsubq_f32(xqv, xiv);
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = diff;
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* y(i) = a(i) + ... */
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = aiv;
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + b(i)*(x-x(i)) + ... */
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, biv, temp);
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + c(i)*(x-x(i))^2 + ... */
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = vmulq_f32(temp, diff);
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, civ, temp);
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* ... + d(i)*(x-x(i))^3 */
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** temp = vmulq_f32(temp, diff);
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** yv = vmlaq_f32(yv, div, temp);
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Store [y(k) y(k+1) y(k+2) y(k+3)] */
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** vst1q_f32(pDst, yv);
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pDst+=4;
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt2--;
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** /* Tail */
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt2 = blkCnt & 3;
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #else
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt2 = blkCnt;
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** #endif
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** while(blkCnt2 > 0)
2822 .loc 20 270 0
2823 00ae 002B cmp r3, #0
2824 00b0 25DD ble .L373
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** x_sc = *pXq++;
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** *pDst = y[i-1]+b[i-1]*(x_sc-x[i-1])+c[i-1]*(x_sc-x[i-1])*(x_sc-x[i-1])+d[i-1]*(x_sc-x[i-1])
2825 .loc 20 274 0
2826 00b2 0CF18040 add r0, ip, #1073741824
2827 00b6 0138 subs r0, r0, #1
2828 00b8 019D ldr r5, [sp, #4]
ARM GAS /tmp/cce2LIhc.s page 120
2829 00ba 009C ldr r4, [sp]
2830 00bc 8000 lsls r0, r0, #2
2831 00be 0544 add r5, r5, r0
2832 00c0 8144 add r9, r9, r0
2833 .LVL343:
2834 00c2 8644 add lr, lr, r0
2835 .LVL344:
2836 00c4 8044 add r8, r8, r0
2837 00c6 0444 add r4, r4, r0
2838 00c8 2846 mov r0, r5
2839 .LVL345:
2840 .L382:
2841 00ca B1EC017A vldmia.32 r1!, {s14}
2842 .LVL346:
2843 00ce D8ED007A vldr.32 s15, [r8]
2844 00d2 D4ED005A vldr.32 s11, [r4]
2845 00d6 90ED005A vldr.32 s10, [r0]
2846 00da 9EED006A vldr.32 s12, [lr]
2847 00de D9ED006A vldr.32 s13, [r9]
2848 00e2 77EE677A vsub.f32 s15, s14, s15
2849 00e6 B0EE657A vmov.f32 s14, s11
2850 00ea A7EE857A vfma.f32 s14, s15, s10
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2851 .loc 20 270 0
2852 00ee 013B subs r3, r3, #1
2853 .LVL347:
2854 .loc 20 274 0
2855 00f0 A7EE876A vfma.f32 s12, s15, s14
2856 00f4 E7EE866A vfma.f32 s13, s15, s12
2857 00f8 E2EC016A vstmia.32 r2!, {s13}
2858 .LVL348:
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2859 .loc 20 270 0
2860 00fc E5D1 bne .L382
2861 .L373:
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c ****
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** pDst++;
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** blkCnt2--;
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** }
2862 .loc 20 279 0
2863 00fe 03B0 add sp, sp, #12
2864 .LCFI41:
2865 .cfi_remember_state
2866 .cfi_def_cfa_offset 36
2867 .LVL349:
2868 @ sp needed
2869 0100 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2870 .LVL350:
2871 .L383:
2872 .LCFI42:
2873 .cfi_restore_state
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_f32.c **** {
2874 .loc 20 182 0
2875 0104 4FF0000C mov ip, #0
2876 0108 D1E7 b .L374
2877 .cfi_endproc
ARM GAS /tmp/cce2LIhc.s page 121
2878 .LFE173:
2880 010a 00BF .section .text.arm_spline_init_f32,"ax",%progbits
2881 .align 1
2882 .p2align 2,,3
2883 .global arm_spline_init_f32
2884 .syntax unified
2885 .thumb
2886 .thumb_func
2887 .fpu fpv4-sp-d16
2889 arm_spline_init_f32:
2890 .LFB174:
2891 .file 21 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_in
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Title: arm_spline_interp_init_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Description: Floating-point cubic spline initialization function
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * $Date: 13 November 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** @addtogroup SplineInterpolate
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** @par Initialization function
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** The initialization function takes as input two arrays that the user has to allocate:
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** <code>coeffs</code> will contain the b, c, and d coefficients for the (n-1) intervals
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** (n is the number of known points), hence its size must be 3*(n-1); <code>tempBuffer</code>
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** is temporally used for internal computations and its size is n+n-1.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
ARM GAS /tmp/cce2LIhc.s page 122
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** @par
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** The x input array must be strictly sorted in ascending order and it must
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** not contain twice the same value (x(i)<x(i+1)).
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** */
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /**
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @brief Initialization function for the floating-point cubic spline interpolation.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in,out] S points to an instance of the floating-point spline structure.
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] type type of cubic spline interpolation (boundary conditions)
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] x points to the x values of the known data points.
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] y points to the y values of the known data points.
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] n number of known data points.
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] coeffs coefficients array for b, c, and d
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** * @param[in] tempBuffer buffer array for internal computations
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** *
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** */
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** void arm_spline_init_f32(
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** arm_spline_instance_f32 * S,
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** arm_spline_type type,
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** const float32_t * x,
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** const float32_t * y,
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** uint32_t n,
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * coeffs,
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * tempBuffer)
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
2892 .loc 21 73 0
2893 .cfi_startproc
2894 @ args = 12, pretend = 0, frame = 8
2895 @ frame_needed = 0, uses_anonymous_args = 0
2896 .LVL351:
2897 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2898 .LCFI43:
2899 .cfi_def_cfa_offset 36
2900 .cfi_offset 4, -36
2901 .cfi_offset 5, -32
2902 .cfi_offset 6, -28
2903 .cfi_offset 7, -24
2904 .cfi_offset 8, -20
2905 .cfi_offset 9, -16
2906 .cfi_offset 10, -12
2907 .cfi_offset 11, -8
2908 .cfi_offset 14, -4
2909 0004 83B0 sub sp, sp, #12
2910 .LCFI44:
2911 .cfi_def_cfa_offset 48
2912 .loc 21 73 0
2913 0006 DDE90C5A ldrd r5, r10, [sp, #48]
2914 .LVL352:
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /*** COEFFICIENTS COMPUTATION ***/
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* Type (boundary conditions):
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** - Natural spline ( S1''(x1) = 0 ; Sn''(xn) = 0 )
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** - Parabolic runout spline ( S1''(x1) = S2''(x2) ; Sn-1''(xn-1) = Sn''(xn) ) */
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* (n-1)-long buffers for b, c, and d coefficients */
ARM GAS /tmp/cce2LIhc.s page 123
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * b = coeffs;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * c = coeffs+(n-1);
2915 .loc 21 81 0
2916 000a 05F18044 add r4, r5, #1073741824
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * d = coeffs+(2*(n-1));
2917 .loc 21 82 0
2918 000e 05F10056 add r6, r5, #536870912
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * d = coeffs+(2*(n-1));
2919 .loc 21 81 0
2920 0012 013C subs r4, r4, #1
2921 .loc 21 82 0
2922 0014 013E subs r6, r6, #1
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * u = tempBuffer; /* (n-1)-long scratch buffer for u elements */
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * z = tempBuffer+(n-1); /* n-long scratch buffer for z elements */
2923 .loc 21 85 0
2924 0016 0E9F ldr r7, [sp, #56]
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t hi, hm1; /* h(i) and h(i-1) */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t Bi; /* B(i), i-th element of matrix B=LZ */
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t li; /* l(i), i-th element of matrix L */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t cp1; /* Temporary value for c(i+1) */
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** int32_t i; /* Loop counter */
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** S->x = x;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** S->y = y;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** S->n_x = n;
2925 .loc 21 96 0
2926 0018 C560 str r5, [r0, #12]
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** float32_t * d = coeffs+(2*(n-1));
2927 .loc 21 81 0
2928 001a A400 lsls r4, r4, #2
2929 .LVL353:
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2930 .loc 21 82 0
2931 001c F600 lsls r6, r6, #3
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** S->n_x = n;
2932 .loc 21 95 0
2933 001e C0E90123 strd r2, r3, [r0, #4]
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2934 .loc 21 85 0
2935 0022 07EB0408 add r8, r7, r4
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2936 .loc 21 82 0
2937 0026 0196 str r6, [sp, #4]
2938 .LVL354:
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* == Solve LZ=B to obtain z(i) and u(i) == */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* -- Row 1 -- */
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* B(0) = 0, not computed */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* u(1,2) = a(1,2)/a(1,1) = a(1,2) */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** if(type == ARM_SPLINE_NATURAL)
2939 .loc 21 103 0
2940 0028 0029 cmp r1, #0
2941 002a 40F0AA80 bne .L393
ARM GAS /tmp/cce2LIhc.s page 124
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** u[0] = 0; /* a(1,2) = 0 */
2942 .loc 21 104 0
2943 002e 0026 movs r6, #0
2944 .LVL355:
2945 0030 3E60 str r6, [r7] @ float
2946 .L394:
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** else if(type == ARM_SPLINE_PARABOLIC_RUNOUT)
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** u[0] = -1; /* a(1,2) = -1 */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[0] = 0; /* z(1) = B(1)/a(1,1) = 0 always */
2947 .loc 21 108 0
2948 0032 0026 movs r6, #0
2949 0034 C8F80060 str r6, [r8] @ float
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* -- Rows 2 to N-1 (N=n+1) -- */
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** hm1 = x[1] - x[0]; /* Initialize h(i-1) = h(1) = x(2)-x(1) */
2950 .loc 21 111 0
2951 0038 92ED015A vldr.32 s10, [r2, #4]
2952 003c D2ED007A vldr.32 s15, [r2]
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** for (i=1; i<(int32_t)n-1; i++)
2953 .loc 21 113 0
2954 0040 022D cmp r5, #2
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2955 .loc 21 111 0
2956 0042 35EE675A vsub.f32 s10, s10, s15
2957 .LVL356:
2958 .loc 21 113 0
2959 0046 44DD ble .L395
2960 0048 DDF838C0 ldr ip, [sp, #56]
2961 004c 161D adds r6, r2, #4
2962 004e 9E46 mov lr, r3
2963 0050 4746 mov r7, r8
2964 .LVL357:
2965 0052 02EB040B add fp, r2, r4
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* Compute B(i) */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** hi = x[i+1]-x[i];
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1;
2966 .loc 21 117 0
2967 0056 F0EE084A vmov.f32 s9, #3.0e+0
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* l(i) = a(i)-a(i,i-1)*u(i-1) = 2[h(i-1)+h(i)]-h(i-1)*u(i-1) */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** li = 2*(hi+hm1) - hm1*u[i-1];
2968 .loc 21 120 0
2969 005a F0EE003A vmov.f32 s7, #2.0e+0
2970 .LVL358:
2971 .L396:
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1;
2972 .loc 21 116 0 discriminator 3
2973 005e 96ED017A vldr.32 s14, [r6, #4]
2974 0062 D6ED007A vldr.32 s15, [r6]
2975 .loc 21 120 0 discriminator 3
2976 0066 DCED005A vldr.32 s11, [ip]
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** Bi = 3*(y[i+1]-y[i])/hi - 3*(y[i]-y[i-1])/hm1;
2977 .loc 21 116 0 discriminator 3
2978 006a 77EE677A vsub.f32 s15, s14, s15
ARM GAS /tmp/cce2LIhc.s page 125
2979 .LVL359:
2980 .loc 21 120 0 discriminator 3
2981 006e 65EE655A vnmul.f32 s11, s10, s11
2982 0072 37EE857A vadd.f32 s14, s15, s10
2983 0076 F146 mov r9, lr
2984 0078 E7EE235A vfma.f32 s11, s14, s7
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2985 .loc 21 117 0 discriminator 3
2986 007c 0EF1040E add lr, lr, #4
2987 0080 0436 adds r6, r6, #4
2988 0082 D9ED006A vldr.32 s13, [r9]
2989 0086 9EED007A vldr.32 s14, [lr]
2990 008a 99ED026A vldr.32 s12, [r9, #8]
2991 008e 36EE476A vsub.f32 s12, s12, s14
2992 0092 36EEC77A vsub.f32 s14, s13, s14
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* u(i) = a(i,i+1)/l(i) = h(i)/l(i) */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** u[i] = hi/li;
2993 .loc 21 123 0 discriminator 3
2994 0096 87EEA54A vdiv.f32 s8, s15, s11
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
2995 .loc 21 113 0 discriminator 3
2996 009a B345 cmp fp, r6
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
2997 .loc 21 117 0 discriminator 3
2998 009c 66EE246A vmul.f32 s13, s12, s9
2999 00a0 27EE247A vmul.f32 s14, s14, s9
3000 00a4 86EEA76A vdiv.f32 s12, s13, s15
3001 00a8 C7EE056A vdiv.f32 s13, s14, s10
3002 .loc 21 123 0 discriminator 3
3003 00ac 14EE109A vmov r9, s8
3004 00b0 4CF8049F str r9, [ip, #4]! @ float
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* z(i) = [B(i)-h(i-1)*z(i-1)]/l(i) */
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[i] = (Bi-hm1*z[i-1])/li;
3005 .loc 21 126 0 discriminator 3
3006 00b4 97ED004A vldr.32 s8, [r7]
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3007 .loc 21 117 0 discriminator 3
3008 00b8 36EE267A vadd.f32 s14, s12, s13
3009 .LVL360:
3010 .loc 21 126 0 discriminator 3
3011 00bc A4EE457A vfms.f32 s14, s8, s10
3012 .LVL361:
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* Update h(i-1) for next iteration */
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** hm1 = hi;
3013 .loc 21 129 0 discriminator 3
3014 00c0 B0EE675A vmov.f32 s10, s15
3015 .LVL362:
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3016 .loc 21 126 0 discriminator 3
3017 00c4 C7EE257A vdiv.f32 s15, s14, s11
3018 .LVL363:
3019 00c8 17EE909A vmov r9, s15
3020 00cc 47F8049F str r9, [r7, #4]! @ float
3021 .LVL364:
ARM GAS /tmp/cce2LIhc.s page 126
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
3022 .loc 21 113 0 discriminator 3
3023 00d0 C5D1 bne .L396
3024 .LVL365:
3025 .L395:
3026 00d2 08EB0407 add r7, r8, r4
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* -- Row N -- */
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* l(N) = a(N,N)-a(N,N-1)u(N-1) */
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* z(N) = [-a(N,N-1)z(N-1)]/l(N) */
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** if(type == ARM_SPLINE_NATURAL)
3027 .loc 21 135 0
3028 00d6 0029 cmp r1, #0
3029 00d8 4ED1 bne .L397
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* li = 1; a(N,N) = 1; a(N,N-1) = 0 */
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[n-1] = 0; /* a(N,N-1) = 0 */
3030 .loc 21 138 0
3031 00da DFED356A vldr.32 s13, .L405
3032 00de C7ED006A vstr.32 s13, [r7]
3033 .LVL366:
3034 .L398:
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** else if(type == ARM_SPLINE_PARABOLIC_RUNOUT)
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** li = 1+u[n-2]; /* a(N,N) = 1; a(N,N-1) = -1 */
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* == Solve UX = Z to obtain c(i) and */
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* compute b(i) and d(i) from c(i) == */
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** cp1 = z[n-1]; /* Initialize c(i+1) = c(N) = z(N) */
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** for (i=n-2; i>=0; i--)
3035 .loc 21 151 0
3036 00e2 023D subs r5, r5, #2
3037 .LVL367:
3038 00e4 43D4 bmi .L400
3039 00e6 0199 ldr r1, [sp, #4]
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* c(i) = z(i)-u(i+1)c(i+1) */
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** c[i] = z[i]-u[i]*cp1;
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** hi = x[i+1]-x[i];
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** b[i] = (y[i+1]-y[i])/hi-hi*(cp1+2*c[i])/3;
3040 .loc 21 158 0
3041 00e8 DFED323A vldr.32 s7, .L405+4
3042 00ec 2144 add r1, r1, r4
3043 00ee 04F1040C add ip, r4, #4
3044 00f2 0E46 mov r6, r1
3045 00f4 02EB0C0E add lr, r2, ip
3046 00f8 0AEB4401 add r1, r10, r4, lsl #1
3047 00fc 9C44 add ip, ip, r3
3048 00fe 2244 add r2, r2, r4
ARM GAS /tmp/cce2LIhc.s page 127
3049 .LVL368:
3050 0100 2344 add r3, r3, r4
3051 .LVL369:
3052 0102 5644 add r6, r6, r10
3053 0104 5444 add r4, r4, r10
3054 .LVL370:
3055 0106 B0EE004A vmov.f32 s8, #2.0e+0
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* d(i) = [c(i+1)-c(i)]/[3*h(i)] */
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** d[i] = (cp1-c[i])/(3*hi);
3056 .loc 21 161 0
3057 010a F0EE084A vmov.f32 s9, #3.0e+0
3058 .LVL371:
3059 .L401:
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3060 .loc 21 154 0 discriminator 3
3061 010e 78ED017A vldmdb.32 r8!, {s15}
3062 0112 37ED015A vldmdb.32 r7!, {s10}
3063 0116 A7EEE65A vfms.f32 s10, s15, s13
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
3064 .loc 21 151 0 discriminator 3
3065 011a 013D subs r5, r5, #1
3066 .LVL372:
3067 011c B5F1FF3F cmp r5, #-1
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3068 .loc 21 154 0 discriminator 3
3069 0120 21ED015A vstmdb.32 r1!, {s10}
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */
3070 .loc 21 156 0 discriminator 3
3071 0124 3EED017A vldmdb.32 lr!, {s14}
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3072 .loc 21 158 0 discriminator 3
3073 0128 7CED015A vldmdb.32 ip!, {s11}
3074 012c 33ED016A vldmdb.32 r3!, {s12}
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* b(i) = [y(i+1)-y(i)]/h(i)-h(i)*[c(i+1)+2*c(i)]/3 */
3075 .loc 21 156 0 discriminator 3
3076 0130 72ED017A vldmdb.32 r2!, {s15}
3077 0134 77EE677A vsub.f32 s15, s14, s15
3078 .LVL373:
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3079 .loc 21 158 0 discriminator 3
3080 0138 35EEC67A vsub.f32 s14, s11, s12
3081 013c F0EE665A vmov.f32 s11, s13
3082 0140 87EE276A vdiv.f32 s12, s14, s15
3083 0144 E5EE045A vfma.f32 s11, s10, s8
3084 0148 27EEA37A vmul.f32 s14, s15, s7
3085 .loc 21 161 0 discriminator 3
3086 014c 67EEA47A vmul.f32 s15, s15, s9
3087 .LVL374:
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3088 .loc 21 158 0 discriminator 3
3089 0150 A5EEC76A vfms.f32 s12, s11, s14
3090 0154 24ED016A vstmdb.32 r4!, {s12}
3091 .LVL375:
3092 .loc 21 161 0 discriminator 3
3093 0158 91ED007A vldr.32 s14, [r1]
3094 015c 76EEC76A vsub.f32 s13, s13, s14
ARM GAS /tmp/cce2LIhc.s page 128
3095 .LVL376:
3096 0160 86EEA77A vdiv.f32 s14, s13, s15
3097 0164 26ED017A vstmdb.32 r6!, {s14}
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* Update c(i+1) for next iteration */
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** cp1 = c[i];
3098 .loc 21 164 0 discriminator 3
3099 0168 D1ED006A vldr.32 s13, [r1]
3100 .LVL377:
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
3101 .loc 21 151 0 discriminator 3
3102 016c CFD1 bne .L401
3103 .LVL378:
3104 .L400:
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** /* == Finally, store the coefficients in the instance == */
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** S->coeffs = coeffs;
3105 .loc 21 169 0
3106 016e C0F810A0 str r10, [r0, #16]
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
3107 .loc 21 170 0
3108 0172 03B0 add sp, sp, #12
3109 .LCFI45:
3110 .cfi_remember_state
3111 .cfi_def_cfa_offset 36
3112 @ sp needed
3113 0174 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
3114 .LVL379:
3115 .L397:
3116 .LCFI46:
3117 .cfi_restore_state
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** {
3118 .loc 21 140 0
3119 0178 0129 cmp r1, #1
3120 017a 07D0 beq .L399
3121 017c D7ED006A vldr.32 s13, [r7]
3122 0180 AFE7 b .L398
3123 .LVL380:
3124 .L393:
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** u[0] = -1; /* a(1,2) = -1 */
3125 .loc 21 105 0
3126 0182 0129 cmp r1, #1
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c ****
3127 .loc 21 106 0
3128 0184 04BF itt eq
3129 0186 0C4E ldreq r6, .L405+8
3130 .LVL381:
3131 0188 3E60 streq r6, [r7] @ float
3132 018a 52E7 b .L394
3133 .LVL382:
3134 .L399:
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */
3135 .loc 21 142 0
3136 018c 0E99 ldr r1, [sp, #56]
3137 .LVL383:
ARM GAS /tmp/cce2LIhc.s page 129
3138 018e 261F subs r6, r4, #4
3139 .LVL384:
3140 0190 3144 add r1, r1, r6
3141 .LVL385:
3142 0192 D1ED007A vldr.32 s15, [r1]
3143 0196 B7EE007A vmov.f32 s14, #1.0e+0
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
3144 .loc 21 143 0
3145 019a 4644 add r6, r6, r8
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** z[n-1] = z[n-2]/li; /* a(N,N-1) = -1 */
3146 .loc 21 142 0
3147 019c 77EE877A vadd.f32 s15, s15, s14
3148 .LVL386:
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_spline_interp_init_f32.c **** }
3149 .loc 21 143 0
3150 01a0 96ED007A vldr.32 s14, [r6]
3151 01a4 C7EE276A vdiv.f32 s13, s14, s15
3152 01a8 C7ED006A vstr.32 s13, [r7]
3153 01ac 99E7 b .L398
3154 .L406:
3155 01ae 00BF .align 2
3156 .L405:
3157 01b0 00000000 .word 0
3158 01b4 ABAAAA3E .word 1051372203
3159 01b8 000080BF .word -1082130432
3160 .cfi_endproc
3161 .LFE174:
3163 .section .text.arm_weighted_sum_f32,"ax",%progbits
3164 .align 1
3165 .p2align 2,,3
3166 .global arm_weighted_sum_f32
3167 .syntax unified
3168 .thumb
3169 .thumb_func
3170 .fpu fpv4-sp-d16
3172 arm_weighted_sum_f32:
3173 .LFB175:
3174 .file 22 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Title: arm_weighted_sum_f32.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Description: Weighted Sum
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Target Processor: Cortex-M and Cortex-A cores
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * -------------------------------------------------------------------- */
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** /*
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * SPDX-License-Identifier: Apache-2.0
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * not use this file except in compliance with the License.
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * You may obtain a copy of the License at
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * www.apache.org/licenses/LICENSE-2.0
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
ARM GAS /tmp/cce2LIhc.s page 130
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * Unless required by applicable law or agreed to in writing, software
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * See the License for the specific language governing permissions and
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * limitations under the License.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** */
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #include "arm_math.h"
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #include <limits.h>
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #include <math.h>
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** /**
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @addtogroup groupSupport
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @{
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** */
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** /**
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @brief Weighted sum
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @param[in] *in Array of input values.
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @param[in] *weigths Weights
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @param[in] blockSize Number of samples in the input array.
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** * @return Weighted sum
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** *
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** */
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #include "arm_helium_utils.h"
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t accum1, accum2;
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** f32x4_t accum1V, accum2V;
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** f32x4_t inV, wV;
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** const float32_t *pIn, *pW;
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** uint32_t blkCnt;
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pIn = in;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pW = weigths;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1V = vdupq_n_f32(0.0);
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2V = vdupq_n_f32(0.0);
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt = blockSize >> 2;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** while (blkCnt > 0)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** inV = vld1q(pIn);
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** wV = vld1q(pW);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pIn += 4;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pW += 4;
ARM GAS /tmp/cce2LIhc.s page 131
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1V = vfmaq(accum1V, inV, wV);
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2V = vaddq(accum2V, wV);
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt--;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1 = vecAddAcrossF32Mve(accum1V);
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 = vecAddAcrossF32Mve(accum2V);
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt = blockSize & 3;
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** while(blkCnt > 0)
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1 += *pIn++ * *pW;
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 += *pW++;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt--;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** return (accum1 / accum2);
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #else
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #if defined(ARM_MATH_NEON)
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #include "NEMath.h"
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t arm_weighted_sum_f32(const float32_t *in,const float32_t *weigths, uint32_t blockSize)
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t accum1, accum2;
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32x4_t accum1V, accum2V;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32x2_t tempV;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32x4_t inV,wV;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** const float32_t *pIn, *pW;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** uint32_t blkCnt;
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pIn = in;
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pW = weigths;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1=0.0f;
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2=0.0f;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1V = vdupq_n_f32(0.0f);
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2V = vdupq_n_f32(0.0f);
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt = blockSize >> 2;
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** while(blkCnt > 0)
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** inV = vld1q_f32(pIn);
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** wV = vld1q_f32(pW);
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pIn += 4;
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pW += 4;
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1V = vmlaq_f32(accum1V,inV,wV);
ARM GAS /tmp/cce2LIhc.s page 132
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2V = vaddq_f32(accum2V,wV);
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt--;
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** tempV = vpadd_f32(vget_low_f32(accum1V),vget_high_f32(accum1V));
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1);
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** tempV = vpadd_f32(vget_low_f32(accum2V),vget_high_f32(accum2V));
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 = vget_lane_f32(tempV, 0) + vget_lane_f32(tempV, 1);
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt = blockSize & 3;
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** while(blkCnt > 0)
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1 += *pIn++ * *pW;
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 += *pW++;
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt--;
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** return(accum1 / accum2);
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** #else
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t arm_weighted_sum_f32(const float32_t *in, const float32_t *weigths, uint32_t blockSize)
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
3175 .loc 22 157 0
3176 .cfi_startproc
3177 @ args = 0, pretend = 0, frame = 0
3178 @ frame_needed = 0, uses_anonymous_args = 0
3179 @ link register save eliminated.
3180 .LVL387:
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** float32_t accum1, accum2;
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** const float32_t *pIn, *pW;
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** uint32_t blkCnt;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pIn = in;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** pW = weigths;
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1=0.0f;
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2=0.0f;
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt = blockSize;
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** while(blkCnt > 0)
3181 .loc 22 171 0
3182 0000 82B1 cbz r2, .L410
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
3183 .loc 22 168 0
3184 0002 9FED0A7A vldr.32 s14, .L412
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2=0.0f;
3185 .loc 22 167 0
3186 0006 F0EE476A vmov.f32 s13, s14
3187 .LVL388:
3188 .L409:
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum1 += *pIn++ * *pW;
3189 .loc 22 173 0
ARM GAS /tmp/cce2LIhc.s page 133
3190 000a F1EC017A vldmia.32 r1!, {s15}
3191 .LVL389:
3192 000e B0EC016A vldmia.32 r0!, {s12}
3193 .LVL390:
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
3194 .loc 22 171 0
3195 0012 013A subs r2, r2, #1
3196 .LVL391:
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 += *pW++;
3197 .loc 22 174 0
3198 0014 37EE277A vadd.f32 s14, s14, s15
3199 .LVL392:
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** accum2 += *pW++;
3200 .loc 22 173 0
3201 0018 E6EE276A vfma.f32 s13, s12, s15
3202 .LVL393:
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** {
3203 .loc 22 171 0
3204 001c F5D1 bne .L409
3205 001e 86EE870A vdiv.f32 s0, s13, s14
3206 0022 7047 bx lr
3207 .LVL394:
3208 .L410:
3209 0024 9FED020A vldr.32 s0, .L412+4
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** blkCnt--;
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** return(accum1 / accum2);
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_weighted_sum_f32.c **** }
3210 .loc 22 179 0
3211 0028 7047 bx lr
3212 .L413:
3213 002a 00BF .align 2
3214 .L412:
3215 002c 00000000 .word 0
3216 0030 0000C07F .word 2143289344
3217 .cfi_endproc
3218 .LFE175:
3220 .section .text.arm_float_to_q15,"ax",%progbits
3221 .align 1
3222 .p2align 2,,3
3223 .global arm_float_to_q15
3224 .syntax unified
3225 .thumb
3226 .thumb_func
3227 .fpu fpv4-sp-d16
3229 arm_float_to_q15:
3230 .LFB176:
3231 .file 23 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Title: arm_float_to_q15.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Description: Converts the elements of the floating-point vector to Q15 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
ARM GAS /tmp/cce2LIhc.s page 134
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @addtogroup float_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @brief Converts the elements of the floating-point vector to Q15 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @param[in] pSrc points to the floating-point input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @param[out] pDst points to the Q15 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @par Scaling and Overflow Behavior
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** The function uses saturating arithmetic.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** @note
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** In order to apply rounding, the library should be rebuilt with the ROUNDING macr
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** defined in the preprocessor section of project options.
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** */
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** void arm_float_to_q15(
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** const float32_t * pSrc,
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** q15_t * pDst,
ARM GAS /tmp/cce2LIhc.s page 135
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blockSize)
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blkCnt;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32_t maxQ = (float32_t) Q15_MAX;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** f32x4x2_t tmp;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** q15x8_t vecDst;
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32_t in;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize >> 3;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* convert from float to q15 and then store the results in the destination buffer */
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** tmp = vld2q(pSrc);
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** tmp.val[0] = vmulq(tmp.val[0], maxQ);
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** tmp.val[1] = vmulq(tmp.val[1], maxQ);
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** vecDst = vqmovnbq(vecDst, vcvtaq_s32_f32(tmp.val[0]));
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** vecDst = vqmovntq(vecDst, vcvtaq_s32_f32(tmp.val[1]));
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** vst1q(pDst, vecDst);
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /*
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** * Decrement the blockSize loop counter
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** */
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pDst += 8;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pSrc += 8;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize & 7;
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* convert from float to Q15 and store result in destination buffer */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pSrc++ * 32768.0f);
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pSrc++ * 32768.0f), 16);
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Decrement loop counter */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
ARM GAS /tmp/cce2LIhc.s page 136
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #if defined(ARM_MATH_NEON_EXPERIMENTAL)
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** void arm_float_to_q15(
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** const float32_t * pSrc,
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** q15_t * pDst,
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blockSize)
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** const float32_t *pIn = pSrc; /* Src pointer */
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blkCnt; /* loop counter */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32x4_t inV;
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32x4_t zeroV = vdupq_n_f32(0.0f);
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f);
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f);
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32x4_t r;
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32x4_t cmp;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32_t in;
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** int32x4_t cvt;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** int16x4_t outV;
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize >> 2U;
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Compute 4 outputs at a time.
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** ** a second loop below computes the remaining 1 to 3 samples. */
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** inV = vld1q_f32(pIn);
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** cmp = vcgtq_f32(inV,zeroV);
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** r = vbslq_f32(cmp,pHalf,mHalf);
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** inV = vaddq_f32(inV, r);
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pIn += 4;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** cvt = vcvtq_n_s32_f32(inV,15);
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** outV = vqmovn_s32(cvt);
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** vst1_s16(pDst, outV);
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pDst += 4;
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** inV = vld1q_f32(pIn);
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** cvt = vcvtq_n_s32_f32(inV,15);
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** outV = vqmovn_s32(cvt);
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** vst1_s16(pDst, outV);
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pDst += 4;
ARM GAS /tmp/cce2LIhc.s page 137
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** pIn += 4;
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Decrement the loop counter */
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** ** No loop unrolling is used. */
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize & 3;
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = *pIn++;
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (in * 32768.0f);
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Decrement the loop counter */
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** void arm_float_to_q15(
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** const float32_t * pSrc,
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** q15_t * pDst,
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blockSize)
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
3232 .loc 23 220 0
3233 .cfi_startproc
3234 @ args = 0, pretend = 0, frame = 0
3235 @ frame_needed = 0, uses_anonymous_args = 0
3236 @ link register save eliminated.
3237 .LVL395:
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** uint32_t blkCnt; /* Loop counter */
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** const float32_t *pIn = pSrc; /* Source pointer */
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** float32_t in;
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #if defined (ARM_MATH_LOOPUNROLL)
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Loop unrolling: Compute 4 outputs at a time */
ARM GAS /tmp/cce2LIhc.s page 138
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize >> 2U;
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* convert from float to Q15 and store result in destination buffer */
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pIn++ * 32768.0f);
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pIn++ * 32768.0f);
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pIn++ * 32768.0f);
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pIn++ * 32768.0f);
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Decrement loop counter */
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Loop unrolling: Compute remaining outputs */
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize % 0x4U;
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Initialize blkCnt with number of samples */
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt = blockSize;
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** while (blkCnt > 0U)
3238 .loc 23 279 0
3239 0000 5AB1 cbz r2, .L414
3240 .LVL396:
3241 .L416:
3242 .LBB106:
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
ARM GAS /tmp/cce2LIhc.s page 139
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* convert from float to Q15 and store result in destination buffer */
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #ifdef ARM_MATH_ROUNDING
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in = (*pIn++ * 32768.0f);
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** in += in > 0.0f ? 0.5f : -0.5f;
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #else
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* C = A * 32768 */
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Convert from float to q15 and then store the results in the destination buffer */
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
3243 .loc 23 294 0
3244 0002 F0EC017A vldmia.32 r0!, {s15}
3245 .LVL397:
3246 0006 FEEEE87A vcvt.s32.f32 s15, s15, #15
3247 .LBE106:
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
3248 .loc 23 279 0
3249 000a 013A subs r2, r2, #1
3250 .LVL398:
3251 .LBB107:
3252 .loc 23 294 0
3253 000c 17EE903A vmov r3, s15 @ int
3254 .syntax unified
3255 @ 294 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c" 1
3256 0010 03F30F03 ssat r3, #16, r3
3257 @ 0 "" 2
3258 .LVL399:
3259 .thumb
3260 .syntax unified
3261 .LBE107:
3262 0014 21F8023B strh r3, [r1], #2 @ movhi
3263 .LVL400:
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** {
3264 .loc 23 279 0
3265 0018 F3D1 bne .L416
3266 .LVL401:
3267 .L414:
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** /* Decrement loop counter */
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** blkCnt--;
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c ****
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c **** }
3268 .loc 23 302 0
3269 001a 7047 bx lr
3270 .cfi_endproc
3271 .LFE176:
3273 .global __aeabi_f2lz
3274 .section .text.arm_float_to_q31,"ax",%progbits
3275 .align 1
3276 .p2align 2,,3
3277 .global arm_float_to_q31
3278 .syntax unified
ARM GAS /tmp/cce2LIhc.s page 140
3279 .thumb
3280 .thumb_func
3281 .fpu fpv4-sp-d16
3283 arm_float_to_q31:
3284 .LFB177:
3285 .file 24 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Title: arm_float_to_q31.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Description: Converts the elements of the floating-point vector to Q31 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * @defgroup float_to_x Convert 32-bit floating point value
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /**
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @addtogroup float_to_x
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @{
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /**
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @brief Converts the elements of the floating-point vector to Q31 vector.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @param[in] pSrc points to the floating-point input vector
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @param[out] pDst points to the Q31 output vector
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @param[in] blockSize number of samples in each vector
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @return none
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @par Details
ARM GAS /tmp/cce2LIhc.s page 141
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** The equation used for the conversion process is:
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** <pre>
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** </pre>
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @par Scaling and Overflow Behavior
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** The function uses saturating arithmetic.
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated.
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** @note
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** In order to apply rounding, the library should be rebuilt with the ROUNDING macr
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** defined in the preprocessor section of project options.
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** void arm_float_to_q31(
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** const float32_t * pSrc,
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** q31_t * pDst,
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blockSize)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blkCnt;
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32_t maxQ = (float32_t) Q31_MAX;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** f32x4_t vecDst;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32_t in;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize >> 2U;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Compute 4 outputs at a time. */
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** vecDst = vldrwq_f32(pSrc);
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* convert from float to Q31 and then store the results in the destination buffer */
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** vecDst = vmulq(vecDst, maxQ);
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** vstrwq_s32(pDst, vcvtaq_s32_f32(vecDst));
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /*
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Decrement the blockSize loop counter
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** * Advance vector source and destination pointers
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** */
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pSrc += 4;
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pDst += 4;
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt --;
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize & 3;
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* convert from float to Q31 and store result in destination buffer */
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
ARM GAS /tmp/cce2LIhc.s page 142
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pSrc++ * 2147483648.0f);
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pSrc++ * 2147483648.0f));
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Decrement loop counter */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt--;
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #if defined(ARM_MATH_NEON)
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** void arm_float_to_q31(
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** const float32_t * pSrc,
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** q31_t * pDst,
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blockSize)
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** const float32_t *pIn = pSrc; /* Src pointer */
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blkCnt; /* loop counter */
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32x4_t inV;
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32_t in;
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32x4_t zeroV = vdupq_n_f32(0.0f);
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f);
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f);
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32x4_t r;
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32x4_t cmp;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** int32x4_t outV;
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize >> 2U;
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Compute 4 outputs at a time.
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** ** a second loop below computes the remaining 1 to 3 samples. */
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 32768 */
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** inV = vld1q_f32(pIn);
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** cmp = vcgtq_f32(inV,zeroV);
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** r = vbslq_f32(cmp,pHalf,mHalf);
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** inV = vaddq_f32(inV, r);
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pIn += 4;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
ARM GAS /tmp/cce2LIhc.s page 143
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** outV = vcvtq_n_s32_f32(inV,31);
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** vst1q_s32(pDst, outV);
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pDst += 4;
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** inV = vld1q_f32(pIn);
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** outV = vcvtq_n_s32_f32(inV,31);
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** vst1q_s32(pDst, outV);
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pDst += 4;
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** pIn += 4;
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Decrement the loop counter */
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt--;
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** ** No loop unrolling is used. */
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize & 3;
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = *pIn++;
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (in * 2147483648.0f);
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Decrement the loop counter */
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt--;
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** void arm_float_to_q31(
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** const float32_t * pSrc,
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** q31_t * pDst,
ARM GAS /tmp/cce2LIhc.s page 144
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blockSize)
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
3286 .loc 24 224 0
3287 .cfi_startproc
3288 @ args = 0, pretend = 0, frame = 0
3289 @ frame_needed = 0, uses_anonymous_args = 0
3290 .LVL402:
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blkCnt; /* Loop counter */
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** const float32_t *pIn = pSrc; /* Source pointer */
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** float32_t in;
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Loop unrolling: Compute 4 outputs at a time */
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize >> 2U;
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* convert from float to Q31 and store result in destination buffer */
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pIn++ * 2147483648.0f);
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pIn++ * 2147483648.0f);
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pIn++ * 2147483648.0f);
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pIn++ * 2147483648.0f);
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Decrement loop counter */
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt--;
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
ARM GAS /tmp/cce2LIhc.s page 145
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Loop unrolling: Compute remaining outputs */
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize % 0x4U;
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Initialize blkCnt with number of samples */
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt = blockSize;
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** while (blkCnt > 0U)
3291 .loc 24 285 0
3292 0000 22B3 cbz r2, .L430
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** uint32_t blkCnt; /* Loop counter */
3293 .loc 24 224 0
3294 0002 F8B5 push {r3, r4, r5, r6, r7, lr}
3295 .LCFI47:
3296 .cfi_def_cfa_offset 24
3297 .cfi_offset 3, -24
3298 .cfi_offset 4, -20
3299 .cfi_offset 5, -16
3300 .cfi_offset 6, -12
3301 .cfi_offset 7, -8
3302 .cfi_offset 14, -4
3303 0004 2DED028B vpush.64 {d8}
3304 .LCFI48:
3305 .cfi_def_cfa_offset 32
3306 .cfi_offset 80, -32
3307 .cfi_offset 81, -28
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* convert from float to Q31 and store result in destination buffer */
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #ifdef ARM_MATH_ROUNDING
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in = (*pIn++ * 2147483648.0f);
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** in += in > 0.0f ? 0.5f : -0.5f;
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (in));
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #else
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* C = A * 2147483648 */
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Convert from float to Q31 and then store the results in the destination buffer */
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
3308 .loc 24 300 0
3309 0008 9FED118A vldr.32 s16, .L433
3310 000c 0646 mov r6, r0
3311 000e 1446 mov r4, r2
3312 0010 0D1F subs r5, r1, #4
3313 .LBB108:
3314 .LBB109:
3315 .file 25 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /******************************************************************************
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @file arm_math.h
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Public header file for CMSIS DSP Library
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @version V1.7.0
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @date 18. March 2019
ARM GAS /tmp/cce2LIhc.s page 146
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ******************************************************************************/
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /*
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * SPDX-License-Identifier: Apache-2.0
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * not use this file except in compliance with the License.
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * You may obtain a copy of the License at
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * www.apache.org/licenses/LICENSE-2.0
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Unless required by applicable law or agreed to in writing, software
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * See the License for the specific language governing permissions and
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * limitations under the License.
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** \mainpage CMSIS DSP Software Library
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Introduction
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * This user manual describes the CMSIS DSP software library,
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * based devices.
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library is divided into a number of functions each covering a specific category:
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Basic math functions
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Fast math functions
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Complex math functions
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Filtering functions
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Matrix functions
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Transform functions
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Motor control functions
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Statistical functions
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Support functions
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Interpolation functions
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Support Vector Machine functions (SVM)
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Bayes classifier functions
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - Distance functions
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * 32-bit integer and 32-bit floating-point values.
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Using the Library
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> fold
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Here is the list of pre-built libraries :
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on
ARM GAS /tmp/cce2LIhc.s page 147
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precis
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library functions are declared in the public file <code>arm_math.h</code> which is placed
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Simply include this file and link the appropriate library in the application and begin calling
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endi
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Examples
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * --------
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library ships with a number of examples which demonstrate how to use the library functions
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Toolchain Support
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library is now tested on Fast Models building with cmake.
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Core M0, M7, A5 are tested.
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Building the Library
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The library installer contains a project file to rebuild libraries on MDK toolchain in the <co
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - arm_cortexM_math.uvprojx
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecti
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There is also a work in progress cmake build. The README file is giving more details.
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Preprocessor Macros
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Each library project have different preprocessor macros.
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_BIG_ENDIAN:
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default libra
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_MATRIX_CHECK:
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
ARM GAS /tmp/cce2LIhc.s page 148
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_ROUNDING:
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_ROUNDING for rounding on support functions
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_LOOPUNROLL:
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_NEON:
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * It is not enabled by default when Neon is available because performances are
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * dependent on the compiler and target architecture.
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_NEON_EXPERIMENTAL:
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * of some DSP functions. Experimental Neon versions currently do not have better
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * performances than the scalar versions.
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_HELIUM:
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16.
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_MVEF:
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Select Helium versions of the f32 algorithms.
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_MVEI:
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Select Helium versions of the int and fixed point algorithms.
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * - ARM_MATH_FLOAT16:
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Float16 implementations of some algorithms (Requires MVE extension).
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <hr>
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * CMSIS-DSP in ARM::CMSIS Pack
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * -----------------------------
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directorie
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |File/Folder |Content
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |---------------------------------|-----------------------------------------------------------
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\Documentation\\DSP | This documentation
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library fu
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\Include | DSP_Lib include files
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * |\b CMSIS\\DSP\\Source | DSP_Lib source files
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <hr>
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Revision History of CMSIS-DSP
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ------------
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Please refer to \ref ChangeLog_pg.
ARM GAS /tmp/cce2LIhc.s page 149
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupMath Basic Math Functions
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupFastMath Fast Math Functions
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * This set of functions provides a fast approximation to sine, cosine, and square root.
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * As compared to most of the other functions in the CMSIS math library, the fast math functions
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * operate on individual values and not arrays.
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There are separate functions for Q15, Q31, and floating-point data.
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupCmplxMath Complex Math Functions
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * This set of functions operates on complex data vectors.
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The data in the complex arrays is stored in an interleaved fashion
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * (real, imag, real, imag, ...).
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * In the API functions, the number of samples in a complex array refers
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * to the number of complex values; the array contains twice this number of
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * real values.
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupFilters Filtering Functions
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupMatrix Matrix Functions
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * This set of functions provides basic matrix math operations.
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The functions operate on matrix data structures. For example,
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * the type
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * definition for the floating-point matrix structure is shown
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * below:
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * typedef struct
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * {
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * uint16_t numRows; // number of rows of the matrix.
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * uint16_t numCols; // number of columns of the matrix.
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * float32_t *pData; // points to the data of the matrix.
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * } arm_matrix_instance_f32;
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There are similar definitions for Q15 and Q31 data types.
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The structure specifies the size of the matrix and then points to
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * an array of data. The array is of size <code>numRows X numCols</code>
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * and the values are arranged in row order. That is, the
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * matrix element (i, j) is stored at:
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * pData[i*numCols + j]
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * \par Init Functions
ARM GAS /tmp/cce2LIhc.s page 150
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There is an associated initialization function for each type of matrix
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * data structure.
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The initialization function sets the values of the internal structure fields.
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * for floating-point, Q31 and Q15 types, respectively.
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * \par
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Use of the initialization function is optional. However, if initialization function is used
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * then the instance structure cannot be placed into a const data section.
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * To place the instance structure in a const data
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * section, manually initialize the data structure. For example:
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * specifies the number of columns, and <code>pData</code> points to the
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * data array.
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * \par Size Checking
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * By default all of the matrix functions perform size checking on the input and
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * output matrices. For example, the matrix addition function verifies that the
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * two input matrices and the output matrix all have the same number of rows and
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * columns. If the size check fails the functions return:
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ARM_MATH_SIZE_MISMATCH
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Otherwise the functions return
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ARM_MATH_SUCCESS
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There is some overhead associated with this matrix size checking.
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The matrix size checking is enabled via the \#define
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * <pre>
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * ARM_MATH_MATRIX_CHECK
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * </pre>
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * within the library project settings. By default this macro is defined
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * and size checking is enabled. By changing the project settings and
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * undefining this macro size checking is eliminated and the functions
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * run a bit faster. With size checking disabled the functions always
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * return <code>ARM_MATH_SUCCESS</code>.
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupTransforms Transform Functions
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupController Controller Functions
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupStats Statistics Functions
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
ARM GAS /tmp/cce2LIhc.s page 151
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupSupport Support Functions
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupInterpolation Interpolation Functions
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * These functions perform 1- and 2-dimensional interpolation of data.
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Linear interpolation is used for 1-dimensional data and
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * bilinear interpolation is used for 2-dimensional data.
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupExamples Examples
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
304:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
305:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
306:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupSVM SVM Functions
307:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * This set of functions is implementing SVM classification on 2 classes.
308:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The training must be done from scikit-learn. The parameters can be easily
309:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * generated from the scikit-learn object. Some examples are given in
310:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * DSP/Testing/PatternGeneration/SVM.py
311:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
312:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * If more than 2 classes are needed, the functions in this folder
313:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * will have to be used, as building blocks, to do multi-class classification.
314:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
315:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * No multi-class classification is provided in this SVM folder.
316:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
317:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
318:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
319:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
320:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
321:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupBayes Bayesian estimators
322:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
323:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Implement the naive gaussian Bayes estimator.
324:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The training must be done from scikit-learn.
325:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
326:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * The parameters can be easily
327:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * generated from the scikit-learn object. Some examples are given in
328:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * DSP/Testing/PatternGeneration/Bayes.py
329:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
330:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
331:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
332:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @defgroup groupDistance Distance functions
333:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
334:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * Distance functions for use with clustering algorithms.
335:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * There are distance functions for float vectors and boolean vectors.
336:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *
337:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
338:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
339:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
340:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifndef _ARM_MATH_H
341:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define _ARM_MATH_H
342:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
343:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __cplusplus
344:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** extern "C"
345:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
346:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
347:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 152
348:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* Compiler specific diagnostic adjustment */
349:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined ( __CC_ARM )
350:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
351:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
352:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
353:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __GNUC__ )
354:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic push
355:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
356:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic ignored "-Wconversion"
357:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
358:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
359:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __ICCARM__ )
360:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
361:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __TI_ARM__ )
362:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
363:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __CSMC__ )
364:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
365:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __TASKING__ )
366:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
367:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( _MSC_VER )
368:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
369:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
370:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #error Unknown compiler
371:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
372:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
373:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
374:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* Included for instrinsics definitions */
375:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined (_MSC_VER )
376:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <stdint.h>
377:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __STATIC_FORCEINLINE static __forceinline
378:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __STATIC_INLINE static __inline
379:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __ALIGNED(x) __declspec(align(x))
380:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
381:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined (__GNUC_PYTHON__)
382:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <stdint.h>
383:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
384:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __STATIC_FORCEINLINE static __attribute__((inline))
385:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __STATIC_INLINE static __attribute__((inline))
386:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic ignored "-Wunused-function"
387:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #pragma GCC diagnostic ignored "-Wattributes"
388:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
389:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
390:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include "cmsis_compiler.h"
391:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
392:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
393:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
394:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
395:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <string.h>
396:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <math.h>
397:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <float.h>
398:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <limits.h>
399:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
400:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
401:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F64_MAX ((float64_t)DBL_MAX)
402:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F32_MAX ((float32_t)FLT_MAX)
403:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
404:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
ARM GAS /tmp/cce2LIhc.s page 153
405:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F16_MAX ((float16_t)FLT_MAX)
406:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
407:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
408:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F64_MIN (-DBL_MAX)
409:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F32_MIN (-FLT_MAX)
410:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
411:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
412:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F16_MIN (-(float16_t)FLT_MAX)
413:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
414:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
415:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F64_ABSMAX ((float64_t)DBL_MAX)
416:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F32_ABSMAX ((float32_t)FLT_MAX)
417:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
418:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
419:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F16_ABSMAX ((float16_t)FLT_MAX)
420:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
421:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
422:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F64_ABSMIN ((float64_t)0.0)
423:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F32_ABSMIN ((float32_t)0.0)
424:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
425:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
426:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define F16_ABSMIN ((float16_t)0.0)
427:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
428:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
429:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q31_MAX ((q31_t)(0x7FFFFFFFL))
430:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q15_MAX ((q15_t)(0x7FFF))
431:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q7_MAX ((q7_t)(0x7F))
432:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q31_MIN ((q31_t)(0x80000000L))
433:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q15_MIN ((q15_t)(0x8000))
434:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q7_MIN ((q7_t)(0x80))
435:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
436:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL))
437:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q15_ABSMAX ((q15_t)(0x7FFF))
438:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q7_ABSMAX ((q7_t)(0x7F))
439:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q31_ABSMIN ((q31_t)0)
440:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q15_ABSMIN ((q15_t)0)
441:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define Q7_ABSMIN ((q7_t)0)
442:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
443:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* evaluate ARM DSP feature */
444:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
445:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define ARM_MATH_DSP 1
446:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
447:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
448:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_NEON)
449:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <arm_neon.h>
450:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
451:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
452:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined (ARM_MATH_HELIUM)
453:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define ARM_MATH_MVEF
454:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define ARM_MATH_FLOAT16
455:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
456:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
457:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined (ARM_MATH_MVEF)
458:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define ARM_MATH_MVEI
459:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define ARM_MATH_FLOAT16
460:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
461:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 154
462:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)
463:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #include <arm_mve.h>
464:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
465:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
466:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
467:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
468:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Macros required for reciprocal calculation in Normalized LMS
469:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
470:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
471:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define DELTA_Q31 ((q31_t)(0x100))
472:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define DELTA_Q15 ((q15_t)0x5)
473:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define INDEX_MASK 0x0000003F
474:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifndef PI
475:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define PI 3.14159265358979f
476:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
477:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
478:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
479:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Macros required for SINE and COSINE Fast math approximations
480:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
481:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
482:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define FAST_MATH_TABLE_SIZE 512
483:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define FAST_MATH_Q31_SHIFT (32 - 10)
484:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define FAST_MATH_Q15_SHIFT (16 - 10)
485:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define CONTROLLER_Q31_SHIFT (32 - 9)
486:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define TABLE_SPACING_Q31 0x400000
487:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define TABLE_SPACING_Q15 0x80
488:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
489:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
490:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Macros required for SINE and COSINE Controller functions
491:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
492:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* 1.31(q31) Fixed value of 2/360 */
493:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
494:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define INPUT_SPACING 0xB60B61
495:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
496:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
497:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Macros for complex numbers
498:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
499:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
500:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* Dimension C vector space */
501:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define CMPLX_DIM 2
502:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
503:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
504:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Error status returned by some functions in the library.
505:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
506:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
507:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef enum
508:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
509:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_SUCCESS = 0, /**< No error */
510:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
511:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
512:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation
513:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
514:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
515:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
516:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** } arm_status;
517:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
518:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
ARM GAS /tmp/cce2LIhc.s page 155
519:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional data type in 1.7 format.
520:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
521:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8_t q7_t;
522:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
523:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
524:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional data type in 1.15 format.
525:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
526:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16_t q15_t;
527:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
528:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
529:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional data type in 1.31 format.
530:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
531:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32_t q31_t;
532:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
533:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
534:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 64-bit fractional data type in 1.63 format.
535:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
536:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int64_t q63_t;
537:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
538:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
539:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point type definition.
540:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
541:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float float32_t;
542:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
543:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
544:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 64-bit floating-point type definition.
545:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
546:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef double float64_t;
547:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
548:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
549:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief vector types
550:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
551:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI)
552:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
553:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 64-bit fractional 128-bit vector data type in 1.63 format
554:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
555:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int64x2_t q63x2_t;
556:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
557:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
558:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 128-bit vector data type in 1.31 format.
559:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
560:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4_t q31x4_t;
561:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
562:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
563:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format.
564:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
565:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(2) int16x8_t q15x8_t;
566:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
567:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
568:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format.
569:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
570:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(1) int8x16_t q7x16_t;
571:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
572:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
573:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
574:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
575:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4x2_t q31x4x2_t;
ARM GAS /tmp/cce2LIhc.s page 156
576:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
577:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
578:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
579:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
580:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4x4_t q31x4x4_t;
581:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
582:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
583:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
584:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
585:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x8x2_t q15x8x2_t;
586:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
587:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
588:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
589:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
590:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x8x4_t q15x8x4_t;
591:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
592:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
593:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
594:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
595:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x16x2_t q7x16x2_t;
596:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
597:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
598:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
599:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
600:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x16x4_t q7x16x4_t;
601:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
602:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
603:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional data type in 9.23 format.
604:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
605:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32_t q23_t;
606:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
607:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
608:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 128-bit vector data type in 9.23 format.
609:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
610:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4_t q23x4_t;
611:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
612:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
613:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 64-bit status 128-bit vector data type.
614:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
615:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int64x2_t status64x2_t;
616:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
617:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
618:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit status 128-bit vector data type.
619:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
620:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4_t status32x4_t;
621:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
622:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
623:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit status 128-bit vector data type.
624:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
625:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x8_t status16x8_t;
626:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
627:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
628:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit status 128-bit vector data type.
629:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
630:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x16_t status8x16_t;
631:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
632:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 157
633:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
634:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
635:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/
636:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
637:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 128-bit vector type
638:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
639:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x4_t f32x4_t;
640:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
641:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
642:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
643:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 128-bit vector data type
644:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
645:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(2) float16x8_t f16x8_t;
646:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
647:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
648:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
649:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 128-bit vector pair data type
650:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
651:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x4x2_t f32x4x2_t;
652:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
653:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
654:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 128-bit vector quadruplet data type
655:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
656:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x4x4_t f32x4x4_t;
657:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
658:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
659:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
660:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 128-bit vector pair data type
661:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
662:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x8x2_t f16x8x2_t;
663:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
664:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
665:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 128-bit vector quadruplet data type
666:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
667:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x8x4_t f16x8x4_t;
668:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
669:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
670:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
671:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit ubiquitous 128-bit vector data type
672:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
673:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef union _any32x4_t
674:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
675:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** float32x4_t f;
676:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** int32x4_t i;
677:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** } any32x4_t;
678:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
679:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
680:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
681:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit ubiquitous 128-bit vector data type
682:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
683:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef union _any16x8_t
684:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
685:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** float16x8_t f;
686:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** int16x8_t i;
687:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** } any16x8_t;
688:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
689:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 158
690:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
691:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
692:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_NEON)
693:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
694:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 64-bit vector data type in 1.31 format.
695:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
696:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x2_t q31x2_t;
697:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
698:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
699:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 64-bit vector data type in 1.15 format.
700:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
701:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(2) int16x4_t q15x4_t;
702:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
703:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
704:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 64-bit vector data type in 1.7 format.
705:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
706:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(1) int8x8_t q7x8_t;
707:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
708:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
709:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit float 64-bit vector data type.
710:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
711:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x2_t f32x2_t;
712:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
713:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
714:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
715:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit float 64-bit vector data type.
716:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
717:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef __ALIGNED(2) float16x4_t f16x4_t;
718:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
719:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
720:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
721:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 128-bit vector triplet data type
722:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
723:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x4x3_t f32x4x3_t;
724:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
725:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
726:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
727:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 128-bit vector triplet data type
728:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
729:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x8x3_t f16x8x3_t;
730:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
731:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
732:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
733:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
734:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
735:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4x3_t q31x4x3_t;
736:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
737:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
738:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
739:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
740:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x8x3_t q15x8x3_t;
741:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
742:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
743:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
744:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
745:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x16x3_t q7x16x3_t;
746:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 159
747:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
748:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 64-bit vector pair data type
749:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
750:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x2x2_t f32x2x2_t;
751:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
752:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
753:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 64-bit vector triplet data type
754:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
755:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x2x3_t f32x2x3_t;
756:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
757:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
758:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit floating-point 64-bit vector quadruplet data type
759:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
760:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float32x2x4_t f32x2x4_t;
761:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
762:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
763:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
764:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 64-bit vector pair data type
765:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
766:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x4x2_t f16x4x2_t;
767:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
768:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
769:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 64-bit vector triplet data type
770:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
771:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x4x3_t f16x4x3_t;
772:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
773:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
774:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit floating-point 64-bit vector quadruplet data type
775:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
776:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef float16x4x4_t f16x4x4_t;
777:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
778:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
779:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
780:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
781:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
782:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x2x2_t q31x2x2_t;
783:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
784:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
785:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
786:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
787:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x2x3_t q31x2x3_t;
788:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
789:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
790:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
791:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
792:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4x3_t q31x2x4_t;
793:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
794:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
795:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
796:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
797:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x4x2_t q15x4x2_t;
798:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
799:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
800:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
801:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
802:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x4x2_t q15x4x3_t;
803:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 160
804:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
805:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
806:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
807:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x4x3_t q15x4x4_t;
808:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
809:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
810:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
811:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
812:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x8x2_t q7x8x2_t;
813:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
814:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
815:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
816:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
817:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x8x3_t q7x8x3_t;
818:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
819:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
820:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
821:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
822:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x8x4_t q7x8x4_t;
823:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
824:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
825:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit ubiquitous 64-bit vector data type
826:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
827:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef union _any32x2_t
828:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
829:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** float32x2_t f;
830:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** int32x2_t i;
831:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** } any32x2_t;
832:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
833:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined(ARM_MATH_FLOAT16)
834:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
835:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit ubiquitous 64-bit vector data type
836:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
837:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef union _any16x4_t
838:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
839:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** float16x4_t f;
840:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** int16x4_t i;
841:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** } any16x4_t;
842:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
843:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
844:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
845:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 32-bit status 64-bit vector data type.
846:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
847:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int32x4_t status32x2_t;
848:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
849:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
850:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 16-bit status 64-bit vector data type.
851:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
852:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int16x8_t status16x4_t;
853:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
854:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
855:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief 8-bit status 64-bit vector data type.
856:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
857:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** typedef int8x16_t status8x8_t;
858:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
859:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
860:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 161
861:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
862:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
863:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
864:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief definition to read/write two 16 bit values.
865:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @deprecated
866:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
867:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined ( __CC_ARM )
868:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t __packed
869:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
870:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t
871:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __GNUC__ )
872:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t
873:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __ICCARM__ )
874:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t __packed
875:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __TI_ARM__ )
876:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t
877:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __CSMC__ )
878:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t
879:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined ( __TASKING__ )
880:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE __un(aligned) int32_t
881:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #elif defined(_MSC_VER )
882:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_TYPE int32_t
883:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
884:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #error Unknown compiler
885:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
886:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
887:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
888:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
889:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
890:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __SIMD64(addr) (*( int64_t **) & (addr))
891:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
892:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define STEP(x) (x) <= 0 ? 0 : 1
893:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define SQ(x) ((x) * (x))
894:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
895:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /* SIMD replacement */
896:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
897:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
898:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
899:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Read 2 Q15 from Q15 pointer.
900:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ15 points to input value
901:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return Q31 value
902:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
903:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t read_q15x2 (
904:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q15_t * pQ15)
905:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
906:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val;
907:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
908:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
909:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (&val, pQ15, 4);
910:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
911:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
912:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
913:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
914:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (val);
915:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
916:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
917:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
ARM GAS /tmp/cce2LIhc.s page 162
918:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
919:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ15 points to input value
920:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return Q31 value
921:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
922:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t read_q15x2_ia (
923:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q15_t ** pQ15)
924:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
925:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val;
926:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
927:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
928:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (&val, *pQ15, 4);
929:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
930:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
931:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
932:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
933:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ15 += 2;
934:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (val);
935:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
936:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
937:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
938:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
939:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ15 points to input value
940:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return Q31 value
941:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
942:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t read_q15x2_da (
943:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q15_t ** pQ15)
944:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
945:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val;
946:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
947:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
948:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (&val, *pQ15, 4);
949:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
950:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF);
951:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
952:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
953:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ15 -= 2;
954:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (val);
955:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
956:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
957:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
958:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
959:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ15 points to input value
960:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] value Q31 value
961:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return none
962:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
963:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE void write_q15x2_ia (
964:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q15_t ** pQ15,
965:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t value)
966:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
967:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val = value;
968:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
969:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (*pQ15, &val, 4);
970:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
971:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ15)[0] = (val & 0x0FFFF);
972:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ15)[1] = (val >> 16) & 0x0FFFF;
973:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
974:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
ARM GAS /tmp/cce2LIhc.s page 163
975:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ15 += 2;
976:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
977:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
978:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
979:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Write 2 Q15 to Q15 pointer.
980:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ15 points to input value
981:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] value Q31 value
982:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return none
983:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
984:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE void write_q15x2 (
985:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q15_t * pQ15,
986:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t value)
987:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
988:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val = value;
989:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
990:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
991:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (pQ15, &val, 4);
992:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
993:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** pQ15[0] = val & 0x0FFFF;
994:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** pQ15[1] = val >> 16;
995:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
996:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
997:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
998:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
999:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1000:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
1001:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ7 points to input value
1002:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return Q31 value
1003:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1004:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t read_q7x4_ia (
1005:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q7_t ** pQ7)
1006:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1007:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val;
1008:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1009:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1010:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
1011:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (&val, *pQ7, 4);
1012:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
1013:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) |
1014:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1015:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1016:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ7 += 4;
1017:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1018:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (val);
1019:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1020:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1021:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1022:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
1023:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ7 points to input value
1024:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return Q31 value
1025:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1026:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t read_q7x4_da (
1027:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q7_t ** pQ7)
1028:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1029:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val;
1030:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
1031:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (&val, *pQ7, 4);
ARM GAS /tmp/cce2LIhc.s page 164
1032:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
1033:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) <<
1034:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1035:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ7 -= 4;
1036:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1037:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (val);
1038:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1039:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1040:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1041:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
1042:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] pQ7 points to input value
1043:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @param[in] value Q31 value
1044:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** @return none
1045:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1046:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE void write_q7x4_ia (
1047:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q7_t ** pQ7,
1048:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t value)
1049:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1050:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q31_t val = value;
1051:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifdef __ARM_FEATURE_UNALIGNED
1052:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** memcpy (*pQ7, &val, 4);
1053:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
1054:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ7)[0] = val & 0x0FF;
1055:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ7)[1] = (val >> 8) & 0x0FF;
1056:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ7)[2] = (val >> 16) & 0x0FF;
1057:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (*pQ7)[3] = (val >> 24) & 0x0FF;
1058:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1059:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1060:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** *pQ7 += 4;
1061:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1062:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1063:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /*
1064:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1065:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** Normally those kind of definitions are in a compiler file
1066:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** in Core or Core_A.
1067:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1068:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** But for MSVC compiler it is a bit special. The goal is very specific
1069:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** to CMSIS-DSP and only to allow the use of this library from other
1070:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** systems like Python or Matlab.
1071:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1072:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
1073:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** compiler file in Core or Core_A would not make sense.
1074:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1075:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1076:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
1077:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
1078:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1079:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** if (data == 0U) { return 32U; }
1080:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1081:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** uint32_t count = 0U;
1082:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** uint32_t mask = 0x80000000U;
1083:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1084:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** while ((data & mask) == 0U)
1085:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1086:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** count += 1U;
1087:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** mask = mask >> 1U;
1088:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
ARM GAS /tmp/cce2LIhc.s page 165
1089:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return count;
1090:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1091:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1092:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
1093:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1094:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** if ((sat >= 1U) && (sat <= 32U))
1095:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1096:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
1097:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** const int32_t min = -1 - max ;
1098:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** if (val > max)
1099:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return max;
1101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** else if (val < min)
1103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return min;
1105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return val;
1108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
1111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** if (sat <= 31U)
1113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** const uint32_t max = ((1U << sat) - 1U);
1115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** if (val > (int32_t)max)
1116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return max;
1118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** else if (val < 0)
1120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return 0U;
1122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return (uint32_t)val;
1125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** }
1126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifndef ARM_MATH_DSP
1129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief definition to pack two 16 bit values.
1131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
1133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
1134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
1135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
1136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief definition to pack four 8 bit values.
1140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #ifndef ARM_MATH_BIG_ENDIAN
1142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
1143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
1144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
1145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
ARM GAS /tmp/cce2LIhc.s page 166
1146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #else
1147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
1148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
1149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
1150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
1151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** #endif
1152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h ****
1154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** /**
1155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** * @brief Clips Q63 to Q31 values.
1156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** */
1157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
1158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** q63_t x)
1159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** {
1160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
1161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Include/arm_math.h **** ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
3316 .loc 25 1161 0
3317 0012 6FF00047 mvn r7, #-2147483648
3318 .LVL403:
3319 .L423:
3320 .LBE109:
3321 .LBE108:
3322 .loc 24 300 0
3323 0016 F6EC017A vldmia.32 r6!, {s15}
3324 .LVL404:
3325 001a 67EE887A vmul.f32 s15, s15, s16
3326 001e 17EE900A vmov r0, s15
3327 0022 FFF7FEFF bl __aeabi_f2lz
3328 .LVL405:
3329 .LBB111:
3330 .LBB110:
3331 .loc 25 1161 0
3332 0026 B1EBE07F cmp r1, r0, asr #31
3333 002a 87EAE173 eor r3, r7, r1, asr #31
3334 002e 06D0 beq .L424
3335 .LBE110:
3336 .LBE111:
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
3337 .loc 24 285 0
3338 0030 013C subs r4, r4, #1
3339 .LVL406:
3340 .loc 24 300 0
3341 0032 45F8043F str r3, [r5, #4]!
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
3342 .loc 24 285 0
3343 0036 EED1 bne .L423
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
304:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** /* Decrement loop counter */
305:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** blkCnt--;
306:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
307:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
308:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** }
3344 .loc 24 308 0
3345 0038 BDEC028B vldm sp!, {d8}
3346 .LCFI49:
ARM GAS /tmp/cce2LIhc.s page 167
3347 .cfi_remember_state
3348 .cfi_restore 80
3349 .cfi_restore 81
3350 .cfi_def_cfa_offset 24
3351 003c F8BD pop {r3, r4, r5, r6, r7, pc}
3352 .LVL407:
3353 .L424:
3354 .LCFI50:
3355 .cfi_restore_state
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
3356 .loc 24 285 0
3357 003e 013C subs r4, r4, #1
3358 .LVL408:
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c ****
3359 .loc 24 300 0
3360 0040 45F8040F str r0, [r5, #4]!
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c **** {
3361 .loc 24 285 0
3362 0044 E7D1 bne .L423
3363 .loc 24 308 0
3364 0046 BDEC028B vldm sp!, {d8}
3365 .LCFI51:
3366 .cfi_restore 80
3367 .cfi_restore 81
3368 .cfi_def_cfa_offset 24
3369 004a F8BD pop {r3, r4, r5, r6, r7, pc}
3370 .LVL409:
3371 .L430:
3372 .LCFI52:
3373 .cfi_def_cfa_offset 0
3374 .cfi_restore 3
3375 .cfi_restore 4
3376 .cfi_restore 5
3377 .cfi_restore 6
3378 .cfi_restore 7
3379 .cfi_restore 14
3380 004c 7047 bx lr
3381 .L434:
3382 004e 00BF .align 2
3383 .L433:
3384 0050 0000004F .word 1325400064
3385 .cfi_endproc
3386 .LFE177:
3388 .section .text.arm_float_to_q7,"ax",%progbits
3389 .align 1
3390 .p2align 2,,3
3391 .global arm_float_to_q7
3392 .syntax unified
3393 .thumb
3394 .thumb_func
3395 .fpu fpv4-sp-d16
3397 arm_float_to_q7:
3398 .LFB178:
3399 .file 26 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Title: arm_float_to_q7.c
ARM GAS /tmp/cce2LIhc.s page 168
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Description: Converts the elements of the floating-point vector to Q7 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** @addtogroup float_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * @brief Converts the elements of the floating-point vector to Q7 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * @param[in] *pSrc points to the floating-point input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * @param[out] *pDst points to the Q7 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * @param[in] blockSize length of the input vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * @return none.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *\par Description:
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * \par
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * The equation used for the conversion process is:
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * <pre>
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * </pre>
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * \par Scaling and Overflow Behavior:
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * \par
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * The function uses saturating arithmetic.
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * \note
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * defined in the preprocessor section of project options.
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
ARM GAS /tmp/cce2LIhc.s page 169
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** void arm_float_to_q7(
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** const float32_t * pSrc,
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** q7_t * pDst,
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blockSize)
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blkCnt; /* loop counters */
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32_t maxQ = powf(2.0, 7);
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** f32x4x4_t tmp;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** q15x8_t evVec, oddVec;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** q7x16_t vecDst;
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32_t const *pSrcVec;
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32_t in;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pSrcVec = (float32_t const *) pSrc;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize >> 4;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U) {
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** tmp = vld4q(pSrcVec);
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pSrcVec += 16;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * C = A * 128.0
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * convert from float to q7 and then store the results in the destination buffer
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** tmp.val[0] = vmulq(tmp.val[0], maxQ);
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** tmp.val[1] = vmulq(tmp.val[1], maxQ);
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** tmp.val[2] = vmulq(tmp.val[2], maxQ);
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** tmp.val[3] = vmulq(tmp.val[3], maxQ);
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * convert and pack evens
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** evVec = vqmovnbq(evVec, vcvtaq_s32_f32(tmp.val[0]));
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** evVec = vqmovntq(evVec, vcvtaq_s32_f32(tmp.val[2]));
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * convert and pack odds
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** oddVec = vqmovnbq(oddVec, vcvtaq_s32_f32(tmp.val[1]));
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** oddVec = vqmovntq(oddVec, vcvtaq_s32_f32(tmp.val[3]));
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * merge
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** vecDst = vqmovnbq(vecDst, evVec);
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** vecDst = vqmovntq(vecDst, oddVec);
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** vst1q(pDst, vecDst);
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pDst += 16;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /*
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** * Decrement the blockSize loop counter
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** */
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize & 0xF;
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U)
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
ARM GAS /tmp/cce2LIhc.s page 170
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and store result in destination buffer */
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pSrcVec++ * 128);
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) __SSAT((q31_t) (*pSrcVec++ * 128.0f), 8);
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Decrement loop counter */
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #if defined(ARM_MATH_NEON)
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** void arm_float_to_q7(
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** const float32_t * pSrc,
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** q7_t * pDst,
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blockSize)
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** const float32_t *pIn = pSrc; /* Src pointer */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blkCnt; /* loop counter */
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32x4_t inV;
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32_t in;
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32x4_t zeroV = vdupq_n_f32(0.0f);
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f);
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f);
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32x4_t r;
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32x4_t cmp;
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** int16x4_t cvt1,cvt2;
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** int8x8_t outV;
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize >> 3U;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Compute 8 outputs at a time.
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** ** a second loop below computes the remaining 1 to 7 samples. */
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U)
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and then store the results in the destination buffer */
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vld1q_f32(pIn);
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cmp = vcgtq_f32(inV,zeroV);
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** r = vbslq_f32(cmp,pHalf,mHalf);
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vaddq_f32(inV, r);
ARM GAS /tmp/cce2LIhc.s page 171
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pIn += 4;
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vld1q_f32(pIn);
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cmp = vcgtq_f32(inV,zeroV);
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** r = vbslq_f32(cmp,pHalf,mHalf);
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vaddq_f32(inV, r);
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pIn += 4;
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** outV = vqmovn_s16(vcombine_s16(cvt1,cvt2));
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** vst1_s8(pDst, outV);
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pDst += 8;
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and then store the results in the destination buffer */
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vld1q_f32(pIn);
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pIn += 4;
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** inV = vld1q_f32(pIn);
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pIn += 4;
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** outV = vqmovn_s16(vcombine_s16(cvt1,cvt2));
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** vst1_s8(pDst, outV);
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** pDst += 8;
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Decrement the loop counter */
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** ** No loop unrolling is used. */
213:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize & 7;
214:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
215:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U)
216:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
217:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
218:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
219:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
220:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and then store the results in the destination buffer */
221:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = *pIn++;
222:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (in * 128);
223:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
224:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
225:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
226:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
227:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
228:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
229:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and then store the results in the destination buffer */
230:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
231:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
ARM GAS /tmp/cce2LIhc.s page 172
232:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
233:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
234:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Decrement the loop counter */
235:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
236:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
237:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
238:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
239:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
240:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** void arm_float_to_q7(
241:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** const float32_t * pSrc,
242:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** q7_t * pDst,
243:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blockSize)
244:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
3400 .loc 26 244 0
3401 .cfi_startproc
3402 @ args = 0, pretend = 0, frame = 0
3403 @ frame_needed = 0, uses_anonymous_args = 0
3404 @ link register save eliminated.
3405 .LVL410:
245:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** uint32_t blkCnt; /* Loop counter */
246:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** const float32_t *pIn = pSrc; /* Source pointer */
247:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
248:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
249:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** float32_t in;
250:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
251:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
252:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #if defined (ARM_MATH_LOOPUNROLL)
253:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
254:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Loop unrolling: Compute 4 outputs at a time */
255:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize >> 2U;
256:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
257:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U)
258:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
259:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
260:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
261:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and store result in destination buffer */
262:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
263:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
264:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pIn++ * 128);
265:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
266:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
267:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
268:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pIn++ * 128);
269:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
270:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
271:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
272:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pIn++ * 128);
273:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
274:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
275:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
276:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pIn++ * 128);
277:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
278:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
279:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
280:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
281:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
282:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
ARM GAS /tmp/cce2LIhc.s page 173
283:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
284:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
285:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
286:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
287:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
288:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
289:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Decrement loop counter */
290:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
291:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
292:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
293:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Loop unrolling: Compute remaining outputs */
294:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize % 0x4U;
295:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
296:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
297:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
298:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Initialize blkCnt with number of samples */
299:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt = blockSize;
300:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
301:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
302:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** while (blkCnt > 0U)
3406 .loc 26 303 0
3407 0000 62B1 cbz r2, .L435
3408 0002 0A44 add r2, r2, r1
3409 .LVL411:
3410 .L437:
3411 .LBB112:
304:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
305:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* C = A * 128 */
306:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
307:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Convert from float to q7 and store result in destination buffer */
308:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #ifdef ARM_MATH_ROUNDING
309:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
310:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in = (*pIn++ * 128);
311:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** in += in > 0.0f ? 0.5f : -0.5f;
312:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
313:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
314:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #else
315:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
316:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
3412 .loc 26 316 0
3413 0004 F0EC017A vldmia.32 r0!, {s15}
3414 .LVL412:
3415 0008 FEEEEC7A vcvt.s32.f32 s15, s15, #7
3416 000c 17EE903A vmov r3, s15 @ int
3417 .syntax unified
3418 @ 316 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c" 1
3419 0010 03F30703 ssat r3, #8, r3
3420 @ 0 "" 2
3421 .LVL413:
3422 .thumb
3423 .syntax unified
3424 .LBE112:
3425 0014 01F8013B strb r3, [r1], #1
3426 .LVL414:
303:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** {
3427 .loc 26 303 0
ARM GAS /tmp/cce2LIhc.s page 174
3428 0018 9142 cmp r1, r2
3429 001a F3D1 bne .L437
3430 .LVL415:
3431 .L435:
317:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
318:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** #endif /* #ifdef ARM_MATH_ROUNDING */
319:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
320:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** /* Decrement loop counter */
321:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** blkCnt--;
322:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
323:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c ****
324:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c **** }
3432 .loc 26 324 0
3433 001c 7047 bx lr
3434 .cfi_endproc
3435 .LFE178:
3437 001e 00BF .section .text.arm_q15_to_float,"ax",%progbits
3438 .align 1
3439 .p2align 2,,3
3440 .global arm_q15_to_float
3441 .syntax unified
3442 .thumb
3443 .thumb_func
3444 .fpu fpv4-sp-d16
3446 arm_q15_to_float:
3447 .LFB179:
3448 .file 27 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Title: arm_q15_to_float.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Description: Converts the elements of the Q15 vector to floating-point vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
ARM GAS /tmp/cce2LIhc.s page 175
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * @defgroup q15_to_x Convert 16-bit Integer value
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /**
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @addtogroup q15_to_x
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @{
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /**
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @brief Converts the elements of the Q15 vector to floating-point vector.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @param[in] pSrc points to the Q15 input vector
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @param[out] pDst points to the floating-point output vector
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @param[in] blockSize number of samples in each vector
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @return none
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** @par Details
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** The equation used for the conversion process is:
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** <pre>
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** </pre>
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** void arm_q15_to_float(
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** const q15_t * pSrc,
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** float32_t * pDst,
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blockSize)
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blkCnt;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** q15x8_t vecDst;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** q15_t const *pSrcVec;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pSrcVec = (q15_t const *) pSrc;
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize >> 2;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* convert from q15 to float and then store the results in the destination buffer */
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** vecDst = vldrhq_s32(pSrcVec);
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pSrcVec += 4;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 15));
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pDst += 4;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /*
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** * Decrement the blockSize loop counter
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** */
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize & 3;
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
ARM GAS /tmp/cce2LIhc.s page 176
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Convert from q15 to float and store result in destination buffer */
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) *pSrcVec++ / 32768.0f);
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Decrement loop counter */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #else
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #if defined(ARM_MATH_NEON_EXPERIMENTAL)
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** void arm_q15_to_float(
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** const q15_t * pSrc,
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** float32_t * pDst,
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blockSize)
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** const q15_t *pIn = pSrc; /* Src pointer */
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blkCnt; /* loop counter */
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** int16x8_t inV;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** int32x4_t inV0, inV1;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** float32x4_t outV;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize >> 3U;
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Compute 8 outputs at a time.
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** ** a second loop below computes the remaining 1 to 7 samples. */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* convert from q15 to float and then store the results in the destination buffer */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** inV = vld1q_s16(pIn);
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pIn += 8;
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** inV0 = vmovl_s16(vget_low_s16(inV));
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** inV1 = vmovl_s16(vget_high_s16(inV));
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** outV = vcvtq_n_f32_s32(inV0,15);
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** vst1q_f32(pDst, outV);
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pDst += 4;
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** outV = vcvtq_n_f32_s32(inV1,15);
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** vst1q_f32(pDst, outV);
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** pDst += 4;
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Decrement the loop counter */
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** ** No loop unrolling is used. */
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize & 7;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
ARM GAS /tmp/cce2LIhc.s page 177
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* convert from q15 to float and then store the results in the destination buffer */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 32768.0f);
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Decrement the loop counter */
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #else
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** void arm_q15_to_float(
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** const q15_t * pSrc,
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** float32_t * pDst,
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blockSize)
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
3449 .loc 27 157 0
3450 .cfi_startproc
3451 @ args = 0, pretend = 0, frame = 0
3452 @ frame_needed = 0, uses_anonymous_args = 0
3453 @ link register save eliminated.
3454 .LVL416:
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** uint32_t blkCnt; /* Loop counter */
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** const q15_t *pIn = pSrc; /* Source pointer */
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #if defined (ARM_MATH_LOOPUNROLL)
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Loop unrolling: Compute 4 outputs at a time */
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize >> 2U;
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Convert from q15 to float and store result in destination buffer */
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 32768.0f);
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 32768.0f);
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 32768.0f);
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 32768.0f);
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Decrement loop counter */
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Loop unrolling: Compute remaining outputs */
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize % 0x4U;
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #else
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Initialize blkCnt with number of samples */
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt = blockSize;
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** while (blkCnt > 0U)
3455 .loc 27 190 0
3456 0000 6AB1 cbz r2, .L442
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* C = (float32_t) A / 32768 */
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
ARM GAS /tmp/cce2LIhc.s page 178
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Convert from q15 to float and store result in destination buffer */
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 32768.0f);
3457 .loc 27 195 0
3458 0002 9FED077A vldr.32 s14, .L449
3459 .LVL417:
3460 .L444:
3461 0006 30F9023B ldrsh r3, [r0], #2
3462 .LVL418:
3463 000a 07EE903A vmov s15, r3 @ int
3464 .LVL419:
3465 000e F8EEE77A vcvt.f32.s32 s15, s15
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
3466 .loc 27 190 0
3467 0012 013A subs r2, r2, #1
3468 .LVL420:
3469 .loc 27 195 0
3470 0014 67EE877A vmul.f32 s15, s15, s14
3471 0018 E1EC017A vstmia.32 r1!, {s15}
3472 .LVL421:
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** {
3473 .loc 27 190 0
3474 001c F3D1 bne .L444
3475 .L442:
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** /* Decrement loop counter */
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** blkCnt--;
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c ****
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c **** }
3476 .loc 27 201 0
3477 001e 7047 bx lr
3478 .L450:
3479 .align 2
3480 .L449:
3481 0020 00000038 .word 939524096
3482 .cfi_endproc
3483 .LFE179:
3485 .section .text.arm_q15_to_q31,"ax",%progbits
3486 .align 1
3487 .p2align 2,,3
3488 .global arm_q15_to_q31
3489 .syntax unified
3490 .thumb
3491 .thumb_func
3492 .fpu fpv4-sp-d16
3494 arm_q15_to_q31:
3495 .LFB180:
3496 .file 28 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Title: arm_q15_to_q31.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Description: Converts the elements of the Q15 vector to Q31 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Target Processor: Cortex-M cores
ARM GAS /tmp/cce2LIhc.s page 179
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @addtogroup q15_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @brief Converts the elements of the Q15 vector to Q31 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @param[in] pSrc points to the Q15 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @param[out] pDst points to the Q31 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #if defined(ARM_MATH_MVEI)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** void arm_q15_to_q31(
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** const q15_t * pSrc,
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** q31_t * pDst,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** uint32_t blockSize)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** uint32_t blkCnt;
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** q31x4_t vecDst;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt = blockSize>> 2;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** while (blkCnt > 0U)
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
ARM GAS /tmp/cce2LIhc.s page 180
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* C = (q31_t)A << 16 */
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* convert from q15 to q31 and then store the results in the destination buffer */
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* load q15 + 32-bit widening */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** vecDst = vldrhq_s32((q15_t const *) pSrc);
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** vecDst = vshlq_n(vecDst, 16);
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** vstrwq_s32(pDst, vecDst);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /*
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Decrement the blockSize loop counter
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** * Advance vector source and destination pointers
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** */
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** pDst += 4;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** pSrc += 4;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt --;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt = blockSize & 3;
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** while (blkCnt > 0U)
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* C = (q31_t) A << 16 */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Convert from q15 to q31 and store result in destination buffer */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = (q31_t) *pSrc++ << 16;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Decrement loop counter */
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt--;
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #else
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** void arm_q15_to_q31(
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** const q15_t * pSrc,
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** q31_t * pDst,
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** uint32_t blockSize)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
3497 .loc 28 101 0
3498 .cfi_startproc
3499 @ args = 0, pretend = 0, frame = 0
3500 @ frame_needed = 0, uses_anonymous_args = 0
3501 @ link register save eliminated.
3502 .LVL422:
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** uint32_t blkCnt; /* Loop counter */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** const q15_t *pIn = pSrc; /* Source pointer */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** q31_t in1, in2;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** q31_t out1, out2, out3, out4;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #endif
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Loop unrolling: Compute 4 outputs at a time */
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt = blockSize >> 2U;
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** while (blkCnt > 0U)
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* C = (q31_t)A << 16 */
ARM GAS /tmp/cce2LIhc.s page 181
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Convert from q15 to q31 and store result in destination buffer */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** in1 = read_q15x2_ia ((q15_t **) &pIn);
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** in2 = read_q15x2_ia ((q15_t **) &pIn);
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #ifndef ARM_MATH_BIG_ENDIAN
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract lower 16 bits to 32 bit result */
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out1 = in1 << 16U;
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract upper 16 bits to 32 bit result */
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out2 = in1 & 0xFFFF0000;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract lower 16 bits to 32 bit result */
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out3 = in2 << 16U;
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract upper 16 bits to 32 bit result */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out4 = in2 & 0xFFFF0000;
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #else
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract upper 16 bits to 32 bit result */
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out1 = in1 & 0xFFFF0000;
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract lower 16 bits to 32 bit result */
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out2 = in1 << 16U;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract upper 16 bits to 32 bit result */
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out3 = in2 & 0xFFFF0000;
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* extract lower 16 bits to 32 bit result */
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** out4 = in2 << 16U;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = out1;
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = out2;
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = out3;
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = out4;
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Decrement loop counter */
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt--;
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Loop unrolling: Compute remaining outputs */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt = blockSize % 0x4U;
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #else
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Initialize blkCnt with number of samples */
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt = blockSize;
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** while (blkCnt > 0U)
3503 .loc 28 166 0
3504 0000 3AB1 cbz r2, .L451
3505 .LVL423:
3506 .L453:
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* C = (q31_t) A << 16 */
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Convert from q15 to q31 and store result in destination buffer */
ARM GAS /tmp/cce2LIhc.s page 182
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** *pDst++ = (q31_t) *pIn++ << 16;
3507 .loc 28 171 0
3508 0002 30F9023B ldrsh r3, [r0], #2
3509 .LVL424:
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
3510 .loc 28 166 0
3511 0006 013A subs r2, r2, #1
3512 .LVL425:
3513 .loc 28 171 0
3514 0008 4FEA0343 lsl r3, r3, #16
3515 000c 41F8043B str r3, [r1], #4
3516 .LVL426:
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** {
3517 .loc 28 166 0
3518 0010 F7D1 bne .L453
3519 .L451:
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** /* Decrement loop counter */
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** blkCnt--;
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c ****
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c **** }
3520 .loc 28 177 0
3521 0012 7047 bx lr
3522 .cfi_endproc
3523 .LFE180:
3525 .section .text.arm_q15_to_q7,"ax",%progbits
3526 .align 1
3527 .p2align 2,,3
3528 .global arm_q15_to_q7
3529 .syntax unified
3530 .thumb
3531 .thumb_func
3532 .fpu fpv4-sp-d16
3534 arm_q15_to_q7:
3535 .LFB181:
3536 .file 29 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Title: arm_q15_to_q7.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Description: Converts the elements of the Q15 vector to Q7 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * www.apache.org/licenses/LICENSE-2.0
ARM GAS /tmp/cce2LIhc.s page 183
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @addtogroup q15_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @brief Converts the elements of the Q15 vector to Q7 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @param[in] pSrc points to the Q15 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @param[out] pDst points to the Q7 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #if defined(ARM_MATH_MVEI)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** void arm_q15_to_q7(
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** const q15_t * pSrc,
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q7_t * pDst,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** uint32_t blockSize)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** uint32_t blkCnt; /* loop counters */
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q15x8x2_t tmp;
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q15_t const *pSrcVec;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q7x16_t vecDst;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** pSrcVec = (q15_t const *) pSrc;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt = blockSize >> 4;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** while (blkCnt > 0U)
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* C = (q7_t) A >> 8 */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* convert from q15 to q7 and then store the results in the destination buffer */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** tmp = vld2q(pSrcVec);
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** pSrcVec += 16;
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** vecDst = vqshrnbq_n_s16(vecDst, tmp.val[0], 8);
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** vecDst = vqshrntq_n_s16(vecDst, tmp.val[1], 8);
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** vst1q(pDst, vecDst);
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** pDst += 16;
ARM GAS /tmp/cce2LIhc.s page 184
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /*
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** * Decrement the blockSize loop counter
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** */
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt--;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt = blockSize & 0xF;
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** while (blkCnt > 0U)
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* C = (q7_t) A >> 8 */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Convert from q15 to q7 and store result in destination buffer */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pSrcVec++ >> 8);
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Decrement loop counter */
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt--;
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #else
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** void arm_q15_to_q7(
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** const q15_t * pSrc,
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q7_t * pDst,
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** uint32_t blockSize)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
3537 .loc 29 101 0
3538 .cfi_startproc
3539 @ args = 0, pretend = 0, frame = 0
3540 @ frame_needed = 0, uses_anonymous_args = 0
3541 @ link register save eliminated.
3542 .LVL427:
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** uint32_t blkCnt; /* Loop counter */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** const q15_t *pIn = pSrc; /* Source pointer */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q31_t in1, in2;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** q31_t out1, out2;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #endif
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #if defined (ARM_MATH_LOOPUNROLL)
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Loop unrolling: Compute 4 outputs at a time */
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt = blockSize >> 2U;
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** while (blkCnt > 0U)
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* C = (q7_t) A >> 8 */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Convert from q15 to q7 and store result in destination buffer */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #if defined (ARM_MATH_DSP)
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** in1 = read_q15x2_ia ((q15_t **) &pIn);
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** in2 = read_q15x2_ia ((q15_t **) &pIn);
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #ifndef ARM_MATH_BIG_ENDIAN
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out1 = __PKHTB(in2, in1, 16);
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out2 = __PKHBT(in2, in1, 16);
ARM GAS /tmp/cce2LIhc.s page 185
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #else
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out1 = __PKHTB(in1, in2, 16);
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out2 = __PKHBT(in1, in2, 16);
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* rotate packed value by 24 */
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* anding with 0xff00ff00 to get two 8 bit values */
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out1 = out1 & 0xFF00FF00;
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* anding with 0x00ff00ff to get two 8 bit values */
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out2 = out2 & 0x00FF00FF;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** out1 = out1 | out2;
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* store 4 samples at a time to destiantion buffer */
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** write_q7x4_ia (&pDst, out1);
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #else
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 8);
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 8);
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 8);
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 8);
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #endif /* #if defined (ARM_MATH_DSP) */
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Decrement loop counter */
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt--;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Loop unrolling: Compute remaining outputs */
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt = blockSize % 0x4U;
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #else
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Initialize blkCnt with number of samples */
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt = blockSize;
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** while (blkCnt > 0U)
3543 .loc 29 174 0
3544 0000 3AB1 cbz r2, .L458
3545 0002 0A44 add r2, r2, r1
3546 .LVL428:
3547 .L460:
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* C = (q7_t) A >> 8 */
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Convert from q15 to q7 and store result in destination buffer */
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 8);
3548 .loc 29 179 0
ARM GAS /tmp/cce2LIhc.s page 186
3549 0004 30F9023B ldrsh r3, [r0], #2
3550 .LVL429:
3551 0008 1B12 asrs r3, r3, #8
3552 000a 01F8013B strb r3, [r1], #1
3553 .LVL430:
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** {
3554 .loc 29 174 0
3555 000e 9142 cmp r1, r2
3556 0010 F8D1 bne .L460
3557 .L458:
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** /* Decrement loop counter */
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** blkCnt--;
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c **** }
3558 .loc 29 185 0
3559 0012 7047 bx lr
3560 .cfi_endproc
3561 .LFE181:
3563 .section .text.arm_q31_to_float,"ax",%progbits
3564 .align 1
3565 .p2align 2,,3
3566 .global arm_q31_to_float
3567 .syntax unified
3568 .thumb
3569 .thumb_func
3570 .fpu fpv4-sp-d16
3572 arm_q31_to_float:
3573 .LFB182:
3574 .file 30 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Title: arm_q31_to_float.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Description: Converts the elements of the Q31 vector to floating-point vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * limitations under the License.
ARM GAS /tmp/cce2LIhc.s page 187
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * @defgroup q31_to_x Convert 32-bit Integer value
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /**
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @addtogroup q31_to_x
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @{
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /**
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @brief Converts the elements of the Q31 vector to floating-point vector.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @param[in] pSrc points to the Q31 input vector
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @param[out] pDst points to the floating-point output vector
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @param[in] blockSize number of samples in each vector
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @return none
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** @par Details
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** The equation used for the conversion process is:
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** <pre>
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** </pre>
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** void arm_q31_to_float(
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** const q31_t * pSrc,
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** float32_t * pDst,
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blockSize)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blkCnt; /* loop counters */
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** q31x4_t vecDst;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** q31_t const *pSrcVec;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pSrcVec = (q31_t const *) pSrc;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize >> 2;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* convert from q31 to float and then store the results in the destination buffer */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** vecDst = vld1q(pSrcVec);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pSrcVec += 4;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 31));
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pDst += 4;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /*
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * Decrement the blockSize loop counter
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /*
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * tail
ARM GAS /tmp/cce2LIhc.s page 188
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** * (will be merged thru tail predication)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize & 3;
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Convert from q31 to float and store result in destination buffer */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pSrcVec++ / 2147483648.0f);
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Decrement loop counter */
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #else
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #if defined(ARM_MATH_NEON_EXPERIMENTAL)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** void arm_q31_to_float(
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** const q31_t * pSrc,
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** float32_t * pDst,
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blockSize)
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** const q31_t *pIn = pSrc; /* Src pointer */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blkCnt; /* loop counter */
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** int32x4_t inV;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** float32x4_t outV;
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize >> 2U;
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Compute 4 outputs at a time.
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** ** a second loop below computes the remaining 1 to 3 samples. */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Convert from q31 to float and then store the results in the destination buffer */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** inV = vld1q_s32(pIn);
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pIn += 4;
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** outV = vcvtq_n_f32_s32(inV,31);
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** vst1q_f32(pDst, outV);
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** pDst += 4;
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Decrement the loop counter */
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** ** No loop unrolling is used. */
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize & 3;
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Convert from q31 to float and then store the results in the destination buffer */
ARM GAS /tmp/cce2LIhc.s page 189
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Decrement the loop counter */
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #else
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** void arm_q31_to_float(
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** const q31_t * pSrc,
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** float32_t * pDst,
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blockSize)
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
3575 .loc 30 152 0
3576 .cfi_startproc
3577 @ args = 0, pretend = 0, frame = 0
3578 @ frame_needed = 0, uses_anonymous_args = 0
3579 @ link register save eliminated.
3580 .LVL431:
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** const q31_t *pIn = pSrc; /* Src pointer */
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** uint32_t blkCnt; /* loop counter */
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #if defined (ARM_MATH_LOOPUNROLL)
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Loop unrolling */
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize >> 2U;
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Convert from q31 to float and store result in destination buffer */
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Decrement loop counter */
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Loop unrolling: Compute remaining outputs */
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize % 0x4U;
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #else
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Initialize blkCnt with number of samples */
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt = blockSize;
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** while (blkCnt > 0U)
3581 .loc 30 185 0
3582 0000 5AB1 cbz r2, .L465
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* C = (float32_t) A / 2147483648 */
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Convert from q31 to float and store result in destination buffer */
ARM GAS /tmp/cce2LIhc.s page 190
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
3583 .loc 30 190 0
3584 0002 9FED067A vldr.32 s14, .L472
3585 .LVL432:
3586 .L467:
3587 0006 F0EC017A vldmia.32 r0!, {s15} @ int
3588 .LVL433:
3589 000a F8EEE77A vcvt.f32.s32 s15, s15
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
3590 .loc 30 185 0
3591 000e 013A subs r2, r2, #1
3592 .LVL434:
3593 .loc 30 190 0
3594 0010 67EE877A vmul.f32 s15, s15, s14
3595 0014 E1EC017A vstmia.32 r1!, {s15}
3596 .LVL435:
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** {
3597 .loc 30 185 0
3598 0018 F5D1 bne .L467
3599 .L465:
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** /* Decrement loop counter */
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** blkCnt--;
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c ****
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c **** }
3600 .loc 30 196 0
3601 001a 7047 bx lr
3602 .L473:
3603 .align 2
3604 .L472:
3605 001c 00000030 .word 805306368
3606 .cfi_endproc
3607 .LFE182:
3609 .section .text.arm_q31_to_q15,"ax",%progbits
3610 .align 1
3611 .p2align 2,,3
3612 .global arm_q31_to_q15
3613 .syntax unified
3614 .thumb
3615 .thumb_func
3616 .fpu fpv4-sp-d16
3618 arm_q31_to_q15:
3619 .LFB183:
3620 .file 31 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Title: arm_q31_to_q15.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Description: Converts the elements of the Q31 vector to Q15 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
ARM GAS /tmp/cce2LIhc.s page 191
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @addtogroup q31_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @brief Converts the elements of the Q31 vector to Q15 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @param[in] pSrc points to the Q31 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @param[out] pDst points to the Q15 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #if defined(ARM_MATH_MVEI)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** void arm_q31_to_q15(
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** const q31_t * pSrc,
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q15_t * pDst,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** uint32_t blockSize)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** uint32_t blkCnt; /* loop counters */
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q31x4x2_t tmp;
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q15x8_t vecDst;
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q31_t const *pSrcVec;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** pSrcVec = (q31_t const *) pSrc;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt = blockSize >> 3;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** while (blkCnt > 0U)
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* C = (q15_t) A >> 16 */
ARM GAS /tmp/cce2LIhc.s page 192
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* convert from q31 to q15 and then store the results in the destination buffer */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** tmp = vld2q(pSrcVec);
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** pSrcVec += 8;
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** vecDst = vshrnbq_n_s32(vecDst, tmp.val[0], 16);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** vecDst = vshrntq_n_s32(vecDst, tmp.val[1], 16);
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** vst1q(pDst, vecDst);
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** pDst += 8;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /*
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * Decrement the blockSize loop counter
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt--;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /*
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** * tail
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt = blockSize & 7;
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** while (blkCnt > 0U)
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* C = (q15_t) (A >> 16) */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Convert from q31 to q15 and store result in destination buffer */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pSrcVec++ >> 16);
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Decrement loop counter */
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt--;
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #else
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** void arm_q31_to_q15(
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** const q31_t * pSrc,
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q15_t * pDst,
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** uint32_t blockSize)
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
3621 .loc 31 104 0
3622 .cfi_startproc
3623 @ args = 0, pretend = 0, frame = 0
3624 @ frame_needed = 0, uses_anonymous_args = 0
3625 @ link register save eliminated.
3626 .LVL436:
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** uint32_t blkCnt; /* Loop counter */
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** const q31_t *pIn = pSrc; /* Source pointer */
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q31_t in1, in2, in3, in4;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** q31_t out1, out2;
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #endif
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #if defined (ARM_MATH_LOOPUNROLL)
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Loop unrolling: Compute 4 outputs at a time */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt = blockSize >> 2U;
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** while (blkCnt > 0U)
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* C = (q15_t) (A >> 16) */
ARM GAS /tmp/cce2LIhc.s page 193
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Convert from q31 to q15 and store result in destination buffer */
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #if defined (ARM_MATH_DSP)
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** in1 = *pIn++;
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** in2 = *pIn++;
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** in3 = *pIn++;
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** in4 = *pIn++;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* pack two higher 16-bit values from two 32-bit values */
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #ifndef ARM_MATH_BIG_ENDIAN
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** out1 = __PKHTB(in2, in1, 16);
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** out2 = __PKHTB(in4, in3, 16);
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #else
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** out1 = __PKHTB(in1, in2, 16);
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** out2 = __PKHTB(in3, in4, 16);
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #endif /* #ifdef ARM_MATH_BIG_ENDIAN */
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** write_q15x2_ia (&pDst, out1);
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** write_q15x2_ia (&pDst, out2);
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #else
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pIn++ >> 16);
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pIn++ >> 16);
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pIn++ >> 16);
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pIn++ >> 16);
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #endif /* #if defined (ARM_MATH_DSP) */
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Decrement loop counter */
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt--;
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Loop unrolling: Compute remaining outputs */
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt = blockSize % 0x4U;
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #else
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Initialize blkCnt with number of samples */
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt = blockSize;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** while (blkCnt > 0U)
3627 .loc 31 165 0
3628 0000 3AB1 cbz r2, .L474
3629 .LVL437:
3630 .L476:
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* C = (q15_t) (A >> 16) */
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Convert from q31 to q15 and store result in destination buffer */
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** *pDst++ = (q15_t) (*pIn++ >> 16);
3631 .loc 31 170 0
3632 0002 50F8043B ldr r3, [r0], #4
3633 .LVL438:
ARM GAS /tmp/cce2LIhc.s page 194
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
3634 .loc 31 165 0
3635 0006 013A subs r2, r2, #1
3636 .LVL439:
3637 .loc 31 170 0
3638 0008 4FEA2343 asr r3, r3, #16
3639 000c 21F8023B strh r3, [r1], #2 @ movhi
3640 .LVL440:
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** {
3641 .loc 31 165 0
3642 0010 F7D1 bne .L476
3643 .L474:
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** /* Decrement loop counter */
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** blkCnt--;
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c ****
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c **** }
3644 .loc 31 176 0
3645 0012 7047 bx lr
3646 .cfi_endproc
3647 .LFE183:
3649 .section .text.arm_q31_to_q7,"ax",%progbits
3650 .align 1
3651 .p2align 2,,3
3652 .global arm_q31_to_q7
3653 .syntax unified
3654 .thumb
3655 .thumb_func
3656 .fpu fpv4-sp-d16
3658 arm_q31_to_q7:
3659 .LFB184:
3660 .file 32 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Title: arm_q31_to_q7.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Description: Converts the elements of the Q31 vector to Q7 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ARM GAS /tmp/cce2LIhc.s page 195
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @addtogroup q31_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @brief Converts the elements of the Q31 vector to Q7 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @param[in] pSrc points to the Q31 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @param[out] pDst points to the Q7 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #if defined(ARM_MATH_MVEI)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** void arm_q31_to_q7(
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** const q31_t * pSrc,
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q7_t * pDst,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** uint32_t blockSize)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** uint32_t blkCnt; /* loop counters */
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q31x4x4_t tmp;
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q15x8_t evVec, oddVec;
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q7x16_t vecDst;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q31_t const *pSrcVec;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** pSrcVec = (q31_t const *) pSrc;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt = blockSize >> 4;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** while (blkCnt > 0U)
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** tmp = vld4q(pSrcVec);
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** pSrcVec += 16;
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* C = (q7_t) A >> 24 */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* convert from q31 to q7 and then store the results in the destination buffer */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * narrow and pack evens
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** evVec = vshrnbq_n_s32(evVec, tmp.val[0], 16);
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** evVec = vshrntq_n_s32(evVec, tmp.val[2], 16);
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * narrow and pack odds
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** oddVec = vshrnbq_n_s32(oddVec, tmp.val[1], 16);
ARM GAS /tmp/cce2LIhc.s page 196
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** oddVec = vshrntq_n_s32(oddVec, tmp.val[3], 16);
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * narrow & merge
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** vecDst = vshrnbq_n_s16(vecDst, evVec, 8);
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** vecDst = vshrntq_n_s16(vecDst, oddVec, 8);
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** vst1q(pDst, vecDst);
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** pDst += 16;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * Decrement the blockSize loop counter
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt--;
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /*
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** * tail
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** */
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt = blockSize & 0xF;
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** while (blkCnt > 0U)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* C = (q7_t) (A >> 24) */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Convert from q31 to q7 and store result in destination buffer */
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *pDst++ = (q7_t) (*pSrcVec++ >> 24);
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Decrement loop counter */
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt--;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #else
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** void arm_q31_to_q7(
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** const q31_t * pSrc,
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q7_t * pDst,
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** uint32_t blockSize)
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
3661 .loc 32 116 0
3662 .cfi_startproc
3663 @ args = 0, pretend = 0, frame = 0
3664 @ frame_needed = 0, uses_anonymous_args = 0
3665 @ link register save eliminated.
3666 .LVL441:
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** uint32_t blkCnt; /* Loop counter */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** const q31_t *pIn = pSrc; /* Source pointer */
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #if defined (ARM_MATH_LOOPUNROLL)
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** q7_t out1, out2, out3, out4;
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Loop unrolling: Compute 4 outputs at a time */
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt = blockSize >> 2U;
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** while (blkCnt > 0U)
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* C = (q7_t) (A >> 24) */
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Convert from q31 to q7 and store result in destination buffer */
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
ARM GAS /tmp/cce2LIhc.s page 197
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** out1 = (q7_t) (*pIn++ >> 24);
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** out2 = (q7_t) (*pIn++ >> 24);
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** out3 = (q7_t) (*pIn++ >> 24);
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** out4 = (q7_t) (*pIn++ >> 24);
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4));
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Decrement loop counter */
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt--;
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Loop unrolling: Compute remaining outputs */
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt = blockSize % 0x4U;
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #else
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Initialize blkCnt with number of samples */
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt = blockSize;
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** while (blkCnt > 0U)
3667 .loc 32 153 0
3668 0000 3AB1 cbz r2, .L481
3669 0002 0A44 add r2, r2, r1
3670 .LVL442:
3671 .L483:
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* C = (q7_t) (A >> 24) */
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Convert from q31 to q7 and store result in destination buffer */
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** *pDst++ = (q7_t) (*pIn++ >> 24);
3672 .loc 32 158 0
3673 0004 50F8043B ldr r3, [r0], #4
3674 .LVL443:
3675 0008 1B16 asrs r3, r3, #24
3676 000a 01F8013B strb r3, [r1], #1
3677 .LVL444:
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** {
3678 .loc 32 153 0
3679 000e 9142 cmp r1, r2
3680 0010 F8D1 bne .L483
3681 .L481:
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** /* Decrement loop counter */
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** blkCnt--;
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c ****
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c **** }
3682 .loc 32 164 0
3683 0012 7047 bx lr
3684 .cfi_endproc
3685 .LFE184:
3687 .section .text.arm_q7_to_float,"ax",%progbits
3688 .align 1
3689 .p2align 2,,3
3690 .global arm_q7_to_float
3691 .syntax unified
ARM GAS /tmp/cce2LIhc.s page 198
3692 .thumb
3693 .thumb_func
3694 .fpu fpv4-sp-d16
3696 arm_q7_to_float:
3697 .LFB185:
3698 .file 33 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Title: arm_q7_to_float.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Description: Converts the elements of the Q7 vector to floating-point vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * @defgroup q7_to_x Convert 8-bit Integer value
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /**
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @addtogroup q7_to_x
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @{
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /**
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @brief Converts the elements of the Q7 vector to floating-point vector.
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @param[in] pSrc points to the Q7 input vector
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @param[out] pDst points to the floating-point output vector
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @param[in] blockSize number of samples in each vector
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @return none
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** @par Details
ARM GAS /tmp/cce2LIhc.s page 199
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** The equation used for the conversion process is:
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** <pre>
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** </pre>
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** void arm_q7_to_float(
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** const q7_t * pSrc,
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** float32_t * pDst,
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blockSize)
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blkCnt; /* loop counters */
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** q7x16_t vecDst;
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** q7_t const *pSrcVec;
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pSrcVec = (q7_t const *) pSrc;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize >> 2;
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 32768 */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* convert from q7 to float and then store the results in the destination buffer */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vecDst = vldrbq_s32(pSrcVec);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pSrcVec += 4;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vstrwq(pDst, vcvtq_n_f32_s32(vecDst, 7));
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst += 4;
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /*
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** * Decrement the blockSize loop counter
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** */
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize & 3;
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 128 */
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Convert from q7 to float and store result in destination buffer */
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pSrcVec++ / 128.0f);
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Decrement loop counter */
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #else
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #if defined(ARM_MATH_NEON)
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** void arm_q7_to_float(
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** const q7_t * pSrc,
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** float32_t * pDst,
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blockSize)
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** const q7_t *pIn = pSrc; /* Src pointer */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blkCnt; /* loop counter */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** int8x16_t inV;
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** int16x8_t inVLO, inVHI;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** int32x4_t inVLL, inVLH, inVHL, inVHH;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** float32x4_t outV;
ARM GAS /tmp/cce2LIhc.s page 200
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize >> 4U;
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Compute 16 outputs at a time.
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** ** a second loop below computes the remaining 1 to 15 samples. */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 128 */
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Convert from q7 to float and then store the results in the destination buffer */
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inV = vld1q_s8(pIn);
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pIn += 16;
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVLO = vmovl_s8(vget_low_s8(inV));
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVHI = vmovl_s8(vget_high_s8(inV));
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVLL = vmovl_s16(vget_low_s16(inVLO));
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVLH = vmovl_s16(vget_high_s16(inVLO));
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVHL = vmovl_s16(vget_low_s16(inVHI));
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** inVHH = vmovl_s16(vget_high_s16(inVHI));
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** outV = vcvtq_n_f32_s32(inVLL,7);
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vst1q_f32(pDst, outV);
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst += 4;
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** outV = vcvtq_n_f32_s32(inVLH,7);
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vst1q_f32(pDst, outV);
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst += 4;
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** outV = vcvtq_n_f32_s32(inVHL,7);
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vst1q_f32(pDst, outV);
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst += 4;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** outV = vcvtq_n_f32_s32(inVHH,7);
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** vst1q_f32(pDst, outV);
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** pDst += 4;
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Decrement the loop counter */
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* If the blockSize is not a multiple of 16, compute any remaining output samples here.
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** ** No loop unrolling is used. */
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize & 0xF;
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 128 */
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Convert from q7 to float and then store the results in the destination buffer */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Decrement the loop counter */
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #else
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** void arm_q7_to_float(
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** const q7_t * pSrc,
ARM GAS /tmp/cce2LIhc.s page 201
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** float32_t * pDst,
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blockSize)
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
3699 .loc 33 168 0
3700 .cfi_startproc
3701 @ args = 0, pretend = 0, frame = 0
3702 @ frame_needed = 0, uses_anonymous_args = 0
3703 @ link register save eliminated.
3704 .LVL445:
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** uint32_t blkCnt; /* Loop counter */
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** const q7_t *pIn = pSrc; /* Source pointer */
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #if defined (ARM_MATH_LOOPUNROLL)
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Loop unrolling: Compute 4 outputs at a time */
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize >> 2U;
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 128 */
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Convert from q7 to float and store result in destination buffer */
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
184:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
185:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
186:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
187:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Decrement loop counter */
188:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
189:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
190:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
191:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Loop unrolling: Compute remaining outputs */
192:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize % 0x4U;
193:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
194:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #else
195:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
196:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Initialize blkCnt with number of samples */
197:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt = blockSize;
198:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
199:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
200:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** while (blkCnt > 0U)
3705 .loc 33 201 0
3706 0000 72B1 cbz r2, .L488
202:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
203:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* C = (float32_t) A / 128 */
204:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
205:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Convert from q7 to float and store result in destination buffer */
206:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** *pDst++ = ((float32_t) * pIn++ / 128.0f);
3707 .loc 33 206 0
3708 0002 9FED087A vldr.32 s14, .L495
3709 0006 0244 add r2, r2, r0
3710 .LVL446:
3711 .L490:
3712 0008 10F9013B ldrsb r3, [r0], #1
3713 .LVL447:
3714 000c 07EE903A vmov s15, r3 @ int
ARM GAS /tmp/cce2LIhc.s page 202
3715 0010 F8EEE77A vcvt.f32.s32 s15, s15
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
3716 .loc 33 201 0
3717 0014 9042 cmp r0, r2
3718 .loc 33 206 0
3719 0016 67EE877A vmul.f32 s15, s15, s14
3720 001a E1EC017A vstmia.32 r1!, {s15}
3721 .LVL448:
201:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** {
3722 .loc 33 201 0
3723 001e F3D1 bne .L490
3724 .LVL449:
3725 .L488:
207:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
208:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** /* Decrement loop counter */
209:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** blkCnt--;
210:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
211:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c ****
212:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c **** }
3726 .loc 33 212 0
3727 0020 7047 bx lr
3728 .L496:
3729 0022 00BF .align 2
3730 .L495:
3731 0024 0000003C .word 1006632960
3732 .cfi_endproc
3733 .LFE185:
3735 .section .text.arm_q7_to_q15,"ax",%progbits
3736 .align 1
3737 .p2align 2,,3
3738 .global arm_q7_to_q15
3739 .syntax unified
3740 .thumb
3741 .thumb_func
3742 .fpu fpv4-sp-d16
3744 arm_q7_to_q15:
3745 .LFB186:
3746 .file 34 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Title: arm_q7_to_q15.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Description: Converts the elements of the Q7 vector to Q15 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
ARM GAS /tmp/cce2LIhc.s page 203
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @addtogroup q7_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @brief Converts the elements of the Q7 vector to Q15 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @param[in] pSrc points to the Q7 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @param[out] pDst points to the Q15 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #if defined(ARM_MATH_MVEI)
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** void arm_q7_to_q15(
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** const q7_t * pSrc,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q15_t * pDst,
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** uint32_t blockSize)
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** uint32_t blkCnt; /* loop counters */
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q15x8_t vecDst;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q7_t const *pSrcVec;
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** pSrcVec = (q7_t const *) pSrc;
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt = blockSize >> 3;
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** while (blkCnt > 0U)
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* C = (q15_t) A << 8 */
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* convert from q7 to q15 and then store the results in the destination buffer */
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* load q7 + 32-bit widening */
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** vecDst = vldrbq_s16(pSrcVec);
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** pSrcVec += 8;
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** vecDst = vecDst << 8;
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** vstrhq(pDst, vecDst);
ARM GAS /tmp/cce2LIhc.s page 204
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** pDst += 8;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /*
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** * Decrement the blockSize loop counter
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** */
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt--;
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt = blockSize & 7;
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** while (blkCnt > 0U)
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* C = (q15_t) A << 8 */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Convert from q7 to q15 and store result in destination buffer */
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) * pSrcVec++ << 8;
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Decrement loop counter */
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt--;
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #else
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** void arm_q7_to_q15(
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** const q7_t * pSrc,
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q15_t * pDst,
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** uint32_t blockSize)
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
3747 .loc 34 102 0
3748 .cfi_startproc
3749 @ args = 0, pretend = 0, frame = 0
3750 @ frame_needed = 0, uses_anonymous_args = 0
3751 @ link register save eliminated.
3752 .LVL450:
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** uint32_t blkCnt; /* Loop counter */
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** const q7_t *pIn = pSrc; /* Source pointer */
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q31_t in;
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q31_t in1, in2;
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** q31_t out1, out2;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #endif
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #if defined (ARM_MATH_LOOPUNROLL)
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Loop unrolling: Compute 4 outputs at a time */
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt = blockSize >> 2U;
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** while (blkCnt > 0U)
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* C = (q15_t) A << 8 */
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Convert from q7 to q15 and store result in destination buffer */
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #if defined (ARM_MATH_DSP)
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in = read_q7x4_ia ((q7_t **) &pIn);
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* rotatate in by 8 and extend two q7_t values to q15_t values */
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in1 = __SXTB16(__ROR(in, 8));
ARM GAS /tmp/cce2LIhc.s page 205
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* extend remainig two q7_t values to q15_t values */
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in2 = __SXTB16(in);
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in1 = in1 << 8U;
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in2 = in2 << 8U;
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in1 = in1 & 0xFF00FF00;
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** in2 = in2 & 0xFF00FF00;
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #ifndef ARM_MATH_BIG_ENDIAN
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** out2 = __PKHTB(in1, in2, 16);
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** out1 = __PKHBT(in2, in1, 16);
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #else
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** out1 = __PKHTB(in1, in2, 16);
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** out2 = __PKHBT(in2, in1, 16);
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #endif
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** write_q15x2_ia (&pDst, out1);
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** write_q15x2_ia (&pDst, out2);
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #else
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) *pIn++ << 8;
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) *pIn++ << 8;
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) *pIn++ << 8;
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) *pIn++ << 8;
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #endif /* #if defined (ARM_MATH_DSP) */
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Decrement loop counter */
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt--;
160:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
161:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
162:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Loop unrolling: Compute remaining outputs */
163:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt = blockSize % 0x4U;
164:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
165:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #else
166:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
167:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Initialize blkCnt with number of samples */
168:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt = blockSize;
169:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
170:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
171:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** while (blkCnt > 0U)
3753 .loc 34 172 0
3754 0000 3AB1 cbz r2, .L497
3755 0002 0244 add r2, r2, r0
3756 .LVL451:
3757 .L499:
173:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
174:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* C = (q15_t) A << 8 */
175:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
176:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Convert from q7 to q15 and store result in destination buffer */
177:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** *pDst++ = (q15_t) * pIn++ << 8;
3758 .loc 34 177 0
3759 0004 10F9013B ldrsb r3, [r0], #1
ARM GAS /tmp/cce2LIhc.s page 206
3760 .LVL452:
3761 0008 1B02 lsls r3, r3, #8
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
3762 .loc 34 172 0
3763 000a 9042 cmp r0, r2
3764 .loc 34 177 0
3765 000c 21F8023B strh r3, [r1], #2 @ movhi
3766 .LVL453:
172:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** {
3767 .loc 34 172 0
3768 0010 F8D1 bne .L499
3769 .LVL454:
3770 .L497:
178:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
179:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** /* Decrement loop counter */
180:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** blkCnt--;
181:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
182:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c ****
183:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c **** }
3771 .loc 34 183 0
3772 0012 7047 bx lr
3773 .cfi_endproc
3774 .LFE186:
3776 .section .text.arm_q7_to_q31,"ax",%progbits
3777 .align 1
3778 .p2align 2,,3
3779 .global arm_q7_to_q31
3780 .syntax unified
3781 .thumb
3782 .thumb_func
3783 .fpu fpv4-sp-d16
3785 arm_q7_to_q31:
3786 .LFB187:
3787 .file 35 "Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c"
1:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* ----------------------------------------------------------------------
2:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Project: CMSIS DSP Library
3:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Title: arm_q7_to_q31.c
4:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Description: Converts the elements of the Q7 vector to Q31 vector
5:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
6:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * $Date: 18. March 2019
7:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * $Revision: V1.6.0
8:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
9:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Target Processor: Cortex-M cores
10:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * -------------------------------------------------------------------- */
11:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /*
12:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
13:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
14:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * SPDX-License-Identifier: Apache-2.0
15:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
16:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Licensed under the Apache License, Version 2.0 (the License); you may
17:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * not use this file except in compliance with the License.
18:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * You may obtain a copy of the License at
19:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
20:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * www.apache.org/licenses/LICENSE-2.0
21:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *
22:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Unless required by applicable law or agreed to in writing, software
23:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ARM GAS /tmp/cce2LIhc.s page 207
24:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * See the License for the specific language governing permissions and
26:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * limitations under the License.
27:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** */
28:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
29:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #include "arm_math.h"
30:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
31:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /**
32:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @ingroup groupSupport
33:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** */
34:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
35:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /**
36:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @addtogroup q7_to_x
37:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @{
38:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** */
39:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
40:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /**
41:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @brief Converts the elements of the Q7 vector to Q31 vector.
42:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @param[in] pSrc points to the Q7 input vector
43:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @param[out] pDst points to the Q31 output vector
44:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @param[in] blockSize number of samples in each vector
45:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @return none
46:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
47:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** @par Details
48:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** The equation used for the conversion process is:
49:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** <pre>
50:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
51:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** </pre>
52:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** */
53:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #if defined(ARM_MATH_MVEI)
54:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** void arm_q7_to_q31(
55:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** const q7_t * pSrc,
56:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** q31_t * pDst,
57:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** uint32_t blockSize)
58:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
59:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** uint32_t blkCnt;
60:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** q31x4_t vecDst;
61:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
62:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt = blockSize >> 2;
63:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** while (blkCnt > 0U)
64:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
65:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
66:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* C = (q31_t)A << 16 */
67:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* convert from q15 to q31 and then store the results in the destination buffer */
68:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* load q15 + 32-bit widening */
69:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** vecDst = vldrbq_s32((q7_t const *) pSrc);
70:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** vecDst = vshlq_n(vecDst, 24);
71:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** vstrwq_s32(pDst, vecDst);
72:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
73:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /*
74:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Decrement the blockSize loop counter
75:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** * Advance vector source and destination pointers
76:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** */
77:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** pDst += 4;
78:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** pSrc += 4;
79:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt --;
80:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
ARM GAS /tmp/cce2LIhc.s page 208
81:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
82:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt = blockSize & 3;
83:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** while (blkCnt > 0U)
84:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
85:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* C = (q31_t) A << 24 */
86:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
87:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Convert from q7 to q31 and store result in destination buffer */
88:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (q31_t) *pSrc++ << 24;
89:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
90:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Decrement loop counter */
91:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt--;
92:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
93:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
94:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
95:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #else
96:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** void arm_q7_to_q31(
97:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** const q7_t * pSrc,
98:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** q31_t * pDst,
99:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** uint32_t blockSize)
100:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
3788 .loc 35 100 0
3789 .cfi_startproc
3790 @ args = 0, pretend = 0, frame = 0
3791 @ frame_needed = 0, uses_anonymous_args = 0
3792 @ link register save eliminated.
3793 .LVL455:
101:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** uint32_t blkCnt; /* Loop counter */
102:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** const q7_t *pIn = pSrc; /* Source pointer */
103:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
104:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #if defined (ARM_MATH_LOOPUNROLL)
105:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
106:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** q31_t in;
107:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
108:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Loop unrolling: Compute 4 outputs at a time */
109:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt = blockSize >> 2U;
110:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
111:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** while (blkCnt > 0U)
112:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
113:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* C = (q31_t) A << 24 */
114:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
115:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Convert from q7 to q31 and store result in destination buffer */
116:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** in = read_q7x4_ia ((q7_t **) &pIn);
117:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
118:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #ifndef ARM_MATH_BIG_ENDIAN
119:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
120:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 8)) & 0xFF000000;
121:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 16)) & 0xFF000000;
122:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 24)) & 0xFF000000;
123:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (in & 0xFF000000);
124:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
125:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #else
126:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
127:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (in & 0xFF000000);
128:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 24)) & 0xFF000000;
129:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 16)) & 0xFF000000;
130:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (__ROR(in, 8)) & 0xFF000000;
131:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
ARM GAS /tmp/cce2LIhc.s page 209
132:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
133:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
134:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Decrement loop counter */
135:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt--;
136:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
137:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
138:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Loop unrolling: Compute remaining outputs */
139:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt = blockSize % 0x4U;
140:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
141:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #else
142:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
143:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Initialize blkCnt with number of samples */
144:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt = blockSize;
145:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
146:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** #endif /* #if defined (ARM_MATH_LOOPUNROLL) */
147:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** while (blkCnt > 0U)
3794 .loc 35 148 0
3795 0000 3AB1 cbz r2, .L504
3796 0002 0244 add r2, r2, r0
3797 .LVL456:
3798 .L506:
149:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
150:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* C = (q31_t) A << 24 */
151:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
152:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Convert from q7 to q31 and store result in destination buffer */
153:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** *pDst++ = (q31_t) * pIn++ << 24;
3799 .loc 35 153 0
3800 0004 10F9013B ldrsb r3, [r0], #1
3801 .LVL457:
3802 0008 1B06 lsls r3, r3, #24
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
3803 .loc 35 148 0
3804 000a 9042 cmp r0, r2
3805 .loc 35 153 0
3806 000c 41F8043B str r3, [r1], #4
3807 .LVL458:
148:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** {
3808 .loc 35 148 0
3809 0010 F8D1 bne .L506
3810 .LVL459:
3811 .L504:
154:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
155:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** /* Decrement loop counter */
156:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** blkCnt--;
157:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
158:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c ****
159:Middlewares/Third_Party/ARM_CMSIS/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c **** }
3812 .loc 35 159 0
3813 0012 7047 bx lr
3814 .cfi_endproc
3815 .LFE187:
3817 .text
3818 .Letext0:
3819 .file 36 "/usr/include/newlib/machine/_default_types.h"
3820 .file 37 "/usr/include/newlib/sys/_stdint.h"
3821 .file 38 "/usr/include/newlib/sys/lock.h"
ARM GAS /tmp/cce2LIhc.s page 210
3822 .file 39 "/usr/include/newlib/sys/_types.h"
3823 .file 40 "/usr/lib/gcc/arm-none-eabi/7.3.1/include/stddef.h"
3824 .file 41 "/usr/include/newlib/sys/reent.h"
3825 .file 42 "/usr/include/newlib/math.h"
3826 .file 43 "<built-in>"
ARM GAS /tmp/cce2LIhc.s page 211
DEFINED SYMBOLS
*ABS*:0000000000000000 SupportFunctions.c
/tmp/cce2LIhc.s:16 .text.arm_quick_sort_core_f32:0000000000000000 $t
/tmp/cce2LIhc.s:23 .text.arm_quick_sort_core_f32:0000000000000000 arm_quick_sort_core_f32
/tmp/cce2LIhc.s:183 .text.arm_merge_sort_core_f32:0000000000000000 $t
/tmp/cce2LIhc.s:190 .text.arm_merge_sort_core_f32:0000000000000000 arm_merge_sort_core_f32
/tmp/cce2LIhc.s:514 .text.arm_barycenter_f32:0000000000000000 $t
/tmp/cce2LIhc.s:522 .text.arm_barycenter_f32:0000000000000000 arm_barycenter_f32
/tmp/cce2LIhc.s:636 .text.arm_barycenter_f32:000000000000007c $d
/tmp/cce2LIhc.s:641 .text.arm_bitonic_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:649 .text.arm_bitonic_sort_f32:0000000000000000 arm_bitonic_sort_f32
/tmp/cce2LIhc.s:854 .text.arm_bubble_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:862 .text.arm_bubble_sort_f32:0000000000000000 arm_bubble_sort_f32
/tmp/cce2LIhc.s:966 .text.arm_copy_f32:0000000000000000 $t
/tmp/cce2LIhc.s:974 .text.arm_copy_f32:0000000000000000 arm_copy_f32
/tmp/cce2LIhc.s:1003 .text.arm_copy_q15:0000000000000000 $t
/tmp/cce2LIhc.s:1011 .text.arm_copy_q15:0000000000000000 arm_copy_q15
/tmp/cce2LIhc.s:1134 .text.arm_copy_q31:0000000000000000 $t
/tmp/cce2LIhc.s:1142 .text.arm_copy_q31:0000000000000000 arm_copy_q31
/tmp/cce2LIhc.s:1172 .text.arm_copy_q7:0000000000000000 $t
/tmp/cce2LIhc.s:1180 .text.arm_copy_q7:0000000000000000 arm_copy_q7
/tmp/cce2LIhc.s:1361 .text.arm_fill_f32:0000000000000000 $t
/tmp/cce2LIhc.s:1369 .text.arm_fill_f32:0000000000000000 arm_fill_f32
/tmp/cce2LIhc.s:1396 .text.arm_fill_q15:0000000000000000 $t
/tmp/cce2LIhc.s:1404 .text.arm_fill_q15:0000000000000000 arm_fill_q15
/tmp/cce2LIhc.s:1516 .text.arm_fill_q31:0000000000000000 $t
/tmp/cce2LIhc.s:1524 .text.arm_fill_q31:0000000000000000 arm_fill_q31
/tmp/cce2LIhc.s:1551 .text.arm_fill_q7:0000000000000000 $t
/tmp/cce2LIhc.s:1559 .text.arm_fill_q7:0000000000000000 arm_fill_q7
/tmp/cce2LIhc.s:1585 .text.arm_heap_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:1593 .text.arm_heap_sort_f32:0000000000000000 arm_heap_sort_f32
/tmp/cce2LIhc.s:1824 .text.arm_insertion_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:1832 .text.arm_insertion_sort_f32:0000000000000000 arm_insertion_sort_f32
/tmp/cce2LIhc.s:1931 .text.arm_merge_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:1939 .text.arm_merge_sort_f32:0000000000000000 arm_merge_sort_f32
/tmp/cce2LIhc.s:2095 .text.arm_merge_sort_init_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2103 .text.arm_merge_sort_init_f32:0000000000000000 arm_merge_sort_init_f32
/tmp/cce2LIhc.s:2122 .text.arm_quick_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2130 .text.arm_quick_sort_f32:0000000000000000 arm_quick_sort_f32
/tmp/cce2LIhc.s:2182 .text.arm_selection_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2190 .text.arm_selection_sort_f32:0000000000000000 arm_selection_sort_f32
/tmp/cce2LIhc.s:2300 .text.arm_sort_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2308 .text.arm_sort_f32:0000000000000000 arm_sort_f32
/tmp/cce2LIhc.s:2341 .text.arm_sort_f32:0000000000000014 $d
/tmp/cce2LIhc.s:2347 .text.arm_sort_f32:000000000000001a $t
/tmp/cce2LIhc.s:2676 .text.arm_sort_init_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2684 .text.arm_sort_init_f32:0000000000000000 arm_sort_init_f32
/tmp/cce2LIhc.s:2703 .text.arm_spline_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2711 .text.arm_spline_f32:0000000000000000 arm_spline_f32
/tmp/cce2LIhc.s:2881 .text.arm_spline_init_f32:0000000000000000 $t
/tmp/cce2LIhc.s:2889 .text.arm_spline_init_f32:0000000000000000 arm_spline_init_f32
/tmp/cce2LIhc.s:3157 .text.arm_spline_init_f32:00000000000001b0 $d
/tmp/cce2LIhc.s:3164 .text.arm_weighted_sum_f32:0000000000000000 $t
/tmp/cce2LIhc.s:3172 .text.arm_weighted_sum_f32:0000000000000000 arm_weighted_sum_f32
/tmp/cce2LIhc.s:3215 .text.arm_weighted_sum_f32:000000000000002c $d
/tmp/cce2LIhc.s:3221 .text.arm_float_to_q15:0000000000000000 $t
/tmp/cce2LIhc.s:3229 .text.arm_float_to_q15:0000000000000000 arm_float_to_q15
ARM GAS /tmp/cce2LIhc.s page 212
/tmp/cce2LIhc.s:3275 .text.arm_float_to_q31:0000000000000000 $t
/tmp/cce2LIhc.s:3283 .text.arm_float_to_q31:0000000000000000 arm_float_to_q31
/tmp/cce2LIhc.s:3384 .text.arm_float_to_q31:0000000000000050 $d
/tmp/cce2LIhc.s:3389 .text.arm_float_to_q7:0000000000000000 $t
/tmp/cce2LIhc.s:3397 .text.arm_float_to_q7:0000000000000000 arm_float_to_q7
/tmp/cce2LIhc.s:3438 .text.arm_q15_to_float:0000000000000000 $t
/tmp/cce2LIhc.s:3446 .text.arm_q15_to_float:0000000000000000 arm_q15_to_float
/tmp/cce2LIhc.s:3481 .text.arm_q15_to_float:0000000000000020 $d
/tmp/cce2LIhc.s:3486 .text.arm_q15_to_q31:0000000000000000 $t
/tmp/cce2LIhc.s:3494 .text.arm_q15_to_q31:0000000000000000 arm_q15_to_q31
/tmp/cce2LIhc.s:3526 .text.arm_q15_to_q7:0000000000000000 $t
/tmp/cce2LIhc.s:3534 .text.arm_q15_to_q7:0000000000000000 arm_q15_to_q7
/tmp/cce2LIhc.s:3564 .text.arm_q31_to_float:0000000000000000 $t
/tmp/cce2LIhc.s:3572 .text.arm_q31_to_float:0000000000000000 arm_q31_to_float
/tmp/cce2LIhc.s:3605 .text.arm_q31_to_float:000000000000001c $d
/tmp/cce2LIhc.s:3610 .text.arm_q31_to_q15:0000000000000000 $t
/tmp/cce2LIhc.s:3618 .text.arm_q31_to_q15:0000000000000000 arm_q31_to_q15
/tmp/cce2LIhc.s:3650 .text.arm_q31_to_q7:0000000000000000 $t
/tmp/cce2LIhc.s:3658 .text.arm_q31_to_q7:0000000000000000 arm_q31_to_q7
/tmp/cce2LIhc.s:3688 .text.arm_q7_to_float:0000000000000000 $t
/tmp/cce2LIhc.s:3696 .text.arm_q7_to_float:0000000000000000 arm_q7_to_float
/tmp/cce2LIhc.s:3731 .text.arm_q7_to_float:0000000000000024 $d
/tmp/cce2LIhc.s:3736 .text.arm_q7_to_q15:0000000000000000 $t
/tmp/cce2LIhc.s:3744 .text.arm_q7_to_q15:0000000000000000 arm_q7_to_q15
/tmp/cce2LIhc.s:3777 .text.arm_q7_to_q31:0000000000000000 $t
/tmp/cce2LIhc.s:3785 .text.arm_q7_to_q31:0000000000000000 arm_q7_to_q31
UNDEFINED SYMBOLS
memset
memcpy
__aeabi_f2lz
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