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28b7af65b6b4b2a27e17d5cd0560fc94bdf146fe
squeow/squeow_sw/build/main.lst
nzasch 28b7af65b6 UI led
2025-06-28 00:58:29 +02:00

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ARM GAS /tmp/cchrMLox.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "main.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Src/main.c"
20 .section .text.MX_GPIO_Init,"ax",%progbits
21 .align 1
22 .syntax unified
23 .thumb
24 .thumb_func
26 MX_GPIO_Init:
27 .LFB342:
1:Src/main.c **** /* USER CODE BEGIN Header */
2:Src/main.c **** /**
3:Src/main.c **** ******************************************************************************
4:Src/main.c **** * @file : main.c
5:Src/main.c **** * @brief : Main program body
6:Src/main.c **** ******************************************************************************
7:Src/main.c **** * @attention
8:Src/main.c **** *
9:Src/main.c **** * Copyright (c) 2022 STMicroelectronics.
10:Src/main.c **** * All rights reserved.
11:Src/main.c **** *
12:Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Src/main.c **** * in the root directory of this software component.
14:Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Src/main.c **** *
16:Src/main.c **** ******************************************************************************
17:Src/main.c **** */
18:Src/main.c **** /* USER CODE END Header */
19:Src/main.c **** /* Includes ------------------------------------------------------------------*/
20:Src/main.c **** #include "main.h"
21:Src/main.c ****
22:Src/main.c **** /* Private includes ----------------------------------------------------------*/
23:Src/main.c **** /* USER CODE BEGIN Includes */
24:Src/main.c **** #include "si5351.h"
25:Src/main.c **** #include "squeow.h"
26:Src/main.c **** #include "squeow_ui.h"
27:Src/main.c ****
28:Src/main.c **** /* USER CODE END Includes */
29:Src/main.c ****
30:Src/main.c **** /* Private typedef -----------------------------------------------------------*/
31:Src/main.c **** /* USER CODE BEGIN PTD */
ARM GAS /tmp/cchrMLox.s page 2
32:Src/main.c ****
33:Src/main.c **** /* USER CODE END PTD */
34:Src/main.c ****
35:Src/main.c **** /* Private define ------------------------------------------------------------*/
36:Src/main.c **** /* USER CODE BEGIN PD */
37:Src/main.c **** /* USER CODE END PD */
38:Src/main.c ****
39:Src/main.c **** /* Private macro -------------------------------------------------------------*/
40:Src/main.c **** /* USER CODE BEGIN PM */
41:Src/main.c ****
42:Src/main.c **** /* USER CODE END PM */
43:Src/main.c ****
44:Src/main.c **** /* Private variables ---------------------------------------------------------*/
45:Src/main.c **** ADC_HandleTypeDef hadc1;
46:Src/main.c **** ADC_HandleTypeDef hadc2;
47:Src/main.c **** DMA_HandleTypeDef hdma_adc2;
48:Src/main.c ****
49:Src/main.c **** I2C_HandleTypeDef hi2c1;
50:Src/main.c ****
51:Src/main.c **** TIM_HandleTypeDef htim2;
52:Src/main.c **** TIM_HandleTypeDef htim3;
53:Src/main.c **** TIM_HandleTypeDef htim8;
54:Src/main.c ****
55:Src/main.c **** UART_HandleTypeDef huart1;
56:Src/main.c **** DMA_HandleTypeDef hdma_usart1_rx;
57:Src/main.c **** DMA_HandleTypeDef hdma_usart1_tx;
58:Src/main.c ****
59:Src/main.c **** /* USER CODE BEGIN PV */
60:Src/main.c ****
61:Src/main.c **** /* USER CODE END PV */
62:Src/main.c ****
63:Src/main.c **** /* Private function prototypes -----------------------------------------------*/
64:Src/main.c **** void SystemClock_Config(void);
65:Src/main.c **** static void MX_GPIO_Init(void);
66:Src/main.c **** static void MX_DMA_Init(void);
67:Src/main.c **** static void MX_TIM2_Init(void);
68:Src/main.c **** static void MX_I2C1_Init(void);
69:Src/main.c **** static void MX_TIM3_Init(void);
70:Src/main.c **** static void MX_ADC1_Init(void);
71:Src/main.c **** static void MX_ADC2_Init(void);
72:Src/main.c **** static void MX_USART1_UART_Init(void);
73:Src/main.c **** static void MX_TIM8_Init(void);
74:Src/main.c **** /* USER CODE BEGIN PFP */
75:Src/main.c ****
76:Src/main.c **** /* USER CODE END PFP */
77:Src/main.c ****
78:Src/main.c **** /* Private user code ---------------------------------------------------------*/
79:Src/main.c **** /* USER CODE BEGIN 0 */
80:Src/main.c ****
81:Src/main.c **** /* USER CODE END 0 */
82:Src/main.c ****
83:Src/main.c **** /**
84:Src/main.c **** * @brief The application entry point.
85:Src/main.c **** * @retval int
86:Src/main.c **** */
87:Src/main.c **** int main(void)
88:Src/main.c **** {
ARM GAS /tmp/cchrMLox.s page 3
89:Src/main.c ****
90:Src/main.c **** /* USER CODE BEGIN 1 */
91:Src/main.c ****
92:Src/main.c **** /* USER CODE END 1 */
93:Src/main.c ****
94:Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
95:Src/main.c ****
96:Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
97:Src/main.c **** HAL_Init();
98:Src/main.c ****
99:Src/main.c **** /* USER CODE BEGIN Init */
100:Src/main.c ****
101:Src/main.c **** /* USER CODE END Init */
102:Src/main.c ****
103:Src/main.c **** /* Configure the system clock */
104:Src/main.c **** SystemClock_Config();
105:Src/main.c ****
106:Src/main.c **** /* USER CODE BEGIN SysInit */
107:Src/main.c ****
108:Src/main.c **** /* USER CODE END SysInit */
109:Src/main.c ****
110:Src/main.c **** /* Initialize all configured peripherals */
111:Src/main.c **** MX_GPIO_Init();
112:Src/main.c **** MX_DMA_Init();
113:Src/main.c **** MX_TIM2_Init();
114:Src/main.c **** MX_I2C1_Init();
115:Src/main.c **** MX_TIM3_Init();
116:Src/main.c **** MX_ADC1_Init();
117:Src/main.c **** MX_ADC2_Init();
118:Src/main.c **** MX_USART1_UART_Init();
119:Src/main.c **** MX_TIM8_Init();
120:Src/main.c **** /* USER CODE BEGIN 2 */
121:Src/main.c ****
122:Src/main.c **** // HAL_Delay(50);
123:Src/main.c **** // HAL_UARTEx_ReceiveToIdle_DMA(&huart1, (uint8_t *)&UART_RX_buf, UART_RX_BUF_SIZE);
124:Src/main.c ****
125:Src/main.c **** // ADC1 audio
126:Src/main.c **** HAL_ADC_Start_IT(&hadc1);
127:Src/main.c ****
128:Src/main.c **** // timer audio e pwm
129:Src/main.c **** HAL_TIM_Base_Start_IT(&htim2);
130:Src/main.c ****
131:Src/main.c **** // timer sys
132:Src/main.c **** HAL_TIM_Base_Start_IT(&htim3);
133:Src/main.c ****
134:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
135:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
136:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
137:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
138:Src/main.c ****
139:Src/main.c **** // timer led
140:Src/main.c **** HAL_TIM_Base_Start_IT(&htim8);
141:Src/main.c **** HAL_TIM_PWM_Start(&htim8, TIM_CHANNEL_3);
142:Src/main.c **** // serve, lo start nonfa partire i CHN
143:Src/main.c **** TIM_CCxChannelCmd(htim8.Instance, TIM_CHANNEL_3, TIM_CCxN_ENABLE);
144:Src/main.c ****
145:Src/main.c **** squeow_init();
ARM GAS /tmp/cchrMLox.s page 4
146:Src/main.c **** squeow_ui_init();
147:Src/main.c ****
148:Src/main.c **** /*
149:Src/main.c **** #ifdef SQUEOW_SYNTH
150:Src/main.c **** squeow_synth_init();
151:Src/main.c **** squeow_synth_set(DEFAULT_SYNTH_FREQUENCY);
152:Src/main.c **** squeow_synth_on();
153:Src/main.c **** #endif
154:Src/main.c **** */
155:Src/main.c ****
156:Src/main.c **** #ifdef SQUEOW_UI_SERIOW
157:Src/main.c **** seriow_stab_dump();
158:Src/main.c **** #endif
159:Src/main.c ****
160:Src/main.c **** // prima lettura
161:Src/main.c **** HAL_ADC_Start_DMA(&hadc2, adc2_valori, 4);
162:Src/main.c ****
163:Src/main.c **** if (UART_TX_buf_lenght)
164:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
165:Src/main.c **** /* USER CODE END 2 */
166:Src/main.c ****
167:Src/main.c **** /* Infinite loop */
168:Src/main.c **** /* USER CODE BEGIN WHILE */
169:Src/main.c **** while (1) {
170:Src/main.c **** /* USER CODE END WHILE */
171:Src/main.c ****
172:Src/main.c **** /* USER CODE BEGIN 3 */
173:Src/main.c **** if (sys_tick) {
174:Src/main.c **** // 100hz
175:Src/main.c **** if (adc2_done) {
176:Src/main.c **** adc_rileva_soglie(adc2_valori);
177:Src/main.c **** HAL_ADC_Start_DMA(&hadc2, adc2_valori, 4);
178:Src/main.c **** adc2_done = 0;
179:Src/main.c **** }
180:Src/main.c ****
181:Src/main.c **** #ifdef SQUEOW_UI_LED
182:Src/main.c **** // visualizza LED volume con valore aggiornato da vu_meter
183:Src/main.c **** led_pwm_duty(ui_volume >> 3);
184:Src/main.c **** processa_blocco();
185:Src/main.c ****
186:Src/main.c **** if (codice_allarme)
187:Src/main.c **** led_blocco(codice_allarme);
188:Src/main.c **** #endif
189:Src/main.c ****
190:Src/main.c **** // eventi lenti
191:Src/main.c **** if (sys_tick_prescale > SYS_TICK_PRESCALE_10HZ) {
192:Src/main.c **** sys_tick_prescale = 0;
193:Src/main.c ****
194:Src/main.c **** #ifdef SQUEOW_UI_TOSTA
195:Src/main.c **** tosta_var_bars();
196:Src/main.c **** #endif
197:Src/main.c **** #ifdef SQUEOW_UI_SERIOW
198:Src/main.c **** seriow_var_dump();
199:Src/main.c **** #endif
200:Src/main.c ****
201:Src/main.c **** if (HAL_GPIO_ReadPin(G1_GPIO_Port, G1_Pin) == GPIO_PIN_RESET) {
202:Src/main.c **** blocco = 0;
ARM GAS /tmp/cchrMLox.s page 5
203:Src/main.c **** }
204:Src/main.c ****
205:Src/main.c **** if (UART_TX_buf_lenght)
206:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
207:Src/main.c **** } else {
208:Src/main.c **** sys_tick_prescale++;
209:Src/main.c **** }
210:Src/main.c **** sys_tick = 0;
211:Src/main.c **** }
212:Src/main.c **** }
213:Src/main.c **** /* USER CODE END 3 */
214:Src/main.c **** }
215:Src/main.c ****
216:Src/main.c **** /**
217:Src/main.c **** * @brief System Clock Configuration
218:Src/main.c **** * @retval None
219:Src/main.c **** */
220:Src/main.c **** void SystemClock_Config(void)
221:Src/main.c **** {
222:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
223:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
224:Src/main.c ****
225:Src/main.c **** /** Configure the main internal regulator output voltage
226:Src/main.c **** */
227:Src/main.c **** HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
228:Src/main.c ****
229:Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
230:Src/main.c **** * in the RCC_OscInitTypeDef structure.
231:Src/main.c **** */
232:Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
233:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
234:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
235:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
236:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
237:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 28;
238:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
239:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
240:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
241:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
242:Src/main.c **** {
243:Src/main.c **** Error_Handler();
244:Src/main.c **** }
245:Src/main.c ****
246:Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
247:Src/main.c **** */
248:Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
249:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
250:Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
251:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
252:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
253:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
254:Src/main.c ****
255:Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
256:Src/main.c **** {
257:Src/main.c **** Error_Handler();
258:Src/main.c **** }
259:Src/main.c **** HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
ARM GAS /tmp/cchrMLox.s page 6
260:Src/main.c **** }
261:Src/main.c ****
262:Src/main.c **** /**
263:Src/main.c **** * @brief ADC1 Initialization Function
264:Src/main.c **** * @param None
265:Src/main.c **** * @retval None
266:Src/main.c **** */
267:Src/main.c **** static void MX_ADC1_Init(void)
268:Src/main.c **** {
269:Src/main.c ****
270:Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */
271:Src/main.c ****
272:Src/main.c **** /* USER CODE END ADC1_Init 0 */
273:Src/main.c ****
274:Src/main.c **** ADC_MultiModeTypeDef multimode = {0};
275:Src/main.c **** ADC_AnalogWDGConfTypeDef AnalogWDGConfig = {0};
276:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
277:Src/main.c ****
278:Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */
279:Src/main.c ****
280:Src/main.c **** /* USER CODE END ADC1_Init 1 */
281:Src/main.c ****
282:Src/main.c **** /** Common config
283:Src/main.c **** */
284:Src/main.c **** hadc1.Instance = ADC1;
285:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
286:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
287:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
288:Src/main.c **** hadc1.Init.GainCompensation = 0;
289:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
290:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
291:Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
292:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
293:Src/main.c **** hadc1.Init.NbrOfConversion = 1;
294:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
295:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
296:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
297:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE;
298:Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
299:Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
300:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
301:Src/main.c **** {
302:Src/main.c **** Error_Handler();
303:Src/main.c **** }
304:Src/main.c ****
305:Src/main.c **** /** Configure the ADC multi-mode
306:Src/main.c **** */
307:Src/main.c **** multimode.Mode = ADC_MODE_INDEPENDENT;
308:Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
309:Src/main.c **** {
310:Src/main.c **** Error_Handler();
311:Src/main.c **** }
312:Src/main.c ****
313:Src/main.c **** /** Configure Analog WatchDog 1
314:Src/main.c **** */
315:Src/main.c **** AnalogWDGConfig.WatchdogNumber = ADC_ANALOGWATCHDOG_1;
316:Src/main.c **** AnalogWDGConfig.WatchdogMode = ADC_ANALOGWATCHDOG_SINGLE_REG;
ARM GAS /tmp/cchrMLox.s page 7
317:Src/main.c **** AnalogWDGConfig.Channel = ADC_CHANNEL_15;
318:Src/main.c **** AnalogWDGConfig.ITMode = ENABLE;
319:Src/main.c **** AnalogWDGConfig.HighThreshold = 4048;
320:Src/main.c **** AnalogWDGConfig.LowThreshold = 48;
321:Src/main.c **** AnalogWDGConfig.FilteringConfig = ADC_AWD_FILTERING_NONE;
322:Src/main.c **** if (HAL_ADC_AnalogWDGConfig(&hadc1, &AnalogWDGConfig) != HAL_OK)
323:Src/main.c **** {
324:Src/main.c **** Error_Handler();
325:Src/main.c **** }
326:Src/main.c ****
327:Src/main.c **** /** Configure Regular Channel
328:Src/main.c **** */
329:Src/main.c **** sConfig.Channel = ADC_CHANNEL_15;
330:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
331:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5;
332:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
333:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
334:Src/main.c **** sConfig.Offset = 0;
335:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
336:Src/main.c **** {
337:Src/main.c **** Error_Handler();
338:Src/main.c **** }
339:Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */
340:Src/main.c ****
341:Src/main.c **** /* USER CODE END ADC1_Init 2 */
342:Src/main.c ****
343:Src/main.c **** }
344:Src/main.c ****
345:Src/main.c **** /**
346:Src/main.c **** * @brief ADC2 Initialization Function
347:Src/main.c **** * @param None
348:Src/main.c **** * @retval None
349:Src/main.c **** */
350:Src/main.c **** static void MX_ADC2_Init(void)
351:Src/main.c **** {
352:Src/main.c ****
353:Src/main.c **** /* USER CODE BEGIN ADC2_Init 0 */
354:Src/main.c ****
355:Src/main.c **** /* USER CODE END ADC2_Init 0 */
356:Src/main.c ****
357:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
358:Src/main.c ****
359:Src/main.c **** /* USER CODE BEGIN ADC2_Init 1 */
360:Src/main.c ****
361:Src/main.c **** /* USER CODE END ADC2_Init 1 */
362:Src/main.c ****
363:Src/main.c **** /** Common config
364:Src/main.c **** */
365:Src/main.c **** hadc2.Instance = ADC2;
366:Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
367:Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_12B;
368:Src/main.c **** hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
369:Src/main.c **** hadc2.Init.GainCompensation = 0;
370:Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
371:Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
372:Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE;
373:Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE;
ARM GAS /tmp/cchrMLox.s page 8
374:Src/main.c **** hadc2.Init.NbrOfConversion = 4;
375:Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE;
376:Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
377:Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
378:Src/main.c **** hadc2.Init.DMAContinuousRequests = DISABLE;
379:Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
380:Src/main.c **** hadc2.Init.OversamplingMode = DISABLE;
381:Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK)
382:Src/main.c **** {
383:Src/main.c **** Error_Handler();
384:Src/main.c **** }
385:Src/main.c ****
386:Src/main.c **** /** Configure Regular Channel
387:Src/main.c **** */
388:Src/main.c **** sConfig.Channel = ADC_CHANNEL_4;
389:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
390:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
391:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
392:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
393:Src/main.c **** sConfig.Offset = 0;
394:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
395:Src/main.c **** {
396:Src/main.c **** Error_Handler();
397:Src/main.c **** }
398:Src/main.c ****
399:Src/main.c **** /** Configure Regular Channel
400:Src/main.c **** */
401:Src/main.c **** sConfig.Channel = ADC_CHANNEL_3;
402:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2;
403:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
404:Src/main.c **** {
405:Src/main.c **** Error_Handler();
406:Src/main.c **** }
407:Src/main.c ****
408:Src/main.c **** /** Configure Regular Channel
409:Src/main.c **** */
410:Src/main.c **** sConfig.Channel = ADC_CHANNEL_13;
411:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3;
412:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
413:Src/main.c **** {
414:Src/main.c **** Error_Handler();
415:Src/main.c **** }
416:Src/main.c ****
417:Src/main.c **** /** Configure Regular Channel
418:Src/main.c **** */
419:Src/main.c **** sConfig.Channel = ADC_CHANNEL_17;
420:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4;
421:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
422:Src/main.c **** {
423:Src/main.c **** Error_Handler();
424:Src/main.c **** }
425:Src/main.c **** /* USER CODE BEGIN ADC2_Init 2 */
426:Src/main.c ****
427:Src/main.c **** /* USER CODE END ADC2_Init 2 */
428:Src/main.c ****
429:Src/main.c **** }
430:Src/main.c ****
ARM GAS /tmp/cchrMLox.s page 9
431:Src/main.c **** /**
432:Src/main.c **** * @brief I2C1 Initialization Function
433:Src/main.c **** * @param None
434:Src/main.c **** * @retval None
435:Src/main.c **** */
436:Src/main.c **** static void MX_I2C1_Init(void)
437:Src/main.c **** {
438:Src/main.c ****
439:Src/main.c **** /* USER CODE BEGIN I2C1_Init 0 */
440:Src/main.c ****
441:Src/main.c **** /* USER CODE END I2C1_Init 0 */
442:Src/main.c ****
443:Src/main.c **** /* USER CODE BEGIN I2C1_Init 1 */
444:Src/main.c ****
445:Src/main.c **** /* USER CODE END I2C1_Init 1 */
446:Src/main.c **** hi2c1.Instance = I2C1;
447:Src/main.c **** hi2c1.Init.Timing = 0x50916E9F;
448:Src/main.c **** hi2c1.Init.OwnAddress1 = 0;
449:Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
450:Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
451:Src/main.c **** hi2c1.Init.OwnAddress2 = 0;
452:Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
453:Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
454:Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
455:Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK)
456:Src/main.c **** {
457:Src/main.c **** Error_Handler();
458:Src/main.c **** }
459:Src/main.c ****
460:Src/main.c **** /** Configure Analogue filter
461:Src/main.c **** */
462:Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
463:Src/main.c **** {
464:Src/main.c **** Error_Handler();
465:Src/main.c **** }
466:Src/main.c ****
467:Src/main.c **** /** Configure Digital filter
468:Src/main.c **** */
469:Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
470:Src/main.c **** {
471:Src/main.c **** Error_Handler();
472:Src/main.c **** }
473:Src/main.c **** /* USER CODE BEGIN I2C1_Init 2 */
474:Src/main.c ****
475:Src/main.c **** /* USER CODE END I2C1_Init 2 */
476:Src/main.c ****
477:Src/main.c **** }
478:Src/main.c ****
479:Src/main.c **** /**
480:Src/main.c **** * @brief TIM2 Initialization Function
481:Src/main.c **** * @param None
482:Src/main.c **** * @retval None
483:Src/main.c **** */
484:Src/main.c **** static void MX_TIM2_Init(void)
485:Src/main.c **** {
486:Src/main.c ****
487:Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */
ARM GAS /tmp/cchrMLox.s page 10
488:Src/main.c ****
489:Src/main.c **** /* USER CODE END TIM2_Init 0 */
490:Src/main.c ****
491:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0};
492:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
493:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
494:Src/main.c ****
495:Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */
496:Src/main.c ****
497:Src/main.c **** /* USER CODE END TIM2_Init 1 */
498:Src/main.c **** htim2.Instance = TIM2;
499:Src/main.c **** htim2.Init.Prescaler = 0;
500:Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
501:Src/main.c **** htim2.Init.Period = 4095;
502:Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
503:Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
504:Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
505:Src/main.c **** {
506:Src/main.c **** Error_Handler();
507:Src/main.c **** }
508:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
509:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
510:Src/main.c **** {
511:Src/main.c **** Error_Handler();
512:Src/main.c **** }
513:Src/main.c **** if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
514:Src/main.c **** {
515:Src/main.c **** Error_Handler();
516:Src/main.c **** }
517:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
518:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
519:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
520:Src/main.c **** {
521:Src/main.c **** Error_Handler();
522:Src/main.c **** }
523:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1;
524:Src/main.c **** sConfigOC.Pulse = 500;
525:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
526:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
527:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
528:Src/main.c **** {
529:Src/main.c **** Error_Handler();
530:Src/main.c **** }
531:Src/main.c **** sConfigOC.Pulse = 1000;
532:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
533:Src/main.c **** {
534:Src/main.c **** Error_Handler();
535:Src/main.c **** }
536:Src/main.c **** sConfigOC.Pulse = 1500;
537:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
538:Src/main.c **** {
539:Src/main.c **** Error_Handler();
540:Src/main.c **** }
541:Src/main.c **** sConfigOC.Pulse = 2000;
542:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
543:Src/main.c **** {
544:Src/main.c **** Error_Handler();
ARM GAS /tmp/cchrMLox.s page 11
545:Src/main.c **** }
546:Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */
547:Src/main.c ****
548:Src/main.c **** /* USER CODE END TIM2_Init 2 */
549:Src/main.c **** HAL_TIM_MspPostInit(&htim2);
550:Src/main.c ****
551:Src/main.c **** }
552:Src/main.c ****
553:Src/main.c **** /**
554:Src/main.c **** * @brief TIM3 Initialization Function
555:Src/main.c **** * @param None
556:Src/main.c **** * @retval None
557:Src/main.c **** */
558:Src/main.c **** static void MX_TIM3_Init(void)
559:Src/main.c **** {
560:Src/main.c ****
561:Src/main.c **** /* USER CODE BEGIN TIM3_Init 0 */
562:Src/main.c ****
563:Src/main.c **** /* USER CODE END TIM3_Init 0 */
564:Src/main.c ****
565:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0};
566:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
567:Src/main.c ****
568:Src/main.c **** /* USER CODE BEGIN TIM3_Init 1 */
569:Src/main.c ****
570:Src/main.c **** /* USER CODE END TIM3_Init 1 */
571:Src/main.c **** htim3.Instance = TIM3;
572:Src/main.c **** htim3.Init.Prescaler = 16799;
573:Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
574:Src/main.c **** htim3.Init.Period = 99;
575:Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
576:Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
577:Src/main.c **** if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
578:Src/main.c **** {
579:Src/main.c **** Error_Handler();
580:Src/main.c **** }
581:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
582:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
583:Src/main.c **** {
584:Src/main.c **** Error_Handler();
585:Src/main.c **** }
586:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
587:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
588:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
589:Src/main.c **** {
590:Src/main.c **** Error_Handler();
591:Src/main.c **** }
592:Src/main.c **** /* USER CODE BEGIN TIM3_Init 2 */
593:Src/main.c ****
594:Src/main.c **** /* USER CODE END TIM3_Init 2 */
595:Src/main.c ****
596:Src/main.c **** }
597:Src/main.c ****
598:Src/main.c **** /**
599:Src/main.c **** * @brief TIM8 Initialization Function
600:Src/main.c **** * @param None
601:Src/main.c **** * @retval None
ARM GAS /tmp/cchrMLox.s page 12
602:Src/main.c **** */
603:Src/main.c **** static void MX_TIM8_Init(void)
604:Src/main.c **** {
605:Src/main.c ****
606:Src/main.c **** /* USER CODE BEGIN TIM8_Init 0 */
607:Src/main.c ****
608:Src/main.c **** /* USER CODE END TIM8_Init 0 */
609:Src/main.c ****
610:Src/main.c **** TIM_ClockConfigTypeDef sClockSourceConfig = {0};
611:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
612:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
613:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
614:Src/main.c ****
615:Src/main.c **** /* USER CODE BEGIN TIM8_Init 1 */
616:Src/main.c ****
617:Src/main.c **** /* USER CODE END TIM8_Init 1 */
618:Src/main.c **** htim8.Instance = TIM8;
619:Src/main.c **** htim8.Init.Prescaler = 1679;
620:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
621:Src/main.c **** htim8.Init.Period = 255;
622:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
623:Src/main.c **** htim8.Init.RepetitionCounter = 0;
624:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
625:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
626:Src/main.c **** {
627:Src/main.c **** Error_Handler();
628:Src/main.c **** }
629:Src/main.c **** sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
630:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
631:Src/main.c **** {
632:Src/main.c **** Error_Handler();
633:Src/main.c **** }
634:Src/main.c **** if (HAL_TIM_PWM_Init(&htim8) != HAL_OK)
635:Src/main.c **** {
636:Src/main.c **** Error_Handler();
637:Src/main.c **** }
638:Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
639:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
640:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
641:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
642:Src/main.c **** {
643:Src/main.c **** Error_Handler();
644:Src/main.c **** }
645:Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1;
646:Src/main.c **** sConfigOC.Pulse = 0;
647:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
648:Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
649:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
650:Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
651:Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
652:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
653:Src/main.c **** {
654:Src/main.c **** Error_Handler();
655:Src/main.c **** }
656:Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
657:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
658:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
ARM GAS /tmp/cchrMLox.s page 13
659:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
660:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
661:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
662:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
663:Src/main.c **** sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
664:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
665:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
666:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
667:Src/main.c **** sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
668:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
669:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
670:Src/main.c **** {
671:Src/main.c **** Error_Handler();
672:Src/main.c **** }
673:Src/main.c **** /* USER CODE BEGIN TIM8_Init 2 */
674:Src/main.c **** htim8.Instance->BDTR |= 0x8000;
675:Src/main.c **** /* USER CODE END TIM8_Init 2 */
676:Src/main.c **** HAL_TIM_MspPostInit(&htim8);
677:Src/main.c ****
678:Src/main.c **** }
679:Src/main.c ****
680:Src/main.c **** /**
681:Src/main.c **** * @brief USART1 Initialization Function
682:Src/main.c **** * @param None
683:Src/main.c **** * @retval None
684:Src/main.c **** */
685:Src/main.c **** static void MX_USART1_UART_Init(void)
686:Src/main.c **** {
687:Src/main.c ****
688:Src/main.c **** /* USER CODE BEGIN USART1_Init 0 */
689:Src/main.c ****
690:Src/main.c **** /* USER CODE END USART1_Init 0 */
691:Src/main.c ****
692:Src/main.c **** /* USER CODE BEGIN USART1_Init 1 */
693:Src/main.c ****
694:Src/main.c **** /* USER CODE END USART1_Init 1 */
695:Src/main.c **** huart1.Instance = USART1;
696:Src/main.c **** huart1.Init.BaudRate = 38400;
697:Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
698:Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1;
699:Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE;
700:Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX;
701:Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
702:Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16;
703:Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
704:Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
705:Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
706:Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
707:Src/main.c **** {
708:Src/main.c **** Error_Handler();
709:Src/main.c **** }
710:Src/main.c **** if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
711:Src/main.c **** {
712:Src/main.c **** Error_Handler();
713:Src/main.c **** }
714:Src/main.c **** if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
715:Src/main.c **** {
ARM GAS /tmp/cchrMLox.s page 14
716:Src/main.c **** Error_Handler();
717:Src/main.c **** }
718:Src/main.c **** if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
719:Src/main.c **** {
720:Src/main.c **** Error_Handler();
721:Src/main.c **** }
722:Src/main.c **** /* USER CODE BEGIN USART1_Init 2 */
723:Src/main.c ****
724:Src/main.c **** /* USER CODE END USART1_Init 2 */
725:Src/main.c ****
726:Src/main.c **** }
727:Src/main.c ****
728:Src/main.c **** /**
729:Src/main.c **** * Enable DMA controller clock
730:Src/main.c **** */
731:Src/main.c **** static void MX_DMA_Init(void)
732:Src/main.c **** {
733:Src/main.c ****
734:Src/main.c **** /* DMA controller clock enable */
735:Src/main.c **** __HAL_RCC_DMAMUX1_CLK_ENABLE();
736:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
737:Src/main.c ****
738:Src/main.c **** /* DMA interrupt init */
739:Src/main.c **** /* DMA1_Channel2_IRQn interrupt configuration */
740:Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);
741:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
742:Src/main.c **** /* DMA1_Channel3_IRQn interrupt configuration */
743:Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);
744:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
745:Src/main.c **** /* DMA1_Channel4_IRQn interrupt configuration */
746:Src/main.c **** HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 0, 0);
747:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
748:Src/main.c ****
749:Src/main.c **** }
750:Src/main.c ****
751:Src/main.c **** /**
752:Src/main.c **** * @brief GPIO Initialization Function
753:Src/main.c **** * @param None
754:Src/main.c **** * @retval None
755:Src/main.c **** */
756:Src/main.c **** static void MX_GPIO_Init(void)
757:Src/main.c **** {
28 .loc 1 757 1 view -0
29 .cfi_startproc
30 @ args = 0, pretend = 0, frame = 32
31 @ frame_needed = 0, uses_anonymous_args = 0
32 0000 F0B5 push {r4, r5, r6, r7, lr}
33 .LCFI0:
34 .cfi_def_cfa_offset 20
35 .cfi_offset 4, -20
36 .cfi_offset 5, -16
37 .cfi_offset 6, -12
38 .cfi_offset 7, -8
39 .cfi_offset 14, -4
40 0002 89B0 sub sp, sp, #36
41 .LCFI1:
42 .cfi_def_cfa_offset 56
ARM GAS /tmp/cchrMLox.s page 15
758:Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
43 .loc 1 758 3 view .LVU1
44 .loc 1 758 20 is_stmt 0 view .LVU2
45 0004 03AD add r5, sp, #12
46 0006 0024 movs r4, #0
47 0008 0394 str r4, [sp, #12]
48 000a 0494 str r4, [sp, #16]
49 000c 0594 str r4, [sp, #20]
50 000e 0694 str r4, [sp, #24]
51 0010 0794 str r4, [sp, #28]
759:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
760:Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */
761:Src/main.c ****
762:Src/main.c **** /* GPIO Ports Clock Enable */
763:Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE();
52 .loc 1 763 3 is_stmt 1 view .LVU3
53 .LBB4:
54 .loc 1 763 3 view .LVU4
55 .loc 1 763 3 view .LVU5
56 0012 214B ldr r3, .L3
57 0014 DA6C ldr r2, [r3, #76]
58 0016 42F02002 orr r2, r2, #32
59 001a DA64 str r2, [r3, #76]
60 .loc 1 763 3 view .LVU6
61 001c DA6C ldr r2, [r3, #76]
62 001e 02F02002 and r2, r2, #32
63 0022 0092 str r2, [sp]
64 .loc 1 763 3 view .LVU7
65 0024 009A ldr r2, [sp]
66 .LBE4:
67 .loc 1 763 3 view .LVU8
764:Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
68 .loc 1 764 3 view .LVU9
69 .LBB5:
70 .loc 1 764 3 view .LVU10
71 .loc 1 764 3 view .LVU11
72 0026 DA6C ldr r2, [r3, #76]
73 0028 42F00102 orr r2, r2, #1
74 002c DA64 str r2, [r3, #76]
75 .loc 1 764 3 view .LVU12
76 002e DA6C ldr r2, [r3, #76]
77 0030 02F00102 and r2, r2, #1
78 0034 0192 str r2, [sp, #4]
79 .loc 1 764 3 view .LVU13
80 0036 019A ldr r2, [sp, #4]
81 .LBE5:
82 .loc 1 764 3 view .LVU14
765:Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
83 .loc 1 765 3 view .LVU15
84 .LBB6:
85 .loc 1 765 3 view .LVU16
86 .loc 1 765 3 view .LVU17
87 0038 DA6C ldr r2, [r3, #76]
88 003a 42F00202 orr r2, r2, #2
89 003e DA64 str r2, [r3, #76]
90 .loc 1 765 3 view .LVU18
91 0040 DB6C ldr r3, [r3, #76]
ARM GAS /tmp/cchrMLox.s page 16
92 0042 03F00203 and r3, r3, #2
93 0046 0293 str r3, [sp, #8]
94 .loc 1 765 3 view .LVU19
95 0048 029B ldr r3, [sp, #8]
96 .LBE6:
97 .loc 1 765 3 view .LVU20
766:Src/main.c ****
767:Src/main.c **** /*Configure GPIO pin Output Level */
768:Src/main.c **** HAL_GPIO_WritePin(GPIOB, G2_Pin|G4_Pin, GPIO_PIN_RESET);
98 .loc 1 768 3 view .LVU21
99 004a 144E ldr r6, .L3+4
100 004c 2246 mov r2, r4
101 004e 5021 movs r1, #80
102 0050 3046 mov r0, r6
103 0052 FFF7FEFF bl HAL_GPIO_WritePin
104 .LVL0:
769:Src/main.c ****
770:Src/main.c **** /*Configure GPIO pin : PA8 */
771:Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_8;
105 .loc 1 771 3 view .LVU22
106 .loc 1 771 23 is_stmt 0 view .LVU23
107 0056 4FF48073 mov r3, #256
108 005a 0393 str r3, [sp, #12]
772:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
109 .loc 1 772 3 is_stmt 1 view .LVU24
110 .loc 1 772 24 is_stmt 0 view .LVU25
111 005c 0223 movs r3, #2
112 005e 0493 str r3, [sp, #16]
773:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
113 .loc 1 773 3 is_stmt 1 view .LVU26
114 .loc 1 773 24 is_stmt 0 view .LVU27
115 0060 0594 str r4, [sp, #20]
774:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
116 .loc 1 774 3 is_stmt 1 view .LVU28
117 .loc 1 774 25 is_stmt 0 view .LVU29
118 0062 0694 str r4, [sp, #24]
775:Src/main.c **** GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
119 .loc 1 775 3 is_stmt 1 view .LVU30
120 .loc 1 775 29 is_stmt 0 view .LVU31
121 0064 0794 str r4, [sp, #28]
776:Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
122 .loc 1 776 3 is_stmt 1 view .LVU32
123 0066 2946 mov r1, r5
124 0068 4FF09040 mov r0, #1207959552
125 006c FFF7FEFF bl HAL_GPIO_Init
126 .LVL1:
777:Src/main.c ****
778:Src/main.c **** /*Configure GPIO pin : G1_Pin */
779:Src/main.c **** GPIO_InitStruct.Pin = G1_Pin;
127 .loc 1 779 3 view .LVU33
128 .loc 1 779 23 is_stmt 0 view .LVU34
129 0070 0823 movs r3, #8
130 0072 0393 str r3, [sp, #12]
780:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
131 .loc 1 780 3 is_stmt 1 view .LVU35
132 .loc 1 780 24 is_stmt 0 view .LVU36
133 0074 0494 str r4, [sp, #16]
ARM GAS /tmp/cchrMLox.s page 17
781:Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLUP;
134 .loc 1 781 3 is_stmt 1 view .LVU37
135 .loc 1 781 24 is_stmt 0 view .LVU38
136 0076 0127 movs r7, #1
137 0078 0597 str r7, [sp, #20]
782:Src/main.c **** HAL_GPIO_Init(G1_GPIO_Port, &GPIO_InitStruct);
138 .loc 1 782 3 is_stmt 1 view .LVU39
139 007a 2946 mov r1, r5
140 007c 3046 mov r0, r6
141 007e FFF7FEFF bl HAL_GPIO_Init
142 .LVL2:
783:Src/main.c ****
784:Src/main.c **** /*Configure GPIO pins : G2_Pin G4_Pin */
785:Src/main.c **** GPIO_InitStruct.Pin = G2_Pin|G4_Pin;
143 .loc 1 785 3 view .LVU40
144 .loc 1 785 23 is_stmt 0 view .LVU41
145 0082 5023 movs r3, #80
146 0084 0393 str r3, [sp, #12]
786:Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
147 .loc 1 786 3 is_stmt 1 view .LVU42
148 .loc 1 786 24 is_stmt 0 view .LVU43
149 0086 0497 str r7, [sp, #16]
787:Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
150 .loc 1 787 3 is_stmt 1 view .LVU44
151 .loc 1 787 24 is_stmt 0 view .LVU45
152 0088 0594 str r4, [sp, #20]
788:Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
153 .loc 1 788 3 is_stmt 1 view .LVU46
154 .loc 1 788 25 is_stmt 0 view .LVU47
155 008a 0694 str r4, [sp, #24]
789:Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
156 .loc 1 789 3 is_stmt 1 view .LVU48
157 008c 2946 mov r1, r5
158 008e 3046 mov r0, r6
159 0090 FFF7FEFF bl HAL_GPIO_Init
160 .LVL3:
790:Src/main.c ****
791:Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */
792:Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */
793:Src/main.c **** }
161 .loc 1 793 1 is_stmt 0 view .LVU49
162 0094 09B0 add sp, sp, #36
163 .LCFI2:
164 .cfi_def_cfa_offset 20
165 @ sp needed
166 0096 F0BD pop {r4, r5, r6, r7, pc}
167 .L4:
168 .align 2
169 .L3:
170 0098 00100240 .word 1073876992
171 009c 00040048 .word 1207960576
172 .cfi_endproc
173 .LFE342:
175 .section .text.MX_DMA_Init,"ax",%progbits
176 .align 1
177 .syntax unified
178 .thumb
ARM GAS /tmp/cchrMLox.s page 18
179 .thumb_func
181 MX_DMA_Init:
182 .LFB341:
732:Src/main.c ****
183 .loc 1 732 1 is_stmt 1 view -0
184 .cfi_startproc
185 @ args = 0, pretend = 0, frame = 8
186 @ frame_needed = 0, uses_anonymous_args = 0
187 0000 00B5 push {lr}
188 .LCFI3:
189 .cfi_def_cfa_offset 4
190 .cfi_offset 14, -4
191 0002 83B0 sub sp, sp, #12
192 .LCFI4:
193 .cfi_def_cfa_offset 16
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
194 .loc 1 735 3 view .LVU51
195 .LBB7:
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
196 .loc 1 735 3 view .LVU52
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
197 .loc 1 735 3 view .LVU53
198 0004 164B ldr r3, .L7
199 0006 9A6C ldr r2, [r3, #72]
200 0008 42F00402 orr r2, r2, #4
201 000c 9A64 str r2, [r3, #72]
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
202 .loc 1 735 3 view .LVU54
203 000e 9A6C ldr r2, [r3, #72]
204 0010 02F00402 and r2, r2, #4
205 0014 0092 str r2, [sp]
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
206 .loc 1 735 3 view .LVU55
207 0016 009A ldr r2, [sp]
208 .LBE7:
735:Src/main.c **** __HAL_RCC_DMA1_CLK_ENABLE();
209 .loc 1 735 3 view .LVU56
736:Src/main.c ****
210 .loc 1 736 3 view .LVU57
211 .LBB8:
736:Src/main.c ****
212 .loc 1 736 3 view .LVU58
736:Src/main.c ****
213 .loc 1 736 3 view .LVU59
214 0018 9A6C ldr r2, [r3, #72]
215 001a 42F00102 orr r2, r2, #1
216 001e 9A64 str r2, [r3, #72]
736:Src/main.c ****
217 .loc 1 736 3 view .LVU60
218 0020 9B6C ldr r3, [r3, #72]
219 0022 03F00103 and r3, r3, #1
220 0026 0193 str r3, [sp, #4]
736:Src/main.c ****
221 .loc 1 736 3 view .LVU61
222 0028 019B ldr r3, [sp, #4]
223 .LBE8:
736:Src/main.c ****
ARM GAS /tmp/cchrMLox.s page 19
224 .loc 1 736 3 view .LVU62
740:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);
225 .loc 1 740 3 view .LVU63
226 002a 0022 movs r2, #0
227 002c 1146 mov r1, r2
228 002e 0C20 movs r0, #12
229 0030 FFF7FEFF bl HAL_NVIC_SetPriority
230 .LVL4:
741:Src/main.c **** /* DMA1_Channel3_IRQn interrupt configuration */
231 .loc 1 741 3 view .LVU64
232 0034 0C20 movs r0, #12
233 0036 FFF7FEFF bl HAL_NVIC_EnableIRQ
234 .LVL5:
743:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
235 .loc 1 743 3 view .LVU65
236 003a 0022 movs r2, #0
237 003c 1146 mov r1, r2
238 003e 0D20 movs r0, #13
239 0040 FFF7FEFF bl HAL_NVIC_SetPriority
240 .LVL6:
744:Src/main.c **** /* DMA1_Channel4_IRQn interrupt configuration */
241 .loc 1 744 3 view .LVU66
242 0044 0D20 movs r0, #13
243 0046 FFF7FEFF bl HAL_NVIC_EnableIRQ
244 .LVL7:
746:Src/main.c **** HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
245 .loc 1 746 3 view .LVU67
246 004a 0022 movs r2, #0
247 004c 1146 mov r1, r2
248 004e 0E20 movs r0, #14
249 0050 FFF7FEFF bl HAL_NVIC_SetPriority
250 .LVL8:
747:Src/main.c ****
251 .loc 1 747 3 view .LVU68
252 0054 0E20 movs r0, #14
253 0056 FFF7FEFF bl HAL_NVIC_EnableIRQ
254 .LVL9:
749:Src/main.c ****
255 .loc 1 749 1 is_stmt 0 view .LVU69
256 005a 03B0 add sp, sp, #12
257 .LCFI5:
258 .cfi_def_cfa_offset 4
259 @ sp needed
260 005c 5DF804FB ldr pc, [sp], #4
261 .L8:
262 .align 2
263 .L7:
264 0060 00100240 .word 1073876992
265 .cfi_endproc
266 .LFE341:
268 .section .text.HAL_ADC_LevelOutOfWindowCallback,"ax",%progbits
269 .align 1
270 .global HAL_ADC_LevelOutOfWindowCallback
271 .syntax unified
272 .thumb
273 .thumb_func
275 HAL_ADC_LevelOutOfWindowCallback:
ARM GAS /tmp/cchrMLox.s page 20
276 .LVL10:
277 .LFB343:
794:Src/main.c ****
795:Src/main.c **** /* USER CODE BEGIN 4 */
796:Src/main.c **** void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) {
278 .loc 1 796 64 is_stmt 1 view -0
279 .cfi_startproc
280 @ args = 0, pretend = 0, frame = 0
281 @ frame_needed = 0, uses_anonymous_args = 0
282 @ link register save eliminated.
797:Src/main.c **** // analog_wd_status = 3;
798:Src/main.c **** }
283 .loc 1 798 1 view .LVU71
284 0000 7047 bx lr
285 .cfi_endproc
286 .LFE343:
288 .section .text.HAL_ADC_ConvCpltCallback,"ax",%progbits
289 .align 1
290 .global HAL_ADC_ConvCpltCallback
291 .syntax unified
292 .thumb
293 .thumb_func
295 HAL_ADC_ConvCpltCallback:
296 .LVL11:
297 .LFB344:
799:Src/main.c ****
800:Src/main.c **** void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { adc2_done = 1; }
298 .loc 1 800 56 view -0
299 .cfi_startproc
300 @ args = 0, pretend = 0, frame = 0
301 @ frame_needed = 0, uses_anonymous_args = 0
302 @ link register save eliminated.
303 .loc 1 800 58 view .LVU73
304 .loc 1 800 68 is_stmt 0 view .LVU74
305 0000 014B ldr r3, .L11
306 0002 0122 movs r2, #1
307 0004 1A70 strb r2, [r3]
308 .loc 1 800 73 view .LVU75
309 0006 7047 bx lr
310 .L12:
311 .align 2
312 .L11:
313 0008 00000000 .word adc2_done
314 .cfi_endproc
315 .LFE344:
317 .section .text.HAL_UARTEx_RxEventCallback,"ax",%progbits
318 .align 1
319 .global HAL_UARTEx_RxEventCallback
320 .syntax unified
321 .thumb
322 .thumb_func
324 HAL_UARTEx_RxEventCallback:
325 .LVL12:
326 .LFB345:
801:Src/main.c ****
802:Src/main.c **** void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t offset) {
327 .loc 1 802 77 is_stmt 1 view -0
ARM GAS /tmp/cchrMLox.s page 21
328 .cfi_startproc
329 @ args = 0, pretend = 0, frame = 0
330 @ frame_needed = 0, uses_anonymous_args = 0
331 @ link register save eliminated.
803:Src/main.c **** static uint16_t last_offset = 0;
332 .loc 1 803 5 view .LVU77
804:Src/main.c **** // Ignore if called twice (which will happen on every half buffer)
805:Src/main.c **** if (offset != last_offset) {
333 .loc 1 805 5 view .LVU78
334 .loc 1 805 16 is_stmt 0 view .LVU79
335 0000 084B ldr r3, .L18
336 0002 1B88 ldrh r3, [r3]
337 .loc 1 805 8 view .LVU80
338 0004 8B42 cmp r3, r1
339 0006 0BD0 beq .L13
806:Src/main.c **** // If wrap around reset last_size
807:Src/main.c **** if (offset < last_offset)
340 .loc 1 807 9 is_stmt 1 view .LVU81
341 .loc 1 807 12 is_stmt 0 view .LVU82
342 0008 06D9 bls .L16
808:Src/main.c **** last_offset = 0;
343 .loc 1 808 13 is_stmt 1 view .LVU83
344 .loc 1 808 25 is_stmt 0 view .LVU84
345 000a 064B ldr r3, .L18
346 000c 0022 movs r2, #0
347 000e 1A80 strh r2, [r3] @ movhi
348 0010 02E0 b .L16
349 .L17:
809:Src/main.c **** while (last_offset < offset) {
810:Src/main.c **** // process_character((char) dmabuf[last_offset]);
811:Src/main.c **** // TODO
812:Src/main.c **** // store_cmd(UART_RX_buf[last_offset]);
813:Src/main.c **** ++last_offset;
350 .loc 1 813 13 is_stmt 1 view .LVU85
351 0012 0133 adds r3, r3, #1
352 0014 034A ldr r2, .L18
353 0016 1380 strh r3, [r2] @ movhi
354 .L16:
809:Src/main.c **** while (last_offset < offset) {
355 .loc 1 809 28 view .LVU86
356 0018 024B ldr r3, .L18
357 001a 1B88 ldrh r3, [r3]
358 001c 8B42 cmp r3, r1
359 001e F8D3 bcc .L17
360 .L13:
814:Src/main.c **** }
815:Src/main.c **** }
816:Src/main.c **** }
361 .loc 1 816 1 is_stmt 0 view .LVU87
362 0020 7047 bx lr
363 .L19:
364 0022 00BF .align 2
365 .L18:
366 0024 00000000 .word last_offset.0
367 .cfi_endproc
368 .LFE345:
370 .section .text.HAL_UART_TxCpltCallback,"ax",%progbits
ARM GAS /tmp/cchrMLox.s page 22
371 .align 1
372 .global HAL_UART_TxCpltCallback
373 .syntax unified
374 .thumb
375 .thumb_func
377 HAL_UART_TxCpltCallback:
378 .LVL13:
379 .LFB346:
817:Src/main.c ****
818:Src/main.c **** void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { uart_sent = 1; }
380 .loc 1 818 57 is_stmt 1 view -0
381 .cfi_startproc
382 @ args = 0, pretend = 0, frame = 0
383 @ frame_needed = 0, uses_anonymous_args = 0
384 @ link register save eliminated.
385 .loc 1 818 59 view .LVU89
386 .loc 1 818 69 is_stmt 0 view .LVU90
387 0000 014B ldr r3, .L21
388 0002 0122 movs r2, #1
389 0004 1A70 strb r2, [r3]
390 .loc 1 818 74 view .LVU91
391 0006 7047 bx lr
392 .L22:
393 .align 2
394 .L21:
395 0008 00000000 .word uart_sent
396 .cfi_endproc
397 .LFE346:
399 .section .text.HAL_UART_TxHalfCpltCallback,"ax",%progbits
400 .align 1
401 .global HAL_UART_TxHalfCpltCallback
402 .syntax unified
403 .thumb
404 .thumb_func
406 HAL_UART_TxHalfCpltCallback:
407 .LVL14:
408 .LFB347:
819:Src/main.c ****
820:Src/main.c **** void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) { uart_sent = 1; }
409 .loc 1 820 61 is_stmt 1 view -0
410 .cfi_startproc
411 @ args = 0, pretend = 0, frame = 0
412 @ frame_needed = 0, uses_anonymous_args = 0
413 @ link register save eliminated.
414 .loc 1 820 63 view .LVU93
415 .loc 1 820 73 is_stmt 0 view .LVU94
416 0000 014B ldr r3, .L24
417 0002 0122 movs r2, #1
418 0004 1A70 strb r2, [r3]
419 .loc 1 820 78 view .LVU95
420 0006 7047 bx lr
421 .L25:
422 .align 2
423 .L24:
424 0008 00000000 .word uart_sent
425 .cfi_endproc
426 .LFE347:
ARM GAS /tmp/cchrMLox.s page 23
428 .section .text.UART_DMATransmitCplt,"ax",%progbits
429 .align 1
430 .global UART_DMATransmitCplt
431 .syntax unified
432 .thumb
433 .thumb_func
435 UART_DMATransmitCplt:
436 .LVL15:
437 .LFB348:
821:Src/main.c ****
822:Src/main.c **** void UART_DMATransmitCplt(UART_HandleTypeDef *huart) { uart_sent = 1; }
438 .loc 1 822 54 is_stmt 1 view -0
439 .cfi_startproc
440 @ args = 0, pretend = 0, frame = 0
441 @ frame_needed = 0, uses_anonymous_args = 0
442 @ link register save eliminated.
443 .loc 1 822 56 view .LVU97
444 .loc 1 822 66 is_stmt 0 view .LVU98
445 0000 014B ldr r3, .L27
446 0002 0122 movs r2, #1
447 0004 1A70 strb r2, [r3]
448 .loc 1 822 71 view .LVU99
449 0006 7047 bx lr
450 .L28:
451 .align 2
452 .L27:
453 0008 00000000 .word uart_sent
454 .cfi_endproc
455 .LFE348:
457 .section .text.Error_Handler,"ax",%progbits
458 .align 1
459 .global Error_Handler
460 .syntax unified
461 .thumb
462 .thumb_func
464 Error_Handler:
465 .LFB349:
823:Src/main.c ****
824:Src/main.c **** /* USER CODE END 4 */
825:Src/main.c ****
826:Src/main.c **** /**
827:Src/main.c **** * @brief This function is executed in case of error occurrence.
828:Src/main.c **** * @retval None
829:Src/main.c **** */
830:Src/main.c **** void Error_Handler(void)
831:Src/main.c **** {
466 .loc 1 831 1 is_stmt 1 view -0
467 .cfi_startproc
468 @ Volatile: function does not return.
469 @ args = 0, pretend = 0, frame = 0
470 @ frame_needed = 0, uses_anonymous_args = 0
471 @ link register save eliminated.
832:Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
833:Src/main.c **** /* User can add his own implementation to report the HAL error return state */
834:Src/main.c **** __disable_irq();
472 .loc 1 834 5 view .LVU101
473 .LBB9:
ARM GAS /tmp/cchrMLox.s page 24
474 .LBI9:
475 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
ARM GAS /tmp/cchrMLox.s page 25
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS /tmp/cchrMLox.s page 26
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER
117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
119:Drivers/CMSIS/Include/cmsis_gcc.h ****
120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */
121:Drivers/CMSIS/Include/cmsis_gcc.h ****
122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss
127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly
128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script.
129:Drivers/CMSIS/Include/cmsis_gcc.h ****
130:Drivers/CMSIS/Include/cmsis_gcc.h **** */
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN;
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src;
137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t;
140:Drivers/CMSIS/Include/cmsis_gcc.h ****
141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct {
142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest;
143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen;
144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t;
145:Drivers/CMSIS/Include/cmsis_gcc.h ****
146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__;
147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__;
148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__;
149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__;
150:Drivers/CMSIS/Include/cmsis_gcc.h ****
151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i];
154:Drivers/CMSIS/Include/cmsis_gcc.h **** }
155:Drivers/CMSIS/Include/cmsis_gcc.h **** }
156:Drivers/CMSIS/Include/cmsis_gcc.h ****
157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; i<pTable->wlen; ++i) {
159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u;
160:Drivers/CMSIS/Include/cmsis_gcc.h **** }
161:Drivers/CMSIS/Include/cmsis_gcc.h **** }
162:Drivers/CMSIS/Include/cmsis_gcc.h ****
163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start();
164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
165:Drivers/CMSIS/Include/cmsis_gcc.h ****
166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start
167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
168:Drivers/CMSIS/Include/cmsis_gcc.h ****
169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
ARM GAS /tmp/cchrMLox.s page 27
170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop
171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
172:Drivers/CMSIS/Include/cmsis_gcc.h ****
173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit
175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
176:Drivers/CMSIS/Include/cmsis_gcc.h ****
177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors
179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
180:Drivers/CMSIS/Include/cmsis_gcc.h ****
181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors")))
183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
184:Drivers/CMSIS/Include/cmsis_gcc.h ****
185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
189:Drivers/CMSIS/Include/cmsis_gcc.h **** */
190:Drivers/CMSIS/Include/cmsis_gcc.h ****
191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
195:Drivers/CMSIS/Include/cmsis_gcc.h **** */
196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
200:Drivers/CMSIS/Include/cmsis_gcc.h ****
201:Drivers/CMSIS/Include/cmsis_gcc.h ****
202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
206:Drivers/CMSIS/Include/cmsis_gcc.h **** */
207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
476 .loc 2 207 27 view .LVU102
477 .LBB10:
208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
478 .loc 2 209 3 view .LVU103
479 .syntax unified
480 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
481 0000 72B6 cpsid i
482 @ 0 "" 2
483 .thumb
484 .syntax unified
485 .L30:
486 .LBE10:
487 .LBE9:
835:Src/main.c **** while (1) {
488 .loc 1 835 5 view .LVU104
836:Src/main.c **** }
489 .loc 1 836 5 view .LVU105
835:Src/main.c **** while (1) {
ARM GAS /tmp/cchrMLox.s page 28
490 .loc 1 835 11 view .LVU106
491 0002 FEE7 b .L30
492 .cfi_endproc
493 .LFE349:
495 .section .text.MX_TIM2_Init,"ax",%progbits
496 .align 1
497 .syntax unified
498 .thumb
499 .thumb_func
501 MX_TIM2_Init:
502 .LFB337:
485:Src/main.c ****
503 .loc 1 485 1 view -0
504 .cfi_startproc
505 @ args = 0, pretend = 0, frame = 56
506 @ frame_needed = 0, uses_anonymous_args = 0
507 0000 00B5 push {lr}
508 .LCFI6:
509 .cfi_def_cfa_offset 4
510 .cfi_offset 14, -4
511 0002 8FB0 sub sp, sp, #60
512 .LCFI7:
513 .cfi_def_cfa_offset 64
491:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
514 .loc 1 491 3 view .LVU108
491:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
515 .loc 1 491 26 is_stmt 0 view .LVU109
516 0004 0023 movs r3, #0
517 0006 0A93 str r3, [sp, #40]
518 0008 0B93 str r3, [sp, #44]
519 000a 0C93 str r3, [sp, #48]
520 000c 0D93 str r3, [sp, #52]
492:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
521 .loc 1 492 3 is_stmt 1 view .LVU110
492:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
522 .loc 1 492 27 is_stmt 0 view .LVU111
523 000e 0793 str r3, [sp, #28]
524 0010 0893 str r3, [sp, #32]
525 0012 0993 str r3, [sp, #36]
493:Src/main.c ****
526 .loc 1 493 3 is_stmt 1 view .LVU112
493:Src/main.c ****
527 .loc 1 493 22 is_stmt 0 view .LVU113
528 0014 0093 str r3, [sp]
529 0016 0193 str r3, [sp, #4]
530 0018 0293 str r3, [sp, #8]
531 001a 0393 str r3, [sp, #12]
532 001c 0493 str r3, [sp, #16]
533 001e 0593 str r3, [sp, #20]
534 0020 0693 str r3, [sp, #24]
498:Src/main.c **** htim2.Init.Prescaler = 0;
535 .loc 1 498 3 is_stmt 1 view .LVU114
498:Src/main.c **** htim2.Init.Prescaler = 0;
536 .loc 1 498 18 is_stmt 0 view .LVU115
537 0022 3348 ldr r0, .L49
538 0024 4FF08042 mov r2, #1073741824
539 0028 0260 str r2, [r0]
ARM GAS /tmp/cchrMLox.s page 29
499:Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
540 .loc 1 499 3 is_stmt 1 view .LVU116
499:Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
541 .loc 1 499 24 is_stmt 0 view .LVU117
542 002a 4360 str r3, [r0, #4]
500:Src/main.c **** htim2.Init.Period = 4095;
543 .loc 1 500 3 is_stmt 1 view .LVU118
500:Src/main.c **** htim2.Init.Period = 4095;
544 .loc 1 500 26 is_stmt 0 view .LVU119
545 002c 8360 str r3, [r0, #8]
501:Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
546 .loc 1 501 3 is_stmt 1 view .LVU120
501:Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
547 .loc 1 501 21 is_stmt 0 view .LVU121
548 002e 40F6FF72 movw r2, #4095
549 0032 C260 str r2, [r0, #12]
502:Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
550 .loc 1 502 3 is_stmt 1 view .LVU122
502:Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
551 .loc 1 502 28 is_stmt 0 view .LVU123
552 0034 0361 str r3, [r0, #16]
503:Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
553 .loc 1 503 3 is_stmt 1 view .LVU124
503:Src/main.c **** if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
554 .loc 1 503 32 is_stmt 0 view .LVU125
555 0036 8361 str r3, [r0, #24]
504:Src/main.c **** {
556 .loc 1 504 3 is_stmt 1 view .LVU126
504:Src/main.c **** {
557 .loc 1 504 7 is_stmt 0 view .LVU127
558 0038 FFF7FEFF bl HAL_TIM_Base_Init
559 .LVL16:
504:Src/main.c **** {
560 .loc 1 504 6 discriminator 1 view .LVU128
561 003c 0028 cmp r0, #0
562 003e 46D1 bne .L41
508:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
563 .loc 1 508 3 is_stmt 1 view .LVU129
508:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
564 .loc 1 508 34 is_stmt 0 view .LVU130
565 0040 4FF48053 mov r3, #4096
566 0044 0A93 str r3, [sp, #40]
509:Src/main.c **** {
567 .loc 1 509 3 is_stmt 1 view .LVU131
509:Src/main.c **** {
568 .loc 1 509 7 is_stmt 0 view .LVU132
569 0046 0AA9 add r1, sp, #40
570 0048 2948 ldr r0, .L49
571 004a FFF7FEFF bl HAL_TIM_ConfigClockSource
572 .LVL17:
509:Src/main.c **** {
573 .loc 1 509 6 discriminator 1 view .LVU133
574 004e 0028 cmp r0, #0
575 0050 3FD1 bne .L42
513:Src/main.c **** {
576 .loc 1 513 3 is_stmt 1 view .LVU134
513:Src/main.c **** {
ARM GAS /tmp/cchrMLox.s page 30
577 .loc 1 513 7 is_stmt 0 view .LVU135
578 0052 2748 ldr r0, .L49
579 0054 FFF7FEFF bl HAL_TIM_PWM_Init
580 .LVL18:
513:Src/main.c **** {
581 .loc 1 513 6 discriminator 1 view .LVU136
582 0058 0028 cmp r0, #0
583 005a 3CD1 bne .L43
517:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
584 .loc 1 517 3 is_stmt 1 view .LVU137
517:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
585 .loc 1 517 37 is_stmt 0 view .LVU138
586 005c 2023 movs r3, #32
587 005e 0793 str r3, [sp, #28]
518:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
588 .loc 1 518 3 is_stmt 1 view .LVU139
518:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
589 .loc 1 518 33 is_stmt 0 view .LVU140
590 0060 0023 movs r3, #0
591 0062 0993 str r3, [sp, #36]
519:Src/main.c **** {
592 .loc 1 519 3 is_stmt 1 view .LVU141
519:Src/main.c **** {
593 .loc 1 519 7 is_stmt 0 view .LVU142
594 0064 07A9 add r1, sp, #28
595 0066 2248 ldr r0, .L49
596 0068 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
597 .LVL19:
519:Src/main.c **** {
598 .loc 1 519 6 discriminator 1 view .LVU143
599 006c 0028 cmp r0, #0
600 006e 34D1 bne .L44
523:Src/main.c **** sConfigOC.Pulse = 500;
601 .loc 1 523 3 is_stmt 1 view .LVU144
523:Src/main.c **** sConfigOC.Pulse = 500;
602 .loc 1 523 20 is_stmt 0 view .LVU145
603 0070 6023 movs r3, #96
604 0072 0093 str r3, [sp]
524:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
605 .loc 1 524 3 is_stmt 1 view .LVU146
524:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
606 .loc 1 524 19 is_stmt 0 view .LVU147
607 0074 4FF4FA73 mov r3, #500
608 0078 0193 str r3, [sp, #4]
525:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
609 .loc 1 525 3 is_stmt 1 view .LVU148
525:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
610 .loc 1 525 24 is_stmt 0 view .LVU149
611 007a 0022 movs r2, #0
612 007c 0292 str r2, [sp, #8]
526:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
613 .loc 1 526 3 is_stmt 1 view .LVU150
526:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
614 .loc 1 526 24 is_stmt 0 view .LVU151
615 007e 0423 movs r3, #4
616 0080 0493 str r3, [sp, #16]
527:Src/main.c **** {
ARM GAS /tmp/cchrMLox.s page 31
617 .loc 1 527 3 is_stmt 1 view .LVU152
527:Src/main.c **** {
618 .loc 1 527 7 is_stmt 0 view .LVU153
619 0082 6946 mov r1, sp
620 0084 1A48 ldr r0, .L49
621 0086 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
622 .LVL20:
527:Src/main.c **** {
623 .loc 1 527 6 discriminator 1 view .LVU154
624 008a 40BB cbnz r0, .L45
531:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
625 .loc 1 531 3 is_stmt 1 view .LVU155
531:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
626 .loc 1 531 19 is_stmt 0 view .LVU156
627 008c 4FF47A73 mov r3, #1000
628 0090 0193 str r3, [sp, #4]
532:Src/main.c **** {
629 .loc 1 532 3 is_stmt 1 view .LVU157
532:Src/main.c **** {
630 .loc 1 532 7 is_stmt 0 view .LVU158
631 0092 0422 movs r2, #4
632 0094 6946 mov r1, sp
633 0096 1648 ldr r0, .L49
634 0098 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
635 .LVL21:
532:Src/main.c **** {
636 .loc 1 532 6 discriminator 1 view .LVU159
637 009c 08BB cbnz r0, .L46
536:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
638 .loc 1 536 3 is_stmt 1 view .LVU160
536:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
639 .loc 1 536 19 is_stmt 0 view .LVU161
640 009e 40F2DC53 movw r3, #1500
641 00a2 0193 str r3, [sp, #4]
537:Src/main.c **** {
642 .loc 1 537 3 is_stmt 1 view .LVU162
537:Src/main.c **** {
643 .loc 1 537 7 is_stmt 0 view .LVU163
644 00a4 0822 movs r2, #8
645 00a6 6946 mov r1, sp
646 00a8 1148 ldr r0, .L49
647 00aa FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
648 .LVL22:
537:Src/main.c **** {
649 .loc 1 537 6 discriminator 1 view .LVU164
650 00ae D0B9 cbnz r0, .L47
541:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
651 .loc 1 541 3 is_stmt 1 view .LVU165
541:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
652 .loc 1 541 19 is_stmt 0 view .LVU166
653 00b0 4FF4FA63 mov r3, #2000
654 00b4 0193 str r3, [sp, #4]
542:Src/main.c **** {
655 .loc 1 542 3 is_stmt 1 view .LVU167
542:Src/main.c **** {
656 .loc 1 542 7 is_stmt 0 view .LVU168
657 00b6 0C22 movs r2, #12
ARM GAS /tmp/cchrMLox.s page 32
658 00b8 6946 mov r1, sp
659 00ba 0D48 ldr r0, .L49
660 00bc FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
661 .LVL23:
542:Src/main.c **** {
662 .loc 1 542 6 discriminator 1 view .LVU169
663 00c0 98B9 cbnz r0, .L48
549:Src/main.c ****
664 .loc 1 549 3 is_stmt 1 view .LVU170
665 00c2 0B48 ldr r0, .L49
666 00c4 FFF7FEFF bl HAL_TIM_MspPostInit
667 .LVL24:
551:Src/main.c ****
668 .loc 1 551 1 is_stmt 0 view .LVU171
669 00c8 0FB0 add sp, sp, #60
670 .LCFI8:
671 .cfi_remember_state
672 .cfi_def_cfa_offset 4
673 @ sp needed
674 00ca 5DF804FB ldr pc, [sp], #4
675 .L41:
676 .LCFI9:
677 .cfi_restore_state
506:Src/main.c **** }
678 .loc 1 506 5 is_stmt 1 view .LVU172
679 00ce FFF7FEFF bl Error_Handler
680 .LVL25:
681 .L42:
511:Src/main.c **** }
682 .loc 1 511 5 view .LVU173
683 00d2 FFF7FEFF bl Error_Handler
684 .LVL26:
685 .L43:
515:Src/main.c **** }
686 .loc 1 515 5 view .LVU174
687 00d6 FFF7FEFF bl Error_Handler
688 .LVL27:
689 .L44:
521:Src/main.c **** }
690 .loc 1 521 5 view .LVU175
691 00da FFF7FEFF bl Error_Handler
692 .LVL28:
693 .L45:
529:Src/main.c **** }
694 .loc 1 529 5 view .LVU176
695 00de FFF7FEFF bl Error_Handler
696 .LVL29:
697 .L46:
534:Src/main.c **** }
698 .loc 1 534 5 view .LVU177
699 00e2 FFF7FEFF bl Error_Handler
700 .LVL30:
701 .L47:
539:Src/main.c **** }
702 .loc 1 539 5 view .LVU178
703 00e6 FFF7FEFF bl Error_Handler
704 .LVL31:
ARM GAS /tmp/cchrMLox.s page 33
705 .L48:
544:Src/main.c **** }
706 .loc 1 544 5 view .LVU179
707 00ea FFF7FEFF bl Error_Handler
708 .LVL32:
709 .L50:
710 00ee 00BF .align 2
711 .L49:
712 00f0 00000000 .word htim2
713 .cfi_endproc
714 .LFE337:
716 .section .text.MX_I2C1_Init,"ax",%progbits
717 .align 1
718 .syntax unified
719 .thumb
720 .thumb_func
722 MX_I2C1_Init:
723 .LFB336:
437:Src/main.c ****
724 .loc 1 437 1 view -0
725 .cfi_startproc
726 @ args = 0, pretend = 0, frame = 0
727 @ frame_needed = 0, uses_anonymous_args = 0
728 0000 08B5 push {r3, lr}
729 .LCFI10:
730 .cfi_def_cfa_offset 8
731 .cfi_offset 3, -8
732 .cfi_offset 14, -4
446:Src/main.c **** hi2c1.Init.Timing = 0x50916E9F;
733 .loc 1 446 3 view .LVU181
446:Src/main.c **** hi2c1.Init.Timing = 0x50916E9F;
734 .loc 1 446 18 is_stmt 0 view .LVU182
735 0002 1148 ldr r0, .L59
736 0004 114B ldr r3, .L59+4
737 0006 0360 str r3, [r0]
447:Src/main.c **** hi2c1.Init.OwnAddress1 = 0;
738 .loc 1 447 3 is_stmt 1 view .LVU183
447:Src/main.c **** hi2c1.Init.OwnAddress1 = 0;
739 .loc 1 447 21 is_stmt 0 view .LVU184
740 0008 114B ldr r3, .L59+8
741 000a 4360 str r3, [r0, #4]
448:Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
742 .loc 1 448 3 is_stmt 1 view .LVU185
448:Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
743 .loc 1 448 26 is_stmt 0 view .LVU186
744 000c 0023 movs r3, #0
745 000e 8360 str r3, [r0, #8]
449:Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
746 .loc 1 449 3 is_stmt 1 view .LVU187
449:Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
747 .loc 1 449 29 is_stmt 0 view .LVU188
748 0010 0122 movs r2, #1
749 0012 C260 str r2, [r0, #12]
450:Src/main.c **** hi2c1.Init.OwnAddress2 = 0;
750 .loc 1 450 3 is_stmt 1 view .LVU189
450:Src/main.c **** hi2c1.Init.OwnAddress2 = 0;
751 .loc 1 450 30 is_stmt 0 view .LVU190
ARM GAS /tmp/cchrMLox.s page 34
752 0014 0361 str r3, [r0, #16]
451:Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
753 .loc 1 451 3 is_stmt 1 view .LVU191
451:Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
754 .loc 1 451 26 is_stmt 0 view .LVU192
755 0016 4361 str r3, [r0, #20]
452:Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
756 .loc 1 452 3 is_stmt 1 view .LVU193
452:Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
757 .loc 1 452 31 is_stmt 0 view .LVU194
758 0018 8361 str r3, [r0, #24]
453:Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
759 .loc 1 453 3 is_stmt 1 view .LVU195
453:Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
760 .loc 1 453 30 is_stmt 0 view .LVU196
761 001a C361 str r3, [r0, #28]
454:Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK)
762 .loc 1 454 3 is_stmt 1 view .LVU197
454:Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK)
763 .loc 1 454 28 is_stmt 0 view .LVU198
764 001c 0362 str r3, [r0, #32]
455:Src/main.c **** {
765 .loc 1 455 3 is_stmt 1 view .LVU199
455:Src/main.c **** {
766 .loc 1 455 7 is_stmt 0 view .LVU200
767 001e FFF7FEFF bl HAL_I2C_Init
768 .LVL33:
455:Src/main.c **** {
769 .loc 1 455 6 discriminator 1 view .LVU201
770 0022 50B9 cbnz r0, .L56
462:Src/main.c **** {
771 .loc 1 462 3 is_stmt 1 view .LVU202
462:Src/main.c **** {
772 .loc 1 462 7 is_stmt 0 view .LVU203
773 0024 0021 movs r1, #0
774 0026 0848 ldr r0, .L59
775 0028 FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter
776 .LVL34:
462:Src/main.c **** {
777 .loc 1 462 6 discriminator 1 view .LVU204
778 002c 38B9 cbnz r0, .L57
469:Src/main.c **** {
779 .loc 1 469 3 is_stmt 1 view .LVU205
469:Src/main.c **** {
780 .loc 1 469 7 is_stmt 0 view .LVU206
781 002e 0021 movs r1, #0
782 0030 0548 ldr r0, .L59
783 0032 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter
784 .LVL35:
469:Src/main.c **** {
785 .loc 1 469 6 discriminator 1 view .LVU207
786 0036 20B9 cbnz r0, .L58
477:Src/main.c ****
787 .loc 1 477 1 view .LVU208
788 0038 08BD pop {r3, pc}
789 .L56:
457:Src/main.c **** }
ARM GAS /tmp/cchrMLox.s page 35
790 .loc 1 457 5 is_stmt 1 view .LVU209
791 003a FFF7FEFF bl Error_Handler
792 .LVL36:
793 .L57:
464:Src/main.c **** }
794 .loc 1 464 5 view .LVU210
795 003e FFF7FEFF bl Error_Handler
796 .LVL37:
797 .L58:
471:Src/main.c **** }
798 .loc 1 471 5 view .LVU211
799 0042 FFF7FEFF bl Error_Handler
800 .LVL38:
801 .L60:
802 0046 00BF .align 2
803 .L59:
804 0048 00000000 .word hi2c1
805 004c 00540040 .word 1073763328
806 0050 9F6E9150 .word 1351708319
807 .cfi_endproc
808 .LFE336:
810 .section .text.MX_TIM3_Init,"ax",%progbits
811 .align 1
812 .syntax unified
813 .thumb
814 .thumb_func
816 MX_TIM3_Init:
817 .LFB338:
559:Src/main.c ****
818 .loc 1 559 1 view -0
819 .cfi_startproc
820 @ args = 0, pretend = 0, frame = 32
821 @ frame_needed = 0, uses_anonymous_args = 0
822 0000 00B5 push {lr}
823 .LCFI11:
824 .cfi_def_cfa_offset 4
825 .cfi_offset 14, -4
826 0002 89B0 sub sp, sp, #36
827 .LCFI12:
828 .cfi_def_cfa_offset 40
565:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
829 .loc 1 565 3 view .LVU213
565:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
830 .loc 1 565 26 is_stmt 0 view .LVU214
831 0004 0023 movs r3, #0
832 0006 0493 str r3, [sp, #16]
833 0008 0593 str r3, [sp, #20]
834 000a 0693 str r3, [sp, #24]
835 000c 0793 str r3, [sp, #28]
566:Src/main.c ****
836 .loc 1 566 3 is_stmt 1 view .LVU215
566:Src/main.c ****
837 .loc 1 566 27 is_stmt 0 view .LVU216
838 000e 0193 str r3, [sp, #4]
839 0010 0293 str r3, [sp, #8]
840 0012 0393 str r3, [sp, #12]
571:Src/main.c **** htim3.Init.Prescaler = 16799;
ARM GAS /tmp/cchrMLox.s page 36
841 .loc 1 571 3 is_stmt 1 view .LVU217
571:Src/main.c **** htim3.Init.Prescaler = 16799;
842 .loc 1 571 18 is_stmt 0 view .LVU218
843 0014 1348 ldr r0, .L69
844 0016 144A ldr r2, .L69+4
845 0018 0260 str r2, [r0]
572:Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
846 .loc 1 572 3 is_stmt 1 view .LVU219
572:Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
847 .loc 1 572 24 is_stmt 0 view .LVU220
848 001a 44F29F12 movw r2, #16799
849 001e 4260 str r2, [r0, #4]
573:Src/main.c **** htim3.Init.Period = 99;
850 .loc 1 573 3 is_stmt 1 view .LVU221
573:Src/main.c **** htim3.Init.Period = 99;
851 .loc 1 573 26 is_stmt 0 view .LVU222
852 0020 8360 str r3, [r0, #8]
574:Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
853 .loc 1 574 3 is_stmt 1 view .LVU223
574:Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
854 .loc 1 574 21 is_stmt 0 view .LVU224
855 0022 6322 movs r2, #99
856 0024 C260 str r2, [r0, #12]
575:Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
857 .loc 1 575 3 is_stmt 1 view .LVU225
575:Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
858 .loc 1 575 28 is_stmt 0 view .LVU226
859 0026 0361 str r3, [r0, #16]
576:Src/main.c **** if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
860 .loc 1 576 3 is_stmt 1 view .LVU227
576:Src/main.c **** if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
861 .loc 1 576 32 is_stmt 0 view .LVU228
862 0028 8361 str r3, [r0, #24]
577:Src/main.c **** {
863 .loc 1 577 3 is_stmt 1 view .LVU229
577:Src/main.c **** {
864 .loc 1 577 7 is_stmt 0 view .LVU230
865 002a FFF7FEFF bl HAL_TIM_Base_Init
866 .LVL39:
577:Src/main.c **** {
867 .loc 1 577 6 discriminator 1 view .LVU231
868 002e 90B9 cbnz r0, .L66
581:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
869 .loc 1 581 3 is_stmt 1 view .LVU232
581:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
870 .loc 1 581 34 is_stmt 0 view .LVU233
871 0030 4FF48053 mov r3, #4096
872 0034 0493 str r3, [sp, #16]
582:Src/main.c **** {
873 .loc 1 582 3 is_stmt 1 view .LVU234
582:Src/main.c **** {
874 .loc 1 582 7 is_stmt 0 view .LVU235
875 0036 04A9 add r1, sp, #16
876 0038 0A48 ldr r0, .L69
877 003a FFF7FEFF bl HAL_TIM_ConfigClockSource
878 .LVL40:
582:Src/main.c **** {
ARM GAS /tmp/cchrMLox.s page 37
879 .loc 1 582 6 discriminator 1 view .LVU236
880 003e 60B9 cbnz r0, .L67
586:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
881 .loc 1 586 3 is_stmt 1 view .LVU237
586:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
882 .loc 1 586 37 is_stmt 0 view .LVU238
883 0040 0023 movs r3, #0
884 0042 0193 str r3, [sp, #4]
587:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
885 .loc 1 587 3 is_stmt 1 view .LVU239
587:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
886 .loc 1 587 33 is_stmt 0 view .LVU240
887 0044 0393 str r3, [sp, #12]
588:Src/main.c **** {
888 .loc 1 588 3 is_stmt 1 view .LVU241
588:Src/main.c **** {
889 .loc 1 588 7 is_stmt 0 view .LVU242
890 0046 01A9 add r1, sp, #4
891 0048 0648 ldr r0, .L69
892 004a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
893 .LVL41:
588:Src/main.c **** {
894 .loc 1 588 6 discriminator 1 view .LVU243
895 004e 30B9 cbnz r0, .L68
596:Src/main.c ****
896 .loc 1 596 1 view .LVU244
897 0050 09B0 add sp, sp, #36
898 .LCFI13:
899 .cfi_remember_state
900 .cfi_def_cfa_offset 4
901 @ sp needed
902 0052 5DF804FB ldr pc, [sp], #4
903 .L66:
904 .LCFI14:
905 .cfi_restore_state
579:Src/main.c **** }
906 .loc 1 579 5 is_stmt 1 view .LVU245
907 0056 FFF7FEFF bl Error_Handler
908 .LVL42:
909 .L67:
584:Src/main.c **** }
910 .loc 1 584 5 view .LVU246
911 005a FFF7FEFF bl Error_Handler
912 .LVL43:
913 .L68:
590:Src/main.c **** }
914 .loc 1 590 5 view .LVU247
915 005e FFF7FEFF bl Error_Handler
916 .LVL44:
917 .L70:
918 0062 00BF .align 2
919 .L69:
920 0064 00000000 .word htim3
921 0068 00040040 .word 1073742848
922 .cfi_endproc
923 .LFE338:
925 .section .text.MX_ADC1_Init,"ax",%progbits
ARM GAS /tmp/cchrMLox.s page 38
926 .align 1
927 .syntax unified
928 .thumb
929 .thumb_func
931 MX_ADC1_Init:
932 .LFB334:
268:Src/main.c ****
933 .loc 1 268 1 view -0
934 .cfi_startproc
935 @ args = 0, pretend = 0, frame = 72
936 @ frame_needed = 0, uses_anonymous_args = 0
937 0000 10B5 push {r4, lr}
938 .LCFI15:
939 .cfi_def_cfa_offset 8
940 .cfi_offset 4, -8
941 .cfi_offset 14, -4
942 0002 92B0 sub sp, sp, #72
943 .LCFI16:
944 .cfi_def_cfa_offset 80
274:Src/main.c **** ADC_AnalogWDGConfTypeDef AnalogWDGConfig = {0};
945 .loc 1 274 3 view .LVU249
274:Src/main.c **** ADC_AnalogWDGConfTypeDef AnalogWDGConfig = {0};
946 .loc 1 274 24 is_stmt 0 view .LVU250
947 0004 0024 movs r4, #0
948 0006 0F94 str r4, [sp, #60]
949 0008 1094 str r4, [sp, #64]
950 000a 1194 str r4, [sp, #68]
275:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
951 .loc 1 275 3 is_stmt 1 view .LVU251
275:Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0};
952 .loc 1 275 28 is_stmt 0 view .LVU252
953 000c 0894 str r4, [sp, #32]
954 000e 0994 str r4, [sp, #36]
955 0010 0A94 str r4, [sp, #40]
956 0012 0B94 str r4, [sp, #44]
957 0014 0C94 str r4, [sp, #48]
958 0016 0D94 str r4, [sp, #52]
959 0018 0E94 str r4, [sp, #56]
276:Src/main.c ****
960 .loc 1 276 3 is_stmt 1 view .LVU253
276:Src/main.c ****
961 .loc 1 276 26 is_stmt 0 view .LVU254
962 001a 2022 movs r2, #32
963 001c 2146 mov r1, r4
964 001e 6846 mov r0, sp
965 0020 FFF7FEFF bl memset
966 .LVL45:
284:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
967 .loc 1 284 3 is_stmt 1 view .LVU255
284:Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
968 .loc 1 284 18 is_stmt 0 view .LVU256
969 0024 2C48 ldr r0, .L81
970 0026 4FF0A043 mov r3, #1342177280
971 002a 0360 str r3, [r0]
285:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
972 .loc 1 285 3 is_stmt 1 view .LVU257
285:Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_12B;
ARM GAS /tmp/cchrMLox.s page 39
973 .loc 1 285 29 is_stmt 0 view .LVU258
974 002c 4FF44033 mov r3, #196608
975 0030 4360 str r3, [r0, #4]
286:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
976 .loc 1 286 3 is_stmt 1 view .LVU259
286:Src/main.c **** hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
977 .loc 1 286 25 is_stmt 0 view .LVU260
978 0032 8460 str r4, [r0, #8]
287:Src/main.c **** hadc1.Init.GainCompensation = 0;
979 .loc 1 287 3 is_stmt 1 view .LVU261
287:Src/main.c **** hadc1.Init.GainCompensation = 0;
980 .loc 1 287 24 is_stmt 0 view .LVU262
981 0034 C460 str r4, [r0, #12]
288:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
982 .loc 1 288 3 is_stmt 1 view .LVU263
288:Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
983 .loc 1 288 31 is_stmt 0 view .LVU264
984 0036 0461 str r4, [r0, #16]
289:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
985 .loc 1 289 3 is_stmt 1 view .LVU265
289:Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
986 .loc 1 289 27 is_stmt 0 view .LVU266
987 0038 4461 str r4, [r0, #20]
290:Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
988 .loc 1 290 3 is_stmt 1 view .LVU267
290:Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE;
989 .loc 1 290 27 is_stmt 0 view .LVU268
990 003a 0423 movs r3, #4
991 003c 8361 str r3, [r0, #24]
291:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
992 .loc 1 291 3 is_stmt 1 view .LVU269
291:Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE;
993 .loc 1 291 31 is_stmt 0 view .LVU270
994 003e 0477 strb r4, [r0, #28]
292:Src/main.c **** hadc1.Init.NbrOfConversion = 1;
995 .loc 1 292 3 is_stmt 1 view .LVU271
292:Src/main.c **** hadc1.Init.NbrOfConversion = 1;
996 .loc 1 292 33 is_stmt 0 view .LVU272
997 0040 4477 strb r4, [r0, #29]
293:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
998 .loc 1 293 3 is_stmt 1 view .LVU273
293:Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE;
999 .loc 1 293 30 is_stmt 0 view .LVU274
1000 0042 0123 movs r3, #1
1001 0044 0362 str r3, [r0, #32]
294:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
1002 .loc 1 294 3 is_stmt 1 view .LVU275
294:Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO;
1003 .loc 1 294 36 is_stmt 0 view .LVU276
1004 0046 80F82440 strb r4, [r0, #36]
295:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
1005 .loc 1 295 3 is_stmt 1 view .LVU277
295:Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING;
1006 .loc 1 295 31 is_stmt 0 view .LVU278
1007 004a 4FF4AC63 mov r3, #1376
1008 004e C362 str r3, [r0, #44]
296:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE;
ARM GAS /tmp/cchrMLox.s page 40
1009 .loc 1 296 3 is_stmt 1 view .LVU279
296:Src/main.c **** hadc1.Init.DMAContinuousRequests = DISABLE;
1010 .loc 1 296 35 is_stmt 0 view .LVU280
1011 0050 4FF48063 mov r3, #1024
1012 0054 0363 str r3, [r0, #48]
297:Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
1013 .loc 1 297 3 is_stmt 1 view .LVU281
297:Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
1014 .loc 1 297 36 is_stmt 0 view .LVU282
1015 0056 80F83840 strb r4, [r0, #56]
298:Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
1016 .loc 1 298 3 is_stmt 1 view .LVU283
298:Src/main.c **** hadc1.Init.OversamplingMode = DISABLE;
1017 .loc 1 298 22 is_stmt 0 view .LVU284
1018 005a C463 str r4, [r0, #60]
299:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
1019 .loc 1 299 3 is_stmt 1 view .LVU285
299:Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK)
1020 .loc 1 299 31 is_stmt 0 view .LVU286
1021 005c 80F84040 strb r4, [r0, #64]
300:Src/main.c **** {
1022 .loc 1 300 3 is_stmt 1 view .LVU287
300:Src/main.c **** {
1023 .loc 1 300 7 is_stmt 0 view .LVU288
1024 0060 FFF7FEFF bl HAL_ADC_Init
1025 .LVL46:
300:Src/main.c **** {
1026 .loc 1 300 6 discriminator 1 view .LVU289
1027 0064 0028 cmp r0, #0
1028 0066 2FD1 bne .L77
307:Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
1029 .loc 1 307 3 is_stmt 1 view .LVU290
307:Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
1030 .loc 1 307 18 is_stmt 0 view .LVU291
1031 0068 0023 movs r3, #0
1032 006a 0F93 str r3, [sp, #60]
308:Src/main.c **** {
1033 .loc 1 308 3 is_stmt 1 view .LVU292
308:Src/main.c **** {
1034 .loc 1 308 7 is_stmt 0 view .LVU293
1035 006c 0FA9 add r1, sp, #60
1036 006e 1A48 ldr r0, .L81
1037 0070 FFF7FEFF bl HAL_ADCEx_MultiModeConfigChannel
1038 .LVL47:
308:Src/main.c **** {
1039 .loc 1 308 6 discriminator 1 view .LVU294
1040 0074 50BB cbnz r0, .L78
315:Src/main.c **** AnalogWDGConfig.WatchdogMode = ADC_ANALOGWATCHDOG_SINGLE_REG;
1041 .loc 1 315 3 is_stmt 1 view .LVU295
315:Src/main.c **** AnalogWDGConfig.WatchdogMode = ADC_ANALOGWATCHDOG_SINGLE_REG;
1042 .loc 1 315 34 is_stmt 0 view .LVU296
1043 0076 194B ldr r3, .L81+4
1044 0078 0893 str r3, [sp, #32]
316:Src/main.c **** AnalogWDGConfig.Channel = ADC_CHANNEL_15;
1045 .loc 1 316 3 is_stmt 1 view .LVU297
316:Src/main.c **** AnalogWDGConfig.Channel = ADC_CHANNEL_15;
1046 .loc 1 316 32 is_stmt 0 view .LVU298
ARM GAS /tmp/cchrMLox.s page 41
1047 007a 4FF44003 mov r3, #12582912
1048 007e 0993 str r3, [sp, #36]
317:Src/main.c **** AnalogWDGConfig.ITMode = ENABLE;
1049 .loc 1 317 3 is_stmt 1 view .LVU299
317:Src/main.c **** AnalogWDGConfig.ITMode = ENABLE;
1050 .loc 1 317 27 is_stmt 0 view .LVU300
1051 0080 174B ldr r3, .L81+8
1052 0082 0A93 str r3, [sp, #40]
318:Src/main.c **** AnalogWDGConfig.HighThreshold = 4048;
1053 .loc 1 318 3 is_stmt 1 view .LVU301
318:Src/main.c **** AnalogWDGConfig.HighThreshold = 4048;
1054 .loc 1 318 26 is_stmt 0 view .LVU302
1055 0084 0123 movs r3, #1
1056 0086 8DF82C30 strb r3, [sp, #44]
319:Src/main.c **** AnalogWDGConfig.LowThreshold = 48;
1057 .loc 1 319 3 is_stmt 1 view .LVU303
319:Src/main.c **** AnalogWDGConfig.LowThreshold = 48;
1058 .loc 1 319 33 is_stmt 0 view .LVU304
1059 008a 4FF47D63 mov r3, #4048
1060 008e 0C93 str r3, [sp, #48]
320:Src/main.c **** AnalogWDGConfig.FilteringConfig = ADC_AWD_FILTERING_NONE;
1061 .loc 1 320 3 is_stmt 1 view .LVU305
320:Src/main.c **** AnalogWDGConfig.FilteringConfig = ADC_AWD_FILTERING_NONE;
1062 .loc 1 320 32 is_stmt 0 view .LVU306
1063 0090 3023 movs r3, #48
1064 0092 0D93 str r3, [sp, #52]
321:Src/main.c **** if (HAL_ADC_AnalogWDGConfig(&hadc1, &AnalogWDGConfig) != HAL_OK)
1065 .loc 1 321 3 is_stmt 1 view .LVU307
321:Src/main.c **** if (HAL_ADC_AnalogWDGConfig(&hadc1, &AnalogWDGConfig) != HAL_OK)
1066 .loc 1 321 35 is_stmt 0 view .LVU308
1067 0094 0023 movs r3, #0
1068 0096 0E93 str r3, [sp, #56]
322:Src/main.c **** {
1069 .loc 1 322 3 is_stmt 1 view .LVU309
322:Src/main.c **** {
1070 .loc 1 322 7 is_stmt 0 view .LVU310
1071 0098 08A9 add r1, sp, #32
1072 009a 0F48 ldr r0, .L81
1073 009c FFF7FEFF bl HAL_ADC_AnalogWDGConfig
1074 .LVL48:
322:Src/main.c **** {
1075 .loc 1 322 6 discriminator 1 view .LVU311
1076 00a0 B0B9 cbnz r0, .L79
329:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1077 .loc 1 329 3 is_stmt 1 view .LVU312
329:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1078 .loc 1 329 19 is_stmt 0 view .LVU313
1079 00a2 0F4B ldr r3, .L81+8
1080 00a4 0093 str r3, [sp]
330:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5;
1081 .loc 1 330 3 is_stmt 1 view .LVU314
330:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_92CYCLES_5;
1082 .loc 1 330 16 is_stmt 0 view .LVU315
1083 00a6 0623 movs r3, #6
1084 00a8 0193 str r3, [sp, #4]
331:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
1085 .loc 1 331 3 is_stmt 1 view .LVU316
ARM GAS /tmp/cchrMLox.s page 42
331:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
1086 .loc 1 331 24 is_stmt 0 view .LVU317
1087 00aa 0523 movs r3, #5
1088 00ac 0293 str r3, [sp, #8]
332:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1089 .loc 1 332 3 is_stmt 1 view .LVU318
332:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1090 .loc 1 332 22 is_stmt 0 view .LVU319
1091 00ae 7F23 movs r3, #127
1092 00b0 0393 str r3, [sp, #12]
333:Src/main.c **** sConfig.Offset = 0;
1093 .loc 1 333 3 is_stmt 1 view .LVU320
333:Src/main.c **** sConfig.Offset = 0;
1094 .loc 1 333 24 is_stmt 0 view .LVU321
1095 00b2 0423 movs r3, #4
1096 00b4 0493 str r3, [sp, #16]
334:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
1097 .loc 1 334 3 is_stmt 1 view .LVU322
334:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
1098 .loc 1 334 18 is_stmt 0 view .LVU323
1099 00b6 0023 movs r3, #0
1100 00b8 0593 str r3, [sp, #20]
335:Src/main.c **** {
1101 .loc 1 335 3 is_stmt 1 view .LVU324
335:Src/main.c **** {
1102 .loc 1 335 7 is_stmt 0 view .LVU325
1103 00ba 6946 mov r1, sp
1104 00bc 0648 ldr r0, .L81
1105 00be FFF7FEFF bl HAL_ADC_ConfigChannel
1106 .LVL49:
335:Src/main.c **** {
1107 .loc 1 335 6 discriminator 1 view .LVU326
1108 00c2 38B9 cbnz r0, .L80
343:Src/main.c ****
1109 .loc 1 343 1 view .LVU327
1110 00c4 12B0 add sp, sp, #72
1111 .LCFI17:
1112 .cfi_remember_state
1113 .cfi_def_cfa_offset 8
1114 @ sp needed
1115 00c6 10BD pop {r4, pc}
1116 .L77:
1117 .LCFI18:
1118 .cfi_restore_state
302:Src/main.c **** }
1119 .loc 1 302 5 is_stmt 1 view .LVU328
1120 00c8 FFF7FEFF bl Error_Handler
1121 .LVL50:
1122 .L78:
310:Src/main.c **** }
1123 .loc 1 310 5 view .LVU329
1124 00cc FFF7FEFF bl Error_Handler
1125 .LVL51:
1126 .L79:
324:Src/main.c **** }
1127 .loc 1 324 5 view .LVU330
1128 00d0 FFF7FEFF bl Error_Handler
ARM GAS /tmp/cchrMLox.s page 43
1129 .LVL52:
1130 .L80:
337:Src/main.c **** }
1131 .loc 1 337 5 view .LVU331
1132 00d4 FFF7FEFF bl Error_Handler
1133 .LVL53:
1134 .L82:
1135 .align 2
1136 .L81:
1137 00d8 00000000 .word hadc1
1138 00dc 0000C07D .word 2109734912
1139 00e0 0080F03E .word 1055948800
1140 .cfi_endproc
1141 .LFE334:
1143 .section .text.MX_ADC2_Init,"ax",%progbits
1144 .align 1
1145 .syntax unified
1146 .thumb
1147 .thumb_func
1149 MX_ADC2_Init:
1150 .LFB335:
351:Src/main.c ****
1151 .loc 1 351 1 view -0
1152 .cfi_startproc
1153 @ args = 0, pretend = 0, frame = 32
1154 @ frame_needed = 0, uses_anonymous_args = 0
1155 0000 00B5 push {lr}
1156 .LCFI19:
1157 .cfi_def_cfa_offset 4
1158 .cfi_offset 14, -4
1159 0002 89B0 sub sp, sp, #36
1160 .LCFI20:
1161 .cfi_def_cfa_offset 40
357:Src/main.c ****
1162 .loc 1 357 3 view .LVU333
357:Src/main.c ****
1163 .loc 1 357 26 is_stmt 0 view .LVU334
1164 0004 2022 movs r2, #32
1165 0006 0021 movs r1, #0
1166 0008 6846 mov r0, sp
1167 000a FFF7FEFF bl memset
1168 .LVL54:
365:Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
1169 .loc 1 365 3 is_stmt 1 view .LVU335
365:Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
1170 .loc 1 365 18 is_stmt 0 view .LVU336
1171 000e 2B48 ldr r0, .L95
1172 0010 2B4B ldr r3, .L95+4
1173 0012 0360 str r3, [r0]
366:Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_12B;
1174 .loc 1 366 3 is_stmt 1 view .LVU337
366:Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_12B;
1175 .loc 1 366 29 is_stmt 0 view .LVU338
1176 0014 4FF44033 mov r3, #196608
1177 0018 4360 str r3, [r0, #4]
367:Src/main.c **** hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
1178 .loc 1 367 3 is_stmt 1 view .LVU339
ARM GAS /tmp/cchrMLox.s page 44
367:Src/main.c **** hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
1179 .loc 1 367 25 is_stmt 0 view .LVU340
1180 001a 0023 movs r3, #0
1181 001c 8360 str r3, [r0, #8]
368:Src/main.c **** hadc2.Init.GainCompensation = 0;
1182 .loc 1 368 3 is_stmt 1 view .LVU341
368:Src/main.c **** hadc2.Init.GainCompensation = 0;
1183 .loc 1 368 24 is_stmt 0 view .LVU342
1184 001e C360 str r3, [r0, #12]
369:Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
1185 .loc 1 369 3 is_stmt 1 view .LVU343
369:Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE;
1186 .loc 1 369 31 is_stmt 0 view .LVU344
1187 0020 0361 str r3, [r0, #16]
370:Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
1188 .loc 1 370 3 is_stmt 1 view .LVU345
370:Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
1189 .loc 1 370 27 is_stmt 0 view .LVU346
1190 0022 0122 movs r2, #1
1191 0024 4261 str r2, [r0, #20]
371:Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE;
1192 .loc 1 371 3 is_stmt 1 view .LVU347
371:Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE;
1193 .loc 1 371 27 is_stmt 0 view .LVU348
1194 0026 0822 movs r2, #8
1195 0028 8261 str r2, [r0, #24]
372:Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE;
1196 .loc 1 372 3 is_stmt 1 view .LVU349
372:Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE;
1197 .loc 1 372 31 is_stmt 0 view .LVU350
1198 002a 0377 strb r3, [r0, #28]
373:Src/main.c **** hadc2.Init.NbrOfConversion = 4;
1199 .loc 1 373 3 is_stmt 1 view .LVU351
373:Src/main.c **** hadc2.Init.NbrOfConversion = 4;
1200 .loc 1 373 33 is_stmt 0 view .LVU352
1201 002c 4377 strb r3, [r0, #29]
374:Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE;
1202 .loc 1 374 3 is_stmt 1 view .LVU353
374:Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE;
1203 .loc 1 374 30 is_stmt 0 view .LVU354
1204 002e 0422 movs r2, #4
1205 0030 0262 str r2, [r0, #32]
375:Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
1206 .loc 1 375 3 is_stmt 1 view .LVU355
375:Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
1207 .loc 1 375 36 is_stmt 0 view .LVU356
1208 0032 80F82430 strb r3, [r0, #36]
376:Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
1209 .loc 1 376 3 is_stmt 1 view .LVU357
376:Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
1210 .loc 1 376 31 is_stmt 0 view .LVU358
1211 0036 C362 str r3, [r0, #44]
377:Src/main.c **** hadc2.Init.DMAContinuousRequests = DISABLE;
1212 .loc 1 377 3 is_stmt 1 view .LVU359
377:Src/main.c **** hadc2.Init.DMAContinuousRequests = DISABLE;
1213 .loc 1 377 35 is_stmt 0 view .LVU360
1214 0038 0363 str r3, [r0, #48]
ARM GAS /tmp/cchrMLox.s page 45
378:Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
1215 .loc 1 378 3 is_stmt 1 view .LVU361
378:Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
1216 .loc 1 378 36 is_stmt 0 view .LVU362
1217 003a 80F83830 strb r3, [r0, #56]
379:Src/main.c **** hadc2.Init.OversamplingMode = DISABLE;
1218 .loc 1 379 3 is_stmt 1 view .LVU363
379:Src/main.c **** hadc2.Init.OversamplingMode = DISABLE;
1219 .loc 1 379 22 is_stmt 0 view .LVU364
1220 003e C363 str r3, [r0, #60]
380:Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK)
1221 .loc 1 380 3 is_stmt 1 view .LVU365
380:Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK)
1222 .loc 1 380 31 is_stmt 0 view .LVU366
1223 0040 80F84030 strb r3, [r0, #64]
381:Src/main.c **** {
1224 .loc 1 381 3 is_stmt 1 view .LVU367
381:Src/main.c **** {
1225 .loc 1 381 7 is_stmt 0 view .LVU368
1226 0044 FFF7FEFF bl HAL_ADC_Init
1227 .LVL55:
381:Src/main.c **** {
1228 .loc 1 381 6 discriminator 1 view .LVU369
1229 0048 0028 cmp r0, #0
1230 004a 2DD1 bne .L90
388:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1231 .loc 1 388 3 is_stmt 1 view .LVU370
388:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1;
1232 .loc 1 388 19 is_stmt 0 view .LVU371
1233 004c 1D4B ldr r3, .L95+8
1234 004e 0093 str r3, [sp]
389:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
1235 .loc 1 389 3 is_stmt 1 view .LVU372
389:Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
1236 .loc 1 389 16 is_stmt 0 view .LVU373
1237 0050 0623 movs r3, #6
1238 0052 0193 str r3, [sp, #4]
390:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
1239 .loc 1 390 3 is_stmt 1 view .LVU374
390:Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED;
1240 .loc 1 390 24 is_stmt 0 view .LVU375
1241 0054 0293 str r3, [sp, #8]
391:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1242 .loc 1 391 3 is_stmt 1 view .LVU376
391:Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE;
1243 .loc 1 391 22 is_stmt 0 view .LVU377
1244 0056 7F23 movs r3, #127
1245 0058 0393 str r3, [sp, #12]
392:Src/main.c **** sConfig.Offset = 0;
1246 .loc 1 392 3 is_stmt 1 view .LVU378
392:Src/main.c **** sConfig.Offset = 0;
1247 .loc 1 392 24 is_stmt 0 view .LVU379
1248 005a 0423 movs r3, #4
1249 005c 0493 str r3, [sp, #16]
393:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1250 .loc 1 393 3 is_stmt 1 view .LVU380
393:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
ARM GAS /tmp/cchrMLox.s page 46
1251 .loc 1 393 18 is_stmt 0 view .LVU381
1252 005e 0023 movs r3, #0
1253 0060 0593 str r3, [sp, #20]
394:Src/main.c **** {
1254 .loc 1 394 3 is_stmt 1 view .LVU382
394:Src/main.c **** {
1255 .loc 1 394 7 is_stmt 0 view .LVU383
1256 0062 6946 mov r1, sp
1257 0064 1548 ldr r0, .L95
1258 0066 FFF7FEFF bl HAL_ADC_ConfigChannel
1259 .LVL56:
394:Src/main.c **** {
1260 .loc 1 394 6 discriminator 1 view .LVU384
1261 006a F8B9 cbnz r0, .L91
401:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2;
1262 .loc 1 401 3 is_stmt 1 view .LVU385
401:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_2;
1263 .loc 1 401 19 is_stmt 0 view .LVU386
1264 006c 164B ldr r3, .L95+12
1265 006e 0093 str r3, [sp]
402:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1266 .loc 1 402 3 is_stmt 1 view .LVU387
402:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1267 .loc 1 402 16 is_stmt 0 view .LVU388
1268 0070 0C23 movs r3, #12
1269 0072 0193 str r3, [sp, #4]
403:Src/main.c **** {
1270 .loc 1 403 3 is_stmt 1 view .LVU389
403:Src/main.c **** {
1271 .loc 1 403 7 is_stmt 0 view .LVU390
1272 0074 6946 mov r1, sp
1273 0076 1148 ldr r0, .L95
1274 0078 FFF7FEFF bl HAL_ADC_ConfigChannel
1275 .LVL57:
403:Src/main.c **** {
1276 .loc 1 403 6 discriminator 1 view .LVU391
1277 007c C0B9 cbnz r0, .L92
410:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3;
1278 .loc 1 410 3 is_stmt 1 view .LVU392
410:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_3;
1279 .loc 1 410 19 is_stmt 0 view .LVU393
1280 007e 134B ldr r3, .L95+16
1281 0080 0093 str r3, [sp]
411:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1282 .loc 1 411 3 is_stmt 1 view .LVU394
411:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1283 .loc 1 411 16 is_stmt 0 view .LVU395
1284 0082 1223 movs r3, #18
1285 0084 0193 str r3, [sp, #4]
412:Src/main.c **** {
1286 .loc 1 412 3 is_stmt 1 view .LVU396
412:Src/main.c **** {
1287 .loc 1 412 7 is_stmt 0 view .LVU397
1288 0086 6946 mov r1, sp
1289 0088 0C48 ldr r0, .L95
1290 008a FFF7FEFF bl HAL_ADC_ConfigChannel
1291 .LVL58:
ARM GAS /tmp/cchrMLox.s page 47
412:Src/main.c **** {
1292 .loc 1 412 6 discriminator 1 view .LVU398
1293 008e 88B9 cbnz r0, .L93
419:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4;
1294 .loc 1 419 3 is_stmt 1 view .LVU399
419:Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_4;
1295 .loc 1 419 19 is_stmt 0 view .LVU400
1296 0090 0F4B ldr r3, .L95+20
1297 0092 0093 str r3, [sp]
420:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1298 .loc 1 420 3 is_stmt 1 view .LVU401
420:Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
1299 .loc 1 420 16 is_stmt 0 view .LVU402
1300 0094 1823 movs r3, #24
1301 0096 0193 str r3, [sp, #4]
421:Src/main.c **** {
1302 .loc 1 421 3 is_stmt 1 view .LVU403
421:Src/main.c **** {
1303 .loc 1 421 7 is_stmt 0 view .LVU404
1304 0098 6946 mov r1, sp
1305 009a 0848 ldr r0, .L95
1306 009c FFF7FEFF bl HAL_ADC_ConfigChannel
1307 .LVL59:
421:Src/main.c **** {
1308 .loc 1 421 6 discriminator 1 view .LVU405
1309 00a0 50B9 cbnz r0, .L94
429:Src/main.c ****
1310 .loc 1 429 1 view .LVU406
1311 00a2 09B0 add sp, sp, #36
1312 .LCFI21:
1313 .cfi_remember_state
1314 .cfi_def_cfa_offset 4
1315 @ sp needed
1316 00a4 5DF804FB ldr pc, [sp], #4
1317 .L90:
1318 .LCFI22:
1319 .cfi_restore_state
383:Src/main.c **** }
1320 .loc 1 383 5 is_stmt 1 view .LVU407
1321 00a8 FFF7FEFF bl Error_Handler
1322 .LVL60:
1323 .L91:
396:Src/main.c **** }
1324 .loc 1 396 5 view .LVU408
1325 00ac FFF7FEFF bl Error_Handler
1326 .LVL61:
1327 .L92:
405:Src/main.c **** }
1328 .loc 1 405 5 view .LVU409
1329 00b0 FFF7FEFF bl Error_Handler
1330 .LVL62:
1331 .L93:
414:Src/main.c **** }
1332 .loc 1 414 5 view .LVU410
1333 00b4 FFF7FEFF bl Error_Handler
1334 .LVL63:
1335 .L94:
ARM GAS /tmp/cchrMLox.s page 48
423:Src/main.c **** }
1336 .loc 1 423 5 view .LVU411
1337 00b8 FFF7FEFF bl Error_Handler
1338 .LVL64:
1339 .L96:
1340 .align 2
1341 .L95:
1342 00bc 00000000 .word hadc2
1343 00c0 00010050 .word 1342177536
1344 00c4 1000C010 .word 281018384
1345 00c8 0800900C .word 210763784
1346 00cc 00209036 .word 915415040
1347 00d0 00005247 .word 1196556288
1348 .cfi_endproc
1349 .LFE335:
1351 .section .text.MX_USART1_UART_Init,"ax",%progbits
1352 .align 1
1353 .syntax unified
1354 .thumb
1355 .thumb_func
1357 MX_USART1_UART_Init:
1358 .LFB340:
686:Src/main.c ****
1359 .loc 1 686 1 view -0
1360 .cfi_startproc
1361 @ args = 0, pretend = 0, frame = 0
1362 @ frame_needed = 0, uses_anonymous_args = 0
1363 0000 08B5 push {r3, lr}
1364 .LCFI23:
1365 .cfi_def_cfa_offset 8
1366 .cfi_offset 3, -8
1367 .cfi_offset 14, -4
695:Src/main.c **** huart1.Init.BaudRate = 38400;
1368 .loc 1 695 3 view .LVU413
695:Src/main.c **** huart1.Init.BaudRate = 38400;
1369 .loc 1 695 19 is_stmt 0 view .LVU414
1370 0002 1548 ldr r0, .L107
1371 0004 154B ldr r3, .L107+4
1372 0006 0360 str r3, [r0]
696:Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
1373 .loc 1 696 3 is_stmt 1 view .LVU415
696:Src/main.c **** huart1.Init.WordLength = UART_WORDLENGTH_8B;
1374 .loc 1 696 24 is_stmt 0 view .LVU416
1375 0008 4FF41643 mov r3, #38400
1376 000c 4360 str r3, [r0, #4]
697:Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1;
1377 .loc 1 697 3 is_stmt 1 view .LVU417
697:Src/main.c **** huart1.Init.StopBits = UART_STOPBITS_1;
1378 .loc 1 697 26 is_stmt 0 view .LVU418
1379 000e 0023 movs r3, #0
1380 0010 8360 str r3, [r0, #8]
698:Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE;
1381 .loc 1 698 3 is_stmt 1 view .LVU419
698:Src/main.c **** huart1.Init.Parity = UART_PARITY_NONE;
1382 .loc 1 698 24 is_stmt 0 view .LVU420
1383 0012 C360 str r3, [r0, #12]
699:Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX;
ARM GAS /tmp/cchrMLox.s page 49
1384 .loc 1 699 3 is_stmt 1 view .LVU421
699:Src/main.c **** huart1.Init.Mode = UART_MODE_TX_RX;
1385 .loc 1 699 22 is_stmt 0 view .LVU422
1386 0014 0361 str r3, [r0, #16]
700:Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
1387 .loc 1 700 3 is_stmt 1 view .LVU423
700:Src/main.c **** huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
1388 .loc 1 700 20 is_stmt 0 view .LVU424
1389 0016 0C22 movs r2, #12
1390 0018 4261 str r2, [r0, #20]
701:Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16;
1391 .loc 1 701 3 is_stmt 1 view .LVU425
701:Src/main.c **** huart1.Init.OverSampling = UART_OVERSAMPLING_16;
1392 .loc 1 701 25 is_stmt 0 view .LVU426
1393 001a 8361 str r3, [r0, #24]
702:Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
1394 .loc 1 702 3 is_stmt 1 view .LVU427
702:Src/main.c **** huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
1395 .loc 1 702 28 is_stmt 0 view .LVU428
1396 001c C361 str r3, [r0, #28]
703:Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
1397 .loc 1 703 3 is_stmt 1 view .LVU429
703:Src/main.c **** huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
1398 .loc 1 703 30 is_stmt 0 view .LVU430
1399 001e 0362 str r3, [r0, #32]
704:Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
1400 .loc 1 704 3 is_stmt 1 view .LVU431
704:Src/main.c **** huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
1401 .loc 1 704 30 is_stmt 0 view .LVU432
1402 0020 4362 str r3, [r0, #36]
705:Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
1403 .loc 1 705 3 is_stmt 1 view .LVU433
705:Src/main.c **** if (HAL_UART_Init(&huart1) != HAL_OK)
1404 .loc 1 705 38 is_stmt 0 view .LVU434
1405 0022 8362 str r3, [r0, #40]
706:Src/main.c **** {
1406 .loc 1 706 3 is_stmt 1 view .LVU435
706:Src/main.c **** {
1407 .loc 1 706 7 is_stmt 0 view .LVU436
1408 0024 FFF7FEFF bl HAL_UART_Init
1409 .LVL65:
706:Src/main.c **** {
1410 .loc 1 706 6 discriminator 1 view .LVU437
1411 0028 70B9 cbnz r0, .L103
710:Src/main.c **** {
1412 .loc 1 710 3 is_stmt 1 view .LVU438
710:Src/main.c **** {
1413 .loc 1 710 7 is_stmt 0 view .LVU439
1414 002a 0021 movs r1, #0
1415 002c 0A48 ldr r0, .L107
1416 002e FFF7FEFF bl HAL_UARTEx_SetTxFifoThreshold
1417 .LVL66:
710:Src/main.c **** {
1418 .loc 1 710 6 discriminator 1 view .LVU440
1419 0032 58B9 cbnz r0, .L104
714:Src/main.c **** {
1420 .loc 1 714 3 is_stmt 1 view .LVU441
ARM GAS /tmp/cchrMLox.s page 50
714:Src/main.c **** {
1421 .loc 1 714 7 is_stmt 0 view .LVU442
1422 0034 0021 movs r1, #0
1423 0036 0848 ldr r0, .L107
1424 0038 FFF7FEFF bl HAL_UARTEx_SetRxFifoThreshold
1425 .LVL67:
714:Src/main.c **** {
1426 .loc 1 714 6 discriminator 1 view .LVU443
1427 003c 40B9 cbnz r0, .L105
718:Src/main.c **** {
1428 .loc 1 718 3 is_stmt 1 view .LVU444
718:Src/main.c **** {
1429 .loc 1 718 7 is_stmt 0 view .LVU445
1430 003e 0648 ldr r0, .L107
1431 0040 FFF7FEFF bl HAL_UARTEx_DisableFifoMode
1432 .LVL68:
718:Src/main.c **** {
1433 .loc 1 718 6 discriminator 1 view .LVU446
1434 0044 30B9 cbnz r0, .L106
726:Src/main.c ****
1435 .loc 1 726 1 view .LVU447
1436 0046 08BD pop {r3, pc}
1437 .L103:
708:Src/main.c **** }
1438 .loc 1 708 5 is_stmt 1 view .LVU448
1439 0048 FFF7FEFF bl Error_Handler
1440 .LVL69:
1441 .L104:
712:Src/main.c **** }
1442 .loc 1 712 5 view .LVU449
1443 004c FFF7FEFF bl Error_Handler
1444 .LVL70:
1445 .L105:
716:Src/main.c **** }
1446 .loc 1 716 5 view .LVU450
1447 0050 FFF7FEFF bl Error_Handler
1448 .LVL71:
1449 .L106:
720:Src/main.c **** }
1450 .loc 1 720 5 view .LVU451
1451 0054 FFF7FEFF bl Error_Handler
1452 .LVL72:
1453 .L108:
1454 .align 2
1455 .L107:
1456 0058 00000000 .word huart1
1457 005c 00380140 .word 1073821696
1458 .cfi_endproc
1459 .LFE340:
1461 .section .text.MX_TIM8_Init,"ax",%progbits
1462 .align 1
1463 .syntax unified
1464 .thumb
1465 .thumb_func
1467 MX_TIM8_Init:
1468 .LFB339:
604:Src/main.c ****
ARM GAS /tmp/cchrMLox.s page 51
1469 .loc 1 604 1 view -0
1470 .cfi_startproc
1471 @ args = 0, pretend = 0, frame = 112
1472 @ frame_needed = 0, uses_anonymous_args = 0
1473 0000 10B5 push {r4, lr}
1474 .LCFI24:
1475 .cfi_def_cfa_offset 8
1476 .cfi_offset 4, -8
1477 .cfi_offset 14, -4
1478 0002 9CB0 sub sp, sp, #112
1479 .LCFI25:
1480 .cfi_def_cfa_offset 120
610:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
1481 .loc 1 610 3 view .LVU453
610:Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0};
1482 .loc 1 610 26 is_stmt 0 view .LVU454
1483 0004 0024 movs r4, #0
1484 0006 1894 str r4, [sp, #96]
1485 0008 1994 str r4, [sp, #100]
1486 000a 1A94 str r4, [sp, #104]
1487 000c 1B94 str r4, [sp, #108]
611:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1488 .loc 1 611 3 is_stmt 1 view .LVU455
611:Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0};
1489 .loc 1 611 27 is_stmt 0 view .LVU456
1490 000e 1594 str r4, [sp, #84]
1491 0010 1694 str r4, [sp, #88]
1492 0012 1794 str r4, [sp, #92]
612:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
1493 .loc 1 612 3 is_stmt 1 view .LVU457
612:Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
1494 .loc 1 612 22 is_stmt 0 view .LVU458
1495 0014 0E94 str r4, [sp, #56]
1496 0016 0F94 str r4, [sp, #60]
1497 0018 1094 str r4, [sp, #64]
1498 001a 1194 str r4, [sp, #68]
1499 001c 1294 str r4, [sp, #72]
1500 001e 1394 str r4, [sp, #76]
1501 0020 1494 str r4, [sp, #80]
613:Src/main.c ****
1502 .loc 1 613 3 is_stmt 1 view .LVU459
613:Src/main.c ****
1503 .loc 1 613 34 is_stmt 0 view .LVU460
1504 0022 3422 movs r2, #52
1505 0024 2146 mov r1, r4
1506 0026 01A8 add r0, sp, #4
1507 0028 FFF7FEFF bl memset
1508 .LVL73:
618:Src/main.c **** htim8.Init.Prescaler = 1679;
1509 .loc 1 618 3 is_stmt 1 view .LVU461
618:Src/main.c **** htim8.Init.Prescaler = 1679;
1510 .loc 1 618 18 is_stmt 0 view .LVU462
1511 002c 3148 ldr r0, .L123
1512 002e 324B ldr r3, .L123+4
1513 0030 0360 str r3, [r0]
619:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
1514 .loc 1 619 3 is_stmt 1 view .LVU463
ARM GAS /tmp/cchrMLox.s page 52
619:Src/main.c **** htim8.Init.CounterMode = TIM_COUNTERMODE_UP;
1515 .loc 1 619 24 is_stmt 0 view .LVU464
1516 0032 40F28F63 movw r3, #1679
1517 0036 4360 str r3, [r0, #4]
620:Src/main.c **** htim8.Init.Period = 255;
1518 .loc 1 620 3 is_stmt 1 view .LVU465
620:Src/main.c **** htim8.Init.Period = 255;
1519 .loc 1 620 26 is_stmt 0 view .LVU466
1520 0038 8460 str r4, [r0, #8]
621:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1521 .loc 1 621 3 is_stmt 1 view .LVU467
621:Src/main.c **** htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
1522 .loc 1 621 21 is_stmt 0 view .LVU468
1523 003a FF23 movs r3, #255
1524 003c C360 str r3, [r0, #12]
622:Src/main.c **** htim8.Init.RepetitionCounter = 0;
1525 .loc 1 622 3 is_stmt 1 view .LVU469
622:Src/main.c **** htim8.Init.RepetitionCounter = 0;
1526 .loc 1 622 28 is_stmt 0 view .LVU470
1527 003e 0461 str r4, [r0, #16]
623:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1528 .loc 1 623 3 is_stmt 1 view .LVU471
623:Src/main.c **** htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
1529 .loc 1 623 32 is_stmt 0 view .LVU472
1530 0040 4461 str r4, [r0, #20]
624:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
1531 .loc 1 624 3 is_stmt 1 view .LVU473
624:Src/main.c **** if (HAL_TIM_Base_Init(&htim8) != HAL_OK)
1532 .loc 1 624 32 is_stmt 0 view .LVU474
1533 0042 8461 str r4, [r0, #24]
625:Src/main.c **** {
1534 .loc 1 625 3 is_stmt 1 view .LVU475
625:Src/main.c **** {
1535 .loc 1 625 7 is_stmt 0 view .LVU476
1536 0044 FFF7FEFF bl HAL_TIM_Base_Init
1537 .LVL74:
625:Src/main.c **** {
1538 .loc 1 625 6 discriminator 1 view .LVU477
1539 0048 0028 cmp r0, #0
1540 004a 47D1 bne .L117
629:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
1541 .loc 1 629 3 is_stmt 1 view .LVU478
629:Src/main.c **** if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK)
1542 .loc 1 629 34 is_stmt 0 view .LVU479
1543 004c 4FF48053 mov r3, #4096
1544 0050 1893 str r3, [sp, #96]
630:Src/main.c **** {
1545 .loc 1 630 3 is_stmt 1 view .LVU480
630:Src/main.c **** {
1546 .loc 1 630 7 is_stmt 0 view .LVU481
1547 0052 18A9 add r1, sp, #96
1548 0054 2748 ldr r0, .L123
1549 0056 FFF7FEFF bl HAL_TIM_ConfigClockSource
1550 .LVL75:
630:Src/main.c **** {
1551 .loc 1 630 6 discriminator 1 view .LVU482
1552 005a 0028 cmp r0, #0
ARM GAS /tmp/cchrMLox.s page 53
1553 005c 40D1 bne .L118
634:Src/main.c **** {
1554 .loc 1 634 3 is_stmt 1 view .LVU483
634:Src/main.c **** {
1555 .loc 1 634 7 is_stmt 0 view .LVU484
1556 005e 2548 ldr r0, .L123
1557 0060 FFF7FEFF bl HAL_TIM_PWM_Init
1558 .LVL76:
634:Src/main.c **** {
1559 .loc 1 634 6 discriminator 1 view .LVU485
1560 0064 0028 cmp r0, #0
1561 0066 3DD1 bne .L119
638:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1562 .loc 1 638 3 is_stmt 1 view .LVU486
638:Src/main.c **** sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
1563 .loc 1 638 37 is_stmt 0 view .LVU487
1564 0068 0023 movs r3, #0
1565 006a 1593 str r3, [sp, #84]
639:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1566 .loc 1 639 3 is_stmt 1 view .LVU488
639:Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
1567 .loc 1 639 38 is_stmt 0 view .LVU489
1568 006c 1693 str r3, [sp, #88]
640:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
1569 .loc 1 640 3 is_stmt 1 view .LVU490
640:Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK)
1570 .loc 1 640 33 is_stmt 0 view .LVU491
1571 006e 1793 str r3, [sp, #92]
641:Src/main.c **** {
1572 .loc 1 641 3 is_stmt 1 view .LVU492
641:Src/main.c **** {
1573 .loc 1 641 7 is_stmt 0 view .LVU493
1574 0070 15A9 add r1, sp, #84
1575 0072 2048 ldr r0, .L123
1576 0074 FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization
1577 .LVL77:
641:Src/main.c **** {
1578 .loc 1 641 6 discriminator 1 view .LVU494
1579 0078 0028 cmp r0, #0
1580 007a 35D1 bne .L120
645:Src/main.c **** sConfigOC.Pulse = 0;
1581 .loc 1 645 3 is_stmt 1 view .LVU495
645:Src/main.c **** sConfigOC.Pulse = 0;
1582 .loc 1 645 20 is_stmt 0 view .LVU496
1583 007c 6023 movs r3, #96
1584 007e 0E93 str r3, [sp, #56]
646:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1585 .loc 1 646 3 is_stmt 1 view .LVU497
646:Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
1586 .loc 1 646 19 is_stmt 0 view .LVU498
1587 0080 0023 movs r3, #0
1588 0082 0F93 str r3, [sp, #60]
647:Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
1589 .loc 1 647 3 is_stmt 1 view .LVU499
647:Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
1590 .loc 1 647 24 is_stmt 0 view .LVU500
1591 0084 1093 str r3, [sp, #64]
ARM GAS /tmp/cchrMLox.s page 54
648:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1592 .loc 1 648 3 is_stmt 1 view .LVU501
648:Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
1593 .loc 1 648 25 is_stmt 0 view .LVU502
1594 0086 1193 str r3, [sp, #68]
649:Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
1595 .loc 1 649 3 is_stmt 1 view .LVU503
649:Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
1596 .loc 1 649 24 is_stmt 0 view .LVU504
1597 0088 1293 str r3, [sp, #72]
650:Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
1598 .loc 1 650 3 is_stmt 1 view .LVU505
650:Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
1599 .loc 1 650 25 is_stmt 0 view .LVU506
1600 008a 1393 str r3, [sp, #76]
651:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
1601 .loc 1 651 3 is_stmt 1 view .LVU507
651:Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim8, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
1602 .loc 1 651 26 is_stmt 0 view .LVU508
1603 008c 1493 str r3, [sp, #80]
652:Src/main.c **** {
1604 .loc 1 652 3 is_stmt 1 view .LVU509
652:Src/main.c **** {
1605 .loc 1 652 7 is_stmt 0 view .LVU510
1606 008e 0822 movs r2, #8
1607 0090 0EA9 add r1, sp, #56
1608 0092 1848 ldr r0, .L123
1609 0094 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel
1610 .LVL78:
652:Src/main.c **** {
1611 .loc 1 652 6 discriminator 1 view .LVU511
1612 0098 40BB cbnz r0, .L121
656:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
1613 .loc 1 656 3 is_stmt 1 view .LVU512
656:Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
1614 .loc 1 656 40 is_stmt 0 view .LVU513
1615 009a 0023 movs r3, #0
1616 009c 0193 str r3, [sp, #4]
657:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
1617 .loc 1 657 3 is_stmt 1 view .LVU514
657:Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
1618 .loc 1 657 41 is_stmt 0 view .LVU515
1619 009e 0293 str r3, [sp, #8]
658:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
1620 .loc 1 658 3 is_stmt 1 view .LVU516
658:Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0;
1621 .loc 1 658 34 is_stmt 0 view .LVU517
1622 00a0 0393 str r3, [sp, #12]
659:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
1623 .loc 1 659 3 is_stmt 1 view .LVU518
659:Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
1624 .loc 1 659 33 is_stmt 0 view .LVU519
1625 00a2 0493 str r3, [sp, #16]
660:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
1626 .loc 1 660 3 is_stmt 1 view .LVU520
660:Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
1627 .loc 1 660 35 is_stmt 0 view .LVU521
ARM GAS /tmp/cchrMLox.s page 55
1628 00a4 0593 str r3, [sp, #20]
661:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
1629 .loc 1 661 3 is_stmt 1 view .LVU522
661:Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0;
1630 .loc 1 661 38 is_stmt 0 view .LVU523
1631 00a6 4FF40052 mov r2, #8192
1632 00aa 0692 str r2, [sp, #24]
662:Src/main.c **** sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
1633 .loc 1 662 3 is_stmt 1 view .LVU524
662:Src/main.c **** sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
1634 .loc 1 662 36 is_stmt 0 view .LVU525
1635 00ac 0793 str r3, [sp, #28]
663:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
1636 .loc 1 663 3 is_stmt 1 view .LVU526
663:Src/main.c **** sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
1637 .loc 1 663 36 is_stmt 0 view .LVU527
1638 00ae 0893 str r3, [sp, #32]
664:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
1639 .loc 1 664 3 is_stmt 1 view .LVU528
664:Src/main.c **** sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
1640 .loc 1 664 36 is_stmt 0 view .LVU529
1641 00b0 0993 str r3, [sp, #36]
665:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
1642 .loc 1 665 3 is_stmt 1 view .LVU530
665:Src/main.c **** sBreakDeadTimeConfig.Break2Filter = 0;
1643 .loc 1 665 39 is_stmt 0 view .LVU531
1644 00b2 4FF00072 mov r2, #33554432
1645 00b6 0A92 str r2, [sp, #40]
666:Src/main.c **** sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
1646 .loc 1 666 3 is_stmt 1 view .LVU532
666:Src/main.c **** sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
1647 .loc 1 666 37 is_stmt 0 view .LVU533
1648 00b8 0B93 str r3, [sp, #44]
667:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
1649 .loc 1 667 3 is_stmt 1 view .LVU534
667:Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
1650 .loc 1 667 37 is_stmt 0 view .LVU535
1651 00ba 0C93 str r3, [sp, #48]
668:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
1652 .loc 1 668 3 is_stmt 1 view .LVU536
668:Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim8, &sBreakDeadTimeConfig) != HAL_OK)
1653 .loc 1 668 40 is_stmt 0 view .LVU537
1654 00bc 0D93 str r3, [sp, #52]
669:Src/main.c **** {
1655 .loc 1 669 3 is_stmt 1 view .LVU538
669:Src/main.c **** {
1656 .loc 1 669 7 is_stmt 0 view .LVU539
1657 00be 01A9 add r1, sp, #4
1658 00c0 0C48 ldr r0, .L123
1659 00c2 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime
1660 .LVL79:
669:Src/main.c **** {
1661 .loc 1 669 6 discriminator 1 view .LVU540
1662 00c6 98B9 cbnz r0, .L122
674:Src/main.c **** /* USER CODE END TIM8_Init 2 */
1663 .loc 1 674 5 is_stmt 1 view .LVU541
674:Src/main.c **** /* USER CODE END TIM8_Init 2 */
ARM GAS /tmp/cchrMLox.s page 56
1664 .loc 1 674 10 is_stmt 0 view .LVU542
1665 00c8 0A48 ldr r0, .L123
1666 00ca 0268 ldr r2, [r0]
674:Src/main.c **** /* USER CODE END TIM8_Init 2 */
1667 .loc 1 674 19 view .LVU543
1668 00cc 536C ldr r3, [r2, #68]
674:Src/main.c **** /* USER CODE END TIM8_Init 2 */
1669 .loc 1 674 26 view .LVU544
1670 00ce 43F40043 orr r3, r3, #32768
1671 00d2 5364 str r3, [r2, #68]
676:Src/main.c ****
1672 .loc 1 676 3 is_stmt 1 view .LVU545
1673 00d4 FFF7FEFF bl HAL_TIM_MspPostInit
1674 .LVL80:
678:Src/main.c ****
1675 .loc 1 678 1 is_stmt 0 view .LVU546
1676 00d8 1CB0 add sp, sp, #112
1677 .LCFI26:
1678 .cfi_remember_state
1679 .cfi_def_cfa_offset 8
1680 @ sp needed
1681 00da 10BD pop {r4, pc}
1682 .L117:
1683 .LCFI27:
1684 .cfi_restore_state
627:Src/main.c **** }
1685 .loc 1 627 5 is_stmt 1 view .LVU547
1686 00dc FFF7FEFF bl Error_Handler
1687 .LVL81:
1688 .L118:
632:Src/main.c **** }
1689 .loc 1 632 5 view .LVU548
1690 00e0 FFF7FEFF bl Error_Handler
1691 .LVL82:
1692 .L119:
636:Src/main.c **** }
1693 .loc 1 636 5 view .LVU549
1694 00e4 FFF7FEFF bl Error_Handler
1695 .LVL83:
1696 .L120:
643:Src/main.c **** }
1697 .loc 1 643 5 view .LVU550
1698 00e8 FFF7FEFF bl Error_Handler
1699 .LVL84:
1700 .L121:
654:Src/main.c **** }
1701 .loc 1 654 5 view .LVU551
1702 00ec FFF7FEFF bl Error_Handler
1703 .LVL85:
1704 .L122:
671:Src/main.c **** }
1705 .loc 1 671 5 view .LVU552
1706 00f0 FFF7FEFF bl Error_Handler
1707 .LVL86:
1708 .L124:
1709 .align 2
1710 .L123:
ARM GAS /tmp/cchrMLox.s page 57
1711 00f4 00000000 .word htim8
1712 00f8 00340140 .word 1073820672
1713 .cfi_endproc
1714 .LFE339:
1716 .section .text.SystemClock_Config,"ax",%progbits
1717 .align 1
1718 .global SystemClock_Config
1719 .syntax unified
1720 .thumb
1721 .thumb_func
1723 SystemClock_Config:
1724 .LFB333:
221:Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
1725 .loc 1 221 1 view -0
1726 .cfi_startproc
1727 @ args = 0, pretend = 0, frame = 80
1728 @ frame_needed = 0, uses_anonymous_args = 0
1729 0000 10B5 push {r4, lr}
1730 .LCFI28:
1731 .cfi_def_cfa_offset 8
1732 .cfi_offset 4, -8
1733 .cfi_offset 14, -4
1734 0002 94B0 sub sp, sp, #80
1735 .LCFI29:
1736 .cfi_def_cfa_offset 88
222:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
1737 .loc 1 222 3 view .LVU554
222:Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
1738 .loc 1 222 22 is_stmt 0 view .LVU555
1739 0004 06AC add r4, sp, #24
1740 0006 3822 movs r2, #56
1741 0008 0021 movs r1, #0
1742 000a 2046 mov r0, r4
1743 000c FFF7FEFF bl memset
1744 .LVL87:
223:Src/main.c ****
1745 .loc 1 223 3 is_stmt 1 view .LVU556
223:Src/main.c ****
1746 .loc 1 223 22 is_stmt 0 view .LVU557
1747 0010 0020 movs r0, #0
1748 0012 0190 str r0, [sp, #4]
1749 0014 0290 str r0, [sp, #8]
1750 0016 0390 str r0, [sp, #12]
1751 0018 0490 str r0, [sp, #16]
1752 001a 0590 str r0, [sp, #20]
227:Src/main.c ****
1753 .loc 1 227 3 is_stmt 1 view .LVU558
1754 001c FFF7FEFF bl HAL_PWREx_ControlVoltageScaling
1755 .LVL88:
232:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
1756 .loc 1 232 3 view .LVU559
232:Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON;
1757 .loc 1 232 36 is_stmt 0 view .LVU560
1758 0020 0123 movs r3, #1
1759 0022 0693 str r3, [sp, #24]
233:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
1760 .loc 1 233 3 is_stmt 1 view .LVU561
ARM GAS /tmp/cchrMLox.s page 58
233:Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
1761 .loc 1 233 30 is_stmt 0 view .LVU562
1762 0024 4FF48033 mov r3, #65536
1763 0028 0793 str r3, [sp, #28]
234:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
1764 .loc 1 234 3 is_stmt 1 view .LVU563
234:Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
1765 .loc 1 234 34 is_stmt 0 view .LVU564
1766 002a 0223 movs r3, #2
1767 002c 0D93 str r3, [sp, #52]
235:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
1768 .loc 1 235 3 is_stmt 1 view .LVU565
235:Src/main.c **** RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
1769 .loc 1 235 35 is_stmt 0 view .LVU566
1770 002e 0322 movs r2, #3
1771 0030 0E92 str r2, [sp, #56]
236:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 28;
1772 .loc 1 236 3 is_stmt 1 view .LVU567
236:Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 28;
1773 .loc 1 236 30 is_stmt 0 view .LVU568
1774 0032 0F93 str r3, [sp, #60]
237:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
1775 .loc 1 237 3 is_stmt 1 view .LVU569
237:Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
1776 .loc 1 237 30 is_stmt 0 view .LVU570
1777 0034 1C22 movs r2, #28
1778 0036 1092 str r2, [sp, #64]
238:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
1779 .loc 1 238 3 is_stmt 1 view .LVU571
238:Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
1780 .loc 1 238 30 is_stmt 0 view .LVU572
1781 0038 1193 str r3, [sp, #68]
239:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
1782 .loc 1 239 3 is_stmt 1 view .LVU573
239:Src/main.c **** RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
1783 .loc 1 239 30 is_stmt 0 view .LVU574
1784 003a 0422 movs r2, #4
1785 003c 1292 str r2, [sp, #72]
240:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
1786 .loc 1 240 3 is_stmt 1 view .LVU575
240:Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
1787 .loc 1 240 30 is_stmt 0 view .LVU576
1788 003e 1393 str r3, [sp, #76]
241:Src/main.c **** {
1789 .loc 1 241 3 is_stmt 1 view .LVU577
241:Src/main.c **** {
1790 .loc 1 241 7 is_stmt 0 view .LVU578
1791 0040 2046 mov r0, r4
1792 0042 FFF7FEFF bl HAL_RCC_OscConfig
1793 .LVL89:
241:Src/main.c **** {
1794 .loc 1 241 6 discriminator 1 view .LVU579
1795 0046 B0B9 cbnz r0, .L129
248:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
1796 .loc 1 248 3 is_stmt 1 view .LVU580
248:Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
1797 .loc 1 248 31 is_stmt 0 view .LVU581
ARM GAS /tmp/cchrMLox.s page 59
1798 0048 0F23 movs r3, #15
1799 004a 0193 str r3, [sp, #4]
250:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
1800 .loc 1 250 3 is_stmt 1 view .LVU582
250:Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
1801 .loc 1 250 34 is_stmt 0 view .LVU583
1802 004c 0323 movs r3, #3
1803 004e 0293 str r3, [sp, #8]
251:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
1804 .loc 1 251 3 is_stmt 1 view .LVU584
251:Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
1805 .loc 1 251 35 is_stmt 0 view .LVU585
1806 0050 0023 movs r3, #0
1807 0052 0393 str r3, [sp, #12]
252:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
1808 .loc 1 252 3 is_stmt 1 view .LVU586
252:Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
1809 .loc 1 252 36 is_stmt 0 view .LVU587
1810 0054 0493 str r3, [sp, #16]
253:Src/main.c ****
1811 .loc 1 253 3 is_stmt 1 view .LVU588
253:Src/main.c ****
1812 .loc 1 253 36 is_stmt 0 view .LVU589
1813 0056 0593 str r3, [sp, #20]
255:Src/main.c **** {
1814 .loc 1 255 3 is_stmt 1 view .LVU590
255:Src/main.c **** {
1815 .loc 1 255 7 is_stmt 0 view .LVU591
1816 0058 0421 movs r1, #4
1817 005a 0DEB0100 add r0, sp, r1
1818 005e FFF7FEFF bl HAL_RCC_ClockConfig
1819 .LVL90:
255:Src/main.c **** {
1820 .loc 1 255 6 discriminator 1 view .LVU592
1821 0062 50B9 cbnz r0, .L130
259:Src/main.c **** }
1822 .loc 1 259 3 is_stmt 1 view .LVU593
1823 0064 0022 movs r2, #0
1824 0066 4FF08061 mov r1, #67108864
1825 006a 4FF48070 mov r0, #256
1826 006e FFF7FEFF bl HAL_RCC_MCOConfig
1827 .LVL91:
260:Src/main.c ****
1828 .loc 1 260 1 is_stmt 0 view .LVU594
1829 0072 14B0 add sp, sp, #80
1830 .LCFI30:
1831 .cfi_remember_state
1832 .cfi_def_cfa_offset 8
1833 @ sp needed
1834 0074 10BD pop {r4, pc}
1835 .L129:
1836 .LCFI31:
1837 .cfi_restore_state
243:Src/main.c **** }
1838 .loc 1 243 5 is_stmt 1 view .LVU595
1839 0076 FFF7FEFF bl Error_Handler
1840 .LVL92:
ARM GAS /tmp/cchrMLox.s page 60
1841 .L130:
257:Src/main.c **** }
1842 .loc 1 257 5 view .LVU596
1843 007a FFF7FEFF bl Error_Handler
1844 .LVL93:
1845 .cfi_endproc
1846 .LFE333:
1848 .section .text.main,"ax",%progbits
1849 .align 1
1850 .global main
1851 .syntax unified
1852 .thumb
1853 .thumb_func
1855 main:
1856 .LFB332:
88:Src/main.c ****
1857 .loc 1 88 1 view -0
1858 .cfi_startproc
1859 @ Volatile: function does not return.
1860 @ args = 0, pretend = 0, frame = 0
1861 @ frame_needed = 0, uses_anonymous_args = 0
1862 0000 08B5 push {r3, lr}
1863 .LCFI32:
1864 .cfi_def_cfa_offset 8
1865 .cfi_offset 3, -8
1866 .cfi_offset 14, -4
97:Src/main.c ****
1867 .loc 1 97 3 view .LVU598
1868 0002 FFF7FEFF bl HAL_Init
1869 .LVL94:
104:Src/main.c ****
1870 .loc 1 104 3 view .LVU599
1871 0006 FFF7FEFF bl SystemClock_Config
1872 .LVL95:
111:Src/main.c **** MX_DMA_Init();
1873 .loc 1 111 3 view .LVU600
1874 000a FFF7FEFF bl MX_GPIO_Init
1875 .LVL96:
112:Src/main.c **** MX_TIM2_Init();
1876 .loc 1 112 3 view .LVU601
1877 000e FFF7FEFF bl MX_DMA_Init
1878 .LVL97:
113:Src/main.c **** MX_I2C1_Init();
1879 .loc 1 113 3 view .LVU602
1880 0012 FFF7FEFF bl MX_TIM2_Init
1881 .LVL98:
114:Src/main.c **** MX_TIM3_Init();
1882 .loc 1 114 3 view .LVU603
1883 0016 FFF7FEFF bl MX_I2C1_Init
1884 .LVL99:
115:Src/main.c **** MX_ADC1_Init();
1885 .loc 1 115 3 view .LVU604
1886 001a FFF7FEFF bl MX_TIM3_Init
1887 .LVL100:
116:Src/main.c **** MX_ADC2_Init();
1888 .loc 1 116 3 view .LVU605
1889 001e FFF7FEFF bl MX_ADC1_Init
ARM GAS /tmp/cchrMLox.s page 61
1890 .LVL101:
117:Src/main.c **** MX_USART1_UART_Init();
1891 .loc 1 117 3 view .LVU606
1892 0022 FFF7FEFF bl MX_ADC2_Init
1893 .LVL102:
118:Src/main.c **** MX_TIM8_Init();
1894 .loc 1 118 3 view .LVU607
1895 0026 FFF7FEFF bl MX_USART1_UART_Init
1896 .LVL103:
119:Src/main.c **** /* USER CODE BEGIN 2 */
1897 .loc 1 119 3 view .LVU608
1898 002a FFF7FEFF bl MX_TIM8_Init
1899 .LVL104:
126:Src/main.c ****
1900 .loc 1 126 5 view .LVU609
1901 002e 3F48 ldr r0, .L143
1902 0030 FFF7FEFF bl HAL_ADC_Start_IT
1903 .LVL105:
129:Src/main.c ****
1904 .loc 1 129 5 view .LVU610
1905 0034 3E4C ldr r4, .L143+4
1906 0036 2046 mov r0, r4
1907 0038 FFF7FEFF bl HAL_TIM_Base_Start_IT
1908 .LVL106:
132:Src/main.c ****
1909 .loc 1 132 5 view .LVU611
1910 003c 3D48 ldr r0, .L143+8
1911 003e FFF7FEFF bl HAL_TIM_Base_Start_IT
1912 .LVL107:
134:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_2);
1913 .loc 1 134 5 view .LVU612
1914 0042 0021 movs r1, #0
1915 0044 2046 mov r0, r4
1916 0046 FFF7FEFF bl HAL_TIM_PWM_Start
1917 .LVL108:
135:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);
1918 .loc 1 135 5 view .LVU613
1919 004a 0421 movs r1, #4
1920 004c 2046 mov r0, r4
1921 004e FFF7FEFF bl HAL_TIM_PWM_Start
1922 .LVL109:
136:Src/main.c **** HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);
1923 .loc 1 136 5 view .LVU614
1924 0052 0821 movs r1, #8
1925 0054 2046 mov r0, r4
1926 0056 FFF7FEFF bl HAL_TIM_PWM_Start
1927 .LVL110:
137:Src/main.c ****
1928 .loc 1 137 5 view .LVU615
1929 005a 0C21 movs r1, #12
1930 005c 2046 mov r0, r4
1931 005e FFF7FEFF bl HAL_TIM_PWM_Start
1932 .LVL111:
140:Src/main.c **** HAL_TIM_PWM_Start(&htim8, TIM_CHANNEL_3);
1933 .loc 1 140 5 view .LVU616
1934 0062 354C ldr r4, .L143+12
1935 0064 2046 mov r0, r4
ARM GAS /tmp/cchrMLox.s page 62
1936 0066 FFF7FEFF bl HAL_TIM_Base_Start_IT
1937 .LVL112:
141:Src/main.c **** // serve, lo start nonfa partire i CHN
1938 .loc 1 141 5 view .LVU617
1939 006a 0821 movs r1, #8
1940 006c 2046 mov r0, r4
1941 006e FFF7FEFF bl HAL_TIM_PWM_Start
1942 .LVL113:
143:Src/main.c ****
1943 .loc 1 143 5 view .LVU618
1944 0072 0422 movs r2, #4
1945 0074 0821 movs r1, #8
1946 0076 2068 ldr r0, [r4]
1947 0078 FFF7FEFF bl TIM_CCxChannelCmd
1948 .LVL114:
145:Src/main.c **** squeow_ui_init();
1949 .loc 1 145 5 view .LVU619
1950 007c FFF7FEFF bl squeow_init
1951 .LVL115:
146:Src/main.c ****
1952 .loc 1 146 5 view .LVU620
1953 0080 FFF7FEFF bl squeow_ui_init
1954 .LVL116:
157:Src/main.c **** #endif
1955 .loc 1 157 5 view .LVU621
1956 0084 FFF7FEFF bl seriow_stab_dump
1957 .LVL117:
161:Src/main.c ****
1958 .loc 1 161 5 view .LVU622
1959 0088 0422 movs r2, #4
1960 008a 2C49 ldr r1, .L143+16
1961 008c 2C48 ldr r0, .L143+20
1962 008e FFF7FEFF bl HAL_ADC_Start_DMA
1963 .LVL118:
163:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
1964 .loc 1 163 5 view .LVU623
163:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
1965 .loc 1 163 9 is_stmt 0 view .LVU624
1966 0092 2C4B ldr r3, .L143+24
1967 0094 1978 ldrb r1, [r3] @ zero_extendqisi2
163:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
1968 .loc 1 163 8 view .LVU625
1969 0096 D9B1 cbz r1, .L133
164:Src/main.c **** /* USER CODE END 2 */
1970 .loc 1 164 9 is_stmt 1 view .LVU626
1971 0098 2B48 ldr r0, .L143+28
1972 009a FFF7FEFF bl serial_write
1973 .LVL119:
1974 009e 17E0 b .L133
1975 .L141:
176:Src/main.c **** HAL_ADC_Start_DMA(&hadc2, adc2_valori, 4);
1976 .loc 1 176 17 view .LVU627
1977 00a0 264C ldr r4, .L143+16
1978 00a2 2046 mov r0, r4
1979 00a4 FFF7FEFF bl adc_rileva_soglie
1980 .LVL120:
177:Src/main.c **** adc2_done = 0;
ARM GAS /tmp/cchrMLox.s page 63
1981 .loc 1 177 17 view .LVU628
1982 00a8 0422 movs r2, #4
1983 00aa 2146 mov r1, r4
1984 00ac 2448 ldr r0, .L143+20
1985 00ae FFF7FEFF bl HAL_ADC_Start_DMA
1986 .LVL121:
178:Src/main.c **** }
1987 .loc 1 178 17 view .LVU629
178:Src/main.c **** }
1988 .loc 1 178 27 is_stmt 0 view .LVU630
1989 00b2 264B ldr r3, .L143+32
1990 00b4 0022 movs r2, #0
1991 00b6 1A70 strb r2, [r3]
1992 00b8 12E0 b .L134
1993 .L142:
187:Src/main.c **** #endif
1994 .loc 1 187 17 is_stmt 1 view .LVU631
1995 00ba FFF7FEFF bl led_blocco
1996 .LVL122:
1997 00be 1BE0 b .L135
1998 .L136:
208:Src/main.c **** }
1999 .loc 1 208 17 view .LVU632
208:Src/main.c **** }
2000 .loc 1 208 34 is_stmt 0 view .LVU633
2001 00c0 234A ldr r2, .L143+36
2002 00c2 1378 ldrb r3, [r2] @ zero_extendqisi2
2003 00c4 0133 adds r3, r3, #1
2004 00c6 DBB2 uxtb r3, r3
2005 00c8 1370 strb r3, [r2]
2006 .L138:
210:Src/main.c **** }
2007 .loc 1 210 13 is_stmt 1 view .LVU634
210:Src/main.c **** }
2008 .loc 1 210 22 is_stmt 0 view .LVU635
2009 00ca 224B ldr r3, .L143+40
2010 00cc 0022 movs r2, #0
2011 00ce 1A70 strb r2, [r3]
2012 .L133:
169:Src/main.c **** /* USER CODE END WHILE */
2013 .loc 1 169 5 is_stmt 1 view .LVU636
173:Src/main.c **** // 100hz
2014 .loc 1 173 9 view .LVU637
173:Src/main.c **** // 100hz
2015 .loc 1 173 13 is_stmt 0 view .LVU638
2016 00d0 204B ldr r3, .L143+40
2017 00d2 1B78 ldrb r3, [r3] @ zero_extendqisi2
173:Src/main.c **** // 100hz
2018 .loc 1 173 12 view .LVU639
2019 00d4 002B cmp r3, #0
2020 00d6 FBD0 beq .L133
175:Src/main.c **** adc_rileva_soglie(adc2_valori);
2021 .loc 1 175 13 is_stmt 1 view .LVU640
175:Src/main.c **** adc_rileva_soglie(adc2_valori);
2022 .loc 1 175 17 is_stmt 0 view .LVU641
2023 00d8 1C4B ldr r3, .L143+32
2024 00da 1B78 ldrb r3, [r3] @ zero_extendqisi2
ARM GAS /tmp/cchrMLox.s page 64
175:Src/main.c **** adc_rileva_soglie(adc2_valori);
2025 .loc 1 175 16 view .LVU642
2026 00dc 002B cmp r3, #0
2027 00de DFD1 bne .L141
2028 .L134:
183:Src/main.c **** processa_blocco();
2029 .loc 1 183 13 is_stmt 1 view .LVU643
2030 00e0 1D4B ldr r3, .L143+44
2031 00e2 1888 ldrh r0, [r3]
2032 00e4 C0F3C700 ubfx r0, r0, #3, #8
2033 00e8 FFF7FEFF bl led_pwm_duty
2034 .LVL123:
184:Src/main.c ****
2035 .loc 1 184 13 view .LVU644
2036 00ec FFF7FEFF bl processa_blocco
2037 .LVL124:
186:Src/main.c **** led_blocco(codice_allarme);
2038 .loc 1 186 13 view .LVU645
186:Src/main.c **** led_blocco(codice_allarme);
2039 .loc 1 186 17 is_stmt 0 view .LVU646
2040 00f0 1A4B ldr r3, .L143+48
2041 00f2 1878 ldrb r0, [r3] @ zero_extendqisi2
186:Src/main.c **** led_blocco(codice_allarme);
2042 .loc 1 186 16 view .LVU647
2043 00f4 0028 cmp r0, #0
2044 00f6 E0D1 bne .L142
2045 .L135:
191:Src/main.c **** sys_tick_prescale = 0;
2046 .loc 1 191 13 is_stmt 1 view .LVU648
191:Src/main.c **** sys_tick_prescale = 0;
2047 .loc 1 191 35 is_stmt 0 view .LVU649
2048 00f8 154B ldr r3, .L143+36
2049 00fa 1B78 ldrb r3, [r3] @ zero_extendqisi2
191:Src/main.c **** sys_tick_prescale = 0;
2050 .loc 1 191 16 view .LVU650
2051 00fc 0A2B cmp r3, #10
2052 00fe DFD9 bls .L136
192:Src/main.c ****
2053 .loc 1 192 17 is_stmt 1 view .LVU651
192:Src/main.c ****
2054 .loc 1 192 35 is_stmt 0 view .LVU652
2055 0100 134B ldr r3, .L143+36
2056 0102 0022 movs r2, #0
2057 0104 1A70 strb r2, [r3]
198:Src/main.c **** #endif
2058 .loc 1 198 17 is_stmt 1 view .LVU653
2059 0106 FFF7FEFF bl seriow_var_dump
2060 .LVL125:
201:Src/main.c **** blocco = 0;
2061 .loc 1 201 17 view .LVU654
201:Src/main.c **** blocco = 0;
2062 .loc 1 201 21 is_stmt 0 view .LVU655
2063 010a 0821 movs r1, #8
2064 010c 1448 ldr r0, .L143+52
2065 010e FFF7FEFF bl HAL_GPIO_ReadPin
2066 .LVL126:
201:Src/main.c **** blocco = 0;
ARM GAS /tmp/cchrMLox.s page 65
2067 .loc 1 201 20 discriminator 1 view .LVU656
2068 0112 10B9 cbnz r0, .L137
202:Src/main.c **** }
2069 .loc 1 202 21 is_stmt 1 view .LVU657
202:Src/main.c **** }
2070 .loc 1 202 28 is_stmt 0 view .LVU658
2071 0114 134B ldr r3, .L143+56
2072 0116 0022 movs r2, #0
2073 0118 1A70 strb r2, [r3]
2074 .L137:
205:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
2075 .loc 1 205 17 is_stmt 1 view .LVU659
205:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
2076 .loc 1 205 21 is_stmt 0 view .LVU660
2077 011a 0A4B ldr r3, .L143+24
2078 011c 1978 ldrb r1, [r3] @ zero_extendqisi2
205:Src/main.c **** serial_write(UART_TX_buf, UART_TX_buf_lenght);
2079 .loc 1 205 20 view .LVU661
2080 011e 0029 cmp r1, #0
2081 0120 D3D0 beq .L138
206:Src/main.c **** } else {
2082 .loc 1 206 21 is_stmt 1 view .LVU662
2083 0122 0948 ldr r0, .L143+28
2084 0124 FFF7FEFF bl serial_write
2085 .LVL127:
2086 0128 CFE7 b .L138
2087 .L144:
2088 012a 00BF .align 2
2089 .L143:
2090 012c 00000000 .word hadc1
2091 0130 00000000 .word htim2
2092 0134 00000000 .word htim3
2093 0138 00000000 .word htim8
2094 013c 00000000 .word adc2_valori
2095 0140 00000000 .word hadc2
2096 0144 00000000 .word UART_TX_buf_lenght
2097 0148 00000000 .word UART_TX_buf
2098 014c 00000000 .word adc2_done
2099 0150 00000000 .word sys_tick_prescale
2100 0154 00000000 .word sys_tick
2101 0158 00000000 .word ui_volume
2102 015c 00000000 .word codice_allarme
2103 0160 00040048 .word 1207960576
2104 0164 00000000 .word blocco
2105 .cfi_endproc
2106 .LFE332:
2108 .section .bss.last_offset.0,"aw",%nobits
2109 .align 1
2112 last_offset.0:
2113 0000 0000 .space 2
2114 .global hdma_usart1_tx
2115 .section .bss.hdma_usart1_tx,"aw",%nobits
2116 .align 2
2119 hdma_usart1_tx:
2120 0000 00000000 .space 96
2120 00000000
2120 00000000
ARM GAS /tmp/cchrMLox.s page 66
2120 00000000
2120 00000000
2121 .global hdma_usart1_rx
2122 .section .bss.hdma_usart1_rx,"aw",%nobits
2123 .align 2
2126 hdma_usart1_rx:
2127 0000 00000000 .space 96
2127 00000000
2127 00000000
2127 00000000
2127 00000000
2128 .global huart1
2129 .section .bss.huart1,"aw",%nobits
2130 .align 2
2133 huart1:
2134 0000 00000000 .space 148
2134 00000000
2134 00000000
2134 00000000
2134 00000000
2135 .global htim8
2136 .section .bss.htim8,"aw",%nobits
2137 .align 2
2140 htim8:
2141 0000 00000000 .space 76
2141 00000000
2141 00000000
2141 00000000
2141 00000000
2142 .global htim3
2143 .section .bss.htim3,"aw",%nobits
2144 .align 2
2147 htim3:
2148 0000 00000000 .space 76
2148 00000000
2148 00000000
2148 00000000
2148 00000000
2149 .global htim2
2150 .section .bss.htim2,"aw",%nobits
2151 .align 2
2154 htim2:
2155 0000 00000000 .space 76
2155 00000000
2155 00000000
2155 00000000
2155 00000000
2156 .global hi2c1
2157 .section .bss.hi2c1,"aw",%nobits
2158 .align 2
2161 hi2c1:
2162 0000 00000000 .space 84
2162 00000000
2162 00000000
2162 00000000
2162 00000000
2163 .global hdma_adc2
ARM GAS /tmp/cchrMLox.s page 67
2164 .section .bss.hdma_adc2,"aw",%nobits
2165 .align 2
2168 hdma_adc2:
2169 0000 00000000 .space 96
2169 00000000
2169 00000000
2169 00000000
2169 00000000
2170 .global hadc2
2171 .section .bss.hadc2,"aw",%nobits
2172 .align 2
2175 hadc2:
2176 0000 00000000 .space 108
2176 00000000
2176 00000000
2176 00000000
2176 00000000
2177 .global hadc1
2178 .section .bss.hadc1,"aw",%nobits
2179 .align 2
2182 hadc1:
2183 0000 00000000 .space 108
2183 00000000
2183 00000000
2183 00000000
2183 00000000
2184 .text
2185 .Letext0:
2186 .file 3 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h"
2187 .file 4 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/mach
2188 .file 5 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/arm-none-eabi/include/sys/
2189 .file 6 "Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4xx.h"
2190 .file 7 "/home/fra/bin/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi/lib/gcc/arm-none-eabi/14.2
2191 .file 8 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h"
2192 .file 9 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h"
2193 .file 10 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h"
2194 .file 11 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h"
2195 .file 12 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h"
2196 .file 13 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h"
2197 .file 14 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h"
2198 .file 15 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h"
2199 .file 16 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h"
2200 .file 17 "Inc/si5351.h"
2201 .file 18 "Inc/squeow.h"
2202 .file 19 "Inc/squeow_ui.h"
2203 .file 20 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr_ex.h"
2204 .file 21 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h"
2205 .file 22 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h"
2206 .file 23 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h"
2207 .file 24 "Inc/main.h"
2208 .file 25 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h"
2209 .file 26 "Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h"
2210 .file 27 "<built-in>"
ARM GAS /tmp/cchrMLox.s page 68
DEFINED SYMBOLS
*ABS*:00000000 main.c
/tmp/cchrMLox.s:21 .text.MX_GPIO_Init:00000000 $t
/tmp/cchrMLox.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init
/tmp/cchrMLox.s:170 .text.MX_GPIO_Init:00000098 $d
/tmp/cchrMLox.s:176 .text.MX_DMA_Init:00000000 $t
/tmp/cchrMLox.s:181 .text.MX_DMA_Init:00000000 MX_DMA_Init
/tmp/cchrMLox.s:264 .text.MX_DMA_Init:00000060 $d
/tmp/cchrMLox.s:269 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 $t
/tmp/cchrMLox.s:275 .text.HAL_ADC_LevelOutOfWindowCallback:00000000 HAL_ADC_LevelOutOfWindowCallback
/tmp/cchrMLox.s:289 .text.HAL_ADC_ConvCpltCallback:00000000 $t
/tmp/cchrMLox.s:295 .text.HAL_ADC_ConvCpltCallback:00000000 HAL_ADC_ConvCpltCallback
/tmp/cchrMLox.s:313 .text.HAL_ADC_ConvCpltCallback:00000008 $d
/tmp/cchrMLox.s:318 .text.HAL_UARTEx_RxEventCallback:00000000 $t
/tmp/cchrMLox.s:324 .text.HAL_UARTEx_RxEventCallback:00000000 HAL_UARTEx_RxEventCallback
/tmp/cchrMLox.s:366 .text.HAL_UARTEx_RxEventCallback:00000024 $d
/tmp/cchrMLox.s:2112 .bss.last_offset.0:00000000 last_offset.0
/tmp/cchrMLox.s:371 .text.HAL_UART_TxCpltCallback:00000000 $t
/tmp/cchrMLox.s:377 .text.HAL_UART_TxCpltCallback:00000000 HAL_UART_TxCpltCallback
/tmp/cchrMLox.s:395 .text.HAL_UART_TxCpltCallback:00000008 $d
/tmp/cchrMLox.s:400 .text.HAL_UART_TxHalfCpltCallback:00000000 $t
/tmp/cchrMLox.s:406 .text.HAL_UART_TxHalfCpltCallback:00000000 HAL_UART_TxHalfCpltCallback
/tmp/cchrMLox.s:424 .text.HAL_UART_TxHalfCpltCallback:00000008 $d
/tmp/cchrMLox.s:429 .text.UART_DMATransmitCplt:00000000 $t
/tmp/cchrMLox.s:435 .text.UART_DMATransmitCplt:00000000 UART_DMATransmitCplt
/tmp/cchrMLox.s:453 .text.UART_DMATransmitCplt:00000008 $d
/tmp/cchrMLox.s:458 .text.Error_Handler:00000000 $t
/tmp/cchrMLox.s:464 .text.Error_Handler:00000000 Error_Handler
/tmp/cchrMLox.s:496 .text.MX_TIM2_Init:00000000 $t
/tmp/cchrMLox.s:501 .text.MX_TIM2_Init:00000000 MX_TIM2_Init
/tmp/cchrMLox.s:712 .text.MX_TIM2_Init:000000f0 $d
/tmp/cchrMLox.s:2154 .bss.htim2:00000000 htim2
/tmp/cchrMLox.s:717 .text.MX_I2C1_Init:00000000 $t
/tmp/cchrMLox.s:722 .text.MX_I2C1_Init:00000000 MX_I2C1_Init
/tmp/cchrMLox.s:804 .text.MX_I2C1_Init:00000048 $d
/tmp/cchrMLox.s:2161 .bss.hi2c1:00000000 hi2c1
/tmp/cchrMLox.s:811 .text.MX_TIM3_Init:00000000 $t
/tmp/cchrMLox.s:816 .text.MX_TIM3_Init:00000000 MX_TIM3_Init
/tmp/cchrMLox.s:920 .text.MX_TIM3_Init:00000064 $d
/tmp/cchrMLox.s:2147 .bss.htim3:00000000 htim3
/tmp/cchrMLox.s:926 .text.MX_ADC1_Init:00000000 $t
/tmp/cchrMLox.s:931 .text.MX_ADC1_Init:00000000 MX_ADC1_Init
/tmp/cchrMLox.s:1137 .text.MX_ADC1_Init:000000d8 $d
/tmp/cchrMLox.s:2182 .bss.hadc1:00000000 hadc1
/tmp/cchrMLox.s:1144 .text.MX_ADC2_Init:00000000 $t
/tmp/cchrMLox.s:1149 .text.MX_ADC2_Init:00000000 MX_ADC2_Init
/tmp/cchrMLox.s:1342 .text.MX_ADC2_Init:000000bc $d
/tmp/cchrMLox.s:2175 .bss.hadc2:00000000 hadc2
/tmp/cchrMLox.s:1352 .text.MX_USART1_UART_Init:00000000 $t
/tmp/cchrMLox.s:1357 .text.MX_USART1_UART_Init:00000000 MX_USART1_UART_Init
/tmp/cchrMLox.s:1456 .text.MX_USART1_UART_Init:00000058 $d
/tmp/cchrMLox.s:2133 .bss.huart1:00000000 huart1
/tmp/cchrMLox.s:1462 .text.MX_TIM8_Init:00000000 $t
/tmp/cchrMLox.s:1467 .text.MX_TIM8_Init:00000000 MX_TIM8_Init
/tmp/cchrMLox.s:1711 .text.MX_TIM8_Init:000000f4 $d
/tmp/cchrMLox.s:2140 .bss.htim8:00000000 htim8
/tmp/cchrMLox.s:1717 .text.SystemClock_Config:00000000 $t
ARM GAS /tmp/cchrMLox.s page 69
/tmp/cchrMLox.s:1723 .text.SystemClock_Config:00000000 SystemClock_Config
/tmp/cchrMLox.s:1849 .text.main:00000000 $t
/tmp/cchrMLox.s:1855 .text.main:00000000 main
/tmp/cchrMLox.s:2090 .text.main:0000012c $d
/tmp/cchrMLox.s:2109 .bss.last_offset.0:00000000 $d
/tmp/cchrMLox.s:2119 .bss.hdma_usart1_tx:00000000 hdma_usart1_tx
/tmp/cchrMLox.s:2116 .bss.hdma_usart1_tx:00000000 $d
/tmp/cchrMLox.s:2126 .bss.hdma_usart1_rx:00000000 hdma_usart1_rx
/tmp/cchrMLox.s:2123 .bss.hdma_usart1_rx:00000000 $d
/tmp/cchrMLox.s:2130 .bss.huart1:00000000 $d
/tmp/cchrMLox.s:2137 .bss.htim8:00000000 $d
/tmp/cchrMLox.s:2144 .bss.htim3:00000000 $d
/tmp/cchrMLox.s:2151 .bss.htim2:00000000 $d
/tmp/cchrMLox.s:2158 .bss.hi2c1:00000000 $d
/tmp/cchrMLox.s:2168 .bss.hdma_adc2:00000000 hdma_adc2
/tmp/cchrMLox.s:2165 .bss.hdma_adc2:00000000 $d
/tmp/cchrMLox.s:2172 .bss.hadc2:00000000 $d
/tmp/cchrMLox.s:2179 .bss.hadc1:00000000 $d
UNDEFINED SYMBOLS
HAL_GPIO_WritePin
HAL_GPIO_Init
HAL_NVIC_SetPriority
HAL_NVIC_EnableIRQ
adc2_done
uart_sent
HAL_TIM_Base_Init
HAL_TIM_ConfigClockSource
HAL_TIM_PWM_Init
HAL_TIMEx_MasterConfigSynchronization
HAL_TIM_PWM_ConfigChannel
HAL_TIM_MspPostInit
HAL_I2C_Init
HAL_I2CEx_ConfigAnalogFilter
HAL_I2CEx_ConfigDigitalFilter
memset
HAL_ADC_Init
HAL_ADCEx_MultiModeConfigChannel
HAL_ADC_AnalogWDGConfig
HAL_ADC_ConfigChannel
HAL_UART_Init
HAL_UARTEx_SetTxFifoThreshold
HAL_UARTEx_SetRxFifoThreshold
HAL_UARTEx_DisableFifoMode
HAL_TIMEx_ConfigBreakDeadTime
HAL_PWREx_ControlVoltageScaling
HAL_RCC_OscConfig
HAL_RCC_ClockConfig
HAL_RCC_MCOConfig
HAL_Init
HAL_ADC_Start_IT
HAL_TIM_Base_Start_IT
HAL_TIM_PWM_Start
TIM_CCxChannelCmd
squeow_init
squeow_ui_init
seriow_stab_dump
ARM GAS /tmp/cchrMLox.s page 70
HAL_ADC_Start_DMA
serial_write
adc_rileva_soglie
led_blocco
led_pwm_duty
processa_blocco
seriow_var_dump
HAL_GPIO_ReadPin
adc2_valori
UART_TX_buf_lenght
UART_TX_buf
sys_tick_prescale
sys_tick
ui_volume
codice_allarme
blocco
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